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pci: sorting out type confusion in pci_register_bar().
[qemu.git] / hw / eepro100.c
blob8cbc3aa7a216e03605259b6802ebb757f3c67ef5
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stddef.h> /* offsetof */
45 #include "hw.h"
46 #include "pci.h"
47 #include "net.h"
48 #include "eeprom93xx.h"
49
50 #define KiB 1024
51
52 /* Debug EEPRO100 card. */
53 #if 0
54 # define DEBUG_EEPRO100
55 #endif
56
57 #ifdef DEBUG_EEPRO100
58 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
59 #else
60 #define logout(fmt, ...) ((void)0)
61 #endif
62
63 /* Set flags to 0 to disable debug output. */
64 #define INT 1 /* interrupt related actions */
65 #define MDI 1 /* mdi related actions */
66 #define OTHER 1
67 #define RXTX 1
68 #define EEPROM 1 /* eeprom related actions */
69
70 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
71
72 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
73
74 #define MAX_ETH_FRAME_SIZE 1514
75
76 /* This driver supports several different devices which are declared here. */
77 #define i82550 0x82550
78 #define i82551 0x82551
79 #define i82557A 0x82557a
80 #define i82557B 0x82557b
81 #define i82557C 0x82557c
82 #define i82558A 0x82558a
83 #define i82558B 0x82558b
84 #define i82559A 0x82559a
85 #define i82559B 0x82559b
86 #define i82559C 0x82559c
87 #define i82559ER 0x82559e
88 #define i82562 0x82562
89 #define i82801 0x82801
90
91 /* Use 64 word EEPROM. TODO: could be a runtime option. */
92 #define EEPROM_SIZE 64
93
94 #define PCI_MEM_SIZE (4 * KiB)
95 #define PCI_IO_SIZE 64
96 #define PCI_FLASH_SIZE (128 * KiB)
97
98 #define BIT(n) (1 << (n))
99 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
100
101 /* The SCB accepts the following controls for the Tx and Rx units: */
102 #define CU_NOP 0x0000 /* No operation. */
103 #define CU_START 0x0010 /* CU start. */
104 #define CU_RESUME 0x0020 /* CU resume. */
105 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
106 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
107 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
108 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
109 #define CU_SRESUME 0x00a0 /* CU static resume. */
110
111 #define RU_NOP 0x0000
112 #define RX_START 0x0001
113 #define RX_RESUME 0x0002
114 #define RU_ABORT 0x0004
115 #define RX_ADDR_LOAD 0x0006
116 #define RX_RESUMENR 0x0007
117 #define INT_MASK 0x0100
118 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
119
120 typedef struct {
121 PCIDeviceInfo pci;
122 uint32_t device;
123 uint16_t device_id;
124 uint8_t revision;
125 uint8_t stats_size;
126 bool has_extended_tcb_support;
127 bool power_management;
128 } E100PCIDeviceInfo;
129
130 /* Offsets to the various registers.
131 All accesses need not be longword aligned. */
132 enum speedo_offsets {
133 SCBStatus = 0, /* Status Word. */
134 SCBAck = 1,
135 SCBCmd = 2, /* Rx/Command Unit command and status. */
136 SCBIntmask = 3,
137 SCBPointer = 4, /* General purpose pointer. */
138 SCBPort = 8, /* Misc. commands and operands. */
139 SCBflash = 12, /* Flash memory control. */
140 SCBeeprom = 14, /* EEPROM control. */
141 SCBCtrlMDI = 16, /* MDI interface control. */
142 SCBEarlyRx = 20, /* Early receive byte count. */
143 SCBFlow = 24, /* Flow Control. */
144 SCBpmdr = 27, /* Power Management Driver. */
145 SCBgctrl = 28, /* General Control. */
146 SCBgstat = 29, /* General Status. */
147 };
148
149 /* A speedo3 transmit buffer descriptor with two buffers... */
150 typedef struct {
151 uint16_t status;
152 uint16_t command;
153 uint32_t link; /* void * */
154 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
155 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
156 uint8_t tx_threshold; /* transmit threshold */
157 uint8_t tbd_count; /* TBD number */
158 #if 0
159 /* This constitutes two "TBD" entries: hdr and data */
160 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
161 int32_t tx_buf_size0; /* Length of Tx hdr. */
162 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
163 int32_t tx_buf_size1; /* Length of Tx data. */
164 #endif
165 } eepro100_tx_t;
166
167 /* Receive frame descriptor. */
168 typedef struct {
169 int16_t status;
170 uint16_t command;
171 uint32_t link; /* struct RxFD * */
172 uint32_t rx_buf_addr; /* void * */
173 uint16_t count;
174 uint16_t size;
175 char packet[MAX_ETH_FRAME_SIZE + 4];
176 } eepro100_rx_t;
177
178 typedef enum {
179 COMMAND_EL = BIT(15),
180 COMMAND_S = BIT(14),
181 COMMAND_I = BIT(13),
182 COMMAND_NC = BIT(4),
183 COMMAND_SF = BIT(3),
184 COMMAND_CMD = BITS(2, 0),
185 } scb_command_bit;
186
187 typedef enum {
188 STATUS_C = BIT(15),
189 STATUS_OK = BIT(13),
190 } scb_status_bit;
191
192 typedef struct {
193 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
194 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
195 tx_multiple_collisions, tx_total_collisions;
196 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
197 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
198 rx_short_frame_errors;
199 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
200 uint16_t xmt_tco_frames, rcv_tco_frames;
201 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
202 uint32_t reserved[4];
203 } eepro100_stats_t;
204
205 typedef enum {
206 cu_idle = 0,
207 cu_suspended = 1,
208 cu_active = 2,
209 cu_lpq_active = 2,
210 cu_hqp_active = 3
211 } cu_state_t;
212
213 typedef enum {
214 ru_idle = 0,
215 ru_suspended = 1,
216 ru_no_resources = 2,
217 ru_ready = 4
218 } ru_state_t;
219
220 typedef struct {
221 PCIDevice dev;
222 uint8_t mult[8]; /* multicast mask array */
223 int mmio_index;
224 NICState *nic;
225 NICConf conf;
226 uint8_t scb_stat; /* SCB stat/ack byte */
227 uint8_t int_stat; /* PCI interrupt status */
228 /* region must not be saved by nic_save. */
229 uint32_t region[3]; /* PCI region addresses */
230 uint16_t mdimem[32];
231 eeprom_t *eeprom;
232 uint32_t device; /* device variant */
233 uint32_t pointer;
234 /* (cu_base + cu_offset) address the next command block in the command block list. */
235 uint32_t cu_base; /* CU base address */
236 uint32_t cu_offset; /* CU address offset */
237 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
238 uint32_t ru_base; /* RU base address */
239 uint32_t ru_offset; /* RU address offset */
240 uint32_t statsaddr; /* pointer to eepro100_stats_t */
241
242 /* Temporary status information (no need to save these values),
243 * used while processing CU commands. */
244 eepro100_tx_t tx; /* transmit buffer descriptor */
245 uint32_t cb_address; /* = cu_base + cu_offset */
246
247 /* Statistical counters. Also used for wake-up packet (i82559). */
248 eepro100_stats_t statistics;
249
250 /* Configuration bytes. */
251 uint8_t configuration[22];
252
253 /* Data in mem is always in the byte order of the controller (le). */
254 uint8_t mem[PCI_MEM_SIZE];
255 /* vmstate for each particular nic */
256 VMStateDescription *vmstate;
257
258 /* Quasi static device properties (no need to save them). */
259 uint16_t stats_size;
260 bool has_extended_tcb_support;
261 } EEPRO100State;
262
263 /* Word indices in EEPROM. */
264 typedef enum {
265 EEPROM_CNFG_MDIX = 0x03,
266 EEPROM_ID = 0x05,
267 EEPROM_PHY_ID = 0x06,
268 EEPROM_VENDOR_ID = 0x0c,
269 EEPROM_CONFIG_ASF = 0x0d,
270 EEPROM_DEVICE_ID = 0x23,
271 EEPROM_SMBUS_ADDR = 0x90,
272 } EEPROMOffset;
273
274 /* Bit values for EEPROM ID word. */
275 typedef enum {
276 EEPROM_ID_MDM = BIT(0), /* Modem */
277 EEPROM_ID_STB = BIT(1), /* Standby Enable */
278 EEPROM_ID_WMR = BIT(2), /* ??? */
279 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
280 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
281 EEPROM_ID_ALT = BIT(7), /* */
282 /* BITS(10, 8) device revision */
283 EEPROM_ID_BD = BIT(11), /* boot disable */
284 EEPROM_ID_ID = BIT(13), /* id bit */
285 /* BITS(15, 14) signature */
286 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
287 } eeprom_id_bit;
288
289 /* Default values for MDI (PHY) registers */
290 static const uint16_t eepro100_mdi_default[] = {
291 /* MDI Registers 0 - 6, 7 */
292 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
293 /* MDI Registers 8 - 15 */
294 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
295 /* MDI Registers 16 - 31 */
296 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
297 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
298 };
299
300 /* Readonly mask for MDI (PHY) registers */
301 static const uint16_t eepro100_mdi_mask[] = {
302 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
303 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
304 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
305 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
306 };
307
308 /* XXX: optimize */
309 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
310 {
311 val = cpu_to_le32(val);
312 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
313 }
314
315 #define POLYNOMIAL 0x04c11db6
316
317 /* From FreeBSD */
318 /* XXX: optimize */
319 static unsigned compute_mcast_idx(const uint8_t * ep)
320 {
321 uint32_t crc;
322 int carry, i, j;
323 uint8_t b;
324
325 crc = 0xffffffff;
326 for (i = 0; i < 6; i++) {
327 b = *ep++;
328 for (j = 0; j < 8; j++) {
329 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
330 crc <<= 1;
331 b >>= 1;
332 if (carry) {
333 crc = ((crc ^ POLYNOMIAL) | carry);
334 }
335 }
336 }
337 return (crc & BITS(7, 2)) >> 2;
338 }
339
340 #if defined(DEBUG_EEPRO100)
341 static const char *nic_dump(const uint8_t * buf, unsigned size)
342 {
343 static char dump[3 * 16 + 1];
344 char *p = &dump[0];
345 if (size > 16) {
346 size = 16;
347 }
348 while (size-- > 0) {
349 p += sprintf(p, " %02x", *buf++);
350 }
351 return dump;
352 }
353 #endif /* DEBUG_EEPRO100 */
354
355 enum scb_stat_ack {
356 stat_ack_not_ours = 0x00,
357 stat_ack_sw_gen = 0x04,
358 stat_ack_rnr = 0x10,
359 stat_ack_cu_idle = 0x20,
360 stat_ack_frame_rx = 0x40,
361 stat_ack_cu_cmd_done = 0x80,
362 stat_ack_not_present = 0xFF,
363 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
364 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
365 };
366
367 static void disable_interrupt(EEPRO100State * s)
368 {
369 if (s->int_stat) {
370 TRACE(INT, logout("interrupt disabled\n"));
371 qemu_irq_lower(s->dev.irq[0]);
372 s->int_stat = 0;
373 }
374 }
375
376 static void enable_interrupt(EEPRO100State * s)
377 {
378 if (!s->int_stat) {
379 TRACE(INT, logout("interrupt enabled\n"));
380 qemu_irq_raise(s->dev.irq[0]);
381 s->int_stat = 1;
382 }
383 }
384
385 static void eepro100_acknowledge(EEPRO100State * s)
386 {
387 s->scb_stat &= ~s->mem[SCBAck];
388 s->mem[SCBAck] = s->scb_stat;
389 if (s->scb_stat == 0) {
390 disable_interrupt(s);
391 }
392 }
393
394 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
395 {
396 uint8_t mask = ~s->mem[SCBIntmask];
397 s->mem[SCBAck] |= status;
398 status = s->scb_stat = s->mem[SCBAck];
399 status &= (mask | 0x0f);
400 #if 0
401 status &= (~s->mem[SCBIntmask] | 0x0xf);
402 #endif
403 if (status && (mask & 0x01)) {
404 /* SCB mask and SCB Bit M do not disable interrupt. */
405 enable_interrupt(s);
406 } else if (s->int_stat) {
407 disable_interrupt(s);
408 }
409 }
410
411 static void eepro100_cx_interrupt(EEPRO100State * s)
412 {
413 /* CU completed action command. */
414 /* Transmit not ok (82557 only, not in emulation). */
415 eepro100_interrupt(s, 0x80);
416 }
417
418 static void eepro100_cna_interrupt(EEPRO100State * s)
419 {
420 /* CU left the active state. */
421 eepro100_interrupt(s, 0x20);
422 }
423
424 static void eepro100_fr_interrupt(EEPRO100State * s)
425 {
426 /* RU received a complete frame. */
427 eepro100_interrupt(s, 0x40);
428 }
429
430 static void eepro100_rnr_interrupt(EEPRO100State * s)
431 {
432 /* RU is not ready. */
433 eepro100_interrupt(s, 0x10);
434 }
435
436 static void eepro100_mdi_interrupt(EEPRO100State * s)
437 {
438 /* MDI completed read or write cycle. */
439 eepro100_interrupt(s, 0x08);
440 }
441
442 static void eepro100_swi_interrupt(EEPRO100State * s)
443 {
444 /* Software has requested an interrupt. */
445 eepro100_interrupt(s, 0x04);
446 }
447
448 #if 0
449 static void eepro100_fcp_interrupt(EEPRO100State * s)
450 {
451 /* Flow control pause interrupt (82558 and later). */
452 eepro100_interrupt(s, 0x01);
453 }
454 #endif
455
456 static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device)
457 {
458 uint32_t device = s->device;
459 uint8_t *pci_conf = s->dev.config;
460
461 TRACE(OTHER, logout("%p\n", s));
462
463 /* PCI Vendor ID */
464 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
465 /* PCI Device ID */
466 pci_config_set_device_id(pci_conf, e100_device->device_id);
467 /* PCI Status */
468 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
469 PCI_STATUS_FAST_BACK);
470 /* PCI Revision ID */
471 pci_config_set_revision(pci_conf, e100_device->revision);
472 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
473 /* PCI Latency Timer */
474 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
475 /* Capability Pointer is set by PCI framework. */
476 /* Interrupt Line */
477 /* Interrupt Pin */
478 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
479 /* Minimum Grant */
480 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
481 /* Maximum Latency */
482 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
483
484 s->stats_size = e100_device->stats_size;
485 s->has_extended_tcb_support = e100_device->has_extended_tcb_support;
486
487 switch (device) {
488 case i82550:
489 case i82551:
490 case i82557A:
491 case i82557B:
492 case i82557C:
493 case i82558A:
494 case i82558B:
495 case i82559A:
496 case i82559B:
497 case i82559ER:
498 case i82562:
499 case i82801:
500 break;
501 case i82559C:
502 #if EEPROM_SIZE > 0
503 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_INTEL);
504 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
505 #endif
506 break;
507 default:
508 logout("Device %X is undefined!\n", device);
509 }
510
511 /* Standard TxCB. */
512 s->configuration[6] |= BIT(4);
513
514 /* Standard statistical counters. */
515 s->configuration[6] |= BIT(5);
516
517 if (s->stats_size == 80) {
518 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
519 if (s->configuration[6] & BIT(2)) {
520 /* TCO statistical counters. */
521 assert(s->configuration[6] & BIT(5));
522 } else {
523 if (s->configuration[6] & BIT(5)) {
524 /* No extended statistical counters, i82557 compatible. */
525 s->stats_size = 64;
526 } else {
527 /* i82558 compatible. */
528 s->stats_size = 76;
529 }
530 }
531 } else {
532 if (s->configuration[6] & BIT(5)) {
533 /* No extended statistical counters. */
534 s->stats_size = 64;
535 }
536 }
537 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
538
539 if (e100_device->power_management) {
540 /* Power Management Capabilities */
541 int cfg_offset = 0xdc;
542 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
543 cfg_offset, PCI_PM_SIZEOF);
544 assert(r >= 0);
545 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
546 #if 0 /* TODO: replace dummy code for power management emulation. */
547 /* TODO: Power Management Control / Status. */
548 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
549 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
550 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
551 #endif
552 }
553
554 #if EEPROM_SIZE > 0
555 if (device == i82557C || device == i82558B || device == i82559C) {
556 /*
557 TODO: get vendor id from EEPROM for i82557C or later.
558 TODO: get device id from EEPROM for i82557C or later.
559 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
560 TODO: header type is determined by EEPROM for i82559.
561 TODO: get subsystem id from EEPROM for i82557C or later.
562 TODO: get subsystem vendor id from EEPROM for i82557C or later.
563 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
564 TODO: capability pointer depends on EEPROM for i82558.
565 */
566 logout("Get device id and revision from EEPROM!!!\n");
567 }
568 #endif /* EEPROM_SIZE > 0 */
569 }
570
571 static void nic_selective_reset(EEPRO100State * s)
572 {
573 size_t i;
574 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
575 #if 0
576 eeprom93xx_reset(s->eeprom);
577 #endif
578 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
579 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
580 if (s->device == i82557B || s->device == i82557C)
581 eeprom_contents[5] = 0x0100;
582 eeprom_contents[EEPROM_PHY_ID] = 1;
583 uint16_t sum = 0;
584 for (i = 0; i < EEPROM_SIZE - 1; i++) {
585 sum += eeprom_contents[i];
586 }
587 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
588 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
589
590 memset(s->mem, 0, sizeof(s->mem));
591 uint32_t val = BIT(21);
592 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
593
594 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
595 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
596 }
597
598 static void nic_reset(void *opaque)
599 {
600 EEPRO100State *s = opaque;
601 TRACE(OTHER, logout("%p\n", s));
602 /* TODO: Clearing of multicast table for selective reset, too? */
603 memset(&s->mult[0], 0, sizeof(s->mult));
604 nic_selective_reset(s);
605 }
606
607 #if defined(DEBUG_EEPRO100)
608 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
609 "Command/Status",
610 "General Pointer",
611 "Port",
612 "EEPROM/Flash Control",
613 "MDI Control",
614 "Receive DMA Byte Count",
615 "Flow Control",
616 "General Status/Control"
617 };
618
619 static char *regname(uint32_t addr)
620 {
621 static char buf[32];
622 if (addr < PCI_IO_SIZE) {
623 const char *r = e100_reg[addr / 4];
624 if (r != 0) {
625 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
626 } else {
627 snprintf(buf, sizeof(buf), "0x%02x", addr);
628 }
629 } else {
630 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
631 }
632 return buf;
633 }
634 #endif /* DEBUG_EEPRO100 */
635
636 /*****************************************************************************
637 *
638 * Command emulation.
639 *
640 ****************************************************************************/
641
642 #if 0
643 static uint16_t eepro100_read_command(EEPRO100State * s)
644 {
645 uint16_t val = 0xffff;
646 TRACE(OTHER, logout("val=0x%04x\n", val));
647 return val;
648 }
649 #endif
650
651 /* Commands that can be put in a command list entry. */
652 enum commands {
653 CmdNOp = 0,
654 CmdIASetup = 1,
655 CmdConfigure = 2,
656 CmdMulticastList = 3,
657 CmdTx = 4,
658 CmdTDR = 5, /* load microcode */
659 CmdDump = 6,
660 CmdDiagnose = 7,
661
662 /* And some extra flags: */
663 CmdSuspend = 0x4000, /* Suspend after completion. */
664 CmdIntr = 0x2000, /* Interrupt after completion. */
665 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
666 };
667
668 static cu_state_t get_cu_state(EEPRO100State * s)
669 {
670 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
671 }
672
673 static void set_cu_state(EEPRO100State * s, cu_state_t state)
674 {
675 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
676 }
677
678 static ru_state_t get_ru_state(EEPRO100State * s)
679 {
680 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
681 }
682
683 static void set_ru_state(EEPRO100State * s, ru_state_t state)
684 {
685 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
686 }
687
688 static void dump_statistics(EEPRO100State * s)
689 {
690 /* Dump statistical data. Most data is never changed by the emulation
691 * and always 0, so we first just copy the whole block and then those
692 * values which really matter.
693 * Number of data should check configuration!!!
694 */
695 cpu_physical_memory_write(s->statsaddr,
696 (uint8_t *) & s->statistics, s->stats_size);
697 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
698 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
699 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
700 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
701 #if 0
702 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
703 stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
704 missing("CU dump statistical counters");
705 #endif
706 }
707
708 static void read_cb(EEPRO100State *s)
709 {
710 cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
711 s->tx.status = le16_to_cpu(s->tx.status);
712 s->tx.command = le16_to_cpu(s->tx.command);
713 s->tx.link = le32_to_cpu(s->tx.link);
714 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
715 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
716 }
717
718 static void tx_command(EEPRO100State *s)
719 {
720 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
721 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
722 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
723 uint8_t buf[2600];
724 uint16_t size = 0;
725 uint32_t tbd_address = s->cb_address + 0x10;
726 TRACE(RXTX, logout
727 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
728 tbd_array, tcb_bytes, s->tx.tbd_count));
729
730 if (tcb_bytes > 2600) {
731 logout("TCB byte count too large, using 2600\n");
732 tcb_bytes = 2600;
733 }
734 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
735 logout
736 ("illegal values of TBD array address and TCB byte count!\n");
737 }
738 assert(tcb_bytes <= sizeof(buf));
739 while (size < tcb_bytes) {
740 uint32_t tx_buffer_address = ldl_phys(tbd_address);
741 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
742 #if 0
743 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
744 #endif
745 tbd_address += 8;
746 TRACE(RXTX, logout
747 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
748 tx_buffer_address, tx_buffer_size));
749 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
750 cpu_physical_memory_read(tx_buffer_address, &buf[size],
751 tx_buffer_size);
752 size += tx_buffer_size;
753 }
754 if (tbd_array == 0xffffffff) {
755 /* Simplified mode. Was already handled by code above. */
756 } else {
757 /* Flexible mode. */
758 uint8_t tbd_count = 0;
759 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
760 /* Extended Flexible TCB. */
761 for (; tbd_count < 2; tbd_count++) {
762 uint32_t tx_buffer_address = ldl_phys(tbd_address);
763 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
764 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
765 tbd_address += 8;
766 TRACE(RXTX, logout
767 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
768 tx_buffer_address, tx_buffer_size));
769 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
770 cpu_physical_memory_read(tx_buffer_address, &buf[size],
771 tx_buffer_size);
772 size += tx_buffer_size;
773 if (tx_buffer_el & 1) {
774 break;
775 }
776 }
777 }
778 tbd_address = tbd_array;
779 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
780 uint32_t tx_buffer_address = ldl_phys(tbd_address);
781 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
782 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
783 tbd_address += 8;
784 TRACE(RXTX, logout
785 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
786 tx_buffer_address, tx_buffer_size));
787 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
788 cpu_physical_memory_read(tx_buffer_address, &buf[size],
789 tx_buffer_size);
790 size += tx_buffer_size;
791 if (tx_buffer_el & 1) {
792 break;
793 }
794 }
795 }
796 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
797 qemu_send_packet(&s->nic->nc, buf, size);
798 s->statistics.tx_good_frames++;
799 /* Transmit with bad status would raise an CX/TNO interrupt.
800 * (82557 only). Emulation never has bad status. */
801 #if 0
802 eepro100_cx_interrupt(s);
803 #endif
804 }
805
806 static void set_multicast_list(EEPRO100State *s)
807 {
808 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
809 uint16_t i;
810 memset(&s->mult[0], 0, sizeof(s->mult));
811 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
812 for (i = 0; i < multicast_count; i += 6) {
813 uint8_t multicast_addr[6];
814 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
815 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
816 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
817 assert(mcast_idx < 64);
818 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
819 }
820 }
821
822 static void action_command(EEPRO100State *s)
823 {
824 for (;;) {
825 bool bit_el;
826 bool bit_s;
827 bool bit_i;
828 bool bit_nc;
829 uint16_t ok_status = STATUS_OK;
830 s->cb_address = s->cu_base + s->cu_offset;
831 read_cb(s);
832 bit_el = ((s->tx.command & COMMAND_EL) != 0);
833 bit_s = ((s->tx.command & COMMAND_S) != 0);
834 bit_i = ((s->tx.command & COMMAND_I) != 0);
835 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
836 #if 0
837 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
838 #endif
839 s->cu_offset = s->tx.link;
840 TRACE(OTHER,
841 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
842 s->tx.status, s->tx.command, s->tx.link));
843 switch (s->tx.command & COMMAND_CMD) {
844 case CmdNOp:
845 /* Do nothing. */
846 break;
847 case CmdIASetup:
848 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
849 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
850 break;
851 case CmdConfigure:
852 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
853 sizeof(s->configuration));
854 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
855 break;
856 case CmdMulticastList:
857 set_multicast_list(s);
858 break;
859 case CmdTx:
860 if (bit_nc) {
861 missing("CmdTx: NC = 0");
862 ok_status = 0;
863 break;
864 }
865 tx_command(s);
866 break;
867 case CmdTDR:
868 TRACE(OTHER, logout("load microcode\n"));
869 /* Starting with offset 8, the command contains
870 * 64 dwords microcode which we just ignore here. */
871 break;
872 case CmdDiagnose:
873 TRACE(OTHER, logout("diagnose\n"));
874 /* Make sure error flag is not set. */
875 s->tx.status = 0;
876 break;
877 default:
878 missing("undefined command");
879 ok_status = 0;
880 break;
881 }
882 /* Write new status. */
883 stw_phys(s->cb_address, s->tx.status | ok_status | STATUS_C);
884 if (bit_i) {
885 /* CU completed action. */
886 eepro100_cx_interrupt(s);
887 }
888 if (bit_el) {
889 /* CU becomes idle. Terminate command loop. */
890 set_cu_state(s, cu_idle);
891 eepro100_cna_interrupt(s);
892 break;
893 } else if (bit_s) {
894 /* CU becomes suspended. Terminate command loop. */
895 set_cu_state(s, cu_suspended);
896 eepro100_cna_interrupt(s);
897 break;
898 } else {
899 /* More entries in list. */
900 TRACE(OTHER, logout("CU list with at least one more entry\n"));
901 }
902 }
903 TRACE(OTHER, logout("CU list empty\n"));
904 /* List is empty. Now CU is idle or suspended. */
905 }
906
907 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
908 {
909 cu_state_t cu_state;
910 switch (val) {
911 case CU_NOP:
912 /* No operation. */
913 break;
914 case CU_START:
915 cu_state = get_cu_state(s);
916 if (cu_state != cu_idle && cu_state != cu_suspended) {
917 /* Intel documentation says that CU must be idle or suspended
918 * for the CU start command. */
919 logout("unexpected CU state is %u\n", cu_state);
920 }
921 set_cu_state(s, cu_active);
922 s->cu_offset = s->pointer;
923 action_command(s);
924 break;
925 case CU_RESUME:
926 if (get_cu_state(s) != cu_suspended) {
927 logout("bad CU resume from CU state %u\n", get_cu_state(s));
928 /* Workaround for bad Linux eepro100 driver which resumes
929 * from idle state. */
930 #if 0
931 missing("cu resume");
932 #endif
933 set_cu_state(s, cu_suspended);
934 }
935 if (get_cu_state(s) == cu_suspended) {
936 TRACE(OTHER, logout("CU resuming\n"));
937 set_cu_state(s, cu_active);
938 action_command(s);
939 }
940 break;
941 case CU_STATSADDR:
942 /* Load dump counters address. */
943 s->statsaddr = s->pointer;
944 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
945 break;
946 case CU_SHOWSTATS:
947 /* Dump statistical counters. */
948 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
949 dump_statistics(s);
950 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
951 break;
952 case CU_CMD_BASE:
953 /* Load CU base. */
954 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
955 s->cu_base = s->pointer;
956 break;
957 case CU_DUMPSTATS:
958 /* Dump and reset statistical counters. */
959 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
960 dump_statistics(s);
961 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
962 memset(&s->statistics, 0, sizeof(s->statistics));
963 break;
964 case CU_SRESUME:
965 /* CU static resume. */
966 missing("CU static resume");
967 break;
968 default:
969 missing("Undefined CU command");
970 }
971 }
972
973 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
974 {
975 switch (val) {
976 case RU_NOP:
977 /* No operation. */
978 break;
979 case RX_START:
980 /* RU start. */
981 if (get_ru_state(s) != ru_idle) {
982 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
983 #if 0
984 assert(!"wrong RU state");
985 #endif
986 }
987 set_ru_state(s, ru_ready);
988 s->ru_offset = s->pointer;
989 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
990 break;
991 case RX_RESUME:
992 /* Restart RU. */
993 if (get_ru_state(s) != ru_suspended) {
994 logout("RU state is %u, should be %u\n", get_ru_state(s),
995 ru_suspended);
996 #if 0
997 assert(!"wrong RU state");
998 #endif
999 }
1000 set_ru_state(s, ru_ready);
1001 break;
1002 case RU_ABORT:
1003 /* RU abort. */
1004 if (get_ru_state(s) == ru_ready) {
1005 eepro100_rnr_interrupt(s);
1006 }
1007 set_ru_state(s, ru_idle);
1008 break;
1009 case RX_ADDR_LOAD:
1010 /* Load RU base. */
1011 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1012 s->ru_base = s->pointer;
1013 break;
1014 default:
1015 logout("val=0x%02x (undefined RU command)\n", val);
1016 missing("Undefined SU command");
1017 }
1018 }
1019
1020 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1021 {
1022 eepro100_ru_command(s, val & 0x0f);
1023 eepro100_cu_command(s, val & 0xf0);
1024 if ((val) == 0) {
1025 TRACE(OTHER, logout("val=0x%02x\n", val));
1026 }
1027 /* Clear command byte after command was accepted. */
1028 s->mem[SCBCmd] = 0;
1029 }
1030
1031 /*****************************************************************************
1032 *
1033 * EEPROM emulation.
1034 *
1035 ****************************************************************************/
1036
1037 #define EEPROM_CS 0x02
1038 #define EEPROM_SK 0x01
1039 #define EEPROM_DI 0x04
1040 #define EEPROM_DO 0x08
1041
1042 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1043 {
1044 uint16_t val;
1045 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1046 if (eeprom93xx_read(s->eeprom)) {
1047 val |= EEPROM_DO;
1048 } else {
1049 val &= ~EEPROM_DO;
1050 }
1051 TRACE(EEPROM, logout("val=0x%04x\n", val));
1052 return val;
1053 }
1054
1055 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1056 {
1057 TRACE(EEPROM, logout("val=0x%02x\n", val));
1058
1059 /* mask unwriteable bits */
1060 #if 0
1061 val = SET_MASKED(val, 0x31, eeprom->value);
1062 #endif
1063
1064 int eecs = ((val & EEPROM_CS) != 0);
1065 int eesk = ((val & EEPROM_SK) != 0);
1066 int eedi = ((val & EEPROM_DI) != 0);
1067 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1068 }
1069
1070 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1071 {
1072 s->pointer = le32_to_cpu(val);
1073 TRACE(OTHER, logout("val=0x%08x\n", val));
1074 }
1075
1076 /*****************************************************************************
1077 *
1078 * MDI emulation.
1079 *
1080 ****************************************************************************/
1081
1082 #if defined(DEBUG_EEPRO100)
1083 static const char * const mdi_op_name[] = {
1084 "opcode 0",
1085 "write",
1086 "read",
1087 "opcode 3"
1088 };
1089
1090 static const char * const mdi_reg_name[] = {
1091 "Control",
1092 "Status",
1093 "PHY Identification (Word 1)",
1094 "PHY Identification (Word 2)",
1095 "Auto-Negotiation Advertisement",
1096 "Auto-Negotiation Link Partner Ability",
1097 "Auto-Negotiation Expansion"
1098 };
1099
1100 static const char *reg2name(uint8_t reg)
1101 {
1102 static char buffer[10];
1103 const char *p = buffer;
1104 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1105 p = mdi_reg_name[reg];
1106 } else {
1107 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1108 }
1109 return p;
1110 }
1111 #endif /* DEBUG_EEPRO100 */
1112
1113 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1114 {
1115 uint32_t val;
1116 memcpy(&val, &s->mem[0x10], sizeof(val));
1117
1118 #ifdef DEBUG_EEPRO100
1119 uint8_t raiseint = (val & BIT(29)) >> 29;
1120 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1121 uint8_t phy = (val & BITS(25, 21)) >> 21;
1122 uint8_t reg = (val & BITS(20, 16)) >> 16;
1123 uint16_t data = (val & BITS(15, 0));
1124 #endif
1125 /* Emulation takes no time to finish MDI transaction. */
1126 val |= BIT(28);
1127 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1128 val, raiseint, mdi_op_name[opcode], phy,
1129 reg2name(reg), data));
1130 return val;
1131 }
1132
1133 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1134 {
1135 uint8_t raiseint = (val & BIT(29)) >> 29;
1136 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1137 uint8_t phy = (val & BITS(25, 21)) >> 21;
1138 uint8_t reg = (val & BITS(20, 16)) >> 16;
1139 uint16_t data = (val & BITS(15, 0));
1140 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1141 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1142 if (phy != 1) {
1143 /* Unsupported PHY address. */
1144 #if 0
1145 logout("phy must be 1 but is %u\n", phy);
1146 #endif
1147 data = 0;
1148 } else if (opcode != 1 && opcode != 2) {
1149 /* Unsupported opcode. */
1150 logout("opcode must be 1 or 2 but is %u\n", opcode);
1151 data = 0;
1152 } else if (reg > 6) {
1153 /* Unsupported register. */
1154 logout("register must be 0...6 but is %u\n", reg);
1155 data = 0;
1156 } else {
1157 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1158 val, raiseint, mdi_op_name[opcode], phy,
1159 reg2name(reg), data));
1160 if (opcode == 1) {
1161 /* MDI write */
1162 switch (reg) {
1163 case 0: /* Control Register */
1164 if (data & 0x8000) {
1165 /* Reset status and control registers to default. */
1166 s->mdimem[0] = eepro100_mdi_default[0];
1167 s->mdimem[1] = eepro100_mdi_default[1];
1168 data = s->mdimem[reg];
1169 } else {
1170 /* Restart Auto Configuration = Normal Operation */
1171 data &= ~0x0200;
1172 }
1173 break;
1174 case 1: /* Status Register */
1175 missing("not writable");
1176 data = s->mdimem[reg];
1177 break;
1178 case 2: /* PHY Identification Register (Word 1) */
1179 case 3: /* PHY Identification Register (Word 2) */
1180 missing("not implemented");
1181 break;
1182 case 4: /* Auto-Negotiation Advertisement Register */
1183 case 5: /* Auto-Negotiation Link Partner Ability Register */
1184 break;
1185 case 6: /* Auto-Negotiation Expansion Register */
1186 default:
1187 missing("not implemented");
1188 }
1189 s->mdimem[reg] = data;
1190 } else if (opcode == 2) {
1191 /* MDI read */
1192 switch (reg) {
1193 case 0: /* Control Register */
1194 if (data & 0x8000) {
1195 /* Reset status and control registers to default. */
1196 s->mdimem[0] = eepro100_mdi_default[0];
1197 s->mdimem[1] = eepro100_mdi_default[1];
1198 }
1199 break;
1200 case 1: /* Status Register */
1201 s->mdimem[reg] |= 0x0020;
1202 break;
1203 case 2: /* PHY Identification Register (Word 1) */
1204 case 3: /* PHY Identification Register (Word 2) */
1205 case 4: /* Auto-Negotiation Advertisement Register */
1206 break;
1207 case 5: /* Auto-Negotiation Link Partner Ability Register */
1208 s->mdimem[reg] = 0x41fe;
1209 break;
1210 case 6: /* Auto-Negotiation Expansion Register */
1211 s->mdimem[reg] = 0x0001;
1212 break;
1213 }
1214 data = s->mdimem[reg];
1215 }
1216 /* Emulation takes no time to finish MDI transaction.
1217 * Set MDI bit in SCB status register. */
1218 s->mem[SCBAck] |= 0x08;
1219 val |= BIT(28);
1220 if (raiseint) {
1221 eepro100_mdi_interrupt(s);
1222 }
1223 }
1224 val = (val & 0xffff0000) + data;
1225 memcpy(&s->mem[0x10], &val, sizeof(val));
1226 }
1227
1228 /*****************************************************************************
1229 *
1230 * Port emulation.
1231 *
1232 ****************************************************************************/
1233
1234 #define PORT_SOFTWARE_RESET 0
1235 #define PORT_SELFTEST 1
1236 #define PORT_SELECTIVE_RESET 2
1237 #define PORT_DUMP 3
1238 #define PORT_SELECTION_MASK 3
1239
1240 typedef struct {
1241 uint32_t st_sign; /* Self Test Signature */
1242 uint32_t st_result; /* Self Test Results */
1243 } eepro100_selftest_t;
1244
1245 static uint32_t eepro100_read_port(EEPRO100State * s)
1246 {
1247 return 0;
1248 }
1249
1250 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1251 {
1252 val = le32_to_cpu(val);
1253 uint32_t address = (val & ~PORT_SELECTION_MASK);
1254 uint8_t selection = (val & PORT_SELECTION_MASK);
1255 switch (selection) {
1256 case PORT_SOFTWARE_RESET:
1257 nic_reset(s);
1258 break;
1259 case PORT_SELFTEST:
1260 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1261 eepro100_selftest_t data;
1262 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1263 data.st_sign = 0xffffffff;
1264 data.st_result = 0;
1265 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1266 break;
1267 case PORT_SELECTIVE_RESET:
1268 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1269 nic_selective_reset(s);
1270 break;
1271 default:
1272 logout("val=0x%08x\n", val);
1273 missing("unknown port selection");
1274 }
1275 }
1276
1277 /*****************************************************************************
1278 *
1279 * General hardware emulation.
1280 *
1281 ****************************************************************************/
1282
1283 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1284 {
1285 uint8_t val;
1286 if (addr <= sizeof(s->mem) - sizeof(val)) {
1287 memcpy(&val, &s->mem[addr], sizeof(val));
1288 }
1289
1290 switch (addr) {
1291 case SCBStatus:
1292 case SCBAck:
1293 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1294 break;
1295 case SCBCmd:
1296 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1297 #if 0
1298 val = eepro100_read_command(s);
1299 #endif
1300 break;
1301 case SCBIntmask:
1302 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1303 break;
1304 case SCBPort + 3:
1305 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1306 break;
1307 case SCBeeprom:
1308 val = eepro100_read_eeprom(s);
1309 break;
1310 case SCBpmdr: /* Power Management Driver Register */
1311 val = 0;
1312 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1313 break;
1314 case SCBgstat: /* General Status Register */
1315 /* 100 Mbps full duplex, valid link */
1316 val = 0x07;
1317 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1318 break;
1319 default:
1320 logout("addr=%s val=0x%02x\n", regname(addr), val);
1321 missing("unknown byte read");
1322 }
1323 return val;
1324 }
1325
1326 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1327 {
1328 uint16_t val;
1329 if (addr <= sizeof(s->mem) - sizeof(val)) {
1330 memcpy(&val, &s->mem[addr], sizeof(val));
1331 }
1332
1333 switch (addr) {
1334 case SCBStatus:
1335 case SCBCmd:
1336 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1337 break;
1338 case SCBeeprom:
1339 val = eepro100_read_eeprom(s);
1340 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1341 break;
1342 default:
1343 logout("addr=%s val=0x%04x\n", regname(addr), val);
1344 missing("unknown word read");
1345 }
1346 return val;
1347 }
1348
1349 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1350 {
1351 uint32_t val;
1352 if (addr <= sizeof(s->mem) - sizeof(val)) {
1353 memcpy(&val, &s->mem[addr], sizeof(val));
1354 }
1355
1356 switch (addr) {
1357 case SCBStatus:
1358 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1359 break;
1360 case SCBPointer:
1361 #if 0
1362 val = eepro100_read_pointer(s);
1363 #endif
1364 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1365 break;
1366 case SCBPort:
1367 val = eepro100_read_port(s);
1368 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1369 break;
1370 case SCBCtrlMDI:
1371 val = eepro100_read_mdi(s);
1372 break;
1373 default:
1374 logout("addr=%s val=0x%08x\n", regname(addr), val);
1375 missing("unknown longword read");
1376 }
1377 return val;
1378 }
1379
1380 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1381 {
1382 /* SCBStatus is readonly. */
1383 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1384 memcpy(&s->mem[addr], &val, sizeof(val));
1385 }
1386
1387 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1388
1389 switch (addr) {
1390 case SCBStatus:
1391 break;
1392 case SCBAck:
1393 eepro100_acknowledge(s);
1394 break;
1395 case SCBCmd:
1396 eepro100_write_command(s, val);
1397 break;
1398 case SCBIntmask:
1399 if (val & BIT(1)) {
1400 eepro100_swi_interrupt(s);
1401 }
1402 eepro100_interrupt(s, 0);
1403 break;
1404 case SCBPort + 3:
1405 case SCBFlow: /* does not exist on 82557 */
1406 case SCBFlow + 1:
1407 case SCBFlow + 2:
1408 case SCBpmdr: /* does not exist on 82557 */
1409 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1410 break;
1411 case SCBeeprom:
1412 eepro100_write_eeprom(s->eeprom, val);
1413 break;
1414 default:
1415 logout("addr=%s val=0x%02x\n", regname(addr), val);
1416 missing("unknown byte write");
1417 }
1418 }
1419
1420 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1421 {
1422 /* SCBStatus is readonly. */
1423 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1424 memcpy(&s->mem[addr], &val, sizeof(val));
1425 }
1426
1427 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1428
1429 switch (addr) {
1430 case SCBStatus:
1431 s->mem[SCBAck] = (val >> 8);
1432 eepro100_acknowledge(s);
1433 break;
1434 case SCBCmd:
1435 eepro100_write_command(s, val);
1436 eepro100_write1(s, SCBIntmask, val >> 8);
1437 break;
1438 case SCBeeprom:
1439 eepro100_write_eeprom(s->eeprom, val);
1440 break;
1441 default:
1442 logout("addr=%s val=0x%04x\n", regname(addr), val);
1443 missing("unknown word write");
1444 }
1445 }
1446
1447 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1448 {
1449 if (addr <= sizeof(s->mem) - sizeof(val)) {
1450 memcpy(&s->mem[addr], &val, sizeof(val));
1451 }
1452
1453 switch (addr) {
1454 case SCBPointer:
1455 eepro100_write_pointer(s, val);
1456 break;
1457 case SCBPort:
1458 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1459 eepro100_write_port(s, val);
1460 break;
1461 case SCBCtrlMDI:
1462 eepro100_write_mdi(s, val);
1463 break;
1464 default:
1465 logout("addr=%s val=0x%08x\n", regname(addr), val);
1466 missing("unknown longword write");
1467 }
1468 }
1469
1470 /*****************************************************************************
1471 *
1472 * Port mapped I/O.
1473 *
1474 ****************************************************************************/
1475
1476 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1477 {
1478 EEPRO100State *s = opaque;
1479 #if 0
1480 logout("addr=%s\n", regname(addr));
1481 #endif
1482 return eepro100_read1(s, addr - s->region[1]);
1483 }
1484
1485 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1486 {
1487 EEPRO100State *s = opaque;
1488 return eepro100_read2(s, addr - s->region[1]);
1489 }
1490
1491 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1492 {
1493 EEPRO100State *s = opaque;
1494 return eepro100_read4(s, addr - s->region[1]);
1495 }
1496
1497 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1498 {
1499 EEPRO100State *s = opaque;
1500 #if 0
1501 logout("addr=%s val=0x%02x\n", regname(addr), val);
1502 #endif
1503 eepro100_write1(s, addr - s->region[1], val);
1504 }
1505
1506 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1507 {
1508 EEPRO100State *s = opaque;
1509 eepro100_write2(s, addr - s->region[1], val);
1510 }
1511
1512 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1513 {
1514 EEPRO100State *s = opaque;
1515 eepro100_write4(s, addr - s->region[1], val);
1516 }
1517
1518 /***********************************************************/
1519 /* PCI EEPRO100 definitions */
1520
1521 static void pci_map(PCIDevice * pci_dev, int region_num,
1522 pcibus_t addr, pcibus_t size, int type)
1523 {
1524 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1525
1526 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1527 "size=0x%08"FMT_PCIBUS", type=%d\n",
1528 region_num, addr, size, type));
1529
1530 assert(region_num == 1);
1531 register_ioport_write(addr, size, 1, ioport_write1, s);
1532 register_ioport_read(addr, size, 1, ioport_read1, s);
1533 register_ioport_write(addr, size, 2, ioport_write2, s);
1534 register_ioport_read(addr, size, 2, ioport_read2, s);
1535 register_ioport_write(addr, size, 4, ioport_write4, s);
1536 register_ioport_read(addr, size, 4, ioport_read4, s);
1537
1538 s->region[region_num] = addr;
1539 }
1540
1541 /*****************************************************************************
1542 *
1543 * Memory mapped I/O.
1544 *
1545 ****************************************************************************/
1546
1547 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1548 {
1549 EEPRO100State *s = opaque;
1550 #if 0
1551 logout("addr=%s val=0x%02x\n", regname(addr), val);
1552 #endif
1553 eepro100_write1(s, addr, val);
1554 }
1555
1556 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1557 {
1558 EEPRO100State *s = opaque;
1559 #if 0
1560 logout("addr=%s val=0x%02x\n", regname(addr), val);
1561 #endif
1562 eepro100_write2(s, addr, val);
1563 }
1564
1565 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1566 {
1567 EEPRO100State *s = opaque;
1568 #if 0
1569 logout("addr=%s val=0x%02x\n", regname(addr), val);
1570 #endif
1571 eepro100_write4(s, addr, val);
1572 }
1573
1574 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1575 {
1576 EEPRO100State *s = opaque;
1577 #if 0
1578 logout("addr=%s\n", regname(addr));
1579 #endif
1580 return eepro100_read1(s, addr);
1581 }
1582
1583 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1584 {
1585 EEPRO100State *s = opaque;
1586 #if 0
1587 logout("addr=%s\n", regname(addr));
1588 #endif
1589 return eepro100_read2(s, addr);
1590 }
1591
1592 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1593 {
1594 EEPRO100State *s = opaque;
1595 #if 0
1596 logout("addr=%s\n", regname(addr));
1597 #endif
1598 return eepro100_read4(s, addr);
1599 }
1600
1601 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1602 pci_mmio_writeb,
1603 pci_mmio_writew,
1604 pci_mmio_writel
1605 };
1606
1607 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1608 pci_mmio_readb,
1609 pci_mmio_readw,
1610 pci_mmio_readl
1611 };
1612
1613 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1614 pcibus_t addr, pcibus_t size, int type)
1615 {
1616 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1617
1618 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1619 "size=0x%08"FMT_PCIBUS", type=%d\n",
1620 region_num, addr, size, type));
1621
1622 assert(region_num == 0 || region_num == 2);
1623
1624 /* Map control / status registers and flash. */
1625 cpu_register_physical_memory(addr, size, s->mmio_index);
1626 s->region[region_num] = addr;
1627 }
1628
1629 static int nic_can_receive(VLANClientState *nc)
1630 {
1631 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1632 TRACE(RXTX, logout("%p\n", s));
1633 return get_ru_state(s) == ru_ready;
1634 #if 0
1635 return !eepro100_buffer_full(s);
1636 #endif
1637 }
1638
1639 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1640 {
1641 /* TODO:
1642 * - Magic packets should set bit 30 in power management driver register.
1643 * - Interesting packets should set bit 29 in power management driver register.
1644 */
1645 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1646 uint16_t rfd_status = 0xa000;
1647 static const uint8_t broadcast_macaddr[6] =
1648 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1649
1650 /* TODO: check multiple IA bit. */
1651 if (s->configuration[20] & BIT(6)) {
1652 missing("Multiple IA bit");
1653 return -1;
1654 }
1655
1656 if (s->configuration[8] & 0x80) {
1657 /* CSMA is disabled. */
1658 logout("%p received while CSMA is disabled\n", s);
1659 return -1;
1660 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1661 /* Short frame and configuration byte 7/0 (discard short receive) set:
1662 * Short frame is discarded */
1663 logout("%p received short frame (%zu byte)\n", s, size);
1664 s->statistics.rx_short_frame_errors++;
1665 #if 0
1666 return -1;
1667 #endif
1668 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1669 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1670 * Long frames are discarded. */
1671 logout("%p received long frame (%zu byte), ignored\n", s, size);
1672 return -1;
1673 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1674 /* Frame matches individual address. */
1675 /* TODO: check configuration byte 15/4 (ignore U/L). */
1676 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1677 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1678 /* Broadcast frame. */
1679 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1680 rfd_status |= 0x0002;
1681 } else if (buf[0] & 0x01) {
1682 /* Multicast frame. */
1683 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1684 if (s->configuration[21] & BIT(3)) {
1685 /* Multicast all bit is set, receive all multicast frames. */
1686 } else {
1687 unsigned mcast_idx = compute_mcast_idx(buf);
1688 assert(mcast_idx < 64);
1689 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1690 /* Multicast frame is allowed in hash table. */
1691 } else if (s->configuration[15] & BIT(0)) {
1692 /* Promiscuous: receive all. */
1693 rfd_status |= 0x0004;
1694 } else {
1695 TRACE(RXTX, logout("%p multicast ignored\n", s));
1696 return -1;
1697 }
1698 }
1699 /* TODO: Next not for promiscuous mode? */
1700 rfd_status |= 0x0002;
1701 } else if (s->configuration[15] & BIT(0)) {
1702 /* Promiscuous: receive all. */
1703 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1704 rfd_status |= 0x0004;
1705 } else {
1706 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1707 nic_dump(buf, size)));
1708 return size;
1709 }
1710
1711 if (get_ru_state(s) != ru_ready) {
1712 /* No resources available. */
1713 logout("no resources, state=%u\n", get_ru_state(s));
1714 /* TODO: RNR interrupt only at first failed frame? */
1715 eepro100_rnr_interrupt(s);
1716 s->statistics.rx_resource_errors++;
1717 #if 0
1718 assert(!"no resources");
1719 #endif
1720 return -1;
1721 }
1722 /* !!! */
1723 eepro100_rx_t rx;
1724 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1725 offsetof(eepro100_rx_t, packet));
1726 uint16_t rfd_command = le16_to_cpu(rx.command);
1727 uint16_t rfd_size = le16_to_cpu(rx.size);
1728
1729 if (size > rfd_size) {
1730 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1731 "(%zu bytes); data truncated\n", rfd_size, size);
1732 size = rfd_size;
1733 }
1734 if (size < 64) {
1735 rfd_status |= 0x0080;
1736 }
1737 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1738 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1739 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1740 rfd_status);
1741 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1742 /* Early receive interrupt not supported. */
1743 #if 0
1744 eepro100_er_interrupt(s);
1745 #endif
1746 /* Receive CRC Transfer not supported. */
1747 if (s->configuration[18] & BIT(2)) {
1748 missing("Receive CRC Transfer");
1749 return -1;
1750 }
1751 /* TODO: check stripping enable bit. */
1752 #if 0
1753 assert(!(s->configuration[17] & BIT(0)));
1754 #endif
1755 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1756 offsetof(eepro100_rx_t, packet), buf, size);
1757 s->statistics.rx_good_frames++;
1758 eepro100_fr_interrupt(s);
1759 s->ru_offset = le32_to_cpu(rx.link);
1760 if (rfd_command & COMMAND_EL) {
1761 /* EL bit is set, so this was the last frame. */
1762 logout("receive: Running out of frames\n");
1763 set_ru_state(s, ru_suspended);
1764 }
1765 if (rfd_command & COMMAND_S) {
1766 /* S bit is set. */
1767 set_ru_state(s, ru_suspended);
1768 }
1769 return size;
1770 }
1771
1772 static const VMStateDescription vmstate_eepro100 = {
1773 .version_id = 3,
1774 .minimum_version_id = 2,
1775 .minimum_version_id_old = 2,
1776 .fields = (VMStateField []) {
1777 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1778 VMSTATE_UNUSED(32),
1779 VMSTATE_BUFFER(mult, EEPRO100State),
1780 VMSTATE_BUFFER(mem, EEPRO100State),
1781 /* Save all members of struct between scb_stat and mem. */
1782 VMSTATE_UINT8(scb_stat, EEPRO100State),
1783 VMSTATE_UINT8(int_stat, EEPRO100State),
1784 VMSTATE_UNUSED(3*4),
1785 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1786 VMSTATE_UNUSED(19*4),
1787 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1788 /* The eeprom should be saved and restored by its own routines. */
1789 VMSTATE_UINT32(device, EEPRO100State),
1790 /* TODO check device. */
1791 VMSTATE_UINT32(pointer, EEPRO100State),
1792 VMSTATE_UINT32(cu_base, EEPRO100State),
1793 VMSTATE_UINT32(cu_offset, EEPRO100State),
1794 VMSTATE_UINT32(ru_base, EEPRO100State),
1795 VMSTATE_UINT32(ru_offset, EEPRO100State),
1796 VMSTATE_UINT32(statsaddr, EEPRO100State),
1797 /* Save eepro100_stats_t statistics. */
1798 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1799 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1800 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1801 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1802 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1803 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1804 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1805 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1806 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1807 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1808 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1809 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1810 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1811 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1812 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1813 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1814 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1815 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1816 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1817 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1818 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1819 /* Configuration bytes. */
1820 VMSTATE_BUFFER(configuration, EEPRO100State),
1821 VMSTATE_END_OF_LIST()
1822 }
1823 };
1824
1825 static void nic_cleanup(VLANClientState *nc)
1826 {
1827 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1828
1829 s->nic = NULL;
1830 }
1831
1832 static int pci_nic_uninit(PCIDevice *pci_dev)
1833 {
1834 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1835
1836 cpu_unregister_io_memory(s->mmio_index);
1837 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1838 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1839 qemu_del_vlan_client(&s->nic->nc);
1840 return 0;
1841 }
1842
1843 static NetClientInfo net_eepro100_info = {
1844 .type = NET_CLIENT_TYPE_NIC,
1845 .size = sizeof(NICState),
1846 .can_receive = nic_can_receive,
1847 .receive = nic_receive,
1848 .cleanup = nic_cleanup,
1849 };
1850
1851 static int e100_nic_init(PCIDevice *pci_dev)
1852 {
1853 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1854 E100PCIDeviceInfo *e100_device = DO_UPCAST(E100PCIDeviceInfo, pci.qdev,
1855 pci_dev->qdev.info);
1856
1857 TRACE(OTHER, logout("\n"));
1858
1859 s->device = e100_device->device;
1860
1861 e100_pci_reset(s, e100_device);
1862
1863 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1864 * i82559 and later support 64 or 256 word EEPROM. */
1865 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1866
1867 /* Handler for memory-mapped I/O */
1868 s->mmio_index =
1869 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1870
1871 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1872 PCI_BASE_ADDRESS_SPACE_MEMORY |
1873 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1874 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1875 pci_map);
1876 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1877 pci_mmio_map);
1878
1879 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1880 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1881 assert(s->region[1] == 0);
1882
1883 nic_reset(s);
1884
1885 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1886 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1887
1888 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1889 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1890
1891 qemu_register_reset(nic_reset, s);
1892
1893 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1894 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1895 s->vmstate->name = s->nic->nc.model;
1896 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1897
1898 return 0;
1899 }
1900
1901 static E100PCIDeviceInfo e100_devices[] = {
1902 {
1903 .pci.qdev.name = "i82550",
1904 .pci.qdev.desc = "Intel i82550 Ethernet",
1905 .device = i82550,
1906 /* TODO: check device id. */
1907 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1908 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1909 .revision = 0x0e,
1910 /* TODO: check size of statistical counters. */
1911 .stats_size = 80,
1912 /* TODO: check extended tcb support. */
1913 .has_extended_tcb_support = true,
1914 .power_management = true,
1915 },{
1916 .pci.qdev.name = "i82551",
1917 .pci.qdev.desc = "Intel i82551 Ethernet",
1918 .device = i82551,
1919 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1920 /* Revision ID: 0x0f, 0x10. */
1921 .revision = 0x0f,
1922 /* TODO: check size of statistical counters. */
1923 .stats_size = 80,
1924 .has_extended_tcb_support = true,
1925 .power_management = true,
1926 },{
1927 .pci.qdev.name = "i82557a",
1928 .pci.qdev.desc = "Intel i82557A Ethernet",
1929 .device = i82557A,
1930 .device_id = PCI_DEVICE_ID_INTEL_82557,
1931 .revision = 0x01,
1932 .power_management = false,
1933 },{
1934 .pci.qdev.name = "i82557b",
1935 .pci.qdev.desc = "Intel i82557B Ethernet",
1936 .device = i82557B,
1937 .device_id = PCI_DEVICE_ID_INTEL_82557,
1938 .revision = 0x02,
1939 .power_management = false,
1940 },{
1941 .pci.qdev.name = "i82557c",
1942 .pci.qdev.desc = "Intel i82557C Ethernet",
1943 .device = i82557C,
1944 .device_id = PCI_DEVICE_ID_INTEL_82557,
1945 .revision = 0x03,
1946 .power_management = false,
1947 },{
1948 .pci.qdev.name = "i82558a",
1949 .pci.qdev.desc = "Intel i82558A Ethernet",
1950 .device = i82558A,
1951 .device_id = PCI_DEVICE_ID_INTEL_82557,
1952 .revision = 0x04,
1953 .stats_size = 76,
1954 .has_extended_tcb_support = true,
1955 .power_management = true,
1956 },{
1957 .pci.qdev.name = "i82558b",
1958 .pci.qdev.desc = "Intel i82558B Ethernet",
1959 .device = i82558B,
1960 .device_id = PCI_DEVICE_ID_INTEL_82557,
1961 .revision = 0x05,
1962 .stats_size = 76,
1963 .has_extended_tcb_support = true,
1964 .power_management = true,
1965 },{
1966 .pci.qdev.name = "i82559a",
1967 .pci.qdev.desc = "Intel i82559A Ethernet",
1968 .device = i82559A,
1969 .device_id = PCI_DEVICE_ID_INTEL_82557,
1970 .revision = 0x06,
1971 .stats_size = 80,
1972 .has_extended_tcb_support = true,
1973 .power_management = true,
1974 },{
1975 .pci.qdev.name = "i82559b",
1976 .pci.qdev.desc = "Intel i82559B Ethernet",
1977 .device = i82559B,
1978 .device_id = PCI_DEVICE_ID_INTEL_82557,
1979 .revision = 0x07,
1980 .stats_size = 80,
1981 .has_extended_tcb_support = true,
1982 .power_management = true,
1983 },{
1984 .pci.qdev.name = "i82559c",
1985 .pci.qdev.desc = "Intel i82559C Ethernet",
1986 .device = i82559C,
1987 .device_id = PCI_DEVICE_ID_INTEL_82557,
1988 #if 0
1989 .revision = 0x08,
1990 #endif
1991 /* TODO: Windows wants revision id 0x0c. */
1992 .revision = 0x0c,
1993 .stats_size = 80,
1994 .has_extended_tcb_support = true,
1995 .power_management = true,
1996 },{
1997 .pci.qdev.name = "i82559er",
1998 .pci.qdev.desc = "Intel i82559ER Ethernet",
1999 .device = i82559ER,
2000 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2001 .revision = 0x09,
2002 .stats_size = 80,
2003 .has_extended_tcb_support = true,
2004 .power_management = true,
2005 },{
2006 .pci.qdev.name = "i82562",
2007 .pci.qdev.desc = "Intel i82562 Ethernet",
2008 .device = i82562,
2009 /* TODO: check device id. */
2010 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2011 /* TODO: wrong revision id. */
2012 .revision = 0x0e,
2013 .stats_size = 80,
2014 .has_extended_tcb_support = true,
2015 .power_management = true,
2016 },{
2017 /* Toshiba Tecra 8200. */
2018 .pci.qdev.name = "i82801",
2019 .pci.qdev.desc = "Intel i82801 Ethernet",
2020 .device = i82801,
2021 .device_id = 0x2449,
2022 .revision = 0x03,
2023 .stats_size = 80,
2024 .has_extended_tcb_support = true,
2025 .power_management = true,
2026 }
2027 };
2028
2029 static Property e100_properties[] = {
2030 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2031 DEFINE_PROP_END_OF_LIST(),
2032 };
2033
2034 static void eepro100_register_devices(void)
2035 {
2036 size_t i;
2037 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2038 PCIDeviceInfo *pci_dev = &e100_devices[i].pci;
2039 switch (e100_devices[i].device_id) {
2040 case PCI_DEVICE_ID_INTEL_82551IT:
2041 pci_dev->romfile = "gpxe-eepro100-80861209.rom";
2042 break;
2043 case PCI_DEVICE_ID_INTEL_82557:
2044 pci_dev->romfile = "gpxe-eepro100-80861229.rom";
2045 break;
2046 case 0x2449:
2047 pci_dev->romfile = "gpxe-eepro100-80862449.rom";
2048 break;
2049 }
2050 pci_dev->init = e100_nic_init;
2051 pci_dev->exit = pci_nic_uninit;
2052 pci_dev->qdev.props = e100_properties;
2053 pci_dev->qdev.size = sizeof(EEPRO100State);
2054 pci_qdev_register(pci_dev);
2055 }
2056 }
2057
2058 device_init(eepro100_register_devices)
QEmu