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target-tricore: Add instructions of SLR, SSRO and SRO opcode format
[qemu.git] / target-tricore / translate.c
blobe24479d2938cae06591498268fa3818c42c57cae
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "exec/cpu_ldst.h"
25
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28
29 #include "tricore-opcodes.h"
30
31 /*
32 * TCG registers
33 */
34 static TCGv cpu_PC;
35 static TCGv cpu_PCXI;
36 static TCGv cpu_PSW;
37 static TCGv cpu_ICR;
38 /* GPR registers */
39 static TCGv cpu_gpr_a[16];
40 static TCGv cpu_gpr_d[16];
41 /* PSW Flag cache */
42 static TCGv cpu_PSW_C;
43 static TCGv cpu_PSW_V;
44 static TCGv cpu_PSW_SV;
45 static TCGv cpu_PSW_AV;
46 static TCGv cpu_PSW_SAV;
47 /* CPU env */
48 static TCGv_ptr cpu_env;
49
50 #include "exec/gen-icount.h"
51
52 static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58 static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
64 typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73 } DisasContext;
74
75 enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81 };
82
83 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
84 fprintf_function cpu_fprintf, int flags)
85 {
86 TriCoreCPU *cpu = TRICORE_CPU(cs);
87 CPUTriCoreState *env = &cpu->env;
88 int i;
89
90 cpu_fprintf(f, "PC=%08x\n", env->PC);
91 for (i = 0; i < 16; ++i) {
92 if ((i & 3) == 0) {
93 cpu_fprintf(f, "GPR A%02d:", i);
94 }
95 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_a[i], env->gpr_a[i]);
96 }
97 for (i = 0; i < 16; ++i) {
98 if ((i & 3) == 0) {
99 cpu_fprintf(f, "GPR D%02d:", i);
100 }
101 cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames_d[i], env->gpr_d[i]);
102 }
103
104 }
105
106 /*
107 * Functions to generate micro-ops
108 */
109
110 /* Makros for generating helpers */
111
112 #define gen_helper_1arg(name, arg) do { \
113 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
114 gen_helper_##name(cpu_env, helper_tmp); \
115 tcg_temp_free_i32(helper_tmp); \
116 } while (0)
117
118 /* Functions for load/save to/from memory */
119
120 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
121 int16_t con, TCGMemOp mop)
122 {
123 TCGv temp = tcg_temp_new();
124 tcg_gen_addi_tl(temp, r2, con);
125 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
126 tcg_temp_free(temp);
127 }
128
129 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
130 int16_t con, TCGMemOp mop)
131 {
132 TCGv temp = tcg_temp_new();
133 tcg_gen_addi_tl(temp, r2, con);
134 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
135 tcg_temp_free(temp);
136 }
137
138 /* Functions for arithmetic instructions */
139
140 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
141 {
142 TCGv t0 = tcg_temp_new_i32();
143 TCGv result = tcg_temp_new_i32();
144 /* Addition and set V/SV bits */
145 tcg_gen_add_tl(result, r1, r2);
146 /* calc V bit */
147 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
148 tcg_gen_xor_tl(t0, r1, r2);
149 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
150 /* Calc SV bit */
151 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
152 /* Calc AV/SAV bits */
153 tcg_gen_add_tl(cpu_PSW_AV, result, result);
154 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
155 /* calc SAV */
156 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
157 /* write back result */
158 tcg_gen_mov_tl(ret, result);
159
160 tcg_temp_free(result);
161 tcg_temp_free(t0);
162 }
163
164 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
165 {
166 TCGv temp = tcg_const_i32(r2);
167 gen_add_d(ret, r1, temp);
168 tcg_temp_free(temp);
169 }
170
171 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
172 TCGv r4)
173 {
174 TCGv temp = tcg_temp_new();
175 TCGv temp2 = tcg_temp_new();
176 TCGv result = tcg_temp_new();
177 TCGv mask = tcg_temp_new();
178 TCGv t0 = tcg_const_i32(0);
179
180 /* create mask for sticky bits */
181 tcg_gen_setcond_tl(cond, mask, r4, t0);
182 tcg_gen_shli_tl(mask, mask, 31);
183
184 tcg_gen_add_tl(result, r1, r2);
185 /* Calc PSW_V */
186 tcg_gen_xor_tl(temp, result, r1);
187 tcg_gen_xor_tl(temp2, r1, r2);
188 tcg_gen_andc_tl(temp, temp, temp2);
189 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
190 /* Set PSW_SV */
191 tcg_gen_and_tl(temp, temp, mask);
192 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
193 /* calc AV bit */
194 tcg_gen_add_tl(temp, result, result);
195 tcg_gen_xor_tl(temp, temp, result);
196 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
197 /* calc SAV bit */
198 tcg_gen_and_tl(temp, temp, mask);
199 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
200 /* write back result */
201 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r3);
202
203 tcg_temp_free(t0);
204 tcg_temp_free(temp);
205 tcg_temp_free(temp2);
206 tcg_temp_free(result);
207 tcg_temp_free(mask);
208 }
209
210 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
211 TCGv r3, TCGv r4)
212 {
213 TCGv temp = tcg_const_i32(r2);
214 gen_cond_add(cond, r1, temp, r3, r4);
215 tcg_temp_free(temp);
216 }
217
218 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
219 {
220 TCGv temp = tcg_temp_new_i32();
221 TCGv result = tcg_temp_new_i32();
222
223 tcg_gen_sub_tl(result, r1, r2);
224 /* calc V bit */
225 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
226 tcg_gen_xor_tl(temp, r1, r2);
227 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
228 /* calc SV bit */
229 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
230 /* Calc AV bit */
231 tcg_gen_add_tl(cpu_PSW_AV, result, result);
232 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
233 /* calc SAV bit */
234 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
235 /* write back result */
236 tcg_gen_mov_tl(ret, result);
237
238 tcg_temp_free(temp);
239 tcg_temp_free(result);
240 }
241
242 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
243 {
244 TCGv high = tcg_temp_new();
245 TCGv low = tcg_temp_new();
246
247 tcg_gen_muls2_tl(low, high, r1, r2);
248 tcg_gen_mov_tl(ret, low);
249 /* calc V bit */
250 tcg_gen_sari_tl(low, low, 31);
251 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
252 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
253 /* calc SV bit */
254 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
255 /* Calc AV bit */
256 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
257 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
258 /* calc SAV bit */
259 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
260
261 tcg_temp_free(high);
262 tcg_temp_free(low);
263 }
264
265 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
266 {
267 if (shift_count == -32) {
268 tcg_gen_movi_tl(ret, 0);
269 } else if (shift_count >= 0) {
270 tcg_gen_shli_tl(ret, r1, shift_count);
271 } else {
272 tcg_gen_shri_tl(ret, r1, -shift_count);
273 }
274 }
275
276 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
277 {
278 uint32_t msk, msk_start;
279 TCGv temp = tcg_temp_new();
280 TCGv temp2 = tcg_temp_new();
281 TCGv t_0 = tcg_const_i32(0);
282
283 if (shift_count == 0) {
284 /* Clear PSW.C and PSW.V */
285 tcg_gen_movi_tl(cpu_PSW_C, 0);
286 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
287 tcg_gen_mov_tl(ret, r1);
288 } else if (shift_count == -32) {
289 /* set PSW.C */
290 tcg_gen_mov_tl(cpu_PSW_C, r1);
291 /* fill ret completly with sign bit */
292 tcg_gen_sari_tl(ret, r1, 31);
293 /* clear PSW.V */
294 tcg_gen_movi_tl(cpu_PSW_V, 0);
295 } else if (shift_count > 0) {
296 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
297 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
298
299 /* calc carry */
300 msk_start = 32 - shift_count;
301 msk = ((1 << shift_count) - 1) << msk_start;
302 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
303 /* calc v/sv bits */
304 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
305 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
306 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
307 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
308 /* calc sv */
309 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
310 /* do shift */
311 tcg_gen_shli_tl(ret, r1, shift_count);
312
313 tcg_temp_free(t_max);
314 tcg_temp_free(t_min);
315 } else {
316 /* clear PSW.V */
317 tcg_gen_movi_tl(cpu_PSW_V, 0);
318 /* calc carry */
319 msk = (1 << -shift_count) - 1;
320 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
321 /* do shift */
322 tcg_gen_sari_tl(ret, r1, -shift_count);
323 }
324 /* calc av overflow bit */
325 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
326 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
327 /* calc sav overflow bit */
328 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
329
330 tcg_temp_free(temp);
331 tcg_temp_free(temp2);
332 tcg_temp_free(t_0);
333 }
334
335 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
336 {
337 gen_helper_add_ssov(ret, cpu_env, r1, r2);
338 }
339
340 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
341 {
342 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
343 }
344
345 /* helpers for generating program flow micro-ops */
346
347 static inline void gen_save_pc(target_ulong pc)
348 {
349 tcg_gen_movi_tl(cpu_PC, pc);
350 }
351
352 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
353 {
354 TranslationBlock *tb;
355 tb = ctx->tb;
356 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
357 likely(!ctx->singlestep_enabled)) {
358 tcg_gen_goto_tb(n);
359 gen_save_pc(dest);
360 tcg_gen_exit_tb((uintptr_t)tb + n);
361 } else {
362 gen_save_pc(dest);
363 if (ctx->singlestep_enabled) {
364 /* raise exception debug */
365 }
366 tcg_gen_exit_tb(0);
367 }
368 }
369
370 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
371 TCGv r2, int16_t address)
372 {
373 int jumpLabel;
374 jumpLabel = gen_new_label();
375 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
376
377 gen_goto_tb(ctx, 1, ctx->next_pc);
378
379 gen_set_label(jumpLabel);
380 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
381 }
382
383 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
384 int r2, int16_t address)
385 {
386 TCGv temp = tcg_const_i32(r2);
387 gen_branch_cond(ctx, cond, r1, temp, address);
388 tcg_temp_free(temp);
389 }
390
391 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
392 {
393 int l1;
394 l1 = gen_new_label();
395
396 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
397 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
398 gen_goto_tb(ctx, 1, ctx->pc + offset);
399 gen_set_label(l1);
400 gen_goto_tb(ctx, 0, ctx->next_pc);
401 }
402
403 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
404 int r2 , int32_t constant , int32_t offset)
405 {
406 TCGv temp;
407
408 switch (opc) {
409 /* SB-format jumps */
410 case OPC1_16_SB_J:
411 case OPC1_32_B_J:
412 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
413 break;
414 case OPC1_16_SB_CALL:
415 gen_helper_1arg(call, ctx->next_pc);
416 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
417 break;
418 case OPC1_16_SB_JZ:
419 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
420 break;
421 case OPC1_16_SB_JNZ:
422 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
423 break;
424 /* SBC-format jumps */
425 case OPC1_16_SBC_JEQ:
426 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
427 break;
428 case OPC1_16_SBC_JNE:
429 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
430 break;
431 /* SBRN-format jumps */
432 case OPC1_16_SBRN_JZ_T:
433 temp = tcg_temp_new();
434 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
435 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
436 tcg_temp_free(temp);
437 break;
438 case OPC1_16_SBRN_JNZ_T:
439 temp = tcg_temp_new();
440 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
441 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
442 tcg_temp_free(temp);
443 break;
444 /* SBR-format jumps */
445 case OPC1_16_SBR_JEQ:
446 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
447 offset);
448 break;
449 case OPC1_16_SBR_JNE:
450 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
451 offset);
452 break;
453 case OPC1_16_SBR_JNZ:
454 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
455 break;
456 case OPC1_16_SBR_JNZ_A:
457 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
458 break;
459 case OPC1_16_SBR_JGEZ:
460 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
461 break;
462 case OPC1_16_SBR_JGTZ:
463 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
464 break;
465 case OPC1_16_SBR_JLEZ:
466 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
467 break;
468 case OPC1_16_SBR_JLTZ:
469 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
470 break;
471 case OPC1_16_SBR_JZ:
472 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
473 break;
474 case OPC1_16_SBR_JZ_A:
475 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
476 break;
477 case OPC1_16_SBR_LOOP:
478 gen_loop(ctx, r1, offset * 2 - 32);
479 break;
480 default:
481 printf("Branch Error at %x\n", ctx->pc);
482 }
483 ctx->bstate = BS_BRANCH;
484 }
485
486
487 /*
488 * Functions for decoding instructions
489 */
490
491 static void decode_src_opc(DisasContext *ctx, int op1)
492 {
493 int r1;
494 int32_t const4;
495 TCGv temp, temp2;
496
497 r1 = MASK_OP_SRC_S1D(ctx->opcode);
498 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
499
500 switch (op1) {
501 case OPC1_16_SRC_ADD:
502 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
503 break;
504 case OPC1_16_SRC_ADD_A15:
505 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
506 break;
507 case OPC1_16_SRC_ADD_15A:
508 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
509 break;
510 case OPC1_16_SRC_ADD_A:
511 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
512 break;
513 case OPC1_16_SRC_CADD:
514 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
515 cpu_gpr_d[15]);
516 break;
517 case OPC1_16_SRC_CADDN:
518 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
519 cpu_gpr_d[15]);
520 break;
521 case OPC1_16_SRC_CMOV:
522 temp = tcg_const_tl(0);
523 temp2 = tcg_const_tl(const4);
524 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
525 temp2, cpu_gpr_d[r1]);
526 tcg_temp_free(temp);
527 tcg_temp_free(temp2);
528 break;
529 case OPC1_16_SRC_CMOVN:
530 temp = tcg_const_tl(0);
531 temp2 = tcg_const_tl(const4);
532 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
533 temp2, cpu_gpr_d[r1]);
534 tcg_temp_free(temp);
535 tcg_temp_free(temp2);
536 break;
537 case OPC1_16_SRC_EQ:
538 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
539 const4);
540 break;
541 case OPC1_16_SRC_LT:
542 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
543 const4);
544 break;
545 case OPC1_16_SRC_MOV:
546 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
547 break;
548 case OPC1_16_SRC_MOV_A:
549 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
550 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
551 break;
552 case OPC1_16_SRC_SH:
553 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
554 break;
555 case OPC1_16_SRC_SHA:
556 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
557 break;
558 }
559 }
560
561 static void decode_srr_opc(DisasContext *ctx, int op1)
562 {
563 int r1, r2;
564 TCGv temp;
565
566 r1 = MASK_OP_SRR_S1D(ctx->opcode);
567 r2 = MASK_OP_SRR_S2(ctx->opcode);
568
569 switch (op1) {
570 case OPC1_16_SRR_ADD:
571 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
572 break;
573 case OPC1_16_SRR_ADD_A15:
574 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
575 break;
576 case OPC1_16_SRR_ADD_15A:
577 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
578 break;
579 case OPC1_16_SRR_ADD_A:
580 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
581 break;
582 case OPC1_16_SRR_ADDS:
583 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
584 break;
585 case OPC1_16_SRR_AND:
586 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
587 break;
588 case OPC1_16_SRR_CMOV:
589 temp = tcg_const_tl(0);
590 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
591 cpu_gpr_d[r2], cpu_gpr_d[r1]);
592 tcg_temp_free(temp);
593 break;
594 case OPC1_16_SRR_CMOVN:
595 temp = tcg_const_tl(0);
596 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
597 cpu_gpr_d[r2], cpu_gpr_d[r1]);
598 tcg_temp_free(temp);
599 break;
600 case OPC1_16_SRR_EQ:
601 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
602 cpu_gpr_d[r2]);
603 break;
604 case OPC1_16_SRR_LT:
605 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
606 cpu_gpr_d[r2]);
607 break;
608 case OPC1_16_SRR_MOV:
609 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
610 break;
611 case OPC1_16_SRR_MOV_A:
612 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
613 break;
614 case OPC1_16_SRR_MOV_AA:
615 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
616 break;
617 case OPC1_16_SRR_MOV_D:
618 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
619 break;
620 case OPC1_16_SRR_MUL:
621 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
622 break;
623 case OPC1_16_SRR_OR:
624 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
625 break;
626 case OPC1_16_SRR_SUB:
627 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
628 break;
629 case OPC1_16_SRR_SUB_A15B:
630 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
631 break;
632 case OPC1_16_SRR_SUB_15AB:
633 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
634 break;
635 case OPC1_16_SRR_SUBS:
636 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
637 break;
638 case OPC1_16_SRR_XOR:
639 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
640 break;
641 }
642 }
643
644 static void decode_ssr_opc(DisasContext *ctx, int op1)
645 {
646 int r1, r2;
647
648 r1 = MASK_OP_SSR_S1(ctx->opcode);
649 r2 = MASK_OP_SSR_S2(ctx->opcode);
650
651 switch (op1) {
652 case OPC1_16_SSR_ST_A:
653 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
654 break;
655 case OPC1_16_SSR_ST_A_POSTINC:
656 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
657 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
658 break;
659 case OPC1_16_SSR_ST_B:
660 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
661 break;
662 case OPC1_16_SSR_ST_B_POSTINC:
663 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
664 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
665 break;
666 case OPC1_16_SSR_ST_H:
667 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
668 break;
669 case OPC1_16_SSR_ST_H_POSTINC:
670 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
671 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
672 break;
673 case OPC1_16_SSR_ST_W:
674 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
675 break;
676 case OPC1_16_SSR_ST_W_POSTINC:
677 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
678 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
679 break;
680 }
681 }
682
683 static void decode_sc_opc(DisasContext *ctx, int op1)
684 {
685 int32_t const16;
686
687 const16 = MASK_OP_SC_CONST8(ctx->opcode);
688
689 switch (op1) {
690 case OPC1_16_SC_AND:
691 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
692 break;
693 case OPC1_16_SC_BISR:
694 gen_helper_1arg(bisr, const16 & 0xff);
695 break;
696 case OPC1_16_SC_LD_A:
697 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
698 break;
699 case OPC1_16_SC_LD_W:
700 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
701 break;
702 case OPC1_16_SC_MOV:
703 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
704 break;
705 case OPC1_16_SC_OR:
706 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
707 break;
708 case OPC1_16_SC_ST_A:
709 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
710 break;
711 case OPC1_16_SC_ST_W:
712 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
713 break;
714 case OPC1_16_SC_SUB_A:
715 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
716 break;
717 }
718 }
719
720 static void decode_slr_opc(DisasContext *ctx, int op1)
721 {
722 int r1, r2;
723
724 r1 = MASK_OP_SLR_D(ctx->opcode);
725 r2 = MASK_OP_SLR_S2(ctx->opcode);
726
727 switch (op1) {
728 /* SLR-format */
729 case OPC1_16_SLR_LD_A:
730 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
731 break;
732 case OPC1_16_SLR_LD_A_POSTINC:
733 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
734 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
735 break;
736 case OPC1_16_SLR_LD_BU:
737 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
738 break;
739 case OPC1_16_SLR_LD_BU_POSTINC:
740 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
741 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
742 break;
743 case OPC1_16_SLR_LD_H:
744 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
745 break;
746 case OPC1_16_SLR_LD_H_POSTINC:
747 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
748 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
749 break;
750 case OPC1_16_SLR_LD_W:
751 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
752 break;
753 case OPC1_16_SLR_LD_W_POSTINC:
754 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
755 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
756 break;
757 }
758 }
759
760 static void decode_sro_opc(DisasContext *ctx, int op1)
761 {
762 int r2;
763 int32_t address;
764
765 r2 = MASK_OP_SRO_S2(ctx->opcode);
766 address = MASK_OP_SRO_OFF4(ctx->opcode);
767
768 /* SRO-format */
769 switch (op1) {
770 case OPC1_16_SRO_LD_A:
771 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
772 break;
773 case OPC1_16_SRO_LD_BU:
774 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
775 break;
776 case OPC1_16_SRO_LD_H:
777 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
778 break;
779 case OPC1_16_SRO_LD_W:
780 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
781 break;
782 case OPC1_16_SRO_ST_A:
783 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
784 break;
785 case OPC1_16_SRO_ST_B:
786 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
787 break;
788 case OPC1_16_SRO_ST_H:
789 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
790 break;
791 case OPC1_16_SRO_ST_W:
792 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
793 break;
794 }
795 }
796
797 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
798 {
799 int op1;
800 int r1, r2;
801 int32_t const16;
802 int32_t address;
803 TCGv temp;
804
805 op1 = MASK_OP_MAJOR(ctx->opcode);
806
807 /* handle ADDSC.A opcode only being 6 bit long */
808 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
809 op1 = OPC1_16_SRRS_ADDSC_A;
810 }
811
812 switch (op1) {
813 case OPC1_16_SRC_ADD:
814 case OPC1_16_SRC_ADD_A15:
815 case OPC1_16_SRC_ADD_15A:
816 case OPC1_16_SRC_ADD_A:
817 case OPC1_16_SRC_CADD:
818 case OPC1_16_SRC_CADDN:
819 case OPC1_16_SRC_CMOV:
820 case OPC1_16_SRC_CMOVN:
821 case OPC1_16_SRC_EQ:
822 case OPC1_16_SRC_LT:
823 case OPC1_16_SRC_MOV:
824 case OPC1_16_SRC_MOV_A:
825 case OPC1_16_SRC_SH:
826 case OPC1_16_SRC_SHA:
827 decode_src_opc(ctx, op1);
828 break;
829 /* SRR-format */
830 case OPC1_16_SRR_ADD:
831 case OPC1_16_SRR_ADD_A15:
832 case OPC1_16_SRR_ADD_15A:
833 case OPC1_16_SRR_ADD_A:
834 case OPC1_16_SRR_ADDS:
835 case OPC1_16_SRR_AND:
836 case OPC1_16_SRR_CMOV:
837 case OPC1_16_SRR_CMOVN:
838 case OPC1_16_SRR_EQ:
839 case OPC1_16_SRR_LT:
840 case OPC1_16_SRR_MOV:
841 case OPC1_16_SRR_MOV_A:
842 case OPC1_16_SRR_MOV_AA:
843 case OPC1_16_SRR_MOV_D:
844 case OPC1_16_SRR_MUL:
845 case OPC1_16_SRR_OR:
846 case OPC1_16_SRR_SUB:
847 case OPC1_16_SRR_SUB_A15B:
848 case OPC1_16_SRR_SUB_15AB:
849 case OPC1_16_SRR_SUBS:
850 case OPC1_16_SRR_XOR:
851 decode_srr_opc(ctx, op1);
852 break;
853 /* SSR-format */
854 case OPC1_16_SSR_ST_A:
855 case OPC1_16_SSR_ST_A_POSTINC:
856 case OPC1_16_SSR_ST_B:
857 case OPC1_16_SSR_ST_B_POSTINC:
858 case OPC1_16_SSR_ST_H:
859 case OPC1_16_SSR_ST_H_POSTINC:
860 case OPC1_16_SSR_ST_W:
861 case OPC1_16_SSR_ST_W_POSTINC:
862 decode_ssr_opc(ctx, op1);
863 break;
864 /* SRRS-format */
865 case OPC1_16_SRRS_ADDSC_A:
866 r2 = MASK_OP_SRRS_S2(ctx->opcode);
867 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
868 const16 = MASK_OP_SRRS_N(ctx->opcode);
869 temp = tcg_temp_new();
870 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
871 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
872 tcg_temp_free(temp);
873 break;
874 /* SLRO-format */
875 case OPC1_16_SLRO_LD_A:
876 r1 = MASK_OP_SLRO_D(ctx->opcode);
877 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
878 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
879 break;
880 case OPC1_16_SLRO_LD_BU:
881 r1 = MASK_OP_SLRO_D(ctx->opcode);
882 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
883 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
884 break;
885 case OPC1_16_SLRO_LD_H:
886 r1 = MASK_OP_SLRO_D(ctx->opcode);
887 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
888 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
889 break;
890 case OPC1_16_SLRO_LD_W:
891 r1 = MASK_OP_SLRO_D(ctx->opcode);
892 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
893 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
894 break;
895 /* SB-format */
896 case OPC1_16_SB_CALL:
897 case OPC1_16_SB_J:
898 case OPC1_16_SB_JNZ:
899 case OPC1_16_SB_JZ:
900 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
901 gen_compute_branch(ctx, op1, 0, 0, 0, address);
902 break;
903 /* SBC-format */
904 case OPC1_16_SBC_JEQ:
905 case OPC1_16_SBC_JNE:
906 address = MASK_OP_SBC_DISP4(ctx->opcode);
907 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
908 gen_compute_branch(ctx, op1, 0, 0, const16, address);
909 break;
910 /* SBRN-format */
911 case OPC1_16_SBRN_JNZ_T:
912 case OPC1_16_SBRN_JZ_T:
913 address = MASK_OP_SBRN_DISP4(ctx->opcode);
914 const16 = MASK_OP_SBRN_N(ctx->opcode);
915 gen_compute_branch(ctx, op1, 0, 0, const16, address);
916 break;
917 /* SBR-format */
918 case OPC1_16_SBR_JEQ:
919 case OPC1_16_SBR_JGEZ:
920 case OPC1_16_SBR_JGTZ:
921 case OPC1_16_SBR_JLEZ:
922 case OPC1_16_SBR_JLTZ:
923 case OPC1_16_SBR_JNE:
924 case OPC1_16_SBR_JNZ:
925 case OPC1_16_SBR_JNZ_A:
926 case OPC1_16_SBR_JZ:
927 case OPC1_16_SBR_JZ_A:
928 case OPC1_16_SBR_LOOP:
929 r1 = MASK_OP_SBR_S2(ctx->opcode);
930 address = MASK_OP_SBR_DISP4(ctx->opcode);
931 gen_compute_branch(ctx, op1, r1, 0, 0, address);
932 break;
933 /* SC-format */
934 case OPC1_16_SC_AND:
935 case OPC1_16_SC_BISR:
936 case OPC1_16_SC_LD_A:
937 case OPC1_16_SC_LD_W:
938 case OPC1_16_SC_MOV:
939 case OPC1_16_SC_OR:
940 case OPC1_16_SC_ST_A:
941 case OPC1_16_SC_ST_W:
942 case OPC1_16_SC_SUB_A:
943 decode_sc_opc(ctx, op1);
944 break;
945 /* SLR-format */
946 case OPC1_16_SLR_LD_A:
947 case OPC1_16_SLR_LD_A_POSTINC:
948 case OPC1_16_SLR_LD_BU:
949 case OPC1_16_SLR_LD_BU_POSTINC:
950 case OPC1_16_SLR_LD_H:
951 case OPC1_16_SLR_LD_H_POSTINC:
952 case OPC1_16_SLR_LD_W:
953 case OPC1_16_SLR_LD_W_POSTINC:
954 decode_slr_opc(ctx, op1);
955 break;
956 /* SRO-format */
957 case OPC1_16_SRO_LD_A:
958 case OPC1_16_SRO_LD_BU:
959 case OPC1_16_SRO_LD_H:
960 case OPC1_16_SRO_LD_W:
961 case OPC1_16_SRO_ST_A:
962 case OPC1_16_SRO_ST_B:
963 case OPC1_16_SRO_ST_H:
964 case OPC1_16_SRO_ST_W:
965 decode_sro_opc(ctx, op1);
966 break;
967 /* SSRO-format */
968 case OPC1_16_SSRO_ST_A:
969 r1 = MASK_OP_SSRO_S1(ctx->opcode);
970 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
971 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
972 break;
973 case OPC1_16_SSRO_ST_B:
974 r1 = MASK_OP_SSRO_S1(ctx->opcode);
975 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
976 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
977 break;
978 case OPC1_16_SSRO_ST_H:
979 r1 = MASK_OP_SSRO_S1(ctx->opcode);
980 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
981 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
982 break;
983 case OPC1_16_SSRO_ST_W:
984 r1 = MASK_OP_SSRO_S1(ctx->opcode);
985 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
986 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
987 break;
988 }
989 }
990
991 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
992 {
993 }
994
995 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
996 {
997 /* 16-Bit Instruction */
998 if ((ctx->opcode & 0x1) == 0) {
999 ctx->next_pc = ctx->pc + 2;
1000 decode_16Bit_opc(env, ctx);
1001 /* 32-Bit Instruction */
1002 } else {
1003 ctx->next_pc = ctx->pc + 4;
1004 decode_32Bit_opc(env, ctx);
1005 }
1006 }
1007
1008 static inline void
1009 gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
1010 int search_pc)
1011 {
1012 CPUState *cs = CPU(cpu);
1013 CPUTriCoreState *env = &cpu->env;
1014 DisasContext ctx;
1015 target_ulong pc_start;
1016 int num_insns;
1017 uint16_t *gen_opc_end;
1018
1019 if (search_pc) {
1020 qemu_log("search pc %d\n", search_pc);
1021 }
1022
1023 num_insns = 0;
1024 pc_start = tb->pc;
1025 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1026 ctx.pc = pc_start;
1027 ctx.saved_pc = -1;
1028 ctx.tb = tb;
1029 ctx.singlestep_enabled = cs->singlestep_enabled;
1030 ctx.bstate = BS_NONE;
1031 ctx.mem_idx = cpu_mmu_index(env);
1032
1033 tcg_clear_temp_count();
1034 gen_tb_start();
1035 while (ctx.bstate == BS_NONE) {
1036 ctx.opcode = cpu_ldl_code(env, ctx.pc);
1037 decode_opc(env, &ctx, 0);
1038
1039 num_insns++;
1040
1041 if (tcg_ctx.gen_opc_ptr >= gen_opc_end) {
1042 gen_save_pc(ctx.next_pc);
1043 tcg_gen_exit_tb(0);
1044 break;
1045 }
1046 if (singlestep) {
1047 gen_save_pc(ctx.next_pc);
1048 tcg_gen_exit_tb(0);
1049 break;
1050 }
1051 ctx.pc = ctx.next_pc;
1052 }
1053
1054 gen_tb_end(tb, num_insns);
1055 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1056 if (search_pc) {
1057 printf("done_generating search pc\n");
1058 } else {
1059 tb->size = ctx.pc - pc_start;
1060 tb->icount = num_insns;
1061 }
1062 if (tcg_check_temp_count()) {
1063 printf("LEAK at %08x\n", env->PC);
1064 }
1065
1066 #ifdef DEBUG_DISAS
1067 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1068 qemu_log("IN: %s\n", lookup_symbol(pc_start));
1069 log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
1070 qemu_log("\n");
1071 }
1072 #endif
1073 }
1074
1075 void
1076 gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
1077 {
1078 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
1079 }
1080
1081 void
1082 gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
1083 {
1084 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
1085 }
1086
1087 void
1088 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
1089 {
1090 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
1091 }
1092 /*
1093 *
1094 * Initialization
1095 *
1096 */
1097
1098 void cpu_state_reset(CPUTriCoreState *env)
1099 {
1100 /* Reset Regs to Default Value */
1101 env->PSW = 0xb80;
1102 }
1103
1104 static void tricore_tcg_init_csfr(void)
1105 {
1106 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
1107 offsetof(CPUTriCoreState, PCXI), "PCXI");
1108 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
1109 offsetof(CPUTriCoreState, PSW), "PSW");
1110 cpu_PC = tcg_global_mem_new(TCG_AREG0,
1111 offsetof(CPUTriCoreState, PC), "PC");
1112 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
1113 offsetof(CPUTriCoreState, ICR), "ICR");
1114 }
1115
1116 void tricore_tcg_init(void)
1117 {
1118 int i;
1119 static int inited;
1120 if (inited) {
1121 return;
1122 }
1123 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1124 /* reg init */
1125 for (i = 0 ; i < 16 ; i++) {
1126 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
1127 offsetof(CPUTriCoreState, gpr_a[i]),
1128 regnames_a[i]);
1129 }
1130 for (i = 0 ; i < 16 ; i++) {
1131 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
1132 offsetof(CPUTriCoreState, gpr_d[i]),
1133 regnames_d[i]);
1134 }
1135 tricore_tcg_init_csfr();
1136 /* init PSW flag cache */
1137 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
1138 offsetof(CPUTriCoreState, PSW_USB_C),
1139 "PSW_C");
1140 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
1141 offsetof(CPUTriCoreState, PSW_USB_V),
1142 "PSW_V");
1143 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
1144 offsetof(CPUTriCoreState, PSW_USB_SV),
1145 "PSW_SV");
1146 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
1147 offsetof(CPUTriCoreState, PSW_USB_AV),
1148 "PSW_AV");
1149 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
1150 offsetof(CPUTriCoreState, PSW_USB_SAV),
1151 "PSW_SAV");
1152 }
QEmu