2 * PowerPC implementation of KVM hooks
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
17 #include "qemu/osdep.h"
19 #include <sys/ioctl.h>
22 #include <linux/kvm.h>
24 #include "qemu-common.h"
25 #include "qapi/error.h"
26 #include "qemu/error-report.h"
28 #include "cpu-models.h"
29 #include "qemu/timer.h"
30 #include "sysemu/hw_accel.h"
32 #include "sysemu/cpus.h"
33 #include "sysemu/device_tree.h"
34 #include "mmu-hash64.h"
36 #include "hw/sysbus.h"
37 #include "hw/ppc/spapr.h"
38 #include "hw/ppc/spapr_cpu_core.h"
40 #include "hw/ppc/ppc.h"
41 #include "migration/qemu-file-types.h"
42 #include "sysemu/watchdog.h"
44 #include "exec/gdbstub.h"
45 #include "exec/memattrs.h"
46 #include "exec/ram_addr.h"
47 #include "sysemu/hostmem.h"
48 #include "qemu/cutils.h"
49 #include "qemu/main-loop.h"
50 #include "qemu/mmap-alloc.h"
52 #include "sysemu/kvm_int.h"
54 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
56 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
60 static int cap_interrupt_unset
;
61 static int cap_segstate
;
62 static int cap_booke_sregs
;
63 static int cap_ppc_smt
;
64 static int cap_ppc_smt_possible
;
65 static int cap_spapr_tce
;
66 static int cap_spapr_tce_64
;
67 static int cap_spapr_multitce
;
68 static int cap_spapr_vfio
;
70 static int cap_one_reg
;
72 static int cap_ppc_watchdog
;
74 static int cap_htab_fd
;
75 static int cap_fixup_hcalls
;
76 static int cap_htm
; /* Hardware transactional memory support */
77 static int cap_mmu_radix
;
78 static int cap_mmu_hash_v3
;
80 static int cap_resize_hpt
;
81 static int cap_ppc_pvr_compat
;
82 static int cap_ppc_safe_cache
;
83 static int cap_ppc_safe_bounds_check
;
84 static int cap_ppc_safe_indirect_branch
;
85 static int cap_ppc_count_cache_flush_assist
;
86 static int cap_ppc_nested_kvm_hv
;
87 static int cap_large_decr
;
89 static uint32_t debug_inst_opcode
;
92 * Check whether we are running with KVM-PR (instead of KVM-HV). This
93 * should only be used for fallback tests - generally we should use
94 * explicit capabilities for the features we want, rather than
95 * assuming what is/isn't available depending on the KVM variant.
97 static bool kvmppc_is_pr(KVMState
*ks
)
99 /* Assume KVM-PR if the GET_PVINFO capability is available */
100 return kvm_vm_check_extension(ks
, KVM_CAP_PPC_GET_PVINFO
) != 0;
103 static int kvm_ppc_register_host_cpu_type(MachineState
*ms
);
104 static void kvmppc_get_cpu_characteristics(KVMState
*s
);
105 static int kvmppc_get_dec_bits(void);
107 int kvm_arch_init(MachineState
*ms
, KVMState
*s
)
109 cap_interrupt_unset
= kvm_check_extension(s
, KVM_CAP_PPC_UNSET_IRQ
);
110 cap_segstate
= kvm_check_extension(s
, KVM_CAP_PPC_SEGSTATE
);
111 cap_booke_sregs
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_SREGS
);
112 cap_ppc_smt_possible
= kvm_vm_check_extension(s
, KVM_CAP_PPC_SMT_POSSIBLE
);
113 cap_spapr_tce
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE
);
114 cap_spapr_tce_64
= kvm_check_extension(s
, KVM_CAP_SPAPR_TCE_64
);
115 cap_spapr_multitce
= kvm_check_extension(s
, KVM_CAP_SPAPR_MULTITCE
);
116 cap_spapr_vfio
= kvm_vm_check_extension(s
, KVM_CAP_SPAPR_TCE_VFIO
);
117 cap_one_reg
= kvm_check_extension(s
, KVM_CAP_ONE_REG
);
118 cap_hior
= kvm_check_extension(s
, KVM_CAP_PPC_HIOR
);
119 cap_epr
= kvm_check_extension(s
, KVM_CAP_PPC_EPR
);
120 cap_ppc_watchdog
= kvm_check_extension(s
, KVM_CAP_PPC_BOOKE_WATCHDOG
);
122 * Note: we don't set cap_papr here, because this capability is
123 * only activated after this by kvmppc_set_papr()
125 cap_htab_fd
= kvm_vm_check_extension(s
, KVM_CAP_PPC_HTAB_FD
);
126 cap_fixup_hcalls
= kvm_check_extension(s
, KVM_CAP_PPC_FIXUP_HCALL
);
127 cap_ppc_smt
= kvm_vm_check_extension(s
, KVM_CAP_PPC_SMT
);
128 cap_htm
= kvm_vm_check_extension(s
, KVM_CAP_PPC_HTM
);
129 cap_mmu_radix
= kvm_vm_check_extension(s
, KVM_CAP_PPC_MMU_RADIX
);
130 cap_mmu_hash_v3
= kvm_vm_check_extension(s
, KVM_CAP_PPC_MMU_HASH_V3
);
131 cap_xive
= kvm_vm_check_extension(s
, KVM_CAP_PPC_IRQ_XIVE
);
132 cap_resize_hpt
= kvm_vm_check_extension(s
, KVM_CAP_SPAPR_RESIZE_HPT
);
133 kvmppc_get_cpu_characteristics(s
);
134 cap_ppc_nested_kvm_hv
= kvm_vm_check_extension(s
, KVM_CAP_PPC_NESTED_HV
);
135 cap_large_decr
= kvmppc_get_dec_bits();
137 * Note: setting it to false because there is not such capability
138 * in KVM at this moment.
140 * TODO: call kvm_vm_check_extension() with the right capability
141 * after the kernel starts implementing it.
143 cap_ppc_pvr_compat
= false;
145 if (!kvm_check_extension(s
, KVM_CAP_PPC_IRQ_LEVEL
)) {
146 error_report("KVM: Host kernel doesn't have level irq capability");
150 kvm_ppc_register_host_cpu_type(ms
);
155 int kvm_arch_irqchip_create(MachineState
*ms
, KVMState
*s
)
160 static int kvm_arch_sync_sregs(PowerPCCPU
*cpu
)
162 CPUPPCState
*cenv
= &cpu
->env
;
163 CPUState
*cs
= CPU(cpu
);
164 struct kvm_sregs sregs
;
167 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
169 * What we're really trying to say is "if we're on BookE, we
170 * use the native PVR for now". This is the only sane way to
171 * check it though, so we potentially confuse users that they
172 * can run BookE guests on BookS. Let's hope nobody dares
178 fprintf(stderr
, "kvm error: missing PVR setting capability\n");
183 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_SREGS
, &sregs
);
188 sregs
.pvr
= cenv
->spr
[SPR_PVR
];
189 return kvm_vcpu_ioctl(cs
, KVM_SET_SREGS
, &sregs
);
192 /* Set up a shared TLB array with KVM */
193 static int kvm_booke206_tlb_init(PowerPCCPU
*cpu
)
195 CPUPPCState
*env
= &cpu
->env
;
196 CPUState
*cs
= CPU(cpu
);
197 struct kvm_book3e_206_tlb_params params
= {};
198 struct kvm_config_tlb cfg
= {};
199 unsigned int entries
= 0;
202 if (!kvm_enabled() ||
203 !kvm_check_extension(cs
->kvm_state
, KVM_CAP_SW_TLB
)) {
207 assert(ARRAY_SIZE(params
.tlb_sizes
) == BOOKE206_MAX_TLBN
);
209 for (i
= 0; i
< BOOKE206_MAX_TLBN
; i
++) {
210 params
.tlb_sizes
[i
] = booke206_tlb_size(env
, i
);
211 params
.tlb_ways
[i
] = booke206_tlb_ways(env
, i
);
212 entries
+= params
.tlb_sizes
[i
];
215 assert(entries
== env
->nb_tlb
);
216 assert(sizeof(struct kvm_book3e_206_tlb_entry
) == sizeof(ppcmas_tlb_t
));
218 env
->tlb_dirty
= true;
220 cfg
.array
= (uintptr_t)env
->tlb
.tlbm
;
221 cfg
.array_len
= sizeof(ppcmas_tlb_t
) * entries
;
222 cfg
.params
= (uintptr_t)¶ms
;
223 cfg
.mmu_type
= KVM_MMU_FSL_BOOKE_NOHV
;
225 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_SW_TLB
, 0, (uintptr_t)&cfg
);
227 fprintf(stderr
, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
228 __func__
, strerror(-ret
));
232 env
->kvm_sw_tlb
= true;
237 #if defined(TARGET_PPC64)
238 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info
*info
, Error
**errp
)
242 assert(kvm_state
!= NULL
);
244 if (!kvm_check_extension(kvm_state
, KVM_CAP_PPC_GET_SMMU_INFO
)) {
245 error_setg(errp
, "KVM doesn't expose the MMU features it supports");
246 error_append_hint(errp
, "Consider switching to a newer KVM\n");
250 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_GET_SMMU_INFO
, info
);
255 error_setg_errno(errp
, -ret
,
256 "KVM failed to provide the MMU features it supports");
259 struct ppc_radix_page_info
*kvm_get_radix_page_info(void)
261 KVMState
*s
= KVM_STATE(current_machine
->accelerator
);
262 struct ppc_radix_page_info
*radix_page_info
;
263 struct kvm_ppc_rmmu_info rmmu_info
;
266 if (!kvm_check_extension(s
, KVM_CAP_PPC_MMU_RADIX
)) {
269 if (kvm_vm_ioctl(s
, KVM_PPC_GET_RMMU_INFO
, &rmmu_info
)) {
272 radix_page_info
= g_malloc0(sizeof(*radix_page_info
));
273 radix_page_info
->count
= 0;
274 for (i
= 0; i
< PPC_PAGE_SIZES_MAX_SZ
; i
++) {
275 if (rmmu_info
.ap_encodings
[i
]) {
276 radix_page_info
->entries
[i
] = rmmu_info
.ap_encodings
[i
];
277 radix_page_info
->count
++;
280 return radix_page_info
;
283 target_ulong
kvmppc_configure_v3_mmu(PowerPCCPU
*cpu
,
284 bool radix
, bool gtse
,
287 CPUState
*cs
= CPU(cpu
);
290 struct kvm_ppc_mmuv3_cfg cfg
= {
291 .process_table
= proc_tbl
,
295 flags
|= KVM_PPC_MMUV3_RADIX
;
298 flags
|= KVM_PPC_MMUV3_GTSE
;
301 ret
= kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_CONFIGURE_V3_MMU
, &cfg
);
308 return H_NOT_AVAILABLE
;
314 bool kvmppc_hpt_needs_host_contiguous_pages(void)
316 static struct kvm_ppc_smmu_info smmu_info
;
318 if (!kvm_enabled()) {
322 kvm_get_smmu_info(&smmu_info
, &error_fatal
);
323 return !!(smmu_info
.flags
& KVM_PPC_PAGE_SIZES_REAL
);
326 void kvm_check_mmu(PowerPCCPU
*cpu
, Error
**errp
)
328 struct kvm_ppc_smmu_info smmu_info
;
330 Error
*local_err
= NULL
;
332 /* For now, we only have anything to check on hash64 MMUs */
333 if (!cpu
->hash64_opts
|| !kvm_enabled()) {
337 kvm_get_smmu_info(&smmu_info
, &local_err
);
339 error_propagate(errp
, local_err
);
343 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)
344 && !(smmu_info
.flags
& KVM_PPC_1T_SEGMENTS
)) {
346 "KVM does not support 1TiB segments which guest expects");
350 if (smmu_info
.slb_size
< cpu
->hash64_opts
->slb_size
) {
351 error_setg(errp
, "KVM only supports %u SLB entries, but guest needs %u",
352 smmu_info
.slb_size
, cpu
->hash64_opts
->slb_size
);
357 * Verify that every pagesize supported by the cpu model is
358 * supported by KVM with the same encodings
360 for (iq
= 0; iq
< ARRAY_SIZE(cpu
->hash64_opts
->sps
); iq
++) {
361 PPCHash64SegmentPageSizes
*qsps
= &cpu
->hash64_opts
->sps
[iq
];
362 struct kvm_ppc_one_seg_page_size
*ksps
;
364 for (ik
= 0; ik
< ARRAY_SIZE(smmu_info
.sps
); ik
++) {
365 if (qsps
->page_shift
== smmu_info
.sps
[ik
].page_shift
) {
369 if (ik
>= ARRAY_SIZE(smmu_info
.sps
)) {
370 error_setg(errp
, "KVM doesn't support for base page shift %u",
375 ksps
= &smmu_info
.sps
[ik
];
376 if (ksps
->slb_enc
!= qsps
->slb_enc
) {
378 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
379 ksps
->slb_enc
, ksps
->page_shift
, qsps
->slb_enc
);
383 for (jq
= 0; jq
< ARRAY_SIZE(qsps
->enc
); jq
++) {
384 for (jk
= 0; jk
< ARRAY_SIZE(ksps
->enc
); jk
++) {
385 if (qsps
->enc
[jq
].page_shift
== ksps
->enc
[jk
].page_shift
) {
390 if (jk
>= ARRAY_SIZE(ksps
->enc
)) {
391 error_setg(errp
, "KVM doesn't support page shift %u/%u",
392 qsps
->enc
[jq
].page_shift
, qsps
->page_shift
);
395 if (qsps
->enc
[jq
].pte_enc
!= ksps
->enc
[jk
].pte_enc
) {
397 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
398 ksps
->enc
[jk
].pte_enc
, qsps
->enc
[jq
].page_shift
,
399 qsps
->page_shift
, qsps
->enc
[jq
].pte_enc
);
405 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
407 * Mostly what guest pagesizes we can use are related to the
408 * host pages used to map guest RAM, which is handled in the
409 * platform code. Cache-Inhibited largepages (64k) however are
410 * used for I/O, so if they're mapped to the host at all it
411 * will be a normal mapping, not a special hugepage one used
414 if (getpagesize() < 0x10000) {
416 "KVM can't supply 64kiB CI pages, which guest expects");
420 #endif /* !defined (TARGET_PPC64) */
422 unsigned long kvm_arch_vcpu_id(CPUState
*cpu
)
424 return POWERPC_CPU(cpu
)->vcpu_id
;
428 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
429 * only 1 watchpoint, so array size of 4 is sufficient for now.
431 #define MAX_HW_BKPTS 4
433 static struct HWBreakpoint
{
436 } hw_debug_points
[MAX_HW_BKPTS
];
438 static CPUWatchpoint hw_watchpoint
;
440 /* Default there is no breakpoint and watchpoint supported */
441 static int max_hw_breakpoint
;
442 static int max_hw_watchpoint
;
443 static int nb_hw_breakpoint
;
444 static int nb_hw_watchpoint
;
446 static void kvmppc_hw_debug_points_init(CPUPPCState
*cenv
)
448 if (cenv
->excp_model
== POWERPC_EXCP_BOOKE
) {
449 max_hw_breakpoint
= 2;
450 max_hw_watchpoint
= 2;
453 if ((max_hw_breakpoint
+ max_hw_watchpoint
) > MAX_HW_BKPTS
) {
454 fprintf(stderr
, "Error initializing h/w breakpoints\n");
459 int kvm_arch_init_vcpu(CPUState
*cs
)
461 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
462 CPUPPCState
*cenv
= &cpu
->env
;
465 /* Synchronize sregs with kvm */
466 ret
= kvm_arch_sync_sregs(cpu
);
468 if (ret
== -EINVAL
) {
469 error_report("Register sync failed... If you're using kvm-hv.ko,"
470 " only \"-cpu host\" is possible");
475 switch (cenv
->mmu_model
) {
476 case POWERPC_MMU_BOOKE206
:
477 /* This target supports access to KVM's guest TLB */
478 ret
= kvm_booke206_tlb_init(cpu
);
480 case POWERPC_MMU_2_07
:
481 if (!cap_htm
&& !kvmppc_is_pr(cs
->kvm_state
)) {
483 * KVM-HV has transactional memory on POWER8 also without
484 * the KVM_CAP_PPC_HTM extension, so enable it here
485 * instead as long as it's availble to userspace on the
488 if (qemu_getauxval(AT_HWCAP2
) & PPC_FEATURE2_HAS_HTM
) {
497 kvm_get_one_reg(cs
, KVM_REG_PPC_DEBUG_INST
, &debug_inst_opcode
);
498 kvmppc_hw_debug_points_init(cenv
);
503 int kvm_arch_destroy_vcpu(CPUState
*cs
)
508 static void kvm_sw_tlb_put(PowerPCCPU
*cpu
)
510 CPUPPCState
*env
= &cpu
->env
;
511 CPUState
*cs
= CPU(cpu
);
512 struct kvm_dirty_tlb dirty_tlb
;
513 unsigned char *bitmap
;
516 if (!env
->kvm_sw_tlb
) {
520 bitmap
= g_malloc((env
->nb_tlb
+ 7) / 8);
521 memset(bitmap
, 0xFF, (env
->nb_tlb
+ 7) / 8);
523 dirty_tlb
.bitmap
= (uintptr_t)bitmap
;
524 dirty_tlb
.num_dirty
= env
->nb_tlb
;
526 ret
= kvm_vcpu_ioctl(cs
, KVM_DIRTY_TLB
, &dirty_tlb
);
528 fprintf(stderr
, "%s: KVM_DIRTY_TLB: %s\n",
529 __func__
, strerror(-ret
));
535 static void kvm_get_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
537 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
538 CPUPPCState
*env
= &cpu
->env
;
543 struct kvm_one_reg reg
= {
545 .addr
= (uintptr_t) &val
,
549 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
551 trace_kvm_failed_spr_get(spr
, strerror(errno
));
553 switch (id
& KVM_REG_SIZE_MASK
) {
554 case KVM_REG_SIZE_U32
:
555 env
->spr
[spr
] = val
.u32
;
558 case KVM_REG_SIZE_U64
:
559 env
->spr
[spr
] = val
.u64
;
563 /* Don't handle this size yet */
569 static void kvm_put_one_spr(CPUState
*cs
, uint64_t id
, int spr
)
571 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
572 CPUPPCState
*env
= &cpu
->env
;
577 struct kvm_one_reg reg
= {
579 .addr
= (uintptr_t) &val
,
583 switch (id
& KVM_REG_SIZE_MASK
) {
584 case KVM_REG_SIZE_U32
:
585 val
.u32
= env
->spr
[spr
];
588 case KVM_REG_SIZE_U64
:
589 val
.u64
= env
->spr
[spr
];
593 /* Don't handle this size yet */
597 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
599 trace_kvm_failed_spr_set(spr
, strerror(errno
));
603 static int kvm_put_fp(CPUState
*cs
)
605 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
606 CPUPPCState
*env
= &cpu
->env
;
607 struct kvm_one_reg reg
;
611 if (env
->insns_flags
& PPC_FLOAT
) {
612 uint64_t fpscr
= env
->fpscr
;
613 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
615 reg
.id
= KVM_REG_PPC_FPSCR
;
616 reg
.addr
= (uintptr_t)&fpscr
;
617 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
619 trace_kvm_failed_fpscr_set(strerror(errno
));
623 for (i
= 0; i
< 32; i
++) {
625 uint64_t *fpr
= cpu_fpr_ptr(&cpu
->env
, i
);
626 uint64_t *vsrl
= cpu_vsrl_ptr(&cpu
->env
, i
);
628 #ifdef HOST_WORDS_BIGENDIAN
629 vsr
[0] = float64_val(*fpr
);
633 vsr
[1] = float64_val(*fpr
);
635 reg
.addr
= (uintptr_t) &vsr
;
636 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
638 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
640 trace_kvm_failed_fp_set(vsx
? "VSR" : "FPR", i
,
647 if (env
->insns_flags
& PPC_ALTIVEC
) {
648 reg
.id
= KVM_REG_PPC_VSCR
;
649 reg
.addr
= (uintptr_t)&env
->vscr
;
650 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
652 trace_kvm_failed_vscr_set(strerror(errno
));
656 for (i
= 0; i
< 32; i
++) {
657 reg
.id
= KVM_REG_PPC_VR(i
);
658 reg
.addr
= (uintptr_t)cpu_avr_ptr(env
, i
);
659 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
661 trace_kvm_failed_vr_set(i
, strerror(errno
));
670 static int kvm_get_fp(CPUState
*cs
)
672 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
673 CPUPPCState
*env
= &cpu
->env
;
674 struct kvm_one_reg reg
;
678 if (env
->insns_flags
& PPC_FLOAT
) {
680 bool vsx
= !!(env
->insns_flags2
& PPC2_VSX
);
682 reg
.id
= KVM_REG_PPC_FPSCR
;
683 reg
.addr
= (uintptr_t)&fpscr
;
684 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
686 trace_kvm_failed_fpscr_get(strerror(errno
));
692 for (i
= 0; i
< 32; i
++) {
694 uint64_t *fpr
= cpu_fpr_ptr(&cpu
->env
, i
);
695 uint64_t *vsrl
= cpu_vsrl_ptr(&cpu
->env
, i
);
697 reg
.addr
= (uintptr_t) &vsr
;
698 reg
.id
= vsx
? KVM_REG_PPC_VSR(i
) : KVM_REG_PPC_FPR(i
);
700 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
702 trace_kvm_failed_fp_get(vsx
? "VSR" : "FPR", i
,
706 #ifdef HOST_WORDS_BIGENDIAN
721 if (env
->insns_flags
& PPC_ALTIVEC
) {
722 reg
.id
= KVM_REG_PPC_VSCR
;
723 reg
.addr
= (uintptr_t)&env
->vscr
;
724 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
726 trace_kvm_failed_vscr_get(strerror(errno
));
730 for (i
= 0; i
< 32; i
++) {
731 reg
.id
= KVM_REG_PPC_VR(i
);
732 reg
.addr
= (uintptr_t)cpu_avr_ptr(env
, i
);
733 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
735 trace_kvm_failed_vr_get(i
, strerror(errno
));
744 #if defined(TARGET_PPC64)
745 static int kvm_get_vpa(CPUState
*cs
)
747 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
748 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
749 struct kvm_one_reg reg
;
752 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
753 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
754 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
756 trace_kvm_failed_vpa_addr_get(strerror(errno
));
760 assert((uintptr_t)&spapr_cpu
->slb_shadow_size
761 == ((uintptr_t)&spapr_cpu
->slb_shadow_addr
+ 8));
762 reg
.id
= KVM_REG_PPC_VPA_SLB
;
763 reg
.addr
= (uintptr_t)&spapr_cpu
->slb_shadow_addr
;
764 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
766 trace_kvm_failed_slb_get(strerror(errno
));
770 assert((uintptr_t)&spapr_cpu
->dtl_size
771 == ((uintptr_t)&spapr_cpu
->dtl_addr
+ 8));
772 reg
.id
= KVM_REG_PPC_VPA_DTL
;
773 reg
.addr
= (uintptr_t)&spapr_cpu
->dtl_addr
;
774 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_ONE_REG
, ®
);
776 trace_kvm_failed_dtl_get(strerror(errno
));
783 static int kvm_put_vpa(CPUState
*cs
)
785 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
786 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
787 struct kvm_one_reg reg
;
791 * SLB shadow or DTL can't be registered unless a master VPA is
792 * registered. That means when restoring state, if a VPA *is*
793 * registered, we need to set that up first. If not, we need to
794 * deregister the others before deregistering the master VPA
796 assert(spapr_cpu
->vpa_addr
797 || !(spapr_cpu
->slb_shadow_addr
|| spapr_cpu
->dtl_addr
));
799 if (spapr_cpu
->vpa_addr
) {
800 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
801 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
802 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
804 trace_kvm_failed_vpa_addr_set(strerror(errno
));
809 assert((uintptr_t)&spapr_cpu
->slb_shadow_size
810 == ((uintptr_t)&spapr_cpu
->slb_shadow_addr
+ 8));
811 reg
.id
= KVM_REG_PPC_VPA_SLB
;
812 reg
.addr
= (uintptr_t)&spapr_cpu
->slb_shadow_addr
;
813 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
815 trace_kvm_failed_slb_set(strerror(errno
));
819 assert((uintptr_t)&spapr_cpu
->dtl_size
820 == ((uintptr_t)&spapr_cpu
->dtl_addr
+ 8));
821 reg
.id
= KVM_REG_PPC_VPA_DTL
;
822 reg
.addr
= (uintptr_t)&spapr_cpu
->dtl_addr
;
823 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
825 trace_kvm_failed_dtl_set(strerror(errno
));
829 if (!spapr_cpu
->vpa_addr
) {
830 reg
.id
= KVM_REG_PPC_VPA_ADDR
;
831 reg
.addr
= (uintptr_t)&spapr_cpu
->vpa_addr
;
832 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
834 trace_kvm_failed_null_vpa_addr_set(strerror(errno
));
841 #endif /* TARGET_PPC64 */
843 int kvmppc_put_books_sregs(PowerPCCPU
*cpu
)
845 CPUPPCState
*env
= &cpu
->env
;
846 struct kvm_sregs sregs
;
849 sregs
.pvr
= env
->spr
[SPR_PVR
];
852 PPCVirtualHypervisorClass
*vhc
=
853 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
854 sregs
.u
.s
.sdr1
= vhc
->encode_hpt_for_kvm_pr(cpu
->vhyp
);
856 sregs
.u
.s
.sdr1
= env
->spr
[SPR_SDR1
];
861 for (i
= 0; i
< ARRAY_SIZE(env
->slb
); i
++) {
862 sregs
.u
.s
.ppc64
.slb
[i
].slbe
= env
->slb
[i
].esid
;
863 if (env
->slb
[i
].esid
& SLB_ESID_V
) {
864 sregs
.u
.s
.ppc64
.slb
[i
].slbe
|= i
;
866 sregs
.u
.s
.ppc64
.slb
[i
].slbv
= env
->slb
[i
].vsid
;
871 for (i
= 0; i
< 16; i
++) {
872 sregs
.u
.s
.ppc32
.sr
[i
] = env
->sr
[i
];
876 for (i
= 0; i
< 8; i
++) {
877 /* Beware. We have to swap upper and lower bits here */
878 sregs
.u
.s
.ppc32
.dbat
[i
] = ((uint64_t)env
->DBAT
[0][i
] << 32)
880 sregs
.u
.s
.ppc32
.ibat
[i
] = ((uint64_t)env
->IBAT
[0][i
] << 32)
884 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
887 int kvm_arch_put_registers(CPUState
*cs
, int level
)
889 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
890 CPUPPCState
*env
= &cpu
->env
;
891 struct kvm_regs regs
;
895 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
902 regs
.xer
= cpu_read_xer(env
);
906 regs
.srr0
= env
->spr
[SPR_SRR0
];
907 regs
.srr1
= env
->spr
[SPR_SRR1
];
909 regs
.sprg0
= env
->spr
[SPR_SPRG0
];
910 regs
.sprg1
= env
->spr
[SPR_SPRG1
];
911 regs
.sprg2
= env
->spr
[SPR_SPRG2
];
912 regs
.sprg3
= env
->spr
[SPR_SPRG3
];
913 regs
.sprg4
= env
->spr
[SPR_SPRG4
];
914 regs
.sprg5
= env
->spr
[SPR_SPRG5
];
915 regs
.sprg6
= env
->spr
[SPR_SPRG6
];
916 regs
.sprg7
= env
->spr
[SPR_SPRG7
];
918 regs
.pid
= env
->spr
[SPR_BOOKE_PID
];
920 for (i
= 0; i
< 32; i
++) {
921 regs
.gpr
[i
] = env
->gpr
[i
];
925 for (i
= 0; i
< 8; i
++) {
926 regs
.cr
|= (env
->crf
[i
] & 15) << (4 * (7 - i
));
929 ret
= kvm_vcpu_ioctl(cs
, KVM_SET_REGS
, ®s
);
936 if (env
->tlb_dirty
) {
938 env
->tlb_dirty
= false;
941 if (cap_segstate
&& (level
>= KVM_PUT_RESET_STATE
)) {
942 ret
= kvmppc_put_books_sregs(cpu
);
948 if (cap_hior
&& (level
>= KVM_PUT_RESET_STATE
)) {
949 kvm_put_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
956 * We deliberately ignore errors here, for kernels which have
957 * the ONE_REG calls, but don't support the specific
958 * registers, there's a reasonable chance things will still
959 * work, at least until we try to migrate.
961 for (i
= 0; i
< 1024; i
++) {
962 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
965 kvm_put_one_spr(cs
, id
, i
);
971 for (i
= 0; i
< ARRAY_SIZE(env
->tm_gpr
); i
++) {
972 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_GPR(i
), &env
->tm_gpr
[i
]);
974 for (i
= 0; i
< ARRAY_SIZE(env
->tm_vsr
); i
++) {
975 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VSR(i
), &env
->tm_vsr
[i
]);
977 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_CR
, &env
->tm_cr
);
978 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_LR
, &env
->tm_lr
);
979 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_CTR
, &env
->tm_ctr
);
980 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_FPSCR
, &env
->tm_fpscr
);
981 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_AMR
, &env
->tm_amr
);
982 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_PPR
, &env
->tm_ppr
);
983 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VRSAVE
, &env
->tm_vrsave
);
984 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_VSCR
, &env
->tm_vscr
);
985 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_DSCR
, &env
->tm_dscr
);
986 kvm_set_one_reg(cs
, KVM_REG_PPC_TM_TAR
, &env
->tm_tar
);
990 if (kvm_put_vpa(cs
) < 0) {
991 trace_kvm_failed_put_vpa();
995 kvm_set_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &env
->tb_env
->tb_offset
);
997 if (level
> KVM_PUT_RUNTIME_STATE
) {
998 kvm_put_one_spr(cs
, KVM_REG_PPC_DPDES
, SPR_DPDES
);
1000 #endif /* TARGET_PPC64 */
1006 static void kvm_sync_excp(CPUPPCState
*env
, int vector
, int ivor
)
1008 env
->excp_vectors
[vector
] = env
->spr
[ivor
] + env
->spr
[SPR_BOOKE_IVPR
];
1011 static int kvmppc_get_booke_sregs(PowerPCCPU
*cpu
)
1013 CPUPPCState
*env
= &cpu
->env
;
1014 struct kvm_sregs sregs
;
1017 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1022 if (sregs
.u
.e
.features
& KVM_SREGS_E_BASE
) {
1023 env
->spr
[SPR_BOOKE_CSRR0
] = sregs
.u
.e
.csrr0
;
1024 env
->spr
[SPR_BOOKE_CSRR1
] = sregs
.u
.e
.csrr1
;
1025 env
->spr
[SPR_BOOKE_ESR
] = sregs
.u
.e
.esr
;
1026 env
->spr
[SPR_BOOKE_DEAR
] = sregs
.u
.e
.dear
;
1027 env
->spr
[SPR_BOOKE_MCSR
] = sregs
.u
.e
.mcsr
;
1028 env
->spr
[SPR_BOOKE_TSR
] = sregs
.u
.e
.tsr
;
1029 env
->spr
[SPR_BOOKE_TCR
] = sregs
.u
.e
.tcr
;
1030 env
->spr
[SPR_DECR
] = sregs
.u
.e
.dec
;
1031 env
->spr
[SPR_TBL
] = sregs
.u
.e
.tb
& 0xffffffff;
1032 env
->spr
[SPR_TBU
] = sregs
.u
.e
.tb
>> 32;
1033 env
->spr
[SPR_VRSAVE
] = sregs
.u
.e
.vrsave
;
1036 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206
) {
1037 env
->spr
[SPR_BOOKE_PIR
] = sregs
.u
.e
.pir
;
1038 env
->spr
[SPR_BOOKE_MCSRR0
] = sregs
.u
.e
.mcsrr0
;
1039 env
->spr
[SPR_BOOKE_MCSRR1
] = sregs
.u
.e
.mcsrr1
;
1040 env
->spr
[SPR_BOOKE_DECAR
] = sregs
.u
.e
.decar
;
1041 env
->spr
[SPR_BOOKE_IVPR
] = sregs
.u
.e
.ivpr
;
1044 if (sregs
.u
.e
.features
& KVM_SREGS_E_64
) {
1045 env
->spr
[SPR_BOOKE_EPCR
] = sregs
.u
.e
.epcr
;
1048 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPRG8
) {
1049 env
->spr
[SPR_BOOKE_SPRG8
] = sregs
.u
.e
.sprg8
;
1052 if (sregs
.u
.e
.features
& KVM_SREGS_E_IVOR
) {
1053 env
->spr
[SPR_BOOKE_IVOR0
] = sregs
.u
.e
.ivor_low
[0];
1054 kvm_sync_excp(env
, POWERPC_EXCP_CRITICAL
, SPR_BOOKE_IVOR0
);
1055 env
->spr
[SPR_BOOKE_IVOR1
] = sregs
.u
.e
.ivor_low
[1];
1056 kvm_sync_excp(env
, POWERPC_EXCP_MCHECK
, SPR_BOOKE_IVOR1
);
1057 env
->spr
[SPR_BOOKE_IVOR2
] = sregs
.u
.e
.ivor_low
[2];
1058 kvm_sync_excp(env
, POWERPC_EXCP_DSI
, SPR_BOOKE_IVOR2
);
1059 env
->spr
[SPR_BOOKE_IVOR3
] = sregs
.u
.e
.ivor_low
[3];
1060 kvm_sync_excp(env
, POWERPC_EXCP_ISI
, SPR_BOOKE_IVOR3
);
1061 env
->spr
[SPR_BOOKE_IVOR4
] = sregs
.u
.e
.ivor_low
[4];
1062 kvm_sync_excp(env
, POWERPC_EXCP_EXTERNAL
, SPR_BOOKE_IVOR4
);
1063 env
->spr
[SPR_BOOKE_IVOR5
] = sregs
.u
.e
.ivor_low
[5];
1064 kvm_sync_excp(env
, POWERPC_EXCP_ALIGN
, SPR_BOOKE_IVOR5
);
1065 env
->spr
[SPR_BOOKE_IVOR6
] = sregs
.u
.e
.ivor_low
[6];
1066 kvm_sync_excp(env
, POWERPC_EXCP_PROGRAM
, SPR_BOOKE_IVOR6
);
1067 env
->spr
[SPR_BOOKE_IVOR7
] = sregs
.u
.e
.ivor_low
[7];
1068 kvm_sync_excp(env
, POWERPC_EXCP_FPU
, SPR_BOOKE_IVOR7
);
1069 env
->spr
[SPR_BOOKE_IVOR8
] = sregs
.u
.e
.ivor_low
[8];
1070 kvm_sync_excp(env
, POWERPC_EXCP_SYSCALL
, SPR_BOOKE_IVOR8
);
1071 env
->spr
[SPR_BOOKE_IVOR9
] = sregs
.u
.e
.ivor_low
[9];
1072 kvm_sync_excp(env
, POWERPC_EXCP_APU
, SPR_BOOKE_IVOR9
);
1073 env
->spr
[SPR_BOOKE_IVOR10
] = sregs
.u
.e
.ivor_low
[10];
1074 kvm_sync_excp(env
, POWERPC_EXCP_DECR
, SPR_BOOKE_IVOR10
);
1075 env
->spr
[SPR_BOOKE_IVOR11
] = sregs
.u
.e
.ivor_low
[11];
1076 kvm_sync_excp(env
, POWERPC_EXCP_FIT
, SPR_BOOKE_IVOR11
);
1077 env
->spr
[SPR_BOOKE_IVOR12
] = sregs
.u
.e
.ivor_low
[12];
1078 kvm_sync_excp(env
, POWERPC_EXCP_WDT
, SPR_BOOKE_IVOR12
);
1079 env
->spr
[SPR_BOOKE_IVOR13
] = sregs
.u
.e
.ivor_low
[13];
1080 kvm_sync_excp(env
, POWERPC_EXCP_DTLB
, SPR_BOOKE_IVOR13
);
1081 env
->spr
[SPR_BOOKE_IVOR14
] = sregs
.u
.e
.ivor_low
[14];
1082 kvm_sync_excp(env
, POWERPC_EXCP_ITLB
, SPR_BOOKE_IVOR14
);
1083 env
->spr
[SPR_BOOKE_IVOR15
] = sregs
.u
.e
.ivor_low
[15];
1084 kvm_sync_excp(env
, POWERPC_EXCP_DEBUG
, SPR_BOOKE_IVOR15
);
1086 if (sregs
.u
.e
.features
& KVM_SREGS_E_SPE
) {
1087 env
->spr
[SPR_BOOKE_IVOR32
] = sregs
.u
.e
.ivor_high
[0];
1088 kvm_sync_excp(env
, POWERPC_EXCP_SPEU
, SPR_BOOKE_IVOR32
);
1089 env
->spr
[SPR_BOOKE_IVOR33
] = sregs
.u
.e
.ivor_high
[1];
1090 kvm_sync_excp(env
, POWERPC_EXCP_EFPDI
, SPR_BOOKE_IVOR33
);
1091 env
->spr
[SPR_BOOKE_IVOR34
] = sregs
.u
.e
.ivor_high
[2];
1092 kvm_sync_excp(env
, POWERPC_EXCP_EFPRI
, SPR_BOOKE_IVOR34
);
1095 if (sregs
.u
.e
.features
& KVM_SREGS_E_PM
) {
1096 env
->spr
[SPR_BOOKE_IVOR35
] = sregs
.u
.e
.ivor_high
[3];
1097 kvm_sync_excp(env
, POWERPC_EXCP_EPERFM
, SPR_BOOKE_IVOR35
);
1100 if (sregs
.u
.e
.features
& KVM_SREGS_E_PC
) {
1101 env
->spr
[SPR_BOOKE_IVOR36
] = sregs
.u
.e
.ivor_high
[4];
1102 kvm_sync_excp(env
, POWERPC_EXCP_DOORI
, SPR_BOOKE_IVOR36
);
1103 env
->spr
[SPR_BOOKE_IVOR37
] = sregs
.u
.e
.ivor_high
[5];
1104 kvm_sync_excp(env
, POWERPC_EXCP_DOORCI
, SPR_BOOKE_IVOR37
);
1108 if (sregs
.u
.e
.features
& KVM_SREGS_E_ARCH206_MMU
) {
1109 env
->spr
[SPR_BOOKE_MAS0
] = sregs
.u
.e
.mas0
;
1110 env
->spr
[SPR_BOOKE_MAS1
] = sregs
.u
.e
.mas1
;
1111 env
->spr
[SPR_BOOKE_MAS2
] = sregs
.u
.e
.mas2
;
1112 env
->spr
[SPR_BOOKE_MAS3
] = sregs
.u
.e
.mas7_3
& 0xffffffff;
1113 env
->spr
[SPR_BOOKE_MAS4
] = sregs
.u
.e
.mas4
;
1114 env
->spr
[SPR_BOOKE_MAS6
] = sregs
.u
.e
.mas6
;
1115 env
->spr
[SPR_BOOKE_MAS7
] = sregs
.u
.e
.mas7_3
>> 32;
1116 env
->spr
[SPR_MMUCFG
] = sregs
.u
.e
.mmucfg
;
1117 env
->spr
[SPR_BOOKE_TLB0CFG
] = sregs
.u
.e
.tlbcfg
[0];
1118 env
->spr
[SPR_BOOKE_TLB1CFG
] = sregs
.u
.e
.tlbcfg
[1];
1121 if (sregs
.u
.e
.features
& KVM_SREGS_EXP
) {
1122 env
->spr
[SPR_BOOKE_EPR
] = sregs
.u
.e
.epr
;
1125 if (sregs
.u
.e
.features
& KVM_SREGS_E_PD
) {
1126 env
->spr
[SPR_BOOKE_EPLC
] = sregs
.u
.e
.eplc
;
1127 env
->spr
[SPR_BOOKE_EPSC
] = sregs
.u
.e
.epsc
;
1130 if (sregs
.u
.e
.impl_id
== KVM_SREGS_E_IMPL_FSL
) {
1131 env
->spr
[SPR_E500_SVR
] = sregs
.u
.e
.impl
.fsl
.svr
;
1132 env
->spr
[SPR_Exxx_MCAR
] = sregs
.u
.e
.impl
.fsl
.mcar
;
1133 env
->spr
[SPR_HID0
] = sregs
.u
.e
.impl
.fsl
.hid0
;
1135 if (sregs
.u
.e
.impl
.fsl
.features
& KVM_SREGS_E_FSL_PIDn
) {
1136 env
->spr
[SPR_BOOKE_PID1
] = sregs
.u
.e
.impl
.fsl
.pid1
;
1137 env
->spr
[SPR_BOOKE_PID2
] = sregs
.u
.e
.impl
.fsl
.pid2
;
1144 static int kvmppc_get_books_sregs(PowerPCCPU
*cpu
)
1146 CPUPPCState
*env
= &cpu
->env
;
1147 struct kvm_sregs sregs
;
1151 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1157 ppc_store_sdr1(env
, sregs
.u
.s
.sdr1
);
1163 * The packed SLB array we get from KVM_GET_SREGS only contains
1164 * information about valid entries. So we flush our internal copy
1165 * to get rid of stale ones, then put all valid SLB entries back
1168 memset(env
->slb
, 0, sizeof(env
->slb
));
1169 for (i
= 0; i
< ARRAY_SIZE(env
->slb
); i
++) {
1170 target_ulong rb
= sregs
.u
.s
.ppc64
.slb
[i
].slbe
;
1171 target_ulong rs
= sregs
.u
.s
.ppc64
.slb
[i
].slbv
;
1173 * Only restore valid entries
1175 if (rb
& SLB_ESID_V
) {
1176 ppc_store_slb(cpu
, rb
& 0xfff, rb
& ~0xfffULL
, rs
);
1182 for (i
= 0; i
< 16; i
++) {
1183 env
->sr
[i
] = sregs
.u
.s
.ppc32
.sr
[i
];
1187 for (i
= 0; i
< 8; i
++) {
1188 env
->DBAT
[0][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] & 0xffffffff;
1189 env
->DBAT
[1][i
] = sregs
.u
.s
.ppc32
.dbat
[i
] >> 32;
1190 env
->IBAT
[0][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] & 0xffffffff;
1191 env
->IBAT
[1][i
] = sregs
.u
.s
.ppc32
.ibat
[i
] >> 32;
1197 int kvm_arch_get_registers(CPUState
*cs
)
1199 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1200 CPUPPCState
*env
= &cpu
->env
;
1201 struct kvm_regs regs
;
1205 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_REGS
, ®s
);
1211 for (i
= 7; i
>= 0; i
--) {
1212 env
->crf
[i
] = cr
& 15;
1216 env
->ctr
= regs
.ctr
;
1218 cpu_write_xer(env
, regs
.xer
);
1219 env
->msr
= regs
.msr
;
1222 env
->spr
[SPR_SRR0
] = regs
.srr0
;
1223 env
->spr
[SPR_SRR1
] = regs
.srr1
;
1225 env
->spr
[SPR_SPRG0
] = regs
.sprg0
;
1226 env
->spr
[SPR_SPRG1
] = regs
.sprg1
;
1227 env
->spr
[SPR_SPRG2
] = regs
.sprg2
;
1228 env
->spr
[SPR_SPRG3
] = regs
.sprg3
;
1229 env
->spr
[SPR_SPRG4
] = regs
.sprg4
;
1230 env
->spr
[SPR_SPRG5
] = regs
.sprg5
;
1231 env
->spr
[SPR_SPRG6
] = regs
.sprg6
;
1232 env
->spr
[SPR_SPRG7
] = regs
.sprg7
;
1234 env
->spr
[SPR_BOOKE_PID
] = regs
.pid
;
1236 for (i
= 0; i
< 32; i
++) {
1237 env
->gpr
[i
] = regs
.gpr
[i
];
1242 if (cap_booke_sregs
) {
1243 ret
= kvmppc_get_booke_sregs(cpu
);
1250 ret
= kvmppc_get_books_sregs(cpu
);
1257 kvm_get_one_spr(cs
, KVM_REG_PPC_HIOR
, SPR_HIOR
);
1264 * We deliberately ignore errors here, for kernels which have
1265 * the ONE_REG calls, but don't support the specific
1266 * registers, there's a reasonable chance things will still
1267 * work, at least until we try to migrate.
1269 for (i
= 0; i
< 1024; i
++) {
1270 uint64_t id
= env
->spr_cb
[i
].one_reg_id
;
1273 kvm_get_one_spr(cs
, id
, i
);
1279 for (i
= 0; i
< ARRAY_SIZE(env
->tm_gpr
); i
++) {
1280 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_GPR(i
), &env
->tm_gpr
[i
]);
1282 for (i
= 0; i
< ARRAY_SIZE(env
->tm_vsr
); i
++) {
1283 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VSR(i
), &env
->tm_vsr
[i
]);
1285 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_CR
, &env
->tm_cr
);
1286 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_LR
, &env
->tm_lr
);
1287 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_CTR
, &env
->tm_ctr
);
1288 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_FPSCR
, &env
->tm_fpscr
);
1289 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_AMR
, &env
->tm_amr
);
1290 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_PPR
, &env
->tm_ppr
);
1291 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VRSAVE
, &env
->tm_vrsave
);
1292 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_VSCR
, &env
->tm_vscr
);
1293 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_DSCR
, &env
->tm_dscr
);
1294 kvm_get_one_reg(cs
, KVM_REG_PPC_TM_TAR
, &env
->tm_tar
);
1298 if (kvm_get_vpa(cs
) < 0) {
1299 trace_kvm_failed_get_vpa();
1303 kvm_get_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &env
->tb_env
->tb_offset
);
1304 kvm_get_one_spr(cs
, KVM_REG_PPC_DPDES
, SPR_DPDES
);
1311 int kvmppc_set_interrupt(PowerPCCPU
*cpu
, int irq
, int level
)
1313 unsigned virq
= level
? KVM_INTERRUPT_SET_LEVEL
: KVM_INTERRUPT_UNSET
;
1315 if (irq
!= PPC_INTERRUPT_EXT
) {
1319 if (!kvm_enabled() || !cap_interrupt_unset
) {
1323 kvm_vcpu_ioctl(CPU(cpu
), KVM_INTERRUPT
, &virq
);
1328 #if defined(TARGET_PPC64)
1329 #define PPC_INPUT_INT PPC970_INPUT_INT
1331 #define PPC_INPUT_INT PPC6xx_INPUT_INT
1334 void kvm_arch_pre_run(CPUState
*cs
, struct kvm_run
*run
)
1339 MemTxAttrs
kvm_arch_post_run(CPUState
*cs
, struct kvm_run
*run
)
1341 return MEMTXATTRS_UNSPECIFIED
;
1344 int kvm_arch_process_async_events(CPUState
*cs
)
1349 static int kvmppc_handle_halt(PowerPCCPU
*cpu
)
1351 CPUState
*cs
= CPU(cpu
);
1352 CPUPPCState
*env
= &cpu
->env
;
1354 if (!(cs
->interrupt_request
& CPU_INTERRUPT_HARD
) && (msr_ee
)) {
1356 cs
->exception_index
= EXCP_HLT
;
1362 /* map dcr access to existing qemu dcr emulation */
1363 static int kvmppc_handle_dcr_read(CPUPPCState
*env
,
1364 uint32_t dcrn
, uint32_t *data
)
1366 if (ppc_dcr_read(env
->dcr_env
, dcrn
, data
) < 0) {
1367 fprintf(stderr
, "Read to unhandled DCR (0x%x)\n", dcrn
);
1373 static int kvmppc_handle_dcr_write(CPUPPCState
*env
,
1374 uint32_t dcrn
, uint32_t data
)
1376 if (ppc_dcr_write(env
->dcr_env
, dcrn
, data
) < 0) {
1377 fprintf(stderr
, "Write to unhandled DCR (0x%x)\n", dcrn
);
1383 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1385 /* Mixed endian case is not handled */
1386 uint32_t sc
= debug_inst_opcode
;
1388 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
,
1390 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&sc
, sizeof(sc
), 1)) {
1397 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
1401 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&sc
, sizeof(sc
), 0) ||
1402 sc
!= debug_inst_opcode
||
1403 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
,
1411 static int find_hw_breakpoint(target_ulong addr
, int type
)
1415 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
)
1416 <= ARRAY_SIZE(hw_debug_points
));
1418 for (n
= 0; n
< nb_hw_breakpoint
+ nb_hw_watchpoint
; n
++) {
1419 if (hw_debug_points
[n
].addr
== addr
&&
1420 hw_debug_points
[n
].type
== type
) {
1428 static int find_hw_watchpoint(target_ulong addr
, int *flag
)
1432 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_ACCESS
);
1434 *flag
= BP_MEM_ACCESS
;
1438 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_WRITE
);
1440 *flag
= BP_MEM_WRITE
;
1444 n
= find_hw_breakpoint(addr
, GDB_WATCHPOINT_READ
);
1446 *flag
= BP_MEM_READ
;
1453 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1454 target_ulong len
, int type
)
1456 if ((nb_hw_breakpoint
+ nb_hw_watchpoint
) >= ARRAY_SIZE(hw_debug_points
)) {
1460 hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
].addr
= addr
;
1461 hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
].type
= type
;
1464 case GDB_BREAKPOINT_HW
:
1465 if (nb_hw_breakpoint
>= max_hw_breakpoint
) {
1469 if (find_hw_breakpoint(addr
, type
) >= 0) {
1476 case GDB_WATCHPOINT_WRITE
:
1477 case GDB_WATCHPOINT_READ
:
1478 case GDB_WATCHPOINT_ACCESS
:
1479 if (nb_hw_watchpoint
>= max_hw_watchpoint
) {
1483 if (find_hw_breakpoint(addr
, type
) >= 0) {
1497 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1498 target_ulong len
, int type
)
1502 n
= find_hw_breakpoint(addr
, type
);
1508 case GDB_BREAKPOINT_HW
:
1512 case GDB_WATCHPOINT_WRITE
:
1513 case GDB_WATCHPOINT_READ
:
1514 case GDB_WATCHPOINT_ACCESS
:
1521 hw_debug_points
[n
] = hw_debug_points
[nb_hw_breakpoint
+ nb_hw_watchpoint
];
1526 void kvm_arch_remove_all_hw_breakpoints(void)
1528 nb_hw_breakpoint
= nb_hw_watchpoint
= 0;
1531 void kvm_arch_update_guest_debug(CPUState
*cs
, struct kvm_guest_debug
*dbg
)
1535 /* Software Breakpoint updates */
1536 if (kvm_sw_breakpoints_active(cs
)) {
1537 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1540 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
)
1541 <= ARRAY_SIZE(hw_debug_points
));
1542 assert((nb_hw_breakpoint
+ nb_hw_watchpoint
) <= ARRAY_SIZE(dbg
->arch
.bp
));
1544 if (nb_hw_breakpoint
+ nb_hw_watchpoint
> 0) {
1545 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1546 memset(dbg
->arch
.bp
, 0, sizeof(dbg
->arch
.bp
));
1547 for (n
= 0; n
< nb_hw_breakpoint
+ nb_hw_watchpoint
; n
++) {
1548 switch (hw_debug_points
[n
].type
) {
1549 case GDB_BREAKPOINT_HW
:
1550 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_BREAKPOINT
;
1552 case GDB_WATCHPOINT_WRITE
:
1553 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_WRITE
;
1555 case GDB_WATCHPOINT_READ
:
1556 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_READ
;
1558 case GDB_WATCHPOINT_ACCESS
:
1559 dbg
->arch
.bp
[n
].type
= KVMPPC_DEBUG_WATCH_WRITE
|
1560 KVMPPC_DEBUG_WATCH_READ
;
1563 cpu_abort(cs
, "Unsupported breakpoint type\n");
1565 dbg
->arch
.bp
[n
].addr
= hw_debug_points
[n
].addr
;
1570 static int kvm_handle_hw_breakpoint(CPUState
*cs
,
1571 struct kvm_debug_exit_arch
*arch_info
)
1577 if (nb_hw_breakpoint
+ nb_hw_watchpoint
> 0) {
1578 if (arch_info
->status
& KVMPPC_DEBUG_BREAKPOINT
) {
1579 n
= find_hw_breakpoint(arch_info
->address
, GDB_BREAKPOINT_HW
);
1583 } else if (arch_info
->status
& (KVMPPC_DEBUG_WATCH_READ
|
1584 KVMPPC_DEBUG_WATCH_WRITE
)) {
1585 n
= find_hw_watchpoint(arch_info
->address
, &flag
);
1588 cs
->watchpoint_hit
= &hw_watchpoint
;
1589 hw_watchpoint
.vaddr
= hw_debug_points
[n
].addr
;
1590 hw_watchpoint
.flags
= flag
;
1597 static int kvm_handle_singlestep(void)
1602 static int kvm_handle_sw_breakpoint(void)
1607 static int kvm_handle_debug(PowerPCCPU
*cpu
, struct kvm_run
*run
)
1609 CPUState
*cs
= CPU(cpu
);
1610 CPUPPCState
*env
= &cpu
->env
;
1611 struct kvm_debug_exit_arch
*arch_info
= &run
->debug
.arch
;
1613 if (cs
->singlestep_enabled
) {
1614 return kvm_handle_singlestep();
1617 if (arch_info
->status
) {
1618 return kvm_handle_hw_breakpoint(cs
, arch_info
);
1621 if (kvm_find_sw_breakpoint(cs
, arch_info
->address
)) {
1622 return kvm_handle_sw_breakpoint();
1626 * QEMU is not able to handle debug exception, so inject
1627 * program exception to guest;
1628 * Yes program exception NOT debug exception !!
1629 * When QEMU is using debug resources then debug exception must
1630 * be always set. To achieve this we set MSR_DE and also set
1631 * MSRP_DEP so guest cannot change MSR_DE.
1632 * When emulating debug resource for guest we want guest
1633 * to control MSR_DE (enable/disable debug interrupt on need).
1634 * Supporting both configurations are NOT possible.
1635 * So the result is that we cannot share debug resources
1636 * between QEMU and Guest on BOOKE architecture.
1637 * In the current design QEMU gets the priority over guest,
1638 * this means that if QEMU is using debug resources then guest
1640 * For software breakpoint QEMU uses a privileged instruction;
1641 * So there cannot be any reason that we are here for guest
1642 * set debug exception, only possibility is guest executed a
1643 * privileged / illegal instruction and that's why we are
1644 * injecting a program interrupt.
1646 cpu_synchronize_state(cs
);
1648 * env->nip is PC, so increment this by 4 to use
1649 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1652 cs
->exception_index
= POWERPC_EXCP_PROGRAM
;
1653 env
->error_code
= POWERPC_EXCP_INVAL
;
1654 ppc_cpu_do_interrupt(cs
);
1659 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
1661 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1662 CPUPPCState
*env
= &cpu
->env
;
1665 qemu_mutex_lock_iothread();
1667 switch (run
->exit_reason
) {
1669 if (run
->dcr
.is_write
) {
1670 trace_kvm_handle_dcr_write();
1671 ret
= kvmppc_handle_dcr_write(env
, run
->dcr
.dcrn
, run
->dcr
.data
);
1673 trace_kvm_handle_dcr_read();
1674 ret
= kvmppc_handle_dcr_read(env
, run
->dcr
.dcrn
, &run
->dcr
.data
);
1678 trace_kvm_handle_halt();
1679 ret
= kvmppc_handle_halt(cpu
);
1681 #if defined(TARGET_PPC64)
1682 case KVM_EXIT_PAPR_HCALL
:
1683 trace_kvm_handle_papr_hcall();
1684 run
->papr_hcall
.ret
= spapr_hypercall(cpu
,
1686 run
->papr_hcall
.args
);
1691 trace_kvm_handle_epr();
1692 run
->epr
.epr
= ldl_phys(cs
->as
, env
->mpic_iack
);
1695 case KVM_EXIT_WATCHDOG
:
1696 trace_kvm_handle_watchdog_expiry();
1697 watchdog_perform_action();
1701 case KVM_EXIT_DEBUG
:
1702 trace_kvm_handle_debug_exception();
1703 if (kvm_handle_debug(cpu
, run
)) {
1707 /* re-enter, this exception was guest-internal */
1712 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
1717 qemu_mutex_unlock_iothread();
1721 int kvmppc_or_tsr_bits(PowerPCCPU
*cpu
, uint32_t tsr_bits
)
1723 CPUState
*cs
= CPU(cpu
);
1724 uint32_t bits
= tsr_bits
;
1725 struct kvm_one_reg reg
= {
1726 .id
= KVM_REG_PPC_OR_TSR
,
1727 .addr
= (uintptr_t) &bits
,
1730 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1733 int kvmppc_clear_tsr_bits(PowerPCCPU
*cpu
, uint32_t tsr_bits
)
1736 CPUState
*cs
= CPU(cpu
);
1737 uint32_t bits
= tsr_bits
;
1738 struct kvm_one_reg reg
= {
1739 .id
= KVM_REG_PPC_CLEAR_TSR
,
1740 .addr
= (uintptr_t) &bits
,
1743 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1746 int kvmppc_set_tcr(PowerPCCPU
*cpu
)
1748 CPUState
*cs
= CPU(cpu
);
1749 CPUPPCState
*env
= &cpu
->env
;
1750 uint32_t tcr
= env
->spr
[SPR_BOOKE_TCR
];
1752 struct kvm_one_reg reg
= {
1753 .id
= KVM_REG_PPC_TCR
,
1754 .addr
= (uintptr_t) &tcr
,
1757 return kvm_vcpu_ioctl(cs
, KVM_SET_ONE_REG
, ®
);
1760 int kvmppc_booke_watchdog_enable(PowerPCCPU
*cpu
)
1762 CPUState
*cs
= CPU(cpu
);
1765 if (!kvm_enabled()) {
1769 if (!cap_ppc_watchdog
) {
1770 printf("warning: KVM does not support watchdog");
1774 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_BOOKE_WATCHDOG
, 0);
1776 fprintf(stderr
, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1777 __func__
, strerror(-ret
));
1784 static int read_cpuinfo(const char *field
, char *value
, int len
)
1788 int field_len
= strlen(field
);
1791 f
= fopen("/proc/cpuinfo", "r");
1797 if (!fgets(line
, sizeof(line
), f
)) {
1800 if (!strncmp(line
, field
, field_len
)) {
1801 pstrcpy(value
, len
, line
);
1812 uint32_t kvmppc_get_tbfreq(void)
1816 uint32_t retval
= NANOSECONDS_PER_SECOND
;
1818 if (read_cpuinfo("timebase", line
, sizeof(line
))) {
1822 ns
= strchr(line
, ':');
1832 bool kvmppc_get_host_serial(char **value
)
1834 return g_file_get_contents("/proc/device-tree/system-id", value
, NULL
,
1838 bool kvmppc_get_host_model(char **value
)
1840 return g_file_get_contents("/proc/device-tree/model", value
, NULL
, NULL
);
1843 /* Try to find a device tree node for a CPU with clock-frequency property */
1844 static int kvmppc_find_cpu_dt(char *buf
, int buf_len
)
1846 struct dirent
*dirp
;
1849 dp
= opendir(PROC_DEVTREE_CPU
);
1851 printf("Can't open directory " PROC_DEVTREE_CPU
"\n");
1856 while ((dirp
= readdir(dp
)) != NULL
) {
1858 snprintf(buf
, buf_len
, "%s%s/clock-frequency", PROC_DEVTREE_CPU
,
1860 f
= fopen(buf
, "r");
1862 snprintf(buf
, buf_len
, "%s%s", PROC_DEVTREE_CPU
, dirp
->d_name
);
1869 if (buf
[0] == '\0') {
1870 printf("Unknown host!\n");
1877 static uint64_t kvmppc_read_int_dt(const char *filename
)
1886 f
= fopen(filename
, "rb");
1891 len
= fread(&u
, 1, sizeof(u
), f
);
1895 /* property is a 32-bit quantity */
1896 return be32_to_cpu(u
.v32
);
1898 return be64_to_cpu(u
.v64
);
1905 * Read a CPU node property from the host device tree that's a single
1906 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1907 * (can't find or open the property, or doesn't understand the format)
1909 static uint64_t kvmppc_read_int_cpu_dt(const char *propname
)
1911 char buf
[PATH_MAX
], *tmp
;
1914 if (kvmppc_find_cpu_dt(buf
, sizeof(buf
))) {
1918 tmp
= g_strdup_printf("%s/%s", buf
, propname
);
1919 val
= kvmppc_read_int_dt(tmp
);
1925 uint64_t kvmppc_get_clockfreq(void)
1927 return kvmppc_read_int_cpu_dt("clock-frequency");
1930 static int kvmppc_get_dec_bits(void)
1932 int nr_bits
= kvmppc_read_int_cpu_dt("ibm,dec-bits");
1940 static int kvmppc_get_pvinfo(CPUPPCState
*env
, struct kvm_ppc_pvinfo
*pvinfo
)
1942 CPUState
*cs
= env_cpu(env
);
1944 if (kvm_vm_check_extension(cs
->kvm_state
, KVM_CAP_PPC_GET_PVINFO
) &&
1945 !kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_GET_PVINFO
, pvinfo
)) {
1952 int kvmppc_get_hasidle(CPUPPCState
*env
)
1954 struct kvm_ppc_pvinfo pvinfo
;
1956 if (!kvmppc_get_pvinfo(env
, &pvinfo
) &&
1957 (pvinfo
.flags
& KVM_PPC_PVINFO_FLAGS_EV_IDLE
)) {
1964 int kvmppc_get_hypercall(CPUPPCState
*env
, uint8_t *buf
, int buf_len
)
1966 uint32_t *hc
= (uint32_t *)buf
;
1967 struct kvm_ppc_pvinfo pvinfo
;
1969 if (!kvmppc_get_pvinfo(env
, &pvinfo
)) {
1970 memcpy(buf
, pvinfo
.hcall
, buf_len
);
1975 * Fallback to always fail hypercalls regardless of endianness:
1977 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
1979 * b .+8 (becomes nop in wrong endian)
1980 * bswap32(li r3, -1)
1983 hc
[0] = cpu_to_be32(0x08000048);
1984 hc
[1] = cpu_to_be32(0x3860ffff);
1985 hc
[2] = cpu_to_be32(0x48000008);
1986 hc
[3] = cpu_to_be32(bswap32(0x3860ffff));
1991 static inline int kvmppc_enable_hcall(KVMState
*s
, target_ulong hcall
)
1993 return kvm_vm_enable_cap(s
, KVM_CAP_PPC_ENABLE_HCALL
, 0, hcall
, 1);
1996 void kvmppc_enable_logical_ci_hcalls(void)
1999 * FIXME: it would be nice if we could detect the cases where
2000 * we're using a device which requires the in kernel
2001 * implementation of these hcalls, but the kernel lacks them and
2002 * produce a warning.
2004 kvmppc_enable_hcall(kvm_state
, H_LOGICAL_CI_LOAD
);
2005 kvmppc_enable_hcall(kvm_state
, H_LOGICAL_CI_STORE
);
2008 void kvmppc_enable_set_mode_hcall(void)
2010 kvmppc_enable_hcall(kvm_state
, H_SET_MODE
);
2013 void kvmppc_enable_clear_ref_mod_hcalls(void)
2015 kvmppc_enable_hcall(kvm_state
, H_CLEAR_REF
);
2016 kvmppc_enable_hcall(kvm_state
, H_CLEAR_MOD
);
2019 void kvmppc_enable_h_page_init(void)
2021 kvmppc_enable_hcall(kvm_state
, H_PAGE_INIT
);
2024 void kvmppc_set_papr(PowerPCCPU
*cpu
)
2026 CPUState
*cs
= CPU(cpu
);
2029 if (!kvm_enabled()) {
2033 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_PAPR
, 0);
2035 error_report("This vCPU type or KVM version does not support PAPR");
2040 * Update the capability flag so we sync the right information
2046 int kvmppc_set_compat(PowerPCCPU
*cpu
, uint32_t compat_pvr
)
2048 return kvm_set_one_reg(CPU(cpu
), KVM_REG_PPC_ARCH_COMPAT
, &compat_pvr
);
2051 void kvmppc_set_mpic_proxy(PowerPCCPU
*cpu
, int mpic_proxy
)
2053 CPUState
*cs
= CPU(cpu
);
2056 ret
= kvm_vcpu_enable_cap(cs
, KVM_CAP_PPC_EPR
, 0, mpic_proxy
);
2057 if (ret
&& mpic_proxy
) {
2058 error_report("This KVM version does not support EPR");
2063 int kvmppc_smt_threads(void)
2065 return cap_ppc_smt
? cap_ppc_smt
: 1;
2068 int kvmppc_set_smt_threads(int smt
)
2072 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_SMT
, 0, smt
, 0);
2079 void kvmppc_hint_smt_possible(Error
**errp
)
2085 assert(kvm_enabled());
2086 if (cap_ppc_smt_possible
) {
2087 g
= g_string_new("Available VSMT modes:");
2088 for (i
= 63; i
>= 0; i
--) {
2089 if ((1UL << i
) & cap_ppc_smt_possible
) {
2090 g_string_append_printf(g
, " %lu", (1UL << i
));
2093 s
= g_string_free(g
, false);
2094 error_append_hint(errp
, "%s.\n", s
);
2097 error_append_hint(errp
,
2098 "This KVM seems to be too old to support VSMT.\n");
2104 uint64_t kvmppc_rma_size(uint64_t current_size
, unsigned int hash_shift
)
2106 struct kvm_ppc_smmu_info info
;
2107 long rampagesize
, best_page_shift
;
2111 * Find the largest hardware supported page size that's less than
2112 * or equal to the (logical) backing page size of guest RAM
2114 kvm_get_smmu_info(&info
, &error_fatal
);
2115 rampagesize
= qemu_minrampagesize();
2116 best_page_shift
= 0;
2118 for (i
= 0; i
< KVM_PPC_PAGE_SIZES_MAX_SZ
; i
++) {
2119 struct kvm_ppc_one_seg_page_size
*sps
= &info
.sps
[i
];
2121 if (!sps
->page_shift
) {
2125 if ((sps
->page_shift
> best_page_shift
)
2126 && ((1UL << sps
->page_shift
) <= rampagesize
)) {
2127 best_page_shift
= sps
->page_shift
;
2131 return MIN(current_size
,
2132 1ULL << (best_page_shift
+ hash_shift
- 7));
2136 bool kvmppc_spapr_use_multitce(void)
2138 return cap_spapr_multitce
;
2141 int kvmppc_spapr_enable_inkernel_multitce(void)
2145 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_ENABLE_HCALL
, 0,
2146 H_PUT_TCE_INDIRECT
, 1);
2148 ret
= kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_ENABLE_HCALL
, 0,
2155 void *kvmppc_create_spapr_tce(uint32_t liobn
, uint32_t page_shift
,
2156 uint64_t bus_offset
, uint32_t nb_table
,
2157 int *pfd
, bool need_vfio
)
2164 * Must set fd to -1 so we don't try to munmap when called for
2165 * destroying the table, which the upper layers -will- do
2168 if (!cap_spapr_tce
|| (need_vfio
&& !cap_spapr_vfio
)) {
2172 if (cap_spapr_tce_64
) {
2173 struct kvm_create_spapr_tce_64 args
= {
2175 .page_shift
= page_shift
,
2176 .offset
= bus_offset
>> page_shift
,
2180 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE_64
, &args
);
2183 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2187 } else if (cap_spapr_tce
) {
2188 uint64_t window_size
= (uint64_t) nb_table
<< page_shift
;
2189 struct kvm_create_spapr_tce args
= {
2191 .window_size
= window_size
,
2193 if ((window_size
!= args
.window_size
) || bus_offset
) {
2196 fd
= kvm_vm_ioctl(kvm_state
, KVM_CREATE_SPAPR_TCE
, &args
);
2198 fprintf(stderr
, "KVM: Failed to create TCE table for liobn 0x%x\n",
2206 len
= nb_table
* sizeof(uint64_t);
2207 /* FIXME: round this up to page size */
2209 table
= mmap(NULL
, len
, PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, 0);
2210 if (table
== MAP_FAILED
) {
2211 fprintf(stderr
, "KVM: Failed to map TCE table for liobn 0x%x\n",
2221 int kvmppc_remove_spapr_tce(void *table
, int fd
, uint32_t nb_table
)
2229 len
= nb_table
* sizeof(uint64_t);
2230 if ((munmap(table
, len
) < 0) ||
2232 fprintf(stderr
, "KVM: Unexpected error removing TCE table: %s",
2234 /* Leak the table */
2240 int kvmppc_reset_htab(int shift_hint
)
2242 uint32_t shift
= shift_hint
;
2244 if (!kvm_enabled()) {
2245 /* Full emulation, tell caller to allocate htab itself */
2248 if (kvm_vm_check_extension(kvm_state
, KVM_CAP_PPC_ALLOC_HTAB
)) {
2250 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_ALLOCATE_HTAB
, &shift
);
2251 if (ret
== -ENOTTY
) {
2253 * At least some versions of PR KVM advertise the
2254 * capability, but don't implement the ioctl(). Oops.
2255 * Return 0 so that we allocate the htab in qemu, as is
2259 } else if (ret
< 0) {
2266 * We have a kernel that predates the htab reset calls. For PR
2267 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2268 * this era, it has allocated a 16MB fixed size hash table
2271 if (kvmppc_is_pr(kvm_state
)) {
2272 /* PR - tell caller to allocate htab */
2275 /* HV - assume 16MB kernel allocated htab */
2280 static inline uint32_t mfpvr(void)
2289 static void alter_insns(uint64_t *word
, uint64_t flags
, bool on
)
2298 static void kvmppc_host_cpu_class_init(ObjectClass
*oc
, void *data
)
2300 PowerPCCPUClass
*pcc
= POWERPC_CPU_CLASS(oc
);
2301 uint32_t dcache_size
= kvmppc_read_int_cpu_dt("d-cache-size");
2302 uint32_t icache_size
= kvmppc_read_int_cpu_dt("i-cache-size");
2304 /* Now fix up the class with information we can query from the host */
2307 alter_insns(&pcc
->insns_flags
, PPC_ALTIVEC
,
2308 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_ALTIVEC
);
2309 alter_insns(&pcc
->insns_flags2
, PPC2_VSX
,
2310 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_VSX
);
2311 alter_insns(&pcc
->insns_flags2
, PPC2_DFP
,
2312 qemu_getauxval(AT_HWCAP
) & PPC_FEATURE_HAS_DFP
);
2314 if (dcache_size
!= -1) {
2315 pcc
->l1_dcache_size
= dcache_size
;
2318 if (icache_size
!= -1) {
2319 pcc
->l1_icache_size
= icache_size
;
2322 #if defined(TARGET_PPC64)
2323 pcc
->radix_page_info
= kvm_get_radix_page_info();
2325 if ((pcc
->pvr
& 0xffffff00) == CPU_POWERPC_POWER9_DD1
) {
2327 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2328 * compliant. More importantly, advertising ISA 3.00
2329 * architected mode may prevent guests from activating
2330 * necessary DD1 workarounds.
2332 pcc
->pcr_supported
&= ~(PCR_COMPAT_3_00
| PCR_COMPAT_2_07
2333 | PCR_COMPAT_2_06
| PCR_COMPAT_2_05
);
2335 #endif /* defined(TARGET_PPC64) */
2338 bool kvmppc_has_cap_epr(void)
2343 bool kvmppc_has_cap_fixup_hcalls(void)
2345 return cap_fixup_hcalls
;
2348 bool kvmppc_has_cap_htm(void)
2353 bool kvmppc_has_cap_mmu_radix(void)
2355 return cap_mmu_radix
;
2358 bool kvmppc_has_cap_mmu_hash_v3(void)
2360 return cap_mmu_hash_v3
;
2363 static bool kvmppc_power8_host(void)
2368 uint32_t base_pvr
= CPU_POWERPC_POWER_SERVER_MASK
& mfpvr();
2369 ret
= (base_pvr
== CPU_POWERPC_POWER8E_BASE
) ||
2370 (base_pvr
== CPU_POWERPC_POWER8NVL_BASE
) ||
2371 (base_pvr
== CPU_POWERPC_POWER8_BASE
);
2373 #endif /* TARGET_PPC64 */
2377 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c
)
2379 bool l1d_thread_priv_req
= !kvmppc_power8_host();
2381 if (~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_L1D_FLUSH_PR
) {
2383 } else if ((!l1d_thread_priv_req
||
2384 c
.character
& c
.character_mask
& H_CPU_CHAR_L1D_THREAD_PRIV
) &&
2385 (c
.character
& c
.character_mask
2386 & (H_CPU_CHAR_L1D_FLUSH_ORI30
| H_CPU_CHAR_L1D_FLUSH_TRIG2
))) {
2393 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c
)
2395 if (~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_BNDS_CHK_SPEC_BAR
) {
2397 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_SPEC_BAR_ORI31
) {
2404 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c
)
2406 if ((~c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_FLUSH_COUNT_CACHE
) &&
2407 (~c
.character
& c
.character_mask
& H_CPU_CHAR_CACHE_COUNT_DIS
) &&
2408 (~c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTRL_SERIALISED
)) {
2409 return SPAPR_CAP_FIXED_NA
;
2410 } else if (c
.behaviour
& c
.behaviour_mask
& H_CPU_BEHAV_FLUSH_COUNT_CACHE
) {
2411 return SPAPR_CAP_WORKAROUND
;
2412 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_CACHE_COUNT_DIS
) {
2413 return SPAPR_CAP_FIXED_CCD
;
2414 } else if (c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTRL_SERIALISED
) {
2415 return SPAPR_CAP_FIXED_IBS
;
2421 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c
)
2423 if (c
.character
& c
.character_mask
& H_CPU_CHAR_BCCTR_FLUSH_ASSIST
) {
2429 bool kvmppc_has_cap_xive(void)
2434 static void kvmppc_get_cpu_characteristics(KVMState
*s
)
2436 struct kvm_ppc_cpu_char c
;
2440 cap_ppc_safe_cache
= 0;
2441 cap_ppc_safe_bounds_check
= 0;
2442 cap_ppc_safe_indirect_branch
= 0;
2444 ret
= kvm_vm_check_extension(s
, KVM_CAP_PPC_GET_CPU_CHAR
);
2448 ret
= kvm_vm_ioctl(s
, KVM_PPC_GET_CPU_CHAR
, &c
);
2453 cap_ppc_safe_cache
= parse_cap_ppc_safe_cache(c
);
2454 cap_ppc_safe_bounds_check
= parse_cap_ppc_safe_bounds_check(c
);
2455 cap_ppc_safe_indirect_branch
= parse_cap_ppc_safe_indirect_branch(c
);
2456 cap_ppc_count_cache_flush_assist
=
2457 parse_cap_ppc_count_cache_flush_assist(c
);
2460 int kvmppc_get_cap_safe_cache(void)
2462 return cap_ppc_safe_cache
;
2465 int kvmppc_get_cap_safe_bounds_check(void)
2467 return cap_ppc_safe_bounds_check
;
2470 int kvmppc_get_cap_safe_indirect_branch(void)
2472 return cap_ppc_safe_indirect_branch
;
2475 int kvmppc_get_cap_count_cache_flush_assist(void)
2477 return cap_ppc_count_cache_flush_assist
;
2480 bool kvmppc_has_cap_nested_kvm_hv(void)
2482 return !!cap_ppc_nested_kvm_hv
;
2485 int kvmppc_set_cap_nested_kvm_hv(int enable
)
2487 return kvm_vm_enable_cap(kvm_state
, KVM_CAP_PPC_NESTED_HV
, 0, enable
);
2490 bool kvmppc_has_cap_spapr_vfio(void)
2492 return cap_spapr_vfio
;
2495 int kvmppc_get_cap_large_decr(void)
2497 return cap_large_decr
;
2500 int kvmppc_enable_cap_large_decr(PowerPCCPU
*cpu
, int enable
)
2502 CPUState
*cs
= CPU(cpu
);
2505 kvm_get_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2506 /* Do we need to modify the LPCR? */
2507 if (!!(lpcr
& LPCR_LD
) != !!enable
) {
2513 kvm_set_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2514 kvm_get_one_reg(cs
, KVM_REG_PPC_LPCR_64
, &lpcr
);
2516 if (!!(lpcr
& LPCR_LD
) != !!enable
) {
2524 PowerPCCPUClass
*kvm_ppc_get_host_cpu_class(void)
2526 uint32_t host_pvr
= mfpvr();
2527 PowerPCCPUClass
*pvr_pcc
;
2529 pvr_pcc
= ppc_cpu_class_by_pvr(host_pvr
);
2530 if (pvr_pcc
== NULL
) {
2531 pvr_pcc
= ppc_cpu_class_by_pvr_mask(host_pvr
);
2537 static int kvm_ppc_register_host_cpu_type(MachineState
*ms
)
2539 TypeInfo type_info
= {
2540 .name
= TYPE_HOST_POWERPC_CPU
,
2541 .class_init
= kvmppc_host_cpu_class_init
,
2543 MachineClass
*mc
= MACHINE_GET_CLASS(ms
);
2544 PowerPCCPUClass
*pvr_pcc
;
2549 pvr_pcc
= kvm_ppc_get_host_cpu_class();
2550 if (pvr_pcc
== NULL
) {
2553 type_info
.parent
= object_class_get_name(OBJECT_CLASS(pvr_pcc
));
2554 type_register(&type_info
);
2555 if (object_dynamic_cast(OBJECT(ms
), TYPE_SPAPR_MACHINE
)) {
2556 /* override TCG default cpu type with 'host' cpu model */
2557 mc
->default_cpu_type
= TYPE_HOST_POWERPC_CPU
;
2560 oc
= object_class_by_name(type_info
.name
);
2564 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2565 * we want "POWER8" to be a "family" alias that points to the current
2566 * host CPU type, too)
2568 dc
= DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc
));
2569 for (i
= 0; ppc_cpu_aliases
[i
].alias
!= NULL
; i
++) {
2570 if (strcasecmp(ppc_cpu_aliases
[i
].alias
, dc
->desc
) == 0) {
2573 ppc_cpu_aliases
[i
].model
= g_strdup(object_class_get_name(oc
));
2574 suffix
= strstr(ppc_cpu_aliases
[i
].model
, POWERPC_CPU_TYPE_SUFFIX
);
2585 int kvmppc_define_rtas_kernel_token(uint32_t token
, const char *function
)
2587 struct kvm_rtas_token_args args
= {
2591 if (!kvm_check_extension(kvm_state
, KVM_CAP_PPC_RTAS
)) {
2595 strncpy(args
.name
, function
, sizeof(args
.name
) - 1);
2597 return kvm_vm_ioctl(kvm_state
, KVM_PPC_RTAS_DEFINE_TOKEN
, &args
);
2600 int kvmppc_get_htab_fd(bool write
, uint64_t index
, Error
**errp
)
2602 struct kvm_get_htab_fd s
= {
2603 .flags
= write
? KVM_GET_HTAB_WRITE
: 0,
2604 .start_index
= index
,
2609 error_setg(errp
, "KVM version doesn't support %s the HPT",
2610 write
? "writing" : "reading");
2614 ret
= kvm_vm_ioctl(kvm_state
, KVM_PPC_GET_HTAB_FD
, &s
);
2616 error_setg(errp
, "Unable to open fd for %s HPT %s KVM: %s",
2617 write
? "writing" : "reading", write
? "to" : "from",
2625 int kvmppc_save_htab(QEMUFile
*f
, int fd
, size_t bufsize
, int64_t max_ns
)
2627 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2628 uint8_t buf
[bufsize
];
2632 rc
= read(fd
, buf
, bufsize
);
2634 fprintf(stderr
, "Error reading data from KVM HTAB fd: %s\n",
2638 uint8_t *buffer
= buf
;
2641 struct kvm_get_htab_header
*head
=
2642 (struct kvm_get_htab_header
*) buffer
;
2643 size_t chunksize
= sizeof(*head
) +
2644 HASH_PTE_SIZE_64
* head
->n_valid
;
2646 qemu_put_be32(f
, head
->index
);
2647 qemu_put_be16(f
, head
->n_valid
);
2648 qemu_put_be16(f
, head
->n_invalid
);
2649 qemu_put_buffer(f
, (void *)(head
+ 1),
2650 HASH_PTE_SIZE_64
* head
->n_valid
);
2652 buffer
+= chunksize
;
2658 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) < max_ns
)));
2660 return (rc
== 0) ? 1 : 0;
2663 int kvmppc_load_htab_chunk(QEMUFile
*f
, int fd
, uint32_t index
,
2664 uint16_t n_valid
, uint16_t n_invalid
)
2666 struct kvm_get_htab_header
*buf
;
2667 size_t chunksize
= sizeof(*buf
) + n_valid
* HASH_PTE_SIZE_64
;
2670 buf
= alloca(chunksize
);
2672 buf
->n_valid
= n_valid
;
2673 buf
->n_invalid
= n_invalid
;
2675 qemu_get_buffer(f
, (void *)(buf
+ 1), HASH_PTE_SIZE_64
* n_valid
);
2677 rc
= write(fd
, buf
, chunksize
);
2679 fprintf(stderr
, "Error writing KVM hash table: %s\n",
2683 if (rc
!= chunksize
) {
2684 /* We should never get a short write on a single chunk */
2685 fprintf(stderr
, "Short write, restoring KVM hash table\n");
2691 bool kvm_arch_stop_on_emulation_error(CPUState
*cpu
)
2696 void kvm_arch_init_irq_routing(KVMState
*s
)
2700 void kvmppc_read_hptes(ppc_hash_pte64_t
*hptes
, hwaddr ptex
, int n
)
2705 fd
= kvmppc_get_htab_fd(false, ptex
, &error_abort
);
2709 struct kvm_get_htab_header
*hdr
;
2710 int m
= n
< HPTES_PER_GROUP
? n
: HPTES_PER_GROUP
;
2711 char buf
[sizeof(*hdr
) + m
* HASH_PTE_SIZE_64
];
2713 rc
= read(fd
, buf
, sizeof(buf
));
2715 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2718 hdr
= (struct kvm_get_htab_header
*)buf
;
2719 while ((i
< n
) && ((char *)hdr
< (buf
+ rc
))) {
2720 int invalid
= hdr
->n_invalid
, valid
= hdr
->n_valid
;
2722 if (hdr
->index
!= (ptex
+ i
)) {
2723 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2724 " != (%"HWADDR_PRIu
" + %d", hdr
->index
, ptex
, i
);
2727 if (n
- i
< valid
) {
2730 memcpy(hptes
+ i
, hdr
+ 1, HASH_PTE_SIZE_64
* valid
);
2733 if ((n
- i
) < invalid
) {
2736 memset(hptes
+ i
, 0, invalid
* HASH_PTE_SIZE_64
);
2739 hdr
= (struct kvm_get_htab_header
*)
2740 ((char *)(hdr
+ 1) + HASH_PTE_SIZE_64
* hdr
->n_valid
);
2747 void kvmppc_write_hpte(hwaddr ptex
, uint64_t pte0
, uint64_t pte1
)
2751 struct kvm_get_htab_header hdr
;
2756 fd
= kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort
);
2758 buf
.hdr
.n_valid
= 1;
2759 buf
.hdr
.n_invalid
= 0;
2760 buf
.hdr
.index
= ptex
;
2761 buf
.pte0
= cpu_to_be64(pte0
);
2762 buf
.pte1
= cpu_to_be64(pte1
);
2764 rc
= write(fd
, &buf
, sizeof(buf
));
2765 if (rc
!= sizeof(buf
)) {
2766 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2771 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry
*route
,
2772 uint64_t address
, uint32_t data
, PCIDevice
*dev
)
2777 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry
*route
,
2778 int vector
, PCIDevice
*dev
)
2783 int kvm_arch_release_virq_post(int virq
)
2788 int kvm_arch_msi_data_to_gsi(uint32_t data
)
2790 return data
& 0xffff;
2793 int kvmppc_enable_hwrng(void)
2795 if (!kvm_enabled() || !kvm_check_extension(kvm_state
, KVM_CAP_PPC_HWRNG
)) {
2799 return kvmppc_enable_hcall(kvm_state
, H_RANDOM
);
2802 void kvmppc_check_papr_resize_hpt(Error
**errp
)
2804 if (!kvm_enabled()) {
2805 return; /* No KVM, we're good */
2808 if (cap_resize_hpt
) {
2809 return; /* Kernel has explicit support, we're good */
2812 /* Otherwise fallback on looking for PR KVM */
2813 if (kvmppc_is_pr(kvm_state
)) {
2818 "Hash page table resizing not available with this KVM version");
2821 int kvmppc_resize_hpt_prepare(PowerPCCPU
*cpu
, target_ulong flags
, int shift
)
2823 CPUState
*cs
= CPU(cpu
);
2824 struct kvm_ppc_resize_hpt rhpt
= {
2829 if (!cap_resize_hpt
) {
2833 return kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_RESIZE_HPT_PREPARE
, &rhpt
);
2836 int kvmppc_resize_hpt_commit(PowerPCCPU
*cpu
, target_ulong flags
, int shift
)
2838 CPUState
*cs
= CPU(cpu
);
2839 struct kvm_ppc_resize_hpt rhpt
= {
2844 if (!cap_resize_hpt
) {
2848 return kvm_vm_ioctl(cs
->kvm_state
, KVM_PPC_RESIZE_HPT_COMMIT
, &rhpt
);
2852 * This is a helper function to detect a post migration scenario
2853 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2854 * the guest kernel can't handle a PVR value other than the actual host
2855 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2857 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2858 * (so, we're HV), return true. The workaround itself is done in
2861 * The order here is important: we'll only check for KVM PR as a
2862 * fallback if the guest kernel can't handle the situation itself.
2863 * We need to avoid as much as possible querying the running KVM type
2866 bool kvmppc_pvr_workaround_required(PowerPCCPU
*cpu
)
2868 CPUState
*cs
= CPU(cpu
);
2870 if (!kvm_enabled()) {
2874 if (cap_ppc_pvr_compat
) {
2878 return !kvmppc_is_pr(cs
->kvm_state
);
2881 void kvmppc_set_reg_ppc_online(PowerPCCPU
*cpu
, unsigned int online
)
2883 CPUState
*cs
= CPU(cpu
);
2885 if (kvm_enabled()) {
2886 kvm_set_one_reg(cs
, KVM_REG_PPC_ONLINE
, &online
);
2890 void kvmppc_set_reg_tb_offset(PowerPCCPU
*cpu
, int64_t tb_offset
)
2892 CPUState
*cs
= CPU(cpu
);
2894 if (kvm_enabled()) {
2895 kvm_set_one_reg(cs
, KVM_REG_PPC_TB_OFFSET
, &tb_offset
);