2 * APIC support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
20 #include "hw/i386/apic.h"
21 #include "hw/i386/apic_internal.h"
23 #include "sysemu/kvm.h"
25 #include "hw/sysbus.h"
27 static int apic_irq_delivered
;
28 bool apic_report_tpr_access
;
30 void cpu_set_apic_base(DeviceState
*dev
, uint64_t val
)
32 trace_cpu_set_apic_base(val
);
35 APICCommonState
*s
= APIC_COMMON(dev
);
36 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
37 info
->set_base(s
, val
);
41 uint64_t cpu_get_apic_base(DeviceState
*dev
)
44 APICCommonState
*s
= APIC_COMMON(dev
);
45 trace_cpu_get_apic_base((uint64_t)s
->apicbase
);
48 trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP
);
49 return MSR_IA32_APICBASE_BSP
;
53 void cpu_set_apic_tpr(DeviceState
*dev
, uint8_t val
)
56 APICCommonClass
*info
;
63 info
= APIC_COMMON_GET_CLASS(s
);
65 info
->set_tpr(s
, val
);
68 uint8_t cpu_get_apic_tpr(DeviceState
*dev
)
71 APICCommonClass
*info
;
78 info
= APIC_COMMON_GET_CLASS(s
);
80 return info
->get_tpr(s
);
83 void apic_enable_tpr_access_reporting(DeviceState
*dev
, bool enable
)
85 APICCommonState
*s
= APIC_COMMON(dev
);
86 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
88 apic_report_tpr_access
= enable
;
89 if (info
->enable_tpr_reporting
) {
90 info
->enable_tpr_reporting(s
, enable
);
94 void apic_enable_vapic(DeviceState
*dev
, hwaddr paddr
)
96 APICCommonState
*s
= APIC_COMMON(dev
);
97 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
99 s
->vapic_paddr
= paddr
;
100 info
->vapic_base_update(s
);
103 void apic_handle_tpr_access_report(DeviceState
*dev
, target_ulong ip
,
106 APICCommonState
*s
= APIC_COMMON(dev
);
108 vapic_report_tpr_access(s
->vapic
, CPU(s
->cpu
), ip
, access
);
111 void apic_report_irq_delivered(int delivered
)
113 apic_irq_delivered
+= delivered
;
115 trace_apic_report_irq_delivered(apic_irq_delivered
);
118 void apic_reset_irq_delivered(void)
120 /* Copy this into a local variable to encourage gcc to emit a plain
121 * register for a sys/sdt.h marker. For details on this workaround, see:
122 * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
124 volatile int a_i_d
= apic_irq_delivered
;
125 trace_apic_reset_irq_delivered(a_i_d
);
127 apic_irq_delivered
= 0;
130 int apic_get_irq_delivered(void)
132 trace_apic_get_irq_delivered(apic_irq_delivered
);
134 return apic_irq_delivered
;
137 void apic_deliver_nmi(DeviceState
*dev
)
139 APICCommonState
*s
= APIC_COMMON(dev
);
140 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
142 info
->external_nmi(s
);
145 bool apic_next_timer(APICCommonState
*s
, int64_t current_time
)
149 /* We need to store the timer state separately to support APIC
150 * implementations that maintain a non-QEMU timer, e.g. inside the
151 * host kernel. This open-coded state allows us to migrate between
153 s
->timer_expiry
= -1;
155 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_MASKED
) {
159 d
= (current_time
- s
->initial_count_load_time
) >> s
->count_shift
;
161 if (s
->lvt
[APIC_LVT_TIMER
] & APIC_LVT_TIMER_PERIODIC
) {
162 if (!s
->initial_count
) {
165 d
= ((d
/ ((uint64_t)s
->initial_count
+ 1)) + 1) *
166 ((uint64_t)s
->initial_count
+ 1);
168 if (d
>= s
->initial_count
) {
171 d
= (uint64_t)s
->initial_count
+ 1;
173 s
->next_time
= s
->initial_count_load_time
+ (d
<< s
->count_shift
);
174 s
->timer_expiry
= s
->next_time
;
178 void apic_init_reset(DeviceState
*dev
)
181 APICCommonClass
*info
;
187 s
= APIC_COMMON(dev
);
189 s
->spurious_vec
= 0xff;
192 memset(s
->isr
, 0, sizeof(s
->isr
));
193 memset(s
->tmr
, 0, sizeof(s
->tmr
));
194 memset(s
->irr
, 0, sizeof(s
->irr
));
195 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
196 s
->lvt
[i
] = APIC_LVT_MASKED
;
199 memset(s
->icr
, 0, sizeof(s
->icr
));
202 s
->initial_count
= 0;
203 s
->initial_count_load_time
= 0;
205 s
->wait_for_sipi
= !cpu_is_bsp(s
->cpu
);
210 s
->timer_expiry
= -1;
212 info
= APIC_COMMON_GET_CLASS(s
);
218 void apic_designate_bsp(DeviceState
*dev
, bool bsp
)
224 APICCommonState
*s
= APIC_COMMON(dev
);
226 s
->apicbase
|= MSR_IA32_APICBASE_BSP
;
228 s
->apicbase
&= ~MSR_IA32_APICBASE_BSP
;
232 static void apic_reset_common(DeviceState
*dev
)
234 APICCommonState
*s
= APIC_COMMON(dev
);
235 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
238 bsp
= cpu_is_bsp(s
->cpu
);
239 s
->apicbase
= APIC_DEFAULT_ADDRESS
|
240 (bsp
? MSR_IA32_APICBASE_BSP
: 0) | MSR_IA32_APICBASE_ENABLE
;
243 info
->vapic_base_update(s
);
245 apic_init_reset(dev
);
249 * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
250 * time typically by BIOS, so PIC interrupt can be delivered to the
251 * processor when local APIC is enabled.
253 s
->lvt
[APIC_LVT_LINT0
] = 0x700;
257 /* This function is only used for old state version 1 and 2 */
258 static int apic_load_old(QEMUFile
*f
, void *opaque
, int version_id
)
260 APICCommonState
*s
= opaque
;
261 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
264 if (version_id
> 2) {
268 /* XXX: what if the base changes? (registered memory regions) */
269 qemu_get_be32s(f
, &s
->apicbase
);
270 qemu_get_8s(f
, &s
->id
);
271 qemu_get_8s(f
, &s
->arb_id
);
272 qemu_get_8s(f
, &s
->tpr
);
273 qemu_get_be32s(f
, &s
->spurious_vec
);
274 qemu_get_8s(f
, &s
->log_dest
);
275 qemu_get_8s(f
, &s
->dest_mode
);
276 for (i
= 0; i
< 8; i
++) {
277 qemu_get_be32s(f
, &s
->isr
[i
]);
278 qemu_get_be32s(f
, &s
->tmr
[i
]);
279 qemu_get_be32s(f
, &s
->irr
[i
]);
281 for (i
= 0; i
< APIC_LVT_NB
; i
++) {
282 qemu_get_be32s(f
, &s
->lvt
[i
]);
284 qemu_get_be32s(f
, &s
->esr
);
285 qemu_get_be32s(f
, &s
->icr
[0]);
286 qemu_get_be32s(f
, &s
->icr
[1]);
287 qemu_get_be32s(f
, &s
->divide_conf
);
288 s
->count_shift
= qemu_get_be32(f
);
289 qemu_get_be32s(f
, &s
->initial_count
);
290 s
->initial_count_load_time
= qemu_get_be64(f
);
291 s
->next_time
= qemu_get_be64(f
);
293 if (version_id
>= 2) {
294 s
->timer_expiry
= qemu_get_be64(f
);
297 if (info
->post_load
) {
303 static void apic_common_realize(DeviceState
*dev
, Error
**errp
)
305 APICCommonState
*s
= APIC_COMMON(dev
);
306 APICCommonClass
*info
;
307 static DeviceState
*vapic
;
309 static bool mmio_registered
;
311 if (apic_no
>= MAX_APICS
) {
312 error_setg(errp
, "%s initialization failed.",
313 object_get_typename(OBJECT(dev
)));
318 info
= APIC_COMMON_GET_CLASS(s
);
319 info
->realize(dev
, errp
);
320 if (!mmio_registered
) {
321 ICCBus
*b
= ICC_BUS(qdev_get_parent_bus(dev
));
322 memory_region_add_subregion(b
->apic_address_space
, 0, &s
->io_memory
);
323 mmio_registered
= true;
326 /* Note: We need at least 1M to map the VAPIC option ROM */
327 if (!vapic
&& s
->vapic_control
& VAPIC_ENABLE_MASK
&&
328 ram_size
>= 1024 * 1024) {
329 vapic
= sysbus_create_simple("kvmvapic", -1, NULL
);
332 if (apic_report_tpr_access
&& info
->enable_tpr_reporting
) {
333 info
->enable_tpr_reporting(s
, true);
338 static int apic_pre_load(void *opaque
)
340 APICCommonState
*s
= APIC_COMMON(opaque
);
342 /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
343 * so that's what apic_common_sipi_needed checks for. Reset to
344 * the value that is assumed when the apic_sipi subsection is
347 s
->wait_for_sipi
= 0;
351 static void apic_dispatch_pre_save(void *opaque
)
353 APICCommonState
*s
= APIC_COMMON(opaque
);
354 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
356 if (info
->pre_save
) {
361 static int apic_dispatch_post_load(void *opaque
, int version_id
)
363 APICCommonState
*s
= APIC_COMMON(opaque
);
364 APICCommonClass
*info
= APIC_COMMON_GET_CLASS(s
);
366 if (info
->post_load
) {
372 static bool apic_common_sipi_needed(void *opaque
)
374 APICCommonState
*s
= APIC_COMMON(opaque
);
375 return s
->wait_for_sipi
!= 0;
378 static const VMStateDescription vmstate_apic_common_sipi
= {
381 .minimum_version_id
= 1,
382 .fields
= (VMStateField
[]) {
383 VMSTATE_INT32(sipi_vector
, APICCommonState
),
384 VMSTATE_INT32(wait_for_sipi
, APICCommonState
),
385 VMSTATE_END_OF_LIST()
389 static const VMStateDescription vmstate_apic_common
= {
392 .minimum_version_id
= 3,
393 .minimum_version_id_old
= 1,
394 .load_state_old
= apic_load_old
,
395 .pre_load
= apic_pre_load
,
396 .pre_save
= apic_dispatch_pre_save
,
397 .post_load
= apic_dispatch_post_load
,
398 .fields
= (VMStateField
[]) {
399 VMSTATE_UINT32(apicbase
, APICCommonState
),
400 VMSTATE_UINT8(id
, APICCommonState
),
401 VMSTATE_UINT8(arb_id
, APICCommonState
),
402 VMSTATE_UINT8(tpr
, APICCommonState
),
403 VMSTATE_UINT32(spurious_vec
, APICCommonState
),
404 VMSTATE_UINT8(log_dest
, APICCommonState
),
405 VMSTATE_UINT8(dest_mode
, APICCommonState
),
406 VMSTATE_UINT32_ARRAY(isr
, APICCommonState
, 8),
407 VMSTATE_UINT32_ARRAY(tmr
, APICCommonState
, 8),
408 VMSTATE_UINT32_ARRAY(irr
, APICCommonState
, 8),
409 VMSTATE_UINT32_ARRAY(lvt
, APICCommonState
, APIC_LVT_NB
),
410 VMSTATE_UINT32(esr
, APICCommonState
),
411 VMSTATE_UINT32_ARRAY(icr
, APICCommonState
, 2),
412 VMSTATE_UINT32(divide_conf
, APICCommonState
),
413 VMSTATE_INT32(count_shift
, APICCommonState
),
414 VMSTATE_UINT32(initial_count
, APICCommonState
),
415 VMSTATE_INT64(initial_count_load_time
, APICCommonState
),
416 VMSTATE_INT64(next_time
, APICCommonState
),
417 VMSTATE_INT64(timer_expiry
,
418 APICCommonState
), /* open-coded timer state */
419 VMSTATE_END_OF_LIST()
421 .subsections
= (VMStateSubsection
[]) {
423 .vmsd
= &vmstate_apic_common_sipi
,
424 .needed
= apic_common_sipi_needed
,
426 VMSTATE_END_OF_LIST()
430 static Property apic_properties_common
[] = {
431 DEFINE_PROP_UINT8("id", APICCommonState
, id
, -1),
432 DEFINE_PROP_UINT8("version", APICCommonState
, version
, 0x14),
433 DEFINE_PROP_BIT("vapic", APICCommonState
, vapic_control
, VAPIC_ENABLE_BIT
,
435 DEFINE_PROP_END_OF_LIST(),
438 static void apic_common_class_init(ObjectClass
*klass
, void *data
)
440 ICCDeviceClass
*idc
= ICC_DEVICE_CLASS(klass
);
441 DeviceClass
*dc
= DEVICE_CLASS(klass
);
443 dc
->vmsd
= &vmstate_apic_common
;
444 dc
->reset
= apic_reset_common
;
445 dc
->props
= apic_properties_common
;
446 idc
->realize
= apic_common_realize
;
448 * Reason: APIC and CPU need to be wired up by
449 * x86_cpu_apic_create()
451 dc
->cannot_instantiate_with_device_add_yet
= true;
454 static const TypeInfo apic_common_type
= {
455 .name
= TYPE_APIC_COMMON
,
456 .parent
= TYPE_ICC_DEVICE
,
457 .instance_size
= sizeof(APICCommonState
),
458 .class_size
= sizeof(APICCommonClass
),
459 .class_init
= apic_common_class_init
,
463 static void apic_common_register_types(void)
465 type_register_static(&apic_common_type
);
468 type_init(apic_common_register_types
)