hw/s390x/s390-pci-inst.c

   1 /*
   2  * s390 PCI instructions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #include "s390-pci-inst.h"
  15 #include "s390-pci-bus.h"
  16 #include <exec/memory-internal.h>
  17 #include <qemu/error-report.h>
  18
  19 /* #define DEBUG_S390PCI_INST */
  20 #ifdef DEBUG_S390PCI_INST
  21 #define DPRINTF(fmt, ...) \
  22     do { fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); } while (0)
  23 #else
  24 #define DPRINTF(fmt, ...) \
  25     do { } while (0)
  26 #endif
  27
  28 static void s390_set_status_code(CPUS390XState *env,
  29                                  uint8_t r, uint64_t status_code)
  30 {
  31     env->regs[r] &= ~0xff000000ULL;
  32     env->regs[r] |= (status_code & 0xff) << 24;
  33 }
  34
  35 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
  36 {
  37     S390PCIBusDevice *pbdev;
  38     uint32_t res_code, initial_l2, g_l2, finish;
  39     int rc, idx;
  40     uint64_t resume_token;
  41
  42     rc = 0;
  43     if (lduw_p(&rrb->request.hdr.len) != 32) {
  44         res_code = CLP_RC_LEN;
  45         rc = -EINVAL;
  46         goto out;
  47     }
  48
  49     if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
  50         res_code = CLP_RC_FMT;
  51         rc = -EINVAL;
  52         goto out;
  53     }
  54
  55     if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
  56         ldq_p(&rrb->request.reserved1) != 0 ||
  57         ldq_p(&rrb->request.reserved2) != 0) {
  58         res_code = CLP_RC_RESNOT0;
  59         rc = -EINVAL;
  60         goto out;
  61     }
  62
  63     resume_token = ldq_p(&rrb->request.resume_token);
  64
  65     if (resume_token) {
  66         pbdev = s390_pci_find_dev_by_idx(resume_token);
  67         if (!pbdev) {
  68             res_code = CLP_RC_LISTPCI_BADRT;
  69             rc = -EINVAL;
  70             goto out;
  71         }
  72     }
  73
  74     if (lduw_p(&rrb->response.hdr.len) < 48) {
  75         res_code = CLP_RC_8K;
  76         rc = -EINVAL;
  77         goto out;
  78     }
  79
  80     initial_l2 = lduw_p(&rrb->response.hdr.len);
  81     if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
  82         != 0) {
  83         res_code = CLP_RC_LEN;
  84         rc = -EINVAL;
  85         *cc = 3;
  86         goto out;
  87     }
  88
  89     stl_p(&rrb->response.fmt, 0);
  90     stq_p(&rrb->response.reserved1, 0);
  91     stq_p(&rrb->response.reserved2, 0);
  92     stl_p(&rrb->response.mdd, FH_VIRT);
  93     stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
  94     rrb->response.entry_size = sizeof(ClpFhListEntry);
  95     finish = 0;
  96     idx = resume_token;
  97     g_l2 = LIST_PCI_HDR_LEN;
  98     do {
  99         pbdev = s390_pci_find_dev_by_idx(idx);
 100         if (!pbdev) {
 101             finish = 1;
 102             break;
 103         }
 104         stw_p(&rrb->response.fh_list[idx - resume_token].device_id,
 105             pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
 106         stw_p(&rrb->response.fh_list[idx - resume_token].vendor_id,
 107             pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
 108         stl_p(&rrb->response.fh_list[idx - resume_token].config, 0x80000000);
 109         stl_p(&rrb->response.fh_list[idx - resume_token].fid, pbdev->fid);
 110         stl_p(&rrb->response.fh_list[idx - resume_token].fh, pbdev->fh);
 111
 112         g_l2 += sizeof(ClpFhListEntry);
 113         /* Add endian check for DPRINTF? */
 114         DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
 115             g_l2,
 116             lduw_p(&rrb->response.fh_list[idx - resume_token].vendor_id),
 117             lduw_p(&rrb->response.fh_list[idx - resume_token].device_id),
 118             ldl_p(&rrb->response.fh_list[idx - resume_token].fid),
 119             ldl_p(&rrb->response.fh_list[idx - resume_token].fh));
 120         idx++;
 121     } while (g_l2 < initial_l2);
 122
 123     if (finish == 1) {
 124         resume_token = 0;
 125     } else {
 126         resume_token = idx;
 127     }
 128     stq_p(&rrb->response.resume_token, resume_token);
 129     stw_p(&rrb->response.hdr.len, g_l2);
 130     stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
 131 out:
 132     if (rc) {
 133         DPRINTF("list pci failed rc 0x%x\n", rc);
 134         stw_p(&rrb->response.hdr.rsp, res_code);
 135     }
 136     return rc;
 137 }
 138
 139 int clp_service_call(S390CPU *cpu, uint8_t r2)
 140 {
 141     ClpReqHdr *reqh;
 142     ClpRspHdr *resh;
 143     S390PCIBusDevice *pbdev;
 144     uint32_t req_len;
 145     uint32_t res_len;
 146     uint8_t buffer[4096 * 2];
 147     uint8_t cc = 0;
 148     CPUS390XState *env = &cpu->env;
 149     int i;
 150
 151     cpu_synchronize_state(CPU(cpu));
 152
 153     if (env->psw.mask & PSW_MASK_PSTATE) {
 154         program_interrupt(env, PGM_PRIVILEGED, 4);
 155         return 0;
 156     }
 157
 158     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], buffer, sizeof(*reqh))) {
 159         return 0;
 160     }
 161     reqh = (ClpReqHdr *)buffer;
 162     req_len = lduw_p(&reqh->len);
 163     if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
 164         program_interrupt(env, PGM_OPERAND, 4);
 165         return 0;
 166     }
 167
 168     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], buffer,
 169                                req_len + sizeof(*resh))) {
 170         return 0;
 171     }
 172     resh = (ClpRspHdr *)(buffer + req_len);
 173     res_len = lduw_p(&resh->len);
 174     if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
 175         program_interrupt(env, PGM_OPERAND, 4);
 176         return 0;
 177     }
 178     if ((req_len + res_len) > 8192) {
 179         program_interrupt(env, PGM_OPERAND, 4);
 180         return 0;
 181     }
 182
 183     if (s390_cpu_virt_mem_read(cpu, env->regs[r2], buffer,
 184                                req_len + res_len)) {
 185         return 0;
 186     }
 187
 188     if (req_len != 32) {
 189         stw_p(&resh->rsp, CLP_RC_LEN);
 190         goto out;
 191     }
 192
 193     switch (lduw_p(&reqh->cmd)) {
 194     case CLP_LIST_PCI: {
 195         ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
 196         list_pci(rrb, &cc);
 197         break;
 198     }
 199     case CLP_SET_PCI_FN: {
 200         ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
 201         ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
 202
 203         pbdev = s390_pci_find_dev_by_fh(ldl_p(&reqsetpci->fh));
 204         if (!pbdev) {
 205                 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
 206                 goto out;
 207         }
 208
 209         switch (reqsetpci->oc) {
 210         case CLP_SET_ENABLE_PCI_FN:
 211             pbdev->fh = pbdev->fh | 1 << ENABLE_BIT_OFFSET;
 212             stl_p(&ressetpci->fh, pbdev->fh);
 213             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 214             break;
 215         case CLP_SET_DISABLE_PCI_FN:
 216             pbdev->fh = pbdev->fh & ~(1 << ENABLE_BIT_OFFSET);
 217             pbdev->error_state = false;
 218             pbdev->lgstg_blocked = false;
 219             stl_p(&ressetpci->fh, pbdev->fh);
 220             stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
 221             break;
 222         default:
 223             DPRINTF("unknown set pci command\n");
 224             stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
 225             break;
 226         }
 227         break;
 228     }
 229     case CLP_QUERY_PCI_FN: {
 230         ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
 231         ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
 232
 233         pbdev = s390_pci_find_dev_by_fh(ldl_p(&reqquery->fh));
 234         if (!pbdev) {
 235             DPRINTF("query pci no pci dev\n");
 236             stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
 237             goto out;
 238         }
 239
 240         for (i = 0; i < PCI_BAR_COUNT; i++) {
 241             uint32_t data = pci_get_long(pbdev->pdev->config +
 242                 PCI_BASE_ADDRESS_0 + (i * 4));
 243
 244             stl_p(&resquery->bar[i], data);
 245             resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
 246                                     ctz64(pbdev->pdev->io_regions[i].size) : 0;
 247             DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
 248                     ldl_p(&resquery->bar[i]),
 249                     pbdev->pdev->io_regions[i].size,
 250                     resquery->bar_size[i]);
 251         }
 252
 253         stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
 254         stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
 255         stw_p(&resquery->pchid, 0);
 256         stw_p(&resquery->ug, 1);
 257         stl_p(&resquery->uid, pbdev->fid);
 258         stw_p(&resquery->hdr.rsp, CLP_RC_OK);
 259         break;
 260     }
 261     case CLP_QUERY_PCI_FNGRP: {
 262         ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
 263         resgrp->fr = 1;
 264         stq_p(&resgrp->dasm, 0);
 265         stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
 266         stw_p(&resgrp->mui, 0);
 267         stw_p(&resgrp->i, 128);
 268         resgrp->version = 0;
 269
 270         stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
 271         break;
 272     }
 273     default:
 274         DPRINTF("unknown clp command\n");
 275         stw_p(&resh->rsp, CLP_RC_CMD);
 276         break;
 277     }
 278
 279 out:
 280     if (s390_cpu_virt_mem_write(cpu, env->regs[r2], buffer,
 281                                 req_len + res_len)) {
 282         return 0;
 283     }
 284     setcc(cpu, cc);
 285     return 0;
 286 }
 287
 288 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
 289 {
 290     CPUS390XState *env = &cpu->env;
 291     S390PCIBusDevice *pbdev;
 292     uint64_t offset;
 293     uint64_t data;
 294     uint8_t len;
 295     uint32_t fh;
 296     uint8_t pcias;
 297
 298     cpu_synchronize_state(CPU(cpu));
 299
 300     if (env->psw.mask & PSW_MASK_PSTATE) {
 301         program_interrupt(env, PGM_PRIVILEGED, 4);
 302         return 0;
 303     }
 304
 305     if (r2 & 0x1) {
 306         program_interrupt(env, PGM_SPECIFICATION, 4);
 307         return 0;
 308     }
 309
 310     fh = env->regs[r2] >> 32;
 311     pcias = (env->regs[r2] >> 16) & 0xf;
 312     len = env->regs[r2] & 0xf;
 313     offset = env->regs[r2 + 1];
 314
 315     pbdev = s390_pci_find_dev_by_fh(fh);
 316     if (!pbdev) {
 317         DPRINTF("pcilg no pci dev\n");
 318         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 319         return 0;
 320     }
 321
 322     if (pbdev->lgstg_blocked) {
 323         setcc(cpu, ZPCI_PCI_LS_ERR);
 324         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 325         return 0;
 326     }
 327
 328     if (pcias < 6) {
 329         if ((8 - (offset & 0x7)) < len) {
 330             program_interrupt(env, PGM_OPERAND, 4);
 331             return 0;
 332         }
 333         MemoryRegion *mr = pbdev->pdev->io_regions[pcias].memory;
 334         io_mem_read(mr, offset, &data, len);
 335     } else if (pcias == 15) {
 336         if ((4 - (offset & 0x3)) < len) {
 337             program_interrupt(env, PGM_OPERAND, 4);
 338             return 0;
 339         }
 340         data =  pci_host_config_read_common(
 341                    pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
 342
 343         switch (len) {
 344         case 1:
 345             break;
 346         case 2:
 347             data = bswap16(data);
 348             break;
 349         case 4:
 350             data = bswap32(data);
 351             break;
 352         case 8:
 353             data = bswap64(data);
 354             break;
 355         default:
 356             program_interrupt(env, PGM_OPERAND, 4);
 357             return 0;
 358         }
 359     } else {
 360         DPRINTF("invalid space\n");
 361         setcc(cpu, ZPCI_PCI_LS_ERR);
 362         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 363         return 0;
 364     }
 365
 366     env->regs[r1] = data;
 367     setcc(cpu, ZPCI_PCI_LS_OK);
 368     return 0;
 369 }
 370
 371 static void update_msix_table_msg_data(S390PCIBusDevice *pbdev, uint64_t offset,
 372                                        uint64_t *data, uint8_t len)
 373 {
 374     uint32_t val;
 375     uint8_t *msg_data;
 376
 377     if (offset % PCI_MSIX_ENTRY_SIZE != 8) {
 378         return;
 379     }
 380
 381     if (len != 4) {
 382         DPRINTF("access msix table msg data but len is %d\n", len);
 383         return;
 384     }
 385
 386     msg_data = (uint8_t *)data - offset % PCI_MSIX_ENTRY_SIZE +
 387                PCI_MSIX_ENTRY_VECTOR_CTRL;
 388     val = pci_get_long(msg_data) | (pbdev->fid << ZPCI_MSI_VEC_BITS);
 389     pci_set_long(msg_data, val);
 390     DPRINTF("update msix msg_data to 0x%" PRIx64 "\n", *data);
 391 }
 392
 393 static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias)
 394 {
 395     if (pbdev->msix.available && pbdev->msix.table_bar == pcias &&
 396         offset >= pbdev->msix.table_offset &&
 397         offset <= pbdev->msix.table_offset +
 398                   (pbdev->msix.entries - 1) * PCI_MSIX_ENTRY_SIZE) {
 399         return 1;
 400     } else {
 401         return 0;
 402     }
 403 }
 404
 405 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
 406 {
 407     CPUS390XState *env = &cpu->env;
 408     uint64_t offset, data;
 409     S390PCIBusDevice *pbdev;
 410     uint8_t len;
 411     uint32_t fh;
 412     uint8_t pcias;
 413
 414     cpu_synchronize_state(CPU(cpu));
 415
 416     if (env->psw.mask & PSW_MASK_PSTATE) {
 417         program_interrupt(env, PGM_PRIVILEGED, 4);
 418         return 0;
 419     }
 420
 421     if (r2 & 0x1) {
 422         program_interrupt(env, PGM_SPECIFICATION, 4);
 423         return 0;
 424     }
 425
 426     fh = env->regs[r2] >> 32;
 427     pcias = (env->regs[r2] >> 16) & 0xf;
 428     len = env->regs[r2] & 0xf;
 429     offset = env->regs[r2 + 1];
 430
 431     pbdev = s390_pci_find_dev_by_fh(fh);
 432     if (!pbdev) {
 433         DPRINTF("pcistg no pci dev\n");
 434         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 435         return 0;
 436     }
 437
 438     if (pbdev->lgstg_blocked) {
 439         setcc(cpu, ZPCI_PCI_LS_ERR);
 440         s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
 441         return 0;
 442     }
 443
 444     data = env->regs[r1];
 445     if (pcias < 6) {
 446         if ((8 - (offset & 0x7)) < len) {
 447             program_interrupt(env, PGM_OPERAND, 4);
 448             return 0;
 449         }
 450         MemoryRegion *mr;
 451         if (trap_msix(pbdev, offset, pcias)) {
 452             offset = offset - pbdev->msix.table_offset;
 453             mr = &pbdev->pdev->msix_table_mmio;
 454             update_msix_table_msg_data(pbdev, offset, &data, len);
 455         } else {
 456             mr = pbdev->pdev->io_regions[pcias].memory;
 457         }
 458
 459         io_mem_write(mr, offset, data, len);
 460     } else if (pcias == 15) {
 461         if ((4 - (offset & 0x3)) < len) {
 462             program_interrupt(env, PGM_OPERAND, 4);
 463             return 0;
 464         }
 465         switch (len) {
 466         case 1:
 467             break;
 468         case 2:
 469             data = bswap16(data);
 470             break;
 471         case 4:
 472             data = bswap32(data);
 473             break;
 474         case 8:
 475             data = bswap64(data);
 476             break;
 477         default:
 478             program_interrupt(env, PGM_OPERAND, 4);
 479             return 0;
 480         }
 481
 482         pci_host_config_write_common(pbdev->pdev, offset,
 483                                      pci_config_size(pbdev->pdev),
 484                                      data, len);
 485     } else {
 486         DPRINTF("pcistg invalid space\n");
 487         setcc(cpu, ZPCI_PCI_LS_ERR);
 488         s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
 489         return 0;
 490     }
 491
 492     setcc(cpu, ZPCI_PCI_LS_OK);
 493     return 0;
 494 }
 495
 496 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
 497 {
 498     CPUS390XState *env = &cpu->env;
 499     uint32_t fh;
 500     S390PCIBusDevice *pbdev;
 501     hwaddr start, end;
 502     IOMMUTLBEntry entry;
 503     MemoryRegion *mr;
 504
 505     cpu_synchronize_state(CPU(cpu));
 506
 507     if (env->psw.mask & PSW_MASK_PSTATE) {
 508         program_interrupt(env, PGM_PRIVILEGED, 4);
 509         goto out;
 510     }
 511
 512     if (r2 & 0x1) {
 513         program_interrupt(env, PGM_SPECIFICATION, 4);
 514         goto out;
 515     }
 516
 517     fh = env->regs[r1] >> 32;
 518     start = env->regs[r2];
 519     end = start + env->regs[r2 + 1];
 520
 521     pbdev = s390_pci_find_dev_by_fh(fh);
 522
 523     if (!pbdev) {
 524         DPRINTF("rpcit no pci dev\n");
 525         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 526         goto out;
 527     }
 528
 529     mr = pci_device_iommu_address_space(pbdev->pdev)->root;
 530     while (start < end) {
 531         entry = mr->iommu_ops->translate(mr, start, 0);
 532
 533         if (!entry.translated_addr) {
 534             setcc(cpu, ZPCI_PCI_LS_ERR);
 535             goto out;
 536         }
 537
 538         memory_region_notify_iommu(mr, entry);
 539         start += entry.addr_mask + 1;
 540     }
 541
 542     setcc(cpu, ZPCI_PCI_LS_OK);
 543 out:
 544     return 0;
 545 }
 546
 547 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr)
 548 {
 549     CPUS390XState *env = &cpu->env;
 550     S390PCIBusDevice *pbdev;
 551     MemoryRegion *mr;
 552     int i;
 553     uint32_t fh;
 554     uint8_t pcias;
 555     uint8_t len;
 556     uint8_t buffer[128];
 557
 558     if (env->psw.mask & PSW_MASK_PSTATE) {
 559         program_interrupt(env, PGM_PRIVILEGED, 6);
 560         return 0;
 561     }
 562
 563     fh = env->regs[r1] >> 32;
 564     pcias = (env->regs[r1] >> 16) & 0xf;
 565     len = env->regs[r1] & 0xff;
 566
 567     if (pcias > 5) {
 568         DPRINTF("pcistb invalid space\n");
 569         setcc(cpu, ZPCI_PCI_LS_ERR);
 570         s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
 571         return 0;
 572     }
 573
 574     switch (len) {
 575     case 16:
 576     case 32:
 577     case 64:
 578     case 128:
 579         break;
 580     default:
 581         program_interrupt(env, PGM_SPECIFICATION, 6);
 582         return 0;
 583     }
 584
 585     pbdev = s390_pci_find_dev_by_fh(fh);
 586     if (!pbdev) {
 587         DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
 588         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 589         return 0;
 590     }
 591
 592     if (pbdev->lgstg_blocked) {
 593         setcc(cpu, ZPCI_PCI_LS_ERR);
 594         s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
 595         return 0;
 596     }
 597
 598     mr = pbdev->pdev->io_regions[pcias].memory;
 599     if (!memory_region_access_valid(mr, env->regs[r3], len, true)) {
 600         program_interrupt(env, PGM_ADDRESSING, 6);
 601         return 0;
 602     }
 603
 604     if (s390_cpu_virt_mem_read(cpu, gaddr, buffer, len)) {
 605         return 0;
 606     }
 607
 608     for (i = 0; i < len / 8; i++) {
 609         io_mem_write(mr, env->regs[r3] + i * 8, ldq_p(buffer + i * 8), 8);
 610     }
 611
 612     setcc(cpu, ZPCI_PCI_LS_OK);
 613     return 0;
 614 }
 615
 616 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
 617 {
 618     int ret;
 619     S390FLICState *fs = s390_get_flic();
 620     S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
 621
 622     ret = css_register_io_adapter(S390_PCIPT_ADAPTER,
 623                                   FIB_DATA_ISC(ldl_p(&fib.data)), true, false,
 624                                   &pbdev->routes.adapter.adapter_id);
 625     assert(ret == 0);
 626
 627     fsc->io_adapter_map(fs, pbdev->routes.adapter.adapter_id,
 628         ldq_p(&fib.aisb), true);
 629     fsc->io_adapter_map(fs, pbdev->routes.adapter.adapter_id,
 630         ldq_p(&fib.aibv), true);
 631
 632     pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
 633     pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
 634     pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
 635     pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
 636     pbdev->isc = FIB_DATA_ISC(ldl_p(&fib.data));
 637     pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
 638     pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
 639
 640     DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 641     return 0;
 642 }
 643
 644 static int dereg_irqs(S390PCIBusDevice *pbdev)
 645 {
 646     S390FLICState *fs = s390_get_flic();
 647     S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
 648
 649     fsc->io_adapter_map(fs, pbdev->routes.adapter.adapter_id,
 650                         pbdev->routes.adapter.ind_addr, false);
 651
 652     pbdev->routes.adapter.summary_addr = 0;
 653     pbdev->routes.adapter.summary_offset = 0;
 654     pbdev->routes.adapter.ind_addr = 0;
 655     pbdev->routes.adapter.ind_offset = 0;
 656     pbdev->isc = 0;
 657     pbdev->noi = 0;
 658     pbdev->sum = 0;
 659
 660     DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
 661     return 0;
 662 }
 663
 664 static int reg_ioat(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
 665 {
 666     uint64_t pba = ldq_p(&fib.pba);
 667     uint64_t pal = ldq_p(&fib.pal);
 668     uint64_t g_iota = ldq_p(&fib.iota);
 669     uint8_t dt = (g_iota >> 2) & 0x7;
 670     uint8_t t = (g_iota >> 11) & 0x1;
 671
 672     if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
 673         program_interrupt(env, PGM_OPERAND, 6);
 674         return -EINVAL;
 675     }
 676
 677     /* currently we only support designation type 1 with translation */
 678     if (!(dt == ZPCI_IOTA_RTTO && t)) {
 679         error_report("unsupported ioat dt %d t %d", dt, t);
 680         program_interrupt(env, PGM_OPERAND, 6);
 681         return -EINVAL;
 682     }
 683
 684     pbdev->pba = pba;
 685     pbdev->pal = pal;
 686     pbdev->g_iota = g_iota;
 687     return 0;
 688 }
 689
 690 static void dereg_ioat(S390PCIBusDevice *pbdev)
 691 {
 692     pbdev->pba = 0;
 693     pbdev->pal = 0;
 694     pbdev->g_iota = 0;
 695 }
 696
 697 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba)
 698 {
 699     CPUS390XState *env = &cpu->env;
 700     uint8_t oc;
 701     uint32_t fh;
 702     ZpciFib fib;
 703     S390PCIBusDevice *pbdev;
 704     uint64_t cc = ZPCI_PCI_LS_OK;
 705
 706     if (env->psw.mask & PSW_MASK_PSTATE) {
 707         program_interrupt(env, PGM_PRIVILEGED, 6);
 708         return 0;
 709     }
 710
 711     oc = env->regs[r1] & 0xff;
 712     fh = env->regs[r1] >> 32;
 713
 714     if (fiba & 0x7) {
 715         program_interrupt(env, PGM_SPECIFICATION, 6);
 716         return 0;
 717     }
 718
 719     pbdev = s390_pci_find_dev_by_fh(fh);
 720     if (!pbdev) {
 721         DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
 722         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 723         return 0;
 724     }
 725
 726     if (s390_cpu_virt_mem_read(cpu, fiba, (uint8_t *)&fib, sizeof(fib))) {
 727         return 0;
 728     }
 729
 730     switch (oc) {
 731     case ZPCI_MOD_FC_REG_INT:
 732         if (reg_irqs(env, pbdev, fib)) {
 733             cc = ZPCI_PCI_LS_ERR;
 734         }
 735         break;
 736     case ZPCI_MOD_FC_DEREG_INT:
 737         dereg_irqs(pbdev);
 738         break;
 739     case ZPCI_MOD_FC_REG_IOAT:
 740         if (reg_ioat(env, pbdev, fib)) {
 741             cc = ZPCI_PCI_LS_ERR;
 742         }
 743         break;
 744     case ZPCI_MOD_FC_DEREG_IOAT:
 745         dereg_ioat(pbdev);
 746         break;
 747     case ZPCI_MOD_FC_REREG_IOAT:
 748         dereg_ioat(pbdev);
 749         if (reg_ioat(env, pbdev, fib)) {
 750             cc = ZPCI_PCI_LS_ERR;
 751         }
 752         break;
 753     case ZPCI_MOD_FC_RESET_ERROR:
 754         pbdev->error_state = false;
 755         pbdev->lgstg_blocked = false;
 756         break;
 757     case ZPCI_MOD_FC_RESET_BLOCK:
 758         pbdev->lgstg_blocked = false;
 759         break;
 760     case ZPCI_MOD_FC_SET_MEASURE:
 761         pbdev->fmb_addr = ldq_p(&fib.fmb_addr);
 762         break;
 763     default:
 764         program_interrupt(&cpu->env, PGM_OPERAND, 6);
 765         cc = ZPCI_PCI_LS_ERR;
 766     }
 767
 768     setcc(cpu, cc);
 769     return 0;
 770 }
 771
 772 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba)
 773 {
 774     CPUS390XState *env = &cpu->env;
 775     uint32_t fh;
 776     ZpciFib fib;
 777     S390PCIBusDevice *pbdev;
 778     uint32_t data;
 779     uint64_t cc = ZPCI_PCI_LS_OK;
 780
 781     if (env->psw.mask & PSW_MASK_PSTATE) {
 782         program_interrupt(env, PGM_PRIVILEGED, 6);
 783         return 0;
 784     }
 785
 786     fh = env->regs[r1] >> 32;
 787
 788     if (fiba & 0x7) {
 789         program_interrupt(env, PGM_SPECIFICATION, 6);
 790         return 0;
 791     }
 792
 793     pbdev = s390_pci_find_dev_by_fh(fh);
 794     if (!pbdev) {
 795         setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
 796         return 0;
 797     }
 798
 799     memset(&fib, 0, sizeof(fib));
 800     stq_p(&fib.pba, pbdev->pba);
 801     stq_p(&fib.pal, pbdev->pal);
 802     stq_p(&fib.iota, pbdev->g_iota);
 803     stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
 804     stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
 805     stq_p(&fib.fmb_addr, pbdev->fmb_addr);
 806
 807     data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
 808            ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
 809            ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
 810     stl_p(&fib.data, data);
 811
 812     if (pbdev->fh >> ENABLE_BIT_OFFSET) {
 813         fib.fc |= 0x80;
 814     }
 815
 816     if (pbdev->error_state) {
 817         fib.fc |= 0x40;
 818     }
 819
 820     if (pbdev->lgstg_blocked) {
 821         fib.fc |= 0x20;
 822     }
 823
 824     if (pbdev->g_iota) {
 825         fib.fc |= 0x10;
 826     }
 827
 828     if (s390_cpu_virt_mem_write(cpu, fiba, (uint8_t *)&fib, sizeof(fib))) {
 829         return 0;
 830     }
 831
 832     setcc(cpu, cc);
 833     return 0;
 834 }