target/arm/kvm32.c

   1 /*
   2  * ARM implementation of KVM hooks, 32 bit specific code.
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include <sys/ioctl.h>
  13
  14 #include <linux/kvm.h>
  15
  16 #include "qemu-common.h"
  17 #include "cpu.h"
  18 #include "qemu/timer.h"
  19 #include "sysemu/runstate.h"
  20 #include "sysemu/kvm.h"
  21 #include "kvm_arm.h"
  22 #include "internals.h"
  23 #include "qemu/log.h"
  24
  25 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
  26 {
  27     struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
  28
  29     assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
  30     return ioctl(fd, KVM_GET_ONE_REG, &idreg);
  31 }
  32
  33 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  34 {
  35     /* Identify the feature bits corresponding to the host CPU, and
  36      * fill out the ARMHostCPUClass fields accordingly. To do this
  37      * we have to create a scratch VM, create a single CPU inside it,
  38      * and then query that CPU for the relevant ID registers.
  39      */
  40     int err = 0, fdarray[3];
  41     uint32_t midr, id_pfr0;
  42     uint64_t features = 0;
  43
  44     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  45      * we know these will only support creating one kind of guest CPU,
  46      * which is its preferred CPU type.
  47      */
  48     static const uint32_t cpus_to_try[] = {
  49         QEMU_KVM_ARM_TARGET_CORTEX_A15,
  50         QEMU_KVM_ARM_TARGET_NONE
  51     };
  52     /*
  53      * target = -1 informs kvm_arm_create_scratch_host_vcpu()
  54      * to use the preferred target
  55      */
  56     struct kvm_vcpu_init init = { .target = -1, };
  57
  58     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  59         return false;
  60     }
  61
  62     ahcf->target = init.target;
  63
  64     /* This is not strictly blessed by the device tree binding docs yet,
  65      * but in practice the kernel does not care about this string so
  66      * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
  67      */
  68     ahcf->dtb_compatible = "arm,arm-v7";
  69
  70     err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
  71     err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
  72
  73     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
  74                           ARM_CP15_REG32(0, 0, 2, 0));
  75     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
  76                           ARM_CP15_REG32(0, 0, 2, 1));
  77     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
  78                           ARM_CP15_REG32(0, 0, 2, 2));
  79     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
  80                           ARM_CP15_REG32(0, 0, 2, 3));
  81     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
  82                           ARM_CP15_REG32(0, 0, 2, 4));
  83     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
  84                           ARM_CP15_REG32(0, 0, 2, 5));
  85     if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
  86                        ARM_CP15_REG32(0, 0, 2, 7))) {
  87         /*
  88          * Older kernels don't support reading ID_ISAR6. This register was
  89          * only introduced in ARMv8, so we can assume that it is zero on a
  90          * CPU that a kernel this old is running on.
  91          */
  92         ahcf->isar.id_isar6 = 0;
  93     }
  94
  95     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
  96                           ARM_CP15_REG32(0, 0, 1, 2));
  97
  98     err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
  99                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
 100                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
 101     err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
 102                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
 103                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
 104     /*
 105      * FIXME: There is not yet a way to read MVFR2.
 106      * Fortunately there is not yet anything in there that affects migration.
 107      */
 108
 109     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
 110                           ARM_CP15_REG32(0, 0, 1, 4));
 111     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
 112                           ARM_CP15_REG32(0, 0, 1, 5));
 113     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
 114                           ARM_CP15_REG32(0, 0, 1, 6));
 115     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
 116                           ARM_CP15_REG32(0, 0, 1, 7));
 117     if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
 118                        ARM_CP15_REG32(0, 0, 2, 6))) {
 119         /*
 120          * Older kernels don't support reading ID_MMFR4 (a new in v8
 121          * register); assume it's zero.
 122          */
 123         ahcf->isar.id_mmfr4 = 0;
 124     }
 125
 126     /*
 127      * There is no way to read DBGDIDR, because currently 32-bit KVM
 128      * doesn't implement debug at all. Leave it at zero.
 129      */
 130
 131     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 132
 133     if (err < 0) {
 134         return false;
 135     }
 136
 137     /* Now we've retrieved all the register information we can
 138      * set the feature bits based on the ID register fields.
 139      * We can assume any KVM supporting CPU is at least a v7
 140      * with VFPv3, virtualization extensions, and the generic
 141      * timers; this in turn implies most of the other feature
 142      * bits, but a few must be tested.
 143      */
 144     features |= 1ULL << ARM_FEATURE_V7VE;
 145     features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
 146
 147     if (extract32(id_pfr0, 12, 4) == 1) {
 148         features |= 1ULL << ARM_FEATURE_THUMB2EE;
 149     }
 150     if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
 151         features |= 1ULL << ARM_FEATURE_NEON;
 152     }
 153
 154     ahcf->features = features;
 155
 156     return true;
 157 }
 158
 159 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 160 {
 161     /* Return true if the regidx is a register we should synchronize
 162      * via the cpreg_tuples array (ie is not a core reg we sync by
 163      * hand in kvm_arch_get/put_registers())
 164      */
 165     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 166     case KVM_REG_ARM_CORE:
 167     case KVM_REG_ARM_VFP:
 168         return false;
 169     default:
 170         return true;
 171     }
 172 }
 173
 174 typedef struct CPRegStateLevel {
 175     uint64_t regidx;
 176     int level;
 177 } CPRegStateLevel;
 178
 179 /* All coprocessor registers not listed in the following table are assumed to
 180  * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
 181  * often, you must add it to this table with a state of either
 182  * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
 183  */
 184 static const CPRegStateLevel non_runtime_cpregs[] = {
 185     { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
 186 };
 187
 188 int kvm_arm_cpreg_level(uint64_t regidx)
 189 {
 190     int i;
 191
 192     for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
 193         const CPRegStateLevel *l = &non_runtime_cpregs[i];
 194         if (l->regidx == regidx) {
 195             return l->level;
 196         }
 197     }
 198
 199     return KVM_PUT_RUNTIME_STATE;
 200 }
 201
 202 #define ARM_CPU_ID_MPIDR       0, 0, 0, 5
 203
 204 int kvm_arch_init_vcpu(CPUState *cs)
 205 {
 206     int ret;
 207     uint64_t v;
 208     uint32_t mpidr;
 209     struct kvm_one_reg r;
 210     ARMCPU *cpu = ARM_CPU(cs);
 211
 212     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 213         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 214         return -EINVAL;
 215     }
 216
 217     qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
 218
 219     /* Determine init features for this CPU */
 220     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 221     if (cpu->start_powered_off) {
 222         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 223     }
 224     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 225         cpu->psci_version = 2;
 226         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 227     }
 228
 229     /* Do KVM_ARM_VCPU_INIT ioctl */
 230     ret = kvm_arm_vcpu_init(cs);
 231     if (ret) {
 232         return ret;
 233     }
 234
 235     /* Query the kernel to make sure it supports 32 VFP
 236      * registers: QEMU's "cortex-a15" CPU is always a
 237      * VFP-D32 core. The simplest way to do this is just
 238      * to attempt to read register d31.
 239      */
 240     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 241     r.addr = (uintptr_t)(&v);
 242     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 243     if (ret == -ENOENT) {
 244         return -EINVAL;
 245     }
 246
 247     /*
 248      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
 249      * Currently KVM has its own idea about MPIDR assignment, so we
 250      * override our defaults with what we get from KVM.
 251      */
 252     ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
 253     if (ret) {
 254         return ret;
 255     }
 256     cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
 257
 258     /* Check whether userspace can specify guest syndrome value */
 259     kvm_arm_init_serror_injection(cs);
 260
 261     return kvm_arm_init_cpreg_list(cpu);
 262 }
 263
 264 int kvm_arch_destroy_vcpu(CPUState *cs)
 265 {
 266         return 0;
 267 }
 268
 269 typedef struct Reg {
 270     uint64_t id;
 271     int offset;
 272 } Reg;
 273
 274 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 275     {                                                        \
 276         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 277         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 278         offsetof(CPUARMState, QEMUFIELD)                     \
 279     }
 280
 281 #define VFPSYSREG(R)                                       \
 282     {                                                      \
 283         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 284         KVM_REG_ARM_VFP_##R,                               \
 285         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 286     }
 287
 288 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 289 #define COREREG64(KERNELNAME, QEMUFIELD)                     \
 290     {                                                        \
 291         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 292         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 293         offsetoflow32(CPUARMState, QEMUFIELD)                \
 294     }
 295
 296 static const Reg regs[] = {
 297     /* R0_usr .. R14_usr */
 298     COREREG(usr_regs.uregs[0], regs[0]),
 299     COREREG(usr_regs.uregs[1], regs[1]),
 300     COREREG(usr_regs.uregs[2], regs[2]),
 301     COREREG(usr_regs.uregs[3], regs[3]),
 302     COREREG(usr_regs.uregs[4], regs[4]),
 303     COREREG(usr_regs.uregs[5], regs[5]),
 304     COREREG(usr_regs.uregs[6], regs[6]),
 305     COREREG(usr_regs.uregs[7], regs[7]),
 306     COREREG(usr_regs.uregs[8], usr_regs[0]),
 307     COREREG(usr_regs.uregs[9], usr_regs[1]),
 308     COREREG(usr_regs.uregs[10], usr_regs[2]),
 309     COREREG(usr_regs.uregs[11], usr_regs[3]),
 310     COREREG(usr_regs.uregs[12], usr_regs[4]),
 311     COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
 312     COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
 313     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 314     COREREG(svc_regs[0], banked_r13[BANK_SVC]),
 315     COREREG(svc_regs[1], banked_r14[BANK_SVC]),
 316     COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
 317     COREREG(abt_regs[0], banked_r13[BANK_ABT]),
 318     COREREG(abt_regs[1], banked_r14[BANK_ABT]),
 319     COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
 320     COREREG(und_regs[0], banked_r13[BANK_UND]),
 321     COREREG(und_regs[1], banked_r14[BANK_UND]),
 322     COREREG64(und_regs[2], banked_spsr[BANK_UND]),
 323     COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
 324     COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
 325     COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
 326     /* R8_fiq .. R14_fiq and SPSR_fiq */
 327     COREREG(fiq_regs[0], fiq_regs[0]),
 328     COREREG(fiq_regs[1], fiq_regs[1]),
 329     COREREG(fiq_regs[2], fiq_regs[2]),
 330     COREREG(fiq_regs[3], fiq_regs[3]),
 331     COREREG(fiq_regs[4], fiq_regs[4]),
 332     COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
 333     COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
 334     COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
 335     /* R15 */
 336     COREREG(usr_regs.uregs[15], regs[15]),
 337     /* VFP system registers */
 338     VFPSYSREG(FPSID),
 339     VFPSYSREG(MVFR1),
 340     VFPSYSREG(MVFR0),
 341     VFPSYSREG(FPEXC),
 342     VFPSYSREG(FPINST),
 343     VFPSYSREG(FPINST2),
 344 };
 345
 346 int kvm_arch_put_registers(CPUState *cs, int level)
 347 {
 348     ARMCPU *cpu = ARM_CPU(cs);
 349     CPUARMState *env = &cpu->env;
 350     struct kvm_one_reg r;
 351     int mode, bn;
 352     int ret, i;
 353     uint32_t cpsr, fpscr;
 354
 355     /* Make sure the banked regs are properly set */
 356     mode = env->uncached_cpsr & CPSR_M;
 357     bn = bank_number(mode);
 358     if (mode == ARM_CPU_MODE_FIQ) {
 359         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 360     } else {
 361         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 362     }
 363     env->banked_r13[bn] = env->regs[13];
 364     env->banked_spsr[bn] = env->spsr;
 365     env->banked_r14[r14_bank_number(mode)] = env->regs[14];
 366
 367     /* Now we can safely copy stuff down to the kernel */
 368     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 369         r.id = regs[i].id;
 370         r.addr = (uintptr_t)(env) + regs[i].offset;
 371         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 372         if (ret) {
 373             return ret;
 374         }
 375     }
 376
 377     /* Special cases which aren't a single CPUARMState field */
 378     cpsr = cpsr_read(env);
 379     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 380         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 381     r.addr = (uintptr_t)(&cpsr);
 382     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 383     if (ret) {
 384         return ret;
 385     }
 386
 387     /* VFP registers */
 388     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 389     for (i = 0; i < 32; i++) {
 390         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 391         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 392         if (ret) {
 393             return ret;
 394         }
 395         r.id++;
 396     }
 397
 398     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 399         KVM_REG_ARM_VFP_FPSCR;
 400     fpscr = vfp_get_fpscr(env);
 401     r.addr = (uintptr_t)&fpscr;
 402     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 403     if (ret) {
 404         return ret;
 405     }
 406
 407     write_cpustate_to_list(cpu, true);
 408
 409     if (!write_list_to_kvmstate(cpu, level)) {
 410         return EINVAL;
 411     }
 412
 413     /*
 414      * Setting VCPU events should be triggered after syncing the registers
 415      * to avoid overwriting potential changes made by KVM upon calling
 416      * KVM_SET_VCPU_EVENTS ioctl
 417      */
 418     ret = kvm_put_vcpu_events(cpu);
 419     if (ret) {
 420         return ret;
 421     }
 422
 423     kvm_arm_sync_mpstate_to_kvm(cpu);
 424
 425     return ret;
 426 }
 427
 428 int kvm_arch_get_registers(CPUState *cs)
 429 {
 430     ARMCPU *cpu = ARM_CPU(cs);
 431     CPUARMState *env = &cpu->env;
 432     struct kvm_one_reg r;
 433     int mode, bn;
 434     int ret, i;
 435     uint32_t cpsr, fpscr;
 436
 437     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 438         r.id = regs[i].id;
 439         r.addr = (uintptr_t)(env) + regs[i].offset;
 440         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 441         if (ret) {
 442             return ret;
 443         }
 444     }
 445
 446     /* Special cases which aren't a single CPUARMState field */
 447     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 448         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 449     r.addr = (uintptr_t)(&cpsr);
 450     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 451     if (ret) {
 452         return ret;
 453     }
 454     cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
 455
 456     /* Make sure the current mode regs are properly set */
 457     mode = env->uncached_cpsr & CPSR_M;
 458     bn = bank_number(mode);
 459     if (mode == ARM_CPU_MODE_FIQ) {
 460         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 461     } else {
 462         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 463     }
 464     env->regs[13] = env->banked_r13[bn];
 465     env->spsr = env->banked_spsr[bn];
 466     env->regs[14] = env->banked_r14[r14_bank_number(mode)];
 467
 468     /* VFP registers */
 469     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 470     for (i = 0; i < 32; i++) {
 471         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 472         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 473         if (ret) {
 474             return ret;
 475         }
 476         r.id++;
 477     }
 478
 479     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 480         KVM_REG_ARM_VFP_FPSCR;
 481     r.addr = (uintptr_t)&fpscr;
 482     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 483     if (ret) {
 484         return ret;
 485     }
 486     vfp_set_fpscr(env, fpscr);
 487
 488     ret = kvm_get_vcpu_events(cpu);
 489     if (ret) {
 490         return ret;
 491     }
 492
 493     if (!write_kvmstate_to_list(cpu)) {
 494         return EINVAL;
 495     }
 496     /* Note that it's OK to have registers which aren't in CPUState,
 497      * so we can ignore a failure return here.
 498      */
 499     write_list_to_cpustate(cpu);
 500
 501     kvm_arm_sync_mpstate_to_qemu(cpu);
 502
 503     return 0;
 504 }
 505
 506 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 507 {
 508     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 509     return -EINVAL;
 510 }
 511
 512 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 513 {
 514     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 515     return -EINVAL;
 516 }
 517
 518 bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 519 {
 520     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 521     return false;
 522 }
 523
 524 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 525                                   target_ulong len, int type)
 526 {
 527     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 528     return -EINVAL;
 529 }
 530
 531 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 532                                   target_ulong len, int type)
 533 {
 534     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 535     return -EINVAL;
 536 }
 537
 538 void kvm_arch_remove_all_hw_breakpoints(void)
 539 {
 540     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 541 }
 542
 543 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
 544 {
 545     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 546 }
 547
 548 bool kvm_arm_hw_debug_active(CPUState *cs)
 549 {
 550     return false;
 551 }
 552
 553 void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
 554 {
 555     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 556 }
 557
 558 void kvm_arm_pmu_init(CPUState *cs)
 559 {
 560     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 561 }