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acpi: ipmi: use AcpiDevAmlIf interface to build IPMI device descriptors
[qemu.git] / hw / i386 / acpi-build.c
blob5b963cca3229601d97bc54343498be5ae833614b
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/cxl/cxl.h"
32 #include "hw/core/cpu.h"
33 #include "target/i386/cpu.h"
34 #include "hw/misc/pvpanic.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/acpi/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/acpi/cpu.h"
39 #include "hw/nvram/fw_cfg.h"
40 #include "hw/acpi/bios-linker-loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/acpi/acpi_aml_interface.h"
43 #include "hw/input/i8042.h"
44 #include "hw/acpi/memory_hotplug.h"
45 #include "sysemu/tpm.h"
46 #include "hw/acpi/tpm.h"
47 #include "hw/acpi/vmgenid.h"
48 #include "hw/acpi/erst.h"
49 #include "sysemu/tpm_backend.h"
50 #include "hw/rtc/mc146818rtc_regs.h"
51 #include "migration/vmstate.h"
52 #include "hw/mem/memory-device.h"
53 #include "hw/mem/nvdimm.h"
54 #include "sysemu/numa.h"
55 #include "sysemu/reset.h"
56 #include "hw/hyperv/vmbus-bridge.h"
57
58 /* Supported chipsets: */
59 #include "hw/southbridge/piix.h"
60 #include "hw/acpi/pcihp.h"
61 #include "hw/i386/fw_cfg.h"
62 #include "hw/i386/ich9.h"
63 #include "hw/pci/pci_bus.h"
64 #include "hw/pci-host/q35.h"
65 #include "hw/i386/x86-iommu.h"
66
67 #include "hw/acpi/aml-build.h"
68 #include "hw/acpi/utils.h"
69 #include "hw/acpi/pci.h"
70 #include "hw/acpi/cxl.h"
71
72 #include "qom/qom-qobject.h"
73 #include "hw/i386/amd_iommu.h"
74 #include "hw/i386/intel_iommu.h"
75 #include "hw/virtio/virtio-iommu.h"
76
77 #include "hw/acpi/hmat.h"
78 #include "hw/acpi/viot.h"
79 #include "hw/acpi/cxl.h"
80
81 #include CONFIG_DEVICES
82
83 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
84 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
85 * a little bit, there should be plenty of free space since the DSDT
86 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
87 */
88 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
89 #define ACPI_BUILD_ALIGN_SIZE 0x1000
90
91 #define ACPI_BUILD_TABLE_SIZE 0x20000
92
93 /* #define DEBUG_ACPI_BUILD */
94 #ifdef DEBUG_ACPI_BUILD
95 #define ACPI_BUILD_DPRINTF(fmt, ...) \
96 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
97 #else
98 #define ACPI_BUILD_DPRINTF(fmt, ...)
99 #endif
100
101 typedef struct AcpiPmInfo {
102 bool s3_disabled;
103 bool s4_disabled;
104 bool pcihp_bridge_en;
105 bool smi_on_cpuhp;
106 bool smi_on_cpu_unplug;
107 bool pcihp_root_en;
108 uint8_t s4_val;
109 AcpiFadtData fadt;
110 uint16_t cpu_hp_io_base;
111 uint16_t pcihp_io_base;
112 uint16_t pcihp_io_len;
113 } AcpiPmInfo;
114
115 typedef struct AcpiMiscInfo {
116 bool is_piix4;
117 bool has_hpet;
118 #ifdef CONFIG_TPM
119 TPMVersion tpm_version;
120 #endif
121 const unsigned char *dsdt_code;
122 unsigned dsdt_size;
123 uint16_t pvpanic_port;
124 uint16_t applesmc_io_base;
125 } AcpiMiscInfo;
126
127 typedef struct AcpiBuildPciBusHotplugState {
128 GArray *device_table;
129 GArray *notify_table;
130 struct AcpiBuildPciBusHotplugState *parent;
131 bool pcihp_bridge_en;
132 } AcpiBuildPciBusHotplugState;
133
134 typedef struct FwCfgTPMConfig {
135 uint32_t tpmppi_address;
136 uint8_t tpm_version;
137 uint8_t tpmppi_version;
138 } QEMU_PACKED FwCfgTPMConfig;
139
140 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
141
142 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
143 .space_id = AML_AS_SYSTEM_IO,
144 .address = NVDIMM_ACPI_IO_BASE,
145 .bit_width = NVDIMM_ACPI_IO_LEN << 3
146 };
147
148 static void init_common_fadt_data(MachineState *ms, Object *o,
149 AcpiFadtData *data)
150 {
151 X86MachineState *x86ms = X86_MACHINE(ms);
152 /*
153 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
154 * behavior for compatibility irrelevant to smm_enabled, which doesn't
155 * comforms to ACPI spec.
156 */
157 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
158 true : x86_machine_is_smm_enabled(x86ms);
159 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
160 AmlAddressSpace as = AML_AS_SYSTEM_IO;
161 AcpiFadtData fadt = {
162 .rev = 3,
163 .flags =
164 (1 << ACPI_FADT_F_WBINVD) |
165 (1 << ACPI_FADT_F_PROC_C1) |
166 (1 << ACPI_FADT_F_SLP_BUTTON) |
167 (1 << ACPI_FADT_F_RTC_S4) |
168 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
169 /* APIC destination mode ("Flat Logical") has an upper limit of 8
170 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
171 * used
172 */
173 ((ms->smp.max_cpus > 8) ?
174 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
175 .int_model = 1 /* Multiple APIC */,
176 .rtc_century = RTC_CENTURY,
177 .plvl2_lat = 0xfff /* C2 state not supported */,
178 .plvl3_lat = 0xfff /* C3 state not supported */,
179 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
180 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
181 .acpi_enable_cmd =
182 smm_enabled ?
183 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
184 0,
185 .acpi_disable_cmd =
186 smm_enabled ?
187 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
188 0,
189 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
190 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
191 .address = io + 0x04 },
192 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
193 .gpe0_blk = { .space_id = as, .bit_width =
194 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
195 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
196 },
197 };
198
199 /*
200 * ACPI v2, Table 5-10 - Fixed ACPI Description Table Boot Architecture
201 * Flags, bit offset 1 - 8042.
202 */
203 fadt.iapc_boot_arch = iapc_boot_arch_8042();
204
205 *data = fadt;
206 }
207
208 static Object *object_resolve_type_unambiguous(const char *typename)
209 {
210 bool ambig;
211 Object *o = object_resolve_path_type("", typename, &ambig);
212
213 if (ambig || !o) {
214 return NULL;
215 }
216 return o;
217 }
218
219 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
220 {
221 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
222 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
223 Object *obj = piix ? piix : lpc;
224 QObject *o;
225 pm->cpu_hp_io_base = 0;
226 pm->pcihp_io_base = 0;
227 pm->pcihp_io_len = 0;
228 pm->smi_on_cpuhp = false;
229 pm->smi_on_cpu_unplug = false;
230
231 assert(obj);
232 init_common_fadt_data(machine, obj, &pm->fadt);
233 if (piix) {
234 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
235 pm->fadt.rev = 1;
236 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
237 }
238 if (lpc) {
239 uint64_t smi_features = object_property_get_uint(lpc,
240 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
241 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
242 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
243 pm->fadt.reset_reg = r;
244 pm->fadt.reset_val = 0xf;
245 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
246 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
247 pm->smi_on_cpuhp =
248 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
249 pm->smi_on_cpu_unplug =
250 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
251 }
252 pm->pcihp_io_base =
253 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
254 pm->pcihp_io_len =
255 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
256
257 /* The above need not be conditional on machine type because the reset port
258 * happens to be the same on PIIX (pc) and ICH9 (q35). */
259 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
260
261 /* Fill in optional s3/s4 related properties */
262 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
263 if (o) {
264 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
265 } else {
266 pm->s3_disabled = false;
267 }
268 qobject_unref(o);
269 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
270 if (o) {
271 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
272 } else {
273 pm->s4_disabled = false;
274 }
275 qobject_unref(o);
276 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
277 if (o) {
278 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
279 } else {
280 pm->s4_val = false;
281 }
282 qobject_unref(o);
283
284 pm->pcihp_bridge_en =
285 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCIHP_BRIDGE,
286 NULL);
287 pm->pcihp_root_en =
288 object_property_get_bool(obj, ACPI_PM_PROP_ACPI_PCI_ROOTHP,
289 NULL);
290 }
291
292 static void acpi_get_misc_info(AcpiMiscInfo *info)
293 {
294 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
295 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
296 assert(!!piix != !!lpc);
297
298 if (piix) {
299 info->is_piix4 = true;
300 }
301 if (lpc) {
302 info->is_piix4 = false;
303 }
304
305 info->has_hpet = hpet_find();
306 #ifdef CONFIG_TPM
307 info->tpm_version = tpm_get_version(tpm_find());
308 #endif
309 info->pvpanic_port = pvpanic_port();
310 info->applesmc_io_base = applesmc_port();
311 }
312
313 /*
314 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
315 * On i386 arch we only have two pci hosts, so we can look only for them.
316 */
317 Object *acpi_get_i386_pci_host(void)
318 {
319 PCIHostState *host;
320
321 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/i440fx", NULL));
322 if (!host) {
323 host = PCI_HOST_BRIDGE(object_resolve_path("/machine/q35", NULL));
324 }
325
326 return OBJECT(host);
327 }
328
329 static void acpi_get_pci_holes(Range *hole, Range *hole64)
330 {
331 Object *pci_host;
332
333 pci_host = acpi_get_i386_pci_host();
334
335 if (!pci_host) {
336 return;
337 }
338
339 range_set_bounds1(hole,
340 object_property_get_uint(pci_host,
341 PCI_HOST_PROP_PCI_HOLE_START,
342 NULL),
343 object_property_get_uint(pci_host,
344 PCI_HOST_PROP_PCI_HOLE_END,
345 NULL));
346 range_set_bounds1(hole64,
347 object_property_get_uint(pci_host,
348 PCI_HOST_PROP_PCI_HOLE64_START,
349 NULL),
350 object_property_get_uint(pci_host,
351 PCI_HOST_PROP_PCI_HOLE64_END,
352 NULL));
353 }
354
355 static void acpi_align_size(GArray *blob, unsigned align)
356 {
357 /* Align size to multiple of given size. This reduces the chance
358 * we need to change size in the future (breaking cross version migration).
359 */
360 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
361 }
362
363 /*
364 * ACPI spec 1.0b,
365 * 5.2.6 Firmware ACPI Control Structure
366 */
367 static void
368 build_facs(GArray *table_data)
369 {
370 const char *sig = "FACS";
371 const uint8_t reserved[40] = {};
372
373 g_array_append_vals(table_data, sig, 4); /* Signature */
374 build_append_int_noprefix(table_data, 64, 4); /* Length */
375 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */
376 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */
377 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */
378 build_append_int_noprefix(table_data, 0, 4); /* Flags */
379 g_array_append_vals(table_data, reserved, 40); /* Reserved */
380 }
381
382 static void build_append_pcihp_notify_entry(Aml *method, int slot)
383 {
384 Aml *if_ctx;
385 int32_t devfn = PCI_DEVFN(slot, 0);
386
387 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
388 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
389 aml_append(method, if_ctx);
390 }
391
392 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
393 bool pcihp_bridge_en)
394 {
395 Aml *dev, *notify_method = NULL, *method;
396 QObject *bsel;
397 PCIBus *sec;
398 int devfn;
399
400 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
401 if (bsel) {
402 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
403
404 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
405 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
406 }
407
408 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
409 DeviceClass *dc;
410 PCIDeviceClass *pc;
411 PCIDevice *pdev = bus->devices[devfn];
412 int slot = PCI_SLOT(devfn);
413 int func = PCI_FUNC(devfn);
414 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
415 int adr = slot << 16 | func;
416 bool hotplug_enabled_dev;
417 bool bridge_in_acpi;
418 bool cold_plugged_bridge;
419
420 if (!pdev) {
421 /*
422 * add hotplug slots for non present devices.
423 * hotplug is supported only for non-multifunction device
424 * so generate device description only for function 0
425 */
426 if (bsel && !func) {
427 if (pci_bus_is_express(bus) && slot > 0) {
428 break;
429 }
430 dev = aml_device("S%.02X", devfn);
431 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
432 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
433 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
434 aml_append(method,
435 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
436 );
437 aml_append(dev, method);
438 method = aml_method("_DSM", 4, AML_SERIALIZED);
439 aml_append(method,
440 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1),
441 aml_arg(2), aml_arg(3),
442 aml_name("BSEL"), aml_name("_SUN")))
443 );
444 aml_append(dev, method);
445 aml_append(parent_scope, dev);
446
447 build_append_pcihp_notify_entry(notify_method, slot);
448 }
449 continue;
450 }
451
452 pc = PCI_DEVICE_GET_CLASS(pdev);
453 dc = DEVICE_GET_CLASS(pdev);
454
455 /*
456 * Cold plugged bridges aren't themselves hot-pluggable.
457 * Hotplugged bridges *are* hot-pluggable.
458 */
459 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
460 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
461
462 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
463
464 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
465 continue;
466 }
467
468 /*
469 * allow describing coldplugged bridges in ACPI even if they are not
470 * on function 0, as they are not unpluggable, for all other devices
471 * generate description only for function 0 per slot
472 */
473 if (func && !bridge_in_acpi) {
474 continue;
475 }
476
477 /* start to compose PCI device descriptor */
478 dev = aml_device("S%.02X", devfn);
479 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
480
481 if (bsel) {
482 /*
483 * Can't declare _SUN here for every device as it changes 'slot'
484 * enumeration order in linux kernel, so use another variable for it
485 */
486 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
487 method = aml_method("_DSM", 4, AML_SERIALIZED);
488 aml_append(method, aml_return(
489 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
490 aml_arg(3), aml_name("BSEL"), aml_name("ASUN"))
491 ));
492 aml_append(dev, method);
493 }
494
495 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
496 /* add VGA specific AML methods */
497 int s3d;
498
499 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
500 s3d = 3;
501 } else {
502 s3d = 0;
503 }
504
505 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
506 aml_append(method, aml_return(aml_int(0)));
507 aml_append(dev, method);
508
509 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
510 aml_append(method, aml_return(aml_int(0)));
511 aml_append(dev, method);
512
513 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
514 aml_append(method, aml_return(aml_int(s3d)));
515 aml_append(dev, method);
516 } else if (hotplug_enabled_dev) {
517 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
518 /* add _EJ0 to make slot hotpluggable */
519 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
520 aml_append(method,
521 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
522 );
523 aml_append(dev, method);
524
525 if (bsel) {
526 build_append_pcihp_notify_entry(notify_method, slot);
527 }
528 } else if (bridge_in_acpi) {
529 /*
530 * device is coldplugged bridge,
531 * add child device descriptions into its scope
532 */
533 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
534
535 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
536 }
537 /* device descriptor has been composed, add it into parent context */
538 aml_append(parent_scope, dev);
539 }
540
541 if (bsel) {
542 aml_append(parent_scope, notify_method);
543 }
544
545 /* Append PCNT method to notify about events on local and child buses.
546 * Add this method for root bus only when hotplug is enabled since DSDT
547 * expects it.
548 */
549 if (bsel || pcihp_bridge_en) {
550 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
551
552 /* If bus supports hotplug select it and notify about local events */
553 if (bsel) {
554 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
555
556 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
557 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
558 aml_int(1))); /* Device Check */
559 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
560 aml_int(3))); /* Eject Request */
561 }
562
563 /* Notify about child bus events in any case */
564 if (pcihp_bridge_en) {
565 QLIST_FOREACH(sec, &bus->child, sibling) {
566 if (pci_bus_is_root(sec)) {
567 continue;
568 }
569
570 aml_append(method, aml_name("^S%.02X.PCNT",
571 sec->parent_dev->devfn));
572 }
573 }
574
575 aml_append(parent_scope, method);
576 }
577 qobject_unref(bsel);
578 }
579
580 Aml *aml_pci_device_dsm(void)
581 {
582 Aml *method, *UUID, *ifctx, *ifctx1, *ifctx2, *ifctx3, *elsectx;
583 Aml *acpi_index = aml_local(0);
584 Aml *zero = aml_int(0);
585 Aml *bnum = aml_arg(4);
586 Aml *func = aml_arg(2);
587 Aml *rev = aml_arg(1);
588 Aml *sunum = aml_arg(5);
589
590 method = aml_method("PDSM", 6, AML_SERIALIZED);
591
592 /*
593 * PCI Firmware Specification 3.1
594 * 4.6. _DSM Definitions for PCI
595 */
596 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
597 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
598 {
599 aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
600 ifctx1 = aml_if(aml_equal(func, zero));
601 {
602 uint8_t byte_list[1];
603
604 ifctx2 = aml_if(aml_equal(rev, aml_int(2)));
605 {
606 /*
607 * advertise function 7 if device has acpi-index
608 * acpi_index values:
609 * 0: not present (default value)
610 * FFFFFFFF: not supported (old QEMU without PIDX reg)
611 * other: device's acpi-index
612 */
613 ifctx3 = aml_if(aml_lnot(
614 aml_or(aml_equal(acpi_index, zero),
615 aml_equal(acpi_index, aml_int(0xFFFFFFFF)), NULL)
616 ));
617 {
618 byte_list[0] =
619 1 /* have supported functions */ |
620 1 << 7 /* support for function 7 */
621 ;
622 aml_append(ifctx3, aml_return(aml_buffer(1, byte_list)));
623 }
624 aml_append(ifctx2, ifctx3);
625 }
626 aml_append(ifctx1, ifctx2);
627
628 byte_list[0] = 0; /* nothing supported */
629 aml_append(ifctx1, aml_return(aml_buffer(1, byte_list)));
630 }
631 aml_append(ifctx, ifctx1);
632 elsectx = aml_else();
633 /*
634 * PCI Firmware Specification 3.1
635 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
636 * Operating Systems
637 */
638 ifctx1 = aml_if(aml_equal(func, aml_int(7)));
639 {
640 Aml *pkg = aml_package(2);
641 Aml *ret = aml_local(1);
642
643 aml_append(pkg, zero);
644 /*
645 * optional, if not impl. should return null string
646 */
647 aml_append(pkg, aml_string("%s", ""));
648 aml_append(ifctx1, aml_store(pkg, ret));
649 /*
650 * update acpi-index to actual value
651 */
652 aml_append(ifctx1, aml_store(acpi_index, aml_index(ret, zero)));
653 aml_append(ifctx1, aml_return(ret));
654 }
655 aml_append(elsectx, ifctx1);
656 aml_append(ifctx, elsectx);
657 }
658 aml_append(method, ifctx);
659 return method;
660 }
661
662 /**
663 * build_prt_entry:
664 * @link_name: link name for PCI route entry
665 *
666 * build AML package containing a PCI route entry for @link_name
667 */
668 static Aml *build_prt_entry(const char *link_name)
669 {
670 Aml *a_zero = aml_int(0);
671 Aml *pkg = aml_package(4);
672 aml_append(pkg, a_zero);
673 aml_append(pkg, a_zero);
674 aml_append(pkg, aml_name("%s", link_name));
675 aml_append(pkg, a_zero);
676 return pkg;
677 }
678
679 /*
680 * initialize_route - Initialize the interrupt routing rule
681 * through a specific LINK:
682 * if (lnk_idx == idx)
683 * route using link 'link_name'
684 */
685 static Aml *initialize_route(Aml *route, const char *link_name,
686 Aml *lnk_idx, int idx)
687 {
688 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
689 Aml *pkg = build_prt_entry(link_name);
690
691 aml_append(if_ctx, aml_store(pkg, route));
692
693 return if_ctx;
694 }
695
696 /*
697 * build_prt - Define interrupt rounting rules
698 *
699 * Returns an array of 128 routes, one for each device,
700 * based on device location.
701 * The main goal is to equaly distribute the interrupts
702 * over the 4 existing ACPI links (works only for i440fx).
703 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
704 *
705 */
706 static Aml *build_prt(bool is_pci0_prt)
707 {
708 Aml *method, *while_ctx, *pin, *res;
709
710 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
711 res = aml_local(0);
712 pin = aml_local(1);
713 aml_append(method, aml_store(aml_package(128), res));
714 aml_append(method, aml_store(aml_int(0), pin));
715
716 /* while (pin < 128) */
717 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
718 {
719 Aml *slot = aml_local(2);
720 Aml *lnk_idx = aml_local(3);
721 Aml *route = aml_local(4);
722
723 /* slot = pin >> 2 */
724 aml_append(while_ctx,
725 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
726 /* lnk_idx = (slot + pin) & 3 */
727 aml_append(while_ctx,
728 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
729 lnk_idx));
730
731 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
732 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
733 if (is_pci0_prt) {
734 Aml *if_device_1, *if_pin_4, *else_pin_4;
735
736 /* device 1 is the power-management device, needs SCI */
737 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
738 {
739 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
740 {
741 aml_append(if_pin_4,
742 aml_store(build_prt_entry("LNKS"), route));
743 }
744 aml_append(if_device_1, if_pin_4);
745 else_pin_4 = aml_else();
746 {
747 aml_append(else_pin_4,
748 aml_store(build_prt_entry("LNKA"), route));
749 }
750 aml_append(if_device_1, else_pin_4);
751 }
752 aml_append(while_ctx, if_device_1);
753 } else {
754 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
755 }
756 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
757 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
758
759 /* route[0] = 0x[slot]FFFF */
760 aml_append(while_ctx,
761 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
762 NULL),
763 aml_index(route, aml_int(0))));
764 /* route[1] = pin & 3 */
765 aml_append(while_ctx,
766 aml_store(aml_and(pin, aml_int(3), NULL),
767 aml_index(route, aml_int(1))));
768 /* res[pin] = route */
769 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
770 /* pin++ */
771 aml_append(while_ctx, aml_increment(pin));
772 }
773 aml_append(method, while_ctx);
774 /* return res*/
775 aml_append(method, aml_return(res));
776
777 return method;
778 }
779
780 static void build_hpet_aml(Aml *table)
781 {
782 Aml *crs;
783 Aml *field;
784 Aml *method;
785 Aml *if_ctx;
786 Aml *scope = aml_scope("_SB");
787 Aml *dev = aml_device("HPET");
788 Aml *zero = aml_int(0);
789 Aml *id = aml_local(0);
790 Aml *period = aml_local(1);
791
792 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
793 aml_append(dev, aml_name_decl("_UID", zero));
794
795 aml_append(dev,
796 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
797 HPET_LEN));
798 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
799 aml_append(field, aml_named_field("VEND", 32));
800 aml_append(field, aml_named_field("PRD", 32));
801 aml_append(dev, field);
802
803 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
804 aml_append(method, aml_store(aml_name("VEND"), id));
805 aml_append(method, aml_store(aml_name("PRD"), period));
806 aml_append(method, aml_shiftright(id, aml_int(16), id));
807 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
808 aml_equal(id, aml_int(0xffff))));
809 {
810 aml_append(if_ctx, aml_return(zero));
811 }
812 aml_append(method, if_ctx);
813
814 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
815 aml_lgreater(period, aml_int(100000000))));
816 {
817 aml_append(if_ctx, aml_return(zero));
818 }
819 aml_append(method, if_ctx);
820
821 aml_append(method, aml_return(aml_int(0x0F)));
822 aml_append(dev, method);
823
824 crs = aml_resource_template();
825 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
826 aml_append(dev, aml_name_decl("_CRS", crs));
827
828 aml_append(scope, dev);
829 aml_append(table, scope);
830 }
831
832 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
833 {
834 Aml *dev;
835 Aml *method;
836 Aml *crs;
837
838 dev = aml_device("VMBS");
839 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
840 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
841 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
842 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
843
844 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
845 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
846 aml_name("STA")));
847 aml_append(dev, method);
848
849 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
850 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
851 aml_name("STA")));
852 aml_append(dev, method);
853
854 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
855 aml_append(method, aml_return(aml_name("STA")));
856 aml_append(dev, method);
857
858 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
859
860 crs = aml_resource_template();
861 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
862 aml_append(dev, aml_name_decl("_CRS", crs));
863
864 return dev;
865 }
866
867 static void build_isa_devices_aml(Aml *table)
868 {
869 bool ambiguous;
870 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
871 Aml *scope;
872
873 assert(obj && !ambiguous);
874
875 scope = aml_scope("_SB.PCI0.ISA");
876 isa_build_aml(ISA_BUS(obj), scope);
877
878 aml_append(table, scope);
879 }
880
881 static void build_dbg_aml(Aml *table)
882 {
883 Aml *field;
884 Aml *method;
885 Aml *while_ctx;
886 Aml *scope = aml_scope("\\");
887 Aml *buf = aml_local(0);
888 Aml *len = aml_local(1);
889 Aml *idx = aml_local(2);
890
891 aml_append(scope,
892 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
893 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
894 aml_append(field, aml_named_field("DBGB", 8));
895 aml_append(scope, field);
896
897 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
898
899 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
900 aml_append(method, aml_to_buffer(buf, buf));
901 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
902 aml_append(method, aml_store(aml_int(0), idx));
903
904 while_ctx = aml_while(aml_lless(idx, len));
905 aml_append(while_ctx,
906 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
907 aml_append(while_ctx, aml_increment(idx));
908 aml_append(method, while_ctx);
909
910 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
911 aml_append(scope, method);
912
913 aml_append(table, scope);
914 }
915
916 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
917 {
918 Aml *dev;
919 Aml *crs;
920 Aml *method;
921 uint32_t irqs[] = {5, 10, 11};
922
923 dev = aml_device("%s", name);
924 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
925 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
926
927 crs = aml_resource_template();
928 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
929 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
930 aml_append(dev, aml_name_decl("_PRS", crs));
931
932 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
933 aml_append(method, aml_return(aml_call1("IQST", reg)));
934 aml_append(dev, method);
935
936 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
937 aml_append(method, aml_or(reg, aml_int(0x80), reg));
938 aml_append(dev, method);
939
940 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
941 aml_append(method, aml_return(aml_call1("IQCR", reg)));
942 aml_append(dev, method);
943
944 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
945 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
946 aml_append(method, aml_store(aml_name("PRRI"), reg));
947 aml_append(dev, method);
948
949 return dev;
950 }
951
952 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
953 {
954 Aml *dev;
955 Aml *crs;
956 Aml *method;
957 uint32_t irqs;
958
959 dev = aml_device("%s", name);
960 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
961 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
962
963 crs = aml_resource_template();
964 irqs = gsi;
965 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
966 AML_SHARED, &irqs, 1));
967 aml_append(dev, aml_name_decl("_PRS", crs));
968
969 aml_append(dev, aml_name_decl("_CRS", crs));
970
971 /*
972 * _DIS can be no-op because the interrupt cannot be disabled.
973 */
974 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
975 aml_append(dev, method);
976
977 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
978 aml_append(dev, method);
979
980 return dev;
981 }
982
983 /* _CRS method - get current settings */
984 static Aml *build_iqcr_method(bool is_piix4)
985 {
986 Aml *if_ctx;
987 uint32_t irqs;
988 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
989 Aml *crs = aml_resource_template();
990
991 irqs = 0;
992 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
993 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
994 aml_append(method, aml_name_decl("PRR0", crs));
995
996 aml_append(method,
997 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
998
999 if (is_piix4) {
1000 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1001 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1002 aml_append(method, if_ctx);
1003 } else {
1004 aml_append(method,
1005 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1006 aml_name("PRRI")));
1007 }
1008
1009 aml_append(method, aml_return(aml_name("PRR0")));
1010 return method;
1011 }
1012
1013 /* _STA method - get status */
1014 static Aml *build_irq_status_method(void)
1015 {
1016 Aml *if_ctx;
1017 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1018
1019 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1020 aml_append(if_ctx, aml_return(aml_int(0x09)));
1021 aml_append(method, if_ctx);
1022 aml_append(method, aml_return(aml_int(0x0B)));
1023 return method;
1024 }
1025
1026 static void build_piix4_pci0_int(Aml *table)
1027 {
1028 Aml *dev;
1029 Aml *crs;
1030 Aml *field;
1031 Aml *method;
1032 uint32_t irqs;
1033 Aml *sb_scope = aml_scope("_SB");
1034 Aml *pci0_scope = aml_scope("PCI0");
1035
1036 aml_append(pci0_scope, build_prt(true));
1037 aml_append(sb_scope, pci0_scope);
1038
1039 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1040 aml_append(field, aml_named_field("PRQ0", 8));
1041 aml_append(field, aml_named_field("PRQ1", 8));
1042 aml_append(field, aml_named_field("PRQ2", 8));
1043 aml_append(field, aml_named_field("PRQ3", 8));
1044 aml_append(sb_scope, field);
1045
1046 aml_append(sb_scope, build_irq_status_method());
1047 aml_append(sb_scope, build_iqcr_method(true));
1048
1049 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1050 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1051 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1052 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1053
1054 dev = aml_device("LNKS");
1055 {
1056 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1057 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1058
1059 crs = aml_resource_template();
1060 irqs = 9;
1061 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1062 AML_ACTIVE_HIGH, AML_SHARED,
1063 &irqs, 1));
1064 aml_append(dev, aml_name_decl("_PRS", crs));
1065
1066 /* The SCI cannot be disabled and is always attached to GSI 9,
1067 * so these are no-ops. We only need this link to override the
1068 * polarity to active high and match the content of the MADT.
1069 */
1070 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1071 aml_append(method, aml_return(aml_int(0x0b)));
1072 aml_append(dev, method);
1073
1074 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1075 aml_append(dev, method);
1076
1077 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1078 aml_append(method, aml_return(aml_name("_PRS")));
1079 aml_append(dev, method);
1080
1081 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1082 aml_append(dev, method);
1083 }
1084 aml_append(sb_scope, dev);
1085
1086 aml_append(table, sb_scope);
1087 }
1088
1089 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1090 {
1091 int i;
1092 int head;
1093 Aml *pkg;
1094 char base = name[3] < 'E' ? 'A' : 'E';
1095 char *s = g_strdup(name);
1096 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1097
1098 assert(strlen(s) == 4);
1099
1100 head = name[3] - base;
1101 for (i = 0; i < 4; i++) {
1102 if (head + i > 3) {
1103 head = i * -1;
1104 }
1105 s[3] = base + head + i;
1106 pkg = aml_package(4);
1107 aml_append(pkg, a_nr);
1108 aml_append(pkg, aml_int(i));
1109 aml_append(pkg, aml_name("%s", s));
1110 aml_append(pkg, aml_int(0));
1111 aml_append(ctx, pkg);
1112 }
1113 g_free(s);
1114 }
1115
1116 static Aml *build_q35_routing_table(const char *str)
1117 {
1118 int i;
1119 Aml *pkg;
1120 char *name = g_strdup_printf("%s ", str);
1121
1122 pkg = aml_package(128);
1123 for (i = 0; i < 0x18; i++) {
1124 name[3] = 'E' + (i & 0x3);
1125 append_q35_prt_entry(pkg, i, name);
1126 }
1127
1128 name[3] = 'E';
1129 append_q35_prt_entry(pkg, 0x18, name);
1130
1131 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1132 for (i = 0x0019; i < 0x1e; i++) {
1133 name[3] = 'A';
1134 append_q35_prt_entry(pkg, i, name);
1135 }
1136
1137 /* PCIe->PCI bridge. use PIRQ[E-H] */
1138 name[3] = 'E';
1139 append_q35_prt_entry(pkg, 0x1e, name);
1140 name[3] = 'A';
1141 append_q35_prt_entry(pkg, 0x1f, name);
1142
1143 g_free(name);
1144 return pkg;
1145 }
1146
1147 static void build_q35_pci0_int(Aml *table)
1148 {
1149 Aml *field;
1150 Aml *method;
1151 Aml *sb_scope = aml_scope("_SB");
1152 Aml *pci0_scope = aml_scope("PCI0");
1153
1154 /* Zero => PIC mode, One => APIC Mode */
1155 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1156 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1157 {
1158 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1159 }
1160 aml_append(table, method);
1161
1162 aml_append(pci0_scope,
1163 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1164 aml_append(pci0_scope,
1165 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1166
1167 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1168 {
1169 Aml *if_ctx;
1170 Aml *else_ctx;
1171
1172 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1173 section 6.2.8.1 */
1174 /* Note: we provide the same info as the PCI routing
1175 table of the Bochs BIOS */
1176 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1177 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1178 aml_append(method, if_ctx);
1179 else_ctx = aml_else();
1180 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1181 aml_append(method, else_ctx);
1182 }
1183 aml_append(pci0_scope, method);
1184 aml_append(sb_scope, pci0_scope);
1185
1186 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1187 aml_append(field, aml_named_field("PRQA", 8));
1188 aml_append(field, aml_named_field("PRQB", 8));
1189 aml_append(field, aml_named_field("PRQC", 8));
1190 aml_append(field, aml_named_field("PRQD", 8));
1191 aml_append(field, aml_reserved_field(0x20));
1192 aml_append(field, aml_named_field("PRQE", 8));
1193 aml_append(field, aml_named_field("PRQF", 8));
1194 aml_append(field, aml_named_field("PRQG", 8));
1195 aml_append(field, aml_named_field("PRQH", 8));
1196 aml_append(sb_scope, field);
1197
1198 aml_append(sb_scope, build_irq_status_method());
1199 aml_append(sb_scope, build_iqcr_method(false));
1200
1201 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1202 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1203 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1204 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1205 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1206 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1207 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1208 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1209
1210 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1211 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1212 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1213 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1214 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1215 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1216 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1217 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1218
1219 aml_append(table, sb_scope);
1220 }
1221
1222 static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg)
1223 {
1224 Aml *dev;
1225 Aml *resource_template;
1226
1227 /* DRAM controller */
1228 dev = aml_device("DRAC");
1229 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01")));
1230
1231 resource_template = aml_resource_template();
1232 if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) {
1233 aml_append(resource_template,
1234 aml_qword_memory(AML_POS_DECODE,
1235 AML_MIN_FIXED,
1236 AML_MAX_FIXED,
1237 AML_NON_CACHEABLE,
1238 AML_READ_WRITE,
1239 0x0000000000000000,
1240 mcfg->base,
1241 mcfg->base + mcfg->size - 1,
1242 0x0000000000000000,
1243 mcfg->size));
1244 } else {
1245 aml_append(resource_template,
1246 aml_dword_memory(AML_POS_DECODE,
1247 AML_MIN_FIXED,
1248 AML_MAX_FIXED,
1249 AML_NON_CACHEABLE,
1250 AML_READ_WRITE,
1251 0x0000000000000000,
1252 mcfg->base,
1253 mcfg->base + mcfg->size - 1,
1254 0x0000000000000000,
1255 mcfg->size));
1256 }
1257 aml_append(dev, aml_name_decl("_CRS", resource_template));
1258
1259 return dev;
1260 }
1261
1262 static void build_q35_isa_bridge(Aml *table)
1263 {
1264 Aml *dev;
1265 Aml *scope;
1266
1267 scope = aml_scope("_SB.PCI0");
1268 dev = aml_device("ISA");
1269 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1270
1271 /* ICH9 PCI to ISA irq remapping */
1272 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1273 aml_int(0x60), 0x0C));
1274
1275 aml_append(scope, dev);
1276 aml_append(table, scope);
1277 }
1278
1279 static void build_piix4_isa_bridge(Aml *table)
1280 {
1281 Aml *dev;
1282 Aml *scope;
1283
1284 scope = aml_scope("_SB.PCI0");
1285 dev = aml_device("ISA");
1286 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1287
1288 /* PIIX PCI to ISA irq remapping */
1289 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1290 aml_int(0x60), 0x04));
1291
1292 aml_append(scope, dev);
1293 aml_append(table, scope);
1294 }
1295
1296 static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr)
1297 {
1298 Aml *scope;
1299 Aml *field;
1300 Aml *method;
1301
1302 scope = aml_scope("_SB.PCI0");
1303
1304 aml_append(scope,
1305 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08));
1306 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1307 aml_append(field, aml_named_field("PCIU", 32));
1308 aml_append(field, aml_named_field("PCID", 32));
1309 aml_append(scope, field);
1310
1311 aml_append(scope,
1312 aml_operation_region("SEJ", AML_SYSTEM_IO,
1313 aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04));
1314 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1315 aml_append(field, aml_named_field("B0EJ", 32));
1316 aml_append(scope, field);
1317
1318 aml_append(scope,
1319 aml_operation_region("BNMR", AML_SYSTEM_IO,
1320 aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08));
1321 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1322 aml_append(field, aml_named_field("BNUM", 32));
1323 aml_append(field, aml_named_field("PIDX", 32));
1324 aml_append(scope, field);
1325
1326 aml_append(scope, aml_mutex("BLCK", 0));
1327
1328 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1329 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1330 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1331 aml_append(method,
1332 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1333 aml_append(method, aml_release(aml_name("BLCK")));
1334 aml_append(method, aml_return(aml_int(0)));
1335 aml_append(scope, method);
1336
1337 method = aml_method("AIDX", 2, AML_NOTSERIALIZED);
1338 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1339 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1340 aml_append(method,
1341 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1342 aml_append(method, aml_store(aml_name("PIDX"), aml_local(0)));
1343 aml_append(method, aml_release(aml_name("BLCK")));
1344 aml_append(method, aml_return(aml_local(0)));
1345 aml_append(scope, method);
1346
1347 aml_append(scope, aml_pci_device_dsm());
1348
1349 aml_append(table, scope);
1350 }
1351
1352 static Aml *build_q35_osc_method(bool enable_native_pcie_hotplug)
1353 {
1354 Aml *if_ctx;
1355 Aml *if_ctx2;
1356 Aml *else_ctx;
1357 Aml *method;
1358 Aml *a_cwd1 = aml_name("CDW1");
1359 Aml *a_ctrl = aml_local(0);
1360
1361 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1362 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1363
1364 if_ctx = aml_if(aml_equal(
1365 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1366 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1367 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1368
1369 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1370
1371 /*
1372 * Always allow native PME, AER (no dependencies)
1373 * Allow SHPC (PCI bridges can have SHPC controller)
1374 * Disable PCIe Native Hot-plug if ACPI PCI Hot-plug is enabled.
1375 */
1376 aml_append(if_ctx, aml_and(a_ctrl,
1377 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), a_ctrl));
1378
1379 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1380 /* Unknown revision */
1381 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1382 aml_append(if_ctx, if_ctx2);
1383
1384 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1385 /* Capabilities bits were masked */
1386 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1387 aml_append(if_ctx, if_ctx2);
1388
1389 /* Update DWORD3 in the buffer */
1390 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1391 aml_append(method, if_ctx);
1392
1393 else_ctx = aml_else();
1394 /* Unrecognized UUID */
1395 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1396 aml_append(method, else_ctx);
1397
1398 aml_append(method, aml_return(aml_arg(3)));
1399 return method;
1400 }
1401
1402 static void build_smb0(Aml *table, int devnr, int func)
1403 {
1404 Aml *scope = aml_scope("_SB.PCI0");
1405 Aml *dev = aml_device("SMB0");
1406 bool ambiguous;
1407 Object *obj;
1408 /*
1409 * temporarily fish out device hosting SMBUS, build_smb0 will be gone once
1410 * PCI enumeration will be switched to call_dev_aml_func()
1411 */
1412 obj = object_resolve_path_type("", TYPE_ICH9_SMB_DEVICE, &ambiguous);
1413 assert(obj && !ambiguous);
1414
1415 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1416 call_dev_aml_func(DEVICE(obj), dev);
1417 aml_append(scope, dev);
1418 aml_append(table, scope);
1419 }
1420
1421 static void build_acpi0017(Aml *table)
1422 {
1423 Aml *dev, *scope, *method;
1424
1425 scope = aml_scope("_SB");
1426 dev = aml_device("CXLM");
1427 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0017")));
1428
1429 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1430 aml_append(method, aml_return(aml_int(0x01)));
1431 aml_append(dev, method);
1432
1433 aml_append(scope, dev);
1434 aml_append(table, scope);
1435 }
1436
1437 static void
1438 build_dsdt(GArray *table_data, BIOSLinker *linker,
1439 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1440 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1441 {
1442 CrsRangeEntry *entry;
1443 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1444 CrsRangeSet crs_range_set;
1445 PCMachineState *pcms = PC_MACHINE(machine);
1446 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1447 X86MachineState *x86ms = X86_MACHINE(machine);
1448 AcpiMcfgInfo mcfg;
1449 bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
1450 uint32_t nr_mem = machine->ram_slots;
1451 int root_bus_limit = 0xFF;
1452 PCIBus *bus = NULL;
1453 #ifdef CONFIG_TPM
1454 TPMIf *tpm = tpm_find();
1455 #endif
1456 bool cxl_present = false;
1457 int i;
1458 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1459 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id,
1460 .oem_table_id = x86ms->oem_table_id };
1461
1462 acpi_table_begin(&table, table_data);
1463 dsdt = init_aml_allocator();
1464
1465 build_dbg_aml(dsdt);
1466 if (misc->is_piix4) {
1467 sb_scope = aml_scope("_SB");
1468 dev = aml_device("PCI0");
1469 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1470 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1471 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1472 aml_append(sb_scope, dev);
1473 aml_append(dsdt, sb_scope);
1474
1475 if (misc->has_hpet) {
1476 build_hpet_aml(dsdt);
1477 }
1478 build_piix4_isa_bridge(dsdt);
1479 build_isa_devices_aml(dsdt);
1480 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1481 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1482 }
1483 build_piix4_pci0_int(dsdt);
1484 } else {
1485 sb_scope = aml_scope("_SB");
1486 dev = aml_device("PCI0");
1487 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1488 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1489 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1490 aml_append(dev, aml_name_decl("_UID", aml_int(pcmc->pci_root_uid)));
1491 aml_append(dev, build_q35_osc_method(!pm->pcihp_bridge_en));
1492 aml_append(sb_scope, dev);
1493 if (mcfg_valid) {
1494 aml_append(sb_scope, build_q35_dram_controller(&mcfg));
1495 }
1496
1497 if (pm->smi_on_cpuhp) {
1498 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1499 dev = aml_device("PCI0.SMI0");
1500 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1501 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1502 crs = aml_resource_template();
1503 aml_append(crs,
1504 aml_io(
1505 AML_DECODE16,
1506 ACPI_PORT_SMI_CMD,
1507 ACPI_PORT_SMI_CMD,
1508 1,
1509 2)
1510 );
1511 aml_append(dev, aml_name_decl("_CRS", crs));
1512 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1513 aml_int(ACPI_PORT_SMI_CMD), 2));
1514 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1515 AML_WRITE_AS_ZEROS);
1516 aml_append(field, aml_named_field("SMIC", 8));
1517 aml_append(field, aml_reserved_field(8));
1518 aml_append(dev, field);
1519 aml_append(sb_scope, dev);
1520 }
1521
1522 aml_append(dsdt, sb_scope);
1523
1524 if (misc->has_hpet) {
1525 build_hpet_aml(dsdt);
1526 }
1527 build_q35_isa_bridge(dsdt);
1528 build_isa_devices_aml(dsdt);
1529 if (pm->pcihp_bridge_en) {
1530 build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
1531 }
1532 build_q35_pci0_int(dsdt);
1533 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1534 build_smb0(dsdt, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1535 }
1536 }
1537
1538 if (vmbus_bridge) {
1539 sb_scope = aml_scope("_SB");
1540 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1541 aml_append(dsdt, sb_scope);
1542 }
1543
1544 if (pcmc->legacy_cpu_hotplug) {
1545 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1546 } else {
1547 CPUHotplugFeatures opts = {
1548 .acpi_1_compatible = true, .has_legacy_cphp = true,
1549 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1550 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1551 };
1552 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1553 "\\_SB.PCI0", "\\_GPE._E02");
1554 }
1555
1556 if (pcms->memhp_io_base && nr_mem) {
1557 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1558 "\\_GPE._E03", AML_SYSTEM_IO,
1559 pcms->memhp_io_base);
1560 }
1561
1562 scope = aml_scope("_GPE");
1563 {
1564 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1565
1566 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1567 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1568 aml_append(method,
1569 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1570 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1571 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1572 aml_append(scope, method);
1573 }
1574
1575 if (machine->nvdimms_state->is_enabled) {
1576 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1577 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1578 aml_int(0x80)));
1579 aml_append(scope, method);
1580 }
1581 }
1582 aml_append(dsdt, scope);
1583
1584 crs_range_set_init(&crs_range_set);
1585 bus = PC_MACHINE(machine)->bus;
1586 if (bus) {
1587 QLIST_FOREACH(bus, &bus->child, sibling) {
1588 uint8_t bus_num = pci_bus_num(bus);
1589 uint8_t numa_node = pci_bus_numa_node(bus);
1590
1591 /* look only for expander root buses */
1592 if (!pci_bus_is_root(bus)) {
1593 continue;
1594 }
1595
1596 if (bus_num < root_bus_limit) {
1597 root_bus_limit = bus_num - 1;
1598 }
1599
1600 scope = aml_scope("\\_SB");
1601
1602 if (pci_bus_is_cxl(bus)) {
1603 dev = aml_device("CL%.02X", bus_num);
1604 } else {
1605 dev = aml_device("PC%.02X", bus_num);
1606 }
1607 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1608 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1609 if (pci_bus_is_cxl(bus)) {
1610 struct Aml *pkg = aml_package(2);
1611
1612 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
1613 aml_append(pkg, aml_eisaid("PNP0A08"));
1614 aml_append(pkg, aml_eisaid("PNP0A03"));
1615 aml_append(dev, aml_name_decl("_CID", pkg));
1616 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1617 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1618 build_cxl_osc_method(dev);
1619 } else if (pci_bus_is_express(bus)) {
1620 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1621 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1622
1623 /* Expander bridges do not have ACPI PCI Hot-plug enabled */
1624 aml_append(dev, build_q35_osc_method(true));
1625 } else {
1626 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1627 }
1628
1629 if (numa_node != NUMA_NODE_UNASSIGNED) {
1630 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1631 }
1632
1633 aml_append(dev, build_prt(false));
1634 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1635 0, 0, 0, 0);
1636 aml_append(dev, aml_name_decl("_CRS", crs));
1637 aml_append(scope, dev);
1638 aml_append(dsdt, scope);
1639
1640 /* Handle the ranges for the PXB expanders */
1641 if (pci_bus_is_cxl(bus)) {
1642 MemoryRegion *mr = &machine->cxl_devices_state->host_mr;
1643 uint64_t base = mr->addr;
1644
1645 cxl_present = true;
1646 crs_range_insert(crs_range_set.mem_ranges, base,
1647 base + memory_region_size(mr) - 1);
1648 }
1649 }
1650 }
1651
1652 if (cxl_present) {
1653 build_acpi0017(dsdt);
1654 }
1655
1656 /*
1657 * At this point crs_range_set has all the ranges used by pci
1658 * busses *other* than PCI0. These ranges will be excluded from
1659 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1660 * too.
1661 */
1662 if (mcfg_valid) {
1663 crs_range_insert(crs_range_set.mem_ranges,
1664 mcfg.base, mcfg.base + mcfg.size - 1);
1665 }
1666
1667 scope = aml_scope("\\_SB.PCI0");
1668 /* build PCI0._CRS */
1669 crs = aml_resource_template();
1670 aml_append(crs,
1671 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1672 0x0000, 0x0, root_bus_limit,
1673 0x0000, root_bus_limit + 1));
1674 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1675
1676 aml_append(crs,
1677 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1678 AML_POS_DECODE, AML_ENTIRE_RANGE,
1679 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1680
1681 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1682 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1683 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1684 aml_append(crs,
1685 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1686 AML_POS_DECODE, AML_ENTIRE_RANGE,
1687 0x0000, entry->base, entry->limit,
1688 0x0000, entry->limit - entry->base + 1));
1689 }
1690
1691 aml_append(crs,
1692 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1693 AML_CACHEABLE, AML_READ_WRITE,
1694 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1695
1696 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1697 range_lob(pci_hole),
1698 range_upb(pci_hole));
1699 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1700 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1701 aml_append(crs,
1702 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1703 AML_NON_CACHEABLE, AML_READ_WRITE,
1704 0, entry->base, entry->limit,
1705 0, entry->limit - entry->base + 1));
1706 }
1707
1708 if (!range_is_empty(pci_hole64)) {
1709 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1710 range_lob(pci_hole64),
1711 range_upb(pci_hole64));
1712 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1713 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1714 aml_append(crs,
1715 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1716 AML_MAX_FIXED,
1717 AML_CACHEABLE, AML_READ_WRITE,
1718 0, entry->base, entry->limit,
1719 0, entry->limit - entry->base + 1));
1720 }
1721 }
1722
1723 #ifdef CONFIG_TPM
1724 if (TPM_IS_TIS_ISA(tpm_find())) {
1725 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1726 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1727 }
1728 #endif
1729 aml_append(scope, aml_name_decl("_CRS", crs));
1730
1731 /* reserve GPE0 block resources */
1732 dev = aml_device("GPE0");
1733 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1734 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1735 /* device present, functioning, decoding, not shown in UI */
1736 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1737 crs = aml_resource_template();
1738 aml_append(crs,
1739 aml_io(
1740 AML_DECODE16,
1741 pm->fadt.gpe0_blk.address,
1742 pm->fadt.gpe0_blk.address,
1743 1,
1744 pm->fadt.gpe0_blk.bit_width / 8)
1745 );
1746 aml_append(dev, aml_name_decl("_CRS", crs));
1747 aml_append(scope, dev);
1748
1749 crs_range_set_free(&crs_range_set);
1750
1751 /* reserve PCIHP resources */
1752 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1753 dev = aml_device("PHPR");
1754 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1755 aml_append(dev,
1756 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1757 /* device present, functioning, decoding, not shown in UI */
1758 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1759 crs = aml_resource_template();
1760 aml_append(crs,
1761 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1762 pm->pcihp_io_len)
1763 );
1764 aml_append(dev, aml_name_decl("_CRS", crs));
1765 aml_append(scope, dev);
1766 }
1767 aml_append(dsdt, scope);
1768
1769 /* create S3_ / S4_ / S5_ packages if necessary */
1770 scope = aml_scope("\\");
1771 if (!pm->s3_disabled) {
1772 pkg = aml_package(4);
1773 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1774 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1775 aml_append(pkg, aml_int(0)); /* reserved */
1776 aml_append(pkg, aml_int(0)); /* reserved */
1777 aml_append(scope, aml_name_decl("_S3", pkg));
1778 }
1779
1780 if (!pm->s4_disabled) {
1781 pkg = aml_package(4);
1782 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1783 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1784 aml_append(pkg, aml_int(pm->s4_val));
1785 aml_append(pkg, aml_int(0)); /* reserved */
1786 aml_append(pkg, aml_int(0)); /* reserved */
1787 aml_append(scope, aml_name_decl("_S4", pkg));
1788 }
1789
1790 pkg = aml_package(4);
1791 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1792 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1793 aml_append(pkg, aml_int(0)); /* reserved */
1794 aml_append(pkg, aml_int(0)); /* reserved */
1795 aml_append(scope, aml_name_decl("_S5", pkg));
1796 aml_append(dsdt, scope);
1797
1798 /* create fw_cfg node, unconditionally */
1799 {
1800 scope = aml_scope("\\_SB.PCI0");
1801 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1802 aml_append(dsdt, scope);
1803 }
1804
1805 if (misc->applesmc_io_base) {
1806 scope = aml_scope("\\_SB.PCI0.ISA");
1807 dev = aml_device("SMC");
1808
1809 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1810 /* device present, functioning, decoding, not shown in UI */
1811 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1812
1813 crs = aml_resource_template();
1814 aml_append(crs,
1815 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1816 0x01, APPLESMC_MAX_DATA_LENGTH)
1817 );
1818 aml_append(crs, aml_irq_no_flags(6));
1819 aml_append(dev, aml_name_decl("_CRS", crs));
1820
1821 aml_append(scope, dev);
1822 aml_append(dsdt, scope);
1823 }
1824
1825 if (misc->pvpanic_port) {
1826 scope = aml_scope("\\_SB.PCI0.ISA");
1827
1828 dev = aml_device("PEVT");
1829 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1830
1831 crs = aml_resource_template();
1832 aml_append(crs,
1833 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1834 );
1835 aml_append(dev, aml_name_decl("_CRS", crs));
1836
1837 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1838 aml_int(misc->pvpanic_port), 1));
1839 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1840 aml_append(field, aml_named_field("PEPT", 8));
1841 aml_append(dev, field);
1842
1843 /* device present, functioning, decoding, shown in UI */
1844 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1845
1846 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1847 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1848 aml_append(method, aml_return(aml_local(0)));
1849 aml_append(dev, method);
1850
1851 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1852 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1853 aml_append(dev, method);
1854
1855 aml_append(scope, dev);
1856 aml_append(dsdt, scope);
1857 }
1858
1859 sb_scope = aml_scope("\\_SB");
1860 {
1861 Object *pci_host;
1862 PCIBus *bus = NULL;
1863
1864 pci_host = acpi_get_i386_pci_host();
1865
1866 if (pci_host) {
1867 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1868 }
1869
1870 if (bus) {
1871 Aml *scope = aml_scope("PCI0");
1872 /* Scan all PCI buses. Generate tables to support hotplug. */
1873 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1874
1875 #ifdef CONFIG_TPM
1876 if (TPM_IS_TIS_ISA(tpm)) {
1877 if (misc->tpm_version == TPM_VERSION_2_0) {
1878 dev = aml_device("TPM");
1879 aml_append(dev, aml_name_decl("_HID",
1880 aml_string("MSFT0101")));
1881 aml_append(dev,
1882 aml_name_decl("_STR",
1883 aml_string("TPM 2.0 Device")));
1884 } else {
1885 dev = aml_device("ISA.TPM");
1886 aml_append(dev, aml_name_decl("_HID",
1887 aml_eisaid("PNP0C31")));
1888 }
1889 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1890
1891 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1892 crs = aml_resource_template();
1893 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1894 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1895 /*
1896 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1897 Rewrite to take IRQ from TPM device model and
1898 fix default IRQ value there to use some unused IRQ
1899 */
1900 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1901 aml_append(dev, aml_name_decl("_CRS", crs));
1902
1903 tpm_build_ppi_acpi(tpm, dev);
1904
1905 aml_append(scope, dev);
1906 }
1907 #endif
1908
1909 aml_append(sb_scope, scope);
1910 }
1911 }
1912
1913 #ifdef CONFIG_TPM
1914 if (TPM_IS_CRB(tpm)) {
1915 dev = aml_device("TPM");
1916 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1917 aml_append(dev, aml_name_decl("_STR",
1918 aml_string("TPM 2.0 Device")));
1919 crs = aml_resource_template();
1920 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1921 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1922 aml_append(dev, aml_name_decl("_CRS", crs));
1923
1924 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1925 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1926
1927 tpm_build_ppi_acpi(tpm, dev);
1928
1929 aml_append(sb_scope, dev);
1930 }
1931 #endif
1932
1933 if (pcms->sgx_epc.size != 0) {
1934 uint64_t epc_base = pcms->sgx_epc.base;
1935 uint64_t epc_size = pcms->sgx_epc.size;
1936
1937 dev = aml_device("EPC");
1938 aml_append(dev, aml_name_decl("_HID", aml_eisaid("INT0E0C")));
1939 aml_append(dev, aml_name_decl("_STR",
1940 aml_unicode("Enclave Page Cache 1.0")));
1941 crs = aml_resource_template();
1942 aml_append(crs,
1943 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1944 AML_MAX_FIXED, AML_NON_CACHEABLE,
1945 AML_READ_WRITE, 0, epc_base,
1946 epc_base + epc_size - 1, 0, epc_size));
1947 aml_append(dev, aml_name_decl("_CRS", crs));
1948
1949 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1950 aml_append(method, aml_return(aml_int(0x0f)));
1951 aml_append(dev, method);
1952
1953 aml_append(sb_scope, dev);
1954 }
1955 aml_append(dsdt, sb_scope);
1956
1957 /* copy AML table into ACPI tables blob and patch header there */
1958 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1959 acpi_table_end(linker, &table);
1960 free_aml_allocator();
1961 }
1962
1963 /*
1964 * IA-PC HPET (High Precision Event Timers) Specification (Revision: 1.0a)
1965 * 3.2.4The ACPI 2.0 HPET Description Table (HPET)
1966 */
1967 static void
1968 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1969 const char *oem_table_id)
1970 {
1971 AcpiTable table = { .sig = "HPET", .rev = 1,
1972 .oem_id = oem_id, .oem_table_id = oem_table_id };
1973
1974 acpi_table_begin(&table, table_data);
1975 /* Note timer_block_id value must be kept in sync with value advertised by
1976 * emulated hpet
1977 */
1978 /* Event Timer Block ID */
1979 build_append_int_noprefix(table_data, 0x8086a201, 4);
1980 /* BASE_ADDRESS */
1981 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 0, 0, 0, HPET_BASE);
1982 /* HPET Number */
1983 build_append_int_noprefix(table_data, 0, 1);
1984 /* Main Counter Minimum Clock_tick in Periodic Mode */
1985 build_append_int_noprefix(table_data, 0, 2);
1986 /* Page Protection And OEM Attribute */
1987 build_append_int_noprefix(table_data, 0, 1);
1988 acpi_table_end(linker, &table);
1989 }
1990
1991 #ifdef CONFIG_TPM
1992 /*
1993 * TCPA Description Table
1994 *
1995 * Following Level 00, Rev 00.37 of specs:
1996 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification
1997 * 7.1.2 ACPI Table Layout
1998 */
1999 static void
2000 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
2001 const char *oem_id, const char *oem_table_id)
2002 {
2003 unsigned log_addr_offset;
2004 AcpiTable table = { .sig = "TCPA", .rev = 2,
2005 .oem_id = oem_id, .oem_table_id = oem_table_id };
2006
2007 acpi_table_begin(&table, table_data);
2008 /* Platform Class */
2009 build_append_int_noprefix(table_data, TPM_TCPA_ACPI_CLASS_CLIENT, 2);
2010 /* Log Area Minimum Length (LAML) */
2011 build_append_int_noprefix(table_data, TPM_LOG_AREA_MINIMUM_SIZE, 4);
2012 /* Log Area Start Address (LASA) */
2013 log_addr_offset = table_data->len;
2014 build_append_int_noprefix(table_data, 0, 8);
2015
2016 /* allocate/reserve space for TPM log area */
2017 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
2018 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2019 false /* high memory */);
2020 /* log area start address to be filled by Guest linker */
2021 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2022 log_addr_offset, 8, ACPI_BUILD_TPMLOG_FILE, 0);
2023
2024 acpi_table_end(linker, &table);
2025 }
2026 #endif
2027
2028 #define HOLE_640K_START (640 * KiB)
2029 #define HOLE_640K_END (1 * MiB)
2030
2031 /*
2032 * ACPI spec, Revision 3.0
2033 * 5.2.15 System Resource Affinity Table (SRAT)
2034 */
2035 static void
2036 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2037 {
2038 int i;
2039 int numa_mem_start, slots;
2040 uint64_t mem_len, mem_base, next_base;
2041 MachineClass *mc = MACHINE_GET_CLASS(machine);
2042 X86MachineState *x86ms = X86_MACHINE(machine);
2043 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2044 PCMachineState *pcms = PC_MACHINE(machine);
2045 int nb_numa_nodes = machine->numa_state->num_nodes;
2046 NodeInfo *numa_info = machine->numa_state->nodes;
2047 ram_addr_t hotpluggable_address_space_size =
2048 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
2049 NULL);
2050 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = x86ms->oem_id,
2051 .oem_table_id = x86ms->oem_table_id };
2052
2053 acpi_table_begin(&table, table_data);
2054 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
2055 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
2056
2057 for (i = 0; i < apic_ids->len; i++) {
2058 int node_id = apic_ids->cpus[i].props.node_id;
2059 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2060
2061 if (apic_id < 255) {
2062 /* 5.2.15.1 Processor Local APIC/SAPIC Affinity Structure */
2063 build_append_int_noprefix(table_data, 0, 1); /* Type */
2064 build_append_int_noprefix(table_data, 16, 1); /* Length */
2065 /* Proximity Domain [7:0] */
2066 build_append_int_noprefix(table_data, node_id, 1);
2067 build_append_int_noprefix(table_data, apic_id, 1); /* APIC ID */
2068 /* Flags, Table 5-36 */
2069 build_append_int_noprefix(table_data, 1, 4);
2070 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */
2071 /* Proximity Domain [31:8] */
2072 build_append_int_noprefix(table_data, 0, 3);
2073 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
2074 } else {
2075 /*
2076 * ACPI spec, Revision 4.0
2077 * 5.2.16.3 Processor Local x2APIC Affinity Structure
2078 */
2079 build_append_int_noprefix(table_data, 2, 1); /* Type */
2080 build_append_int_noprefix(table_data, 24, 1); /* Length */
2081 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2082 /* Proximity Domain */
2083 build_append_int_noprefix(table_data, node_id, 4);
2084 build_append_int_noprefix(table_data, apic_id, 4); /* X2APIC ID */
2085 /* Flags, Table 5-39 */
2086 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
2087 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
2088 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
2089 }
2090 }
2091
2092 /* the memory map is a bit tricky, it contains at least one hole
2093 * from 640k-1M and possibly another one from 3.5G-4G.
2094 */
2095 next_base = 0;
2096 numa_mem_start = table_data->len;
2097
2098 for (i = 1; i < nb_numa_nodes + 1; ++i) {
2099 mem_base = next_base;
2100 mem_len = numa_info[i - 1].node_mem;
2101 next_base = mem_base + mem_len;
2102
2103 /* Cut out the 640K hole */
2104 if (mem_base <= HOLE_640K_START &&
2105 next_base > HOLE_640K_START) {
2106 mem_len -= next_base - HOLE_640K_START;
2107 if (mem_len > 0) {
2108 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2109 MEM_AFFINITY_ENABLED);
2110 }
2111
2112 /* Check for the rare case: 640K < RAM < 1M */
2113 if (next_base <= HOLE_640K_END) {
2114 next_base = HOLE_640K_END;
2115 continue;
2116 }
2117 mem_base = HOLE_640K_END;
2118 mem_len = next_base - HOLE_640K_END;
2119 }
2120
2121 /* Cut out the ACPI_PCI hole */
2122 if (mem_base <= x86ms->below_4g_mem_size &&
2123 next_base > x86ms->below_4g_mem_size) {
2124 mem_len -= next_base - x86ms->below_4g_mem_size;
2125 if (mem_len > 0) {
2126 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2127 MEM_AFFINITY_ENABLED);
2128 }
2129 mem_base = 1ULL << 32;
2130 mem_len = next_base - x86ms->below_4g_mem_size;
2131 next_base = mem_base + mem_len;
2132 }
2133
2134 if (mem_len > 0) {
2135 build_srat_memory(table_data, mem_base, mem_len, i - 1,
2136 MEM_AFFINITY_ENABLED);
2137 }
2138 }
2139
2140 if (machine->nvdimms_state->is_enabled) {
2141 nvdimm_build_srat(table_data);
2142 }
2143
2144 sgx_epc_build_srat(table_data);
2145
2146 /*
2147 * TODO: this part is not in ACPI spec and current linux kernel boots fine
2148 * without these entries. But I recall there were issues the last time I
2149 * tried to remove it with some ancient guest OS, however I can't remember
2150 * what that was so keep this around for now
2151 */
2152 slots = (table_data->len - numa_mem_start) / 40 /* mem affinity len */;
2153 for (; slots < nb_numa_nodes + 2; slots++) {
2154 build_srat_memory(table_data, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2155 }
2156
2157 /*
2158 * Entry is required for Windows to enable memory hotplug in OS
2159 * and for Linux to enable SWIOTLB when booted with less than
2160 * 4G of RAM. Windows works better if the entry sets proximity
2161 * to the highest NUMA node in the machine.
2162 * Memory devices may override proximity set by this entry,
2163 * providing _PXM method if necessary.
2164 */
2165 if (hotpluggable_address_space_size) {
2166 build_srat_memory(table_data, machine->device_memory->base,
2167 hotpluggable_address_space_size, nb_numa_nodes - 1,
2168 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2169 }
2170
2171 acpi_table_end(linker, &table);
2172 }
2173
2174 /*
2175 * Insert DMAR scope for PCI bridges and endpoint devcie
2176 */
2177 static void
2178 insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque)
2179 {
2180 const size_t device_scope_size = 6 /* device scope structure */ +
2181 2 /* 1 path entry */;
2182 GArray *scope_blob = opaque;
2183
2184 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2185 /* Dmar Scope Type: 0x02 for PCI Bridge */
2186 build_append_int_noprefix(scope_blob, 0x02, 1);
2187 } else {
2188 /* Dmar Scope Type: 0x01 for PCI Endpoint Device */
2189 build_append_int_noprefix(scope_blob, 0x01, 1);
2190 }
2191
2192 /* length */
2193 build_append_int_noprefix(scope_blob, device_scope_size, 1);
2194 /* reserved */
2195 build_append_int_noprefix(scope_blob, 0, 2);
2196 /* enumeration_id */
2197 build_append_int_noprefix(scope_blob, 0, 1);
2198 /* bus */
2199 build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1);
2200 /* device */
2201 build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1);
2202 /* function */
2203 build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1);
2204 }
2205
2206 /* For a given PCI host bridge, walk and insert DMAR scope */
2207 static int
2208 dmar_host_bridges(Object *obj, void *opaque)
2209 {
2210 GArray *scope_blob = opaque;
2211
2212 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2213 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2214
2215 if (bus && !pci_bus_bypass_iommu(bus)) {
2216 pci_for_each_device_under_bus(bus, insert_scope, scope_blob);
2217 }
2218 }
2219
2220 return 0;
2221 }
2222
2223 /*
2224 * Intel ® Virtualization Technology for Directed I/O
2225 * Architecture Specification. Revision 3.3
2226 * 8.1 DMA Remapping Reporting Structure
2227 */
2228 static void
2229 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2230 const char *oem_table_id)
2231 {
2232 uint8_t dmar_flags = 0;
2233 uint8_t rsvd10[10] = {};
2234 /* Root complex IOAPIC uses one path only */
2235 const size_t ioapic_scope_size = 6 /* device scope structure */ +
2236 2 /* 1 path entry */;
2237 X86IOMMUState *iommu = x86_iommu_get_default();
2238 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
2239 GArray *scope_blob = g_array_new(false, true, 1);
2240
2241 AcpiTable table = { .sig = "DMAR", .rev = 1, .oem_id = oem_id,
2242 .oem_table_id = oem_table_id };
2243
2244 /*
2245 * A PCI bus walk, for each PCI host bridge.
2246 * Insert scope for each PCI bridge and endpoint device which
2247 * is attached to a bus with iommu enabled.
2248 */
2249 object_child_foreach_recursive(object_get_root(),
2250 dmar_host_bridges, scope_blob);
2251
2252 assert(iommu);
2253 if (x86_iommu_ir_supported(iommu)) {
2254 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2255 }
2256
2257 acpi_table_begin(&table, table_data);
2258 /* Host Address Width */
2259 build_append_int_noprefix(table_data, intel_iommu->aw_bits - 1, 1);
2260 build_append_int_noprefix(table_data, dmar_flags, 1); /* Flags */
2261 g_array_append_vals(table_data, rsvd10, sizeof(rsvd10)); /* Reserved */
2262
2263 /* 8.3 DMAR Remapping Hardware Unit Definition structure */
2264 build_append_int_noprefix(table_data, 0, 2); /* Type */
2265 /* Length */
2266 build_append_int_noprefix(table_data,
2267 16 + ioapic_scope_size + scope_blob->len, 2);
2268 /* Flags */
2269 build_append_int_noprefix(table_data, 0 /* Don't include all pci device */ ,
2270 1);
2271 build_append_int_noprefix(table_data, 0 , 1); /* Reserved */
2272 build_append_int_noprefix(table_data, 0 , 2); /* Segment Number */
2273 /* Register Base Address */
2274 build_append_int_noprefix(table_data, Q35_HOST_BRIDGE_IOMMU_ADDR , 8);
2275
2276 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2277 * 8.3.1 (version Oct. 2014 or later). */
2278 build_append_int_noprefix(table_data, 0x03 /* IOAPIC */, 1); /* Type */
2279 build_append_int_noprefix(table_data, ioapic_scope_size, 1); /* Length */
2280 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
2281 /* Enumeration ID */
2282 build_append_int_noprefix(table_data, ACPI_BUILD_IOAPIC_ID, 1);
2283 /* Start Bus Number */
2284 build_append_int_noprefix(table_data, Q35_PSEUDO_BUS_PLATFORM, 1);
2285 /* Path, {Device, Function} pair */
2286 build_append_int_noprefix(table_data, PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2287 build_append_int_noprefix(table_data, PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC), 1);
2288
2289 /* Add scope found above */
2290 g_array_append_vals(table_data, scope_blob->data, scope_blob->len);
2291 g_array_free(scope_blob, true);
2292
2293 if (iommu->dt_supported) {
2294 /* 8.5 Root Port ATS Capability Reporting Structure */
2295 build_append_int_noprefix(table_data, 2, 2); /* Type */
2296 build_append_int_noprefix(table_data, 8, 2); /* Length */
2297 build_append_int_noprefix(table_data, 1 /* ALL_PORTS */, 1); /* Flags */
2298 build_append_int_noprefix(table_data, 0, 1); /* Reserved */
2299 build_append_int_noprefix(table_data, 0, 2); /* Segment Number */
2300 }
2301
2302 acpi_table_end(linker, &table);
2303 }
2304
2305 /*
2306 * Windows ACPI Emulated Devices Table
2307 * (Version 1.0 - April 6, 2009)
2308 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2309 *
2310 * Helpful to speedup Windows guests and ignored by others.
2311 */
2312 static void
2313 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2314 const char *oem_table_id)
2315 {
2316 AcpiTable table = { .sig = "WAET", .rev = 1, .oem_id = oem_id,
2317 .oem_table_id = oem_table_id };
2318
2319 acpi_table_begin(&table, table_data);
2320 /*
2321 * Set "ACPI PM timer good" flag.
2322 *
2323 * Tells Windows guests that our ACPI PM timer is reliable in the
2324 * sense that guest can read it only once to obtain a reliable value.
2325 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2326 */
2327 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
2328 acpi_table_end(linker, &table);
2329 }
2330
2331 /*
2332 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2333 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2334 */
2335 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2336
2337 /*
2338 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2339 * necessary for the PCI topology.
2340 */
2341 static void
2342 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
2343 {
2344 GArray *table_data = opaque;
2345 uint32_t entry;
2346
2347 /* "Select" IVHD entry, type 0x2 */
2348 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
2349 build_append_int_noprefix(table_data, entry, 4);
2350
2351 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
2352 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
2353 uint8_t sec = pci_bus_num(sec_bus);
2354 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
2355
2356 if (pci_bus_is_express(sec_bus)) {
2357 /*
2358 * Walk the bus if there are subordinates, otherwise use a range
2359 * to cover an entire leaf bus. We could potentially also use a
2360 * range for traversed buses, but we'd need to take care not to
2361 * create both Select and Range entries covering the same device.
2362 * This is easier and potentially more compact.
2363 *
2364 * An example bare metal system seems to use Select entries for
2365 * root ports without a slot (ie. built-ins) and Range entries
2366 * when there is a slot. The same system also only hard-codes
2367 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2368 * making no effort to support nested bridges. We attempt to
2369 * be more thorough here.
2370 */
2371 if (sec == sub) { /* leaf bus */
2372 /* "Start of Range" IVHD entry, type 0x3 */
2373 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
2374 build_append_int_noprefix(table_data, entry, 4);
2375 /* "End of Range" IVHD entry, type 0x4 */
2376 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2377 build_append_int_noprefix(table_data, entry, 4);
2378 } else {
2379 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
2380 }
2381 } else {
2382 /*
2383 * If the secondary bus is conventional, then we need to create an
2384 * Alias range for everything downstream. The range covers the
2385 * first devfn on the secondary bus to the last devfn on the
2386 * subordinate bus. The alias target depends on legacy versus
2387 * express bridges, just as in pci_device_iommu_address_space().
2388 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2389 */
2390 uint16_t dev_id_a, dev_id_b;
2391
2392 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
2393
2394 if (pci_is_express(dev) &&
2395 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
2396 dev_id_b = dev_id_a;
2397 } else {
2398 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
2399 }
2400
2401 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2402 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
2403 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
2404
2405 /* "End of Range" IVHD entry, type 0x4 */
2406 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
2407 build_append_int_noprefix(table_data, entry, 4);
2408 }
2409 }
2410 }
2411
2412 /* For all PCI host bridges, walk and insert IVHD entries */
2413 static int
2414 ivrs_host_bridges(Object *obj, void *opaque)
2415 {
2416 GArray *ivhd_blob = opaque;
2417
2418 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2419 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2420
2421 if (bus && !pci_bus_bypass_iommu(bus)) {
2422 pci_for_each_device_under_bus(bus, insert_ivhd, ivhd_blob);
2423 }
2424 }
2425
2426 return 0;
2427 }
2428
2429 static void
2430 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2431 const char *oem_table_id)
2432 {
2433 int ivhd_table_len = 24;
2434 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2435 GArray *ivhd_blob = g_array_new(false, true, 1);
2436 AcpiTable table = { .sig = "IVRS", .rev = 1, .oem_id = oem_id,
2437 .oem_table_id = oem_table_id };
2438
2439 acpi_table_begin(&table, table_data);
2440 /* IVinfo - IO virtualization information common to all
2441 * IOMMU units in a system
2442 */
2443 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2444 /* reserved */
2445 build_append_int_noprefix(table_data, 0, 8);
2446
2447 /* IVHD definition - type 10h */
2448 build_append_int_noprefix(table_data, 0x10, 1);
2449 /* virtualization flags */
2450 build_append_int_noprefix(table_data,
2451 (1UL << 0) | /* HtTunEn */
2452 (1UL << 4) | /* iotblSup */
2453 (1UL << 6) | /* PrefSup */
2454 (1UL << 7), /* PPRSup */
2455 1);
2456
2457 /*
2458 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2459 * complete set of IVHD entries. Do this into a separate blob so that we
2460 * can calculate the total IVRS table length here and then append the new
2461 * blob further below. Fall back to an entry covering all devices, which
2462 * is sufficient when no aliases are present.
2463 */
2464 object_child_foreach_recursive(object_get_root(),
2465 ivrs_host_bridges, ivhd_blob);
2466
2467 if (!ivhd_blob->len) {
2468 /*
2469 * Type 1 device entry reporting all devices
2470 * These are 4-byte device entries currently reporting the range of
2471 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2472 */
2473 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2474 }
2475
2476 ivhd_table_len += ivhd_blob->len;
2477
2478 /*
2479 * When interrupt remapping is supported, we add a special IVHD device
2480 * for type IO-APIC.
2481 */
2482 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2483 ivhd_table_len += 8;
2484 }
2485
2486 /* IVHD length */
2487 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2488 /* DeviceID */
2489 build_append_int_noprefix(table_data, s->devid, 2);
2490 /* Capability offset */
2491 build_append_int_noprefix(table_data, s->capab_offset, 2);
2492 /* IOMMU base address */
2493 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2494 /* PCI Segment Group */
2495 build_append_int_noprefix(table_data, 0, 2);
2496 /* IOMMU info */
2497 build_append_int_noprefix(table_data, 0, 2);
2498 /* IOMMU Feature Reporting */
2499 build_append_int_noprefix(table_data,
2500 (48UL << 30) | /* HATS */
2501 (48UL << 28) | /* GATS */
2502 (1UL << 2) | /* GTSup */
2503 (1UL << 6), /* GASup */
2504 4);
2505
2506 /* IVHD entries as found above */
2507 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2508 g_array_free(ivhd_blob, TRUE);
2509
2510 /*
2511 * Add a special IVHD device type.
2512 * Refer to spec - Table 95: IVHD device entry type codes
2513 *
2514 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2515 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2516 */
2517 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2518 build_append_int_noprefix(table_data,
2519 (0x1ull << 56) | /* type IOAPIC */
2520 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2521 0x48, /* special device */
2522 8);
2523 }
2524 acpi_table_end(linker, &table);
2525 }
2526
2527 typedef
2528 struct AcpiBuildState {
2529 /* Copy of table in RAM (for patching). */
2530 MemoryRegion *table_mr;
2531 /* Is table patched? */
2532 uint8_t patched;
2533 void *rsdp;
2534 MemoryRegion *rsdp_mr;
2535 MemoryRegion *linker_mr;
2536 } AcpiBuildState;
2537
2538 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2539 {
2540 Object *pci_host;
2541 QObject *o;
2542
2543 pci_host = acpi_get_i386_pci_host();
2544 if (!pci_host) {
2545 return false;
2546 }
2547
2548 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2549 if (!o) {
2550 return false;
2551 }
2552 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2553 qobject_unref(o);
2554 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2555 return false;
2556 }
2557
2558 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2559 assert(o);
2560 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2561 qobject_unref(o);
2562 return true;
2563 }
2564
2565 static
2566 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2567 {
2568 PCMachineState *pcms = PC_MACHINE(machine);
2569 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2570 X86MachineState *x86ms = X86_MACHINE(machine);
2571 DeviceState *iommu = pcms->iommu;
2572 GArray *table_offsets;
2573 unsigned facs, dsdt, rsdt, fadt;
2574 AcpiPmInfo pm;
2575 AcpiMiscInfo misc;
2576 AcpiMcfgInfo mcfg;
2577 Range pci_hole = {}, pci_hole64 = {};
2578 uint8_t *u;
2579 size_t aml_len = 0;
2580 GArray *tables_blob = tables->table_data;
2581 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2582 Object *vmgenid_dev;
2583 char *oem_id;
2584 char *oem_table_id;
2585
2586 acpi_get_pm_info(machine, &pm);
2587 acpi_get_misc_info(&misc);
2588 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2589 acpi_get_slic_oem(&slic_oem);
2590
2591 if (slic_oem.id) {
2592 oem_id = slic_oem.id;
2593 } else {
2594 oem_id = x86ms->oem_id;
2595 }
2596
2597 if (slic_oem.table_id) {
2598 oem_table_id = slic_oem.table_id;
2599 } else {
2600 oem_table_id = x86ms->oem_table_id;
2601 }
2602
2603 table_offsets = g_array_new(false, true /* clear */,
2604 sizeof(uint32_t));
2605 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2606
2607 bios_linker_loader_alloc(tables->linker,
2608 ACPI_BUILD_TABLE_FILE, tables_blob,
2609 64 /* Ensure FACS is aligned */,
2610 false /* high memory */);
2611
2612 /*
2613 * FACS is pointed to by FADT.
2614 * We place it first since it's the only table that has alignment
2615 * requirements.
2616 */
2617 facs = tables_blob->len;
2618 build_facs(tables_blob);
2619
2620 /* DSDT is pointed to by FADT */
2621 dsdt = tables_blob->len;
2622 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2623 &pci_hole, &pci_hole64, machine);
2624
2625 /* Count the size of the DSDT and SSDT, we will need it for legacy
2626 * sizing of ACPI tables.
2627 */
2628 aml_len += tables_blob->len - dsdt;
2629
2630 /* ACPI tables pointed to by RSDT */
2631 fadt = tables_blob->len;
2632 acpi_add_table(table_offsets, tables_blob);
2633 pm.fadt.facs_tbl_offset = &facs;
2634 pm.fadt.dsdt_tbl_offset = &dsdt;
2635 pm.fadt.xdsdt_tbl_offset = &dsdt;
2636 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2637 aml_len += tables_blob->len - fadt;
2638
2639 acpi_add_table(table_offsets, tables_blob);
2640 acpi_build_madt(tables_blob, tables->linker, x86ms,
2641 ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
2642 x86ms->oem_table_id);
2643
2644 #ifdef CONFIG_ACPI_ERST
2645 {
2646 Object *erst_dev;
2647 erst_dev = find_erst_dev();
2648 if (erst_dev) {
2649 acpi_add_table(table_offsets, tables_blob);
2650 build_erst(tables_blob, tables->linker, erst_dev,
2651 x86ms->oem_id, x86ms->oem_table_id);
2652 }
2653 }
2654 #endif
2655
2656 vmgenid_dev = find_vmgenid_dev();
2657 if (vmgenid_dev) {
2658 acpi_add_table(table_offsets, tables_blob);
2659 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2660 tables->vmgenid, tables->linker, x86ms->oem_id);
2661 }
2662
2663 if (misc.has_hpet) {
2664 acpi_add_table(table_offsets, tables_blob);
2665 build_hpet(tables_blob, tables->linker, x86ms->oem_id,
2666 x86ms->oem_table_id);
2667 }
2668 #ifdef CONFIG_TPM
2669 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2670 if (misc.tpm_version == TPM_VERSION_1_2) {
2671 acpi_add_table(table_offsets, tables_blob);
2672 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2673 x86ms->oem_id, x86ms->oem_table_id);
2674 } else { /* TPM_VERSION_2_0 */
2675 acpi_add_table(table_offsets, tables_blob);
2676 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2677 x86ms->oem_id, x86ms->oem_table_id);
2678 }
2679 }
2680 #endif
2681 if (machine->numa_state->num_nodes) {
2682 acpi_add_table(table_offsets, tables_blob);
2683 build_srat(tables_blob, tables->linker, machine);
2684 if (machine->numa_state->have_numa_distance) {
2685 acpi_add_table(table_offsets, tables_blob);
2686 build_slit(tables_blob, tables->linker, machine, x86ms->oem_id,
2687 x86ms->oem_table_id);
2688 }
2689 if (machine->numa_state->hmat_enabled) {
2690 acpi_add_table(table_offsets, tables_blob);
2691 build_hmat(tables_blob, tables->linker, machine->numa_state,
2692 x86ms->oem_id, x86ms->oem_table_id);
2693 }
2694 }
2695 if (acpi_get_mcfg(&mcfg)) {
2696 acpi_add_table(table_offsets, tables_blob);
2697 build_mcfg(tables_blob, tables->linker, &mcfg, x86ms->oem_id,
2698 x86ms->oem_table_id);
2699 }
2700 if (object_dynamic_cast(OBJECT(iommu), TYPE_AMD_IOMMU_DEVICE)) {
2701 acpi_add_table(table_offsets, tables_blob);
2702 build_amd_iommu(tables_blob, tables->linker, x86ms->oem_id,
2703 x86ms->oem_table_id);
2704 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_INTEL_IOMMU_DEVICE)) {
2705 acpi_add_table(table_offsets, tables_blob);
2706 build_dmar_q35(tables_blob, tables->linker, x86ms->oem_id,
2707 x86ms->oem_table_id);
2708 } else if (object_dynamic_cast(OBJECT(iommu), TYPE_VIRTIO_IOMMU_PCI)) {
2709 PCIDevice *pdev = PCI_DEVICE(iommu);
2710
2711 acpi_add_table(table_offsets, tables_blob);
2712 build_viot(machine, tables_blob, tables->linker, pci_get_bdf(pdev),
2713 x86ms->oem_id, x86ms->oem_table_id);
2714 }
2715 if (machine->nvdimms_state->is_enabled) {
2716 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2717 machine->nvdimms_state, machine->ram_slots,
2718 x86ms->oem_id, x86ms->oem_table_id);
2719 }
2720 if (machine->cxl_devices_state->is_enabled) {
2721 cxl_build_cedt(machine, table_offsets, tables_blob, tables->linker,
2722 x86ms->oem_id, x86ms->oem_table_id);
2723 }
2724
2725 acpi_add_table(table_offsets, tables_blob);
2726 build_waet(tables_blob, tables->linker, x86ms->oem_id, x86ms->oem_table_id);
2727
2728 /* Add tables supplied by user (if any) */
2729 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2730 unsigned len = acpi_table_len(u);
2731
2732 acpi_add_table(table_offsets, tables_blob);
2733 g_array_append_vals(tables_blob, u, len);
2734 }
2735
2736 /* RSDT is pointed to by RSDP */
2737 rsdt = tables_blob->len;
2738 build_rsdt(tables_blob, tables->linker, table_offsets,
2739 oem_id, oem_table_id);
2740
2741 /* RSDP is in FSEG memory, so allocate it separately */
2742 {
2743 AcpiRsdpData rsdp_data = {
2744 .revision = 0,
2745 .oem_id = x86ms->oem_id,
2746 .xsdt_tbl_offset = NULL,
2747 .rsdt_tbl_offset = &rsdt,
2748 };
2749 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2750 if (!pcmc->rsdp_in_ram) {
2751 /* We used to allocate some extra space for RSDP revision 2 but
2752 * only used the RSDP revision 0 space. The extra bytes were
2753 * zeroed out and not used.
2754 * Here we continue wasting those extra 16 bytes to make sure we
2755 * don't break migration for machine types 2.2 and older due to
2756 * RSDP blob size mismatch.
2757 */
2758 build_append_int_noprefix(tables->rsdp, 0, 16);
2759 }
2760 }
2761
2762 /* We'll expose it all to Guest so we want to reduce
2763 * chance of size changes.
2764 *
2765 * We used to align the tables to 4k, but of course this would
2766 * too simple to be enough. 4k turned out to be too small an
2767 * alignment very soon, and in fact it is almost impossible to
2768 * keep the table size stable for all (max_cpus, max_memory_slots)
2769 * combinations. So the table size is always 64k for pc-i440fx-2.1
2770 * and we give an error if the table grows beyond that limit.
2771 *
2772 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2773 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2774 * than 2.0 and we can always pad the smaller tables with zeros. We can
2775 * then use the exact size of the 2.0 tables.
2776 *
2777 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2778 */
2779 if (pcmc->legacy_acpi_table_size) {
2780 /* Subtracting aml_len gives the size of fixed tables. Then add the
2781 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2782 */
2783 int legacy_aml_len =
2784 pcmc->legacy_acpi_table_size +
2785 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2786 int legacy_table_size =
2787 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2788 ACPI_BUILD_ALIGN_SIZE);
2789 if (tables_blob->len > legacy_table_size) {
2790 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2791 warn_report("ACPI table size %u exceeds %d bytes,"
2792 " migration may not work",
2793 tables_blob->len, legacy_table_size);
2794 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2795 " or PCI bridges.");
2796 }
2797 g_array_set_size(tables_blob, legacy_table_size);
2798 } else {
2799 /* Make sure we have a buffer in case we need to resize the tables. */
2800 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2801 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2802 warn_report("ACPI table size %u exceeds %d bytes,"
2803 " migration may not work",
2804 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2805 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2806 " or PCI bridges.");
2807 }
2808 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2809 }
2810
2811 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2812
2813 /* Cleanup memory that's no longer used. */
2814 g_array_free(table_offsets, true);
2815 g_free(slic_oem.id);
2816 g_free(slic_oem.table_id);
2817 }
2818
2819 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2820 {
2821 uint32_t size = acpi_data_len(data);
2822
2823 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2824 memory_region_ram_resize(mr, size, &error_abort);
2825
2826 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2827 memory_region_set_dirty(mr, 0, size);
2828 }
2829
2830 static void acpi_build_update(void *build_opaque)
2831 {
2832 AcpiBuildState *build_state = build_opaque;
2833 AcpiBuildTables tables;
2834
2835 /* No state to update or already patched? Nothing to do. */
2836 if (!build_state || build_state->patched) {
2837 return;
2838 }
2839 build_state->patched = 1;
2840
2841 acpi_build_tables_init(&tables);
2842
2843 acpi_build(&tables, MACHINE(qdev_get_machine()));
2844
2845 acpi_ram_update(build_state->table_mr, tables.table_data);
2846
2847 if (build_state->rsdp) {
2848 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2849 } else {
2850 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2851 }
2852
2853 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2854 acpi_build_tables_cleanup(&tables, true);
2855 }
2856
2857 static void acpi_build_reset(void *build_opaque)
2858 {
2859 AcpiBuildState *build_state = build_opaque;
2860 build_state->patched = 0;
2861 }
2862
2863 static const VMStateDescription vmstate_acpi_build = {
2864 .name = "acpi_build",
2865 .version_id = 1,
2866 .minimum_version_id = 1,
2867 .fields = (VMStateField[]) {
2868 VMSTATE_UINT8(patched, AcpiBuildState),
2869 VMSTATE_END_OF_LIST()
2870 },
2871 };
2872
2873 void acpi_setup(void)
2874 {
2875 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2876 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2877 X86MachineState *x86ms = X86_MACHINE(pcms);
2878 AcpiBuildTables tables;
2879 AcpiBuildState *build_state;
2880 Object *vmgenid_dev;
2881 #ifdef CONFIG_TPM
2882 TPMIf *tpm;
2883 static FwCfgTPMConfig tpm_config;
2884 #endif
2885
2886 if (!x86ms->fw_cfg) {
2887 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2888 return;
2889 }
2890
2891 if (!pcms->acpi_build_enabled) {
2892 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2893 return;
2894 }
2895
2896 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2897 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2898 return;
2899 }
2900
2901 build_state = g_malloc0(sizeof *build_state);
2902
2903 acpi_build_tables_init(&tables);
2904 acpi_build(&tables, MACHINE(pcms));
2905
2906 /* Now expose it all to Guest */
2907 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2908 build_state, tables.table_data,
2909 ACPI_BUILD_TABLE_FILE);
2910 assert(build_state->table_mr != NULL);
2911
2912 build_state->linker_mr =
2913 acpi_add_rom_blob(acpi_build_update, build_state,
2914 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE);
2915
2916 #ifdef CONFIG_TPM
2917 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2918 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2919
2920 tpm = tpm_find();
2921 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2922 tpm_config = (FwCfgTPMConfig) {
2923 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2924 .tpm_version = tpm_get_version(tpm),
2925 .tpmppi_version = TPM_PPI_VERSION_1_30
2926 };
2927 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2928 &tpm_config, sizeof tpm_config);
2929 }
2930 #endif
2931
2932 vmgenid_dev = find_vmgenid_dev();
2933 if (vmgenid_dev) {
2934 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2935 tables.vmgenid);
2936 }
2937
2938 if (!pcmc->rsdp_in_ram) {
2939 /*
2940 * Keep for compatibility with old machine types.
2941 * Though RSDP is small, its contents isn't immutable, so
2942 * we'll update it along with the rest of tables on guest access.
2943 */
2944 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2945
2946 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2947 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2948 acpi_build_update, NULL, build_state,
2949 build_state->rsdp, rsdp_size, true);
2950 build_state->rsdp_mr = NULL;
2951 } else {
2952 build_state->rsdp = NULL;
2953 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2954 build_state, tables.rsdp,
2955 ACPI_BUILD_RSDP_FILE);
2956 }
2957
2958 qemu_register_reset(acpi_build_reset, build_state);
2959 acpi_build_reset(build_state);
2960 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2961
2962 /* Cleanup tables but don't free the memory: we track it
2963 * in build_state.
2964 */
2965 acpi_build_tables_cleanup(&tables, false);
2966 }
QEmu