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Open 2.13 development tree
[qemu.git] / linux-user / main.c
blob8907a841141183aa1b9a0215e5121d03d42e9242
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qapi/error.h"
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
30 #include "cpu.h"
31 #include "exec/exec-all.h"
32 #include "tcg.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
35 #include "elf.h"
36 #include "exec/log.h"
37 #include "trace/control.h"
38 #include "target_elf.h"
39
40 char *exec_path;
41
42 int singlestep;
43 static const char *filename;
44 static const char *argv0;
45 static int gdbstub_port;
46 static envlist_t *envlist;
47 static const char *cpu_model;
48 static const char *cpu_type;
49 unsigned long mmap_min_addr;
50 unsigned long guest_base;
51 int have_guest_base;
52
53 #define EXCP_DUMP(env, fmt, ...) \
54 do { \
55 CPUState *cs = ENV_GET_CPU(env); \
56 fprintf(stderr, fmt , ## __VA_ARGS__); \
57 cpu_dump_state(cs, stderr, fprintf, 0); \
58 if (qemu_log_separate()) { \
59 qemu_log(fmt, ## __VA_ARGS__); \
60 log_cpu_state(cs, 0); \
61 } \
62 } while (0)
63
64 /*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 *
71 * Many cpus reserve the high bit (or more than one for some 64-bit cpus)
72 * of the address for the kernel. Some cpus rely on this and user space
73 * uses the high bit(s) for pointer tagging and the like. For them, we
74 * must preserve the expected address space.
75 */
76 #ifndef MAX_RESERVED_VA
77 # if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
78 # if TARGET_VIRT_ADDR_SPACE_BITS == 32 && \
79 (TARGET_LONG_BITS == 32 || defined(TARGET_ABI32))
80 /* There are a number of places where we assign reserved_va to a variable
81 of type abi_ulong and expect it to fit. Avoid the last page. */
82 # define MAX_RESERVED_VA (0xfffffffful & TARGET_PAGE_MASK)
83 # else
84 # define MAX_RESERVED_VA (1ul << TARGET_VIRT_ADDR_SPACE_BITS)
85 # endif
86 # else
87 # define MAX_RESERVED_VA 0
88 # endif
89 #endif
90
91 /* That said, reserving *too* much vm space via mmap can run into problems
92 with rlimits, oom due to page table creation, etc. We will still try it,
93 if directed by the command-line option, but not by default. */
94 #if HOST_LONG_BITS == 64 && TARGET_VIRT_ADDR_SPACE_BITS <= 32
95 unsigned long reserved_va = MAX_RESERVED_VA;
96 #else
97 unsigned long reserved_va;
98 #endif
99
100 static void usage(int exitcode);
101
102 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
103 const char *qemu_uname_release;
104
105 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
106 we allocate a bigger stack. Need a better solution, for example
107 by remapping the process stack directly at the right place */
108 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
109
110 void gemu_log(const char *fmt, ...)
111 {
112 va_list ap;
113
114 va_start(ap, fmt);
115 vfprintf(stderr, fmt, ap);
116 va_end(ap);
117 }
118
119 #if defined(TARGET_I386)
120 int cpu_get_pic_interrupt(CPUX86State *env)
121 {
122 return -1;
123 }
124 #endif
125
126 /***********************************************************/
127 /* Helper routines for implementing atomic operations. */
128
129 /* Make sure everything is in a consistent state for calling fork(). */
130 void fork_start(void)
131 {
132 start_exclusive();
133 mmap_fork_start();
134 qemu_mutex_lock(&tb_ctx.tb_lock);
135 cpu_list_lock();
136 }
137
138 void fork_end(int child)
139 {
140 mmap_fork_end(child);
141 if (child) {
142 CPUState *cpu, *next_cpu;
143 /* Child processes created by fork() only have a single thread.
144 Discard information about the parent threads. */
145 CPU_FOREACH_SAFE(cpu, next_cpu) {
146 if (cpu != thread_cpu) {
147 QTAILQ_REMOVE(&cpus, cpu, node);
148 }
149 }
150 qemu_mutex_init(&tb_ctx.tb_lock);
151 qemu_init_cpu_list();
152 gdbserver_fork(thread_cpu);
153 /* qemu_init_cpu_list() takes care of reinitializing the
154 * exclusive state, so we don't need to end_exclusive() here.
155 */
156 } else {
157 qemu_mutex_unlock(&tb_ctx.tb_lock);
158 cpu_list_unlock();
159 end_exclusive();
160 }
161 }
162
163 #ifdef TARGET_I386
164 /***********************************************************/
165 /* CPUX86 core interface */
166
167 uint64_t cpu_get_tsc(CPUX86State *env)
168 {
169 return cpu_get_host_ticks();
170 }
171
172 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
173 int flags)
174 {
175 unsigned int e1, e2;
176 uint32_t *p;
177 e1 = (addr << 16) | (limit & 0xffff);
178 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
179 e2 |= flags;
180 p = ptr;
181 p[0] = tswap32(e1);
182 p[1] = tswap32(e2);
183 }
184
185 static uint64_t *idt_table;
186 #ifdef TARGET_X86_64
187 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
188 uint64_t addr, unsigned int sel)
189 {
190 uint32_t *p, e1, e2;
191 e1 = (addr & 0xffff) | (sel << 16);
192 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
193 p = ptr;
194 p[0] = tswap32(e1);
195 p[1] = tswap32(e2);
196 p[2] = tswap32(addr >> 32);
197 p[3] = 0;
198 }
199 /* only dpl matters as we do only user space emulation */
200 static void set_idt(int n, unsigned int dpl)
201 {
202 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
203 }
204 #else
205 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
206 uint32_t addr, unsigned int sel)
207 {
208 uint32_t *p, e1, e2;
209 e1 = (addr & 0xffff) | (sel << 16);
210 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
211 p = ptr;
212 p[0] = tswap32(e1);
213 p[1] = tswap32(e2);
214 }
215
216 /* only dpl matters as we do only user space emulation */
217 static void set_idt(int n, unsigned int dpl)
218 {
219 set_gate(idt_table + n, 0, dpl, 0, 0);
220 }
221 #endif
222
223 void cpu_loop(CPUX86State *env)
224 {
225 CPUState *cs = CPU(x86_env_get_cpu(env));
226 int trapnr;
227 abi_ulong pc;
228 abi_ulong ret;
229 target_siginfo_t info;
230
231 for(;;) {
232 cpu_exec_start(cs);
233 trapnr = cpu_exec(cs);
234 cpu_exec_end(cs);
235 process_queued_cpu_work(cs);
236
237 switch(trapnr) {
238 case 0x80:
239 /* linux syscall from int $0x80 */
240 ret = do_syscall(env,
241 env->regs[R_EAX],
242 env->regs[R_EBX],
243 env->regs[R_ECX],
244 env->regs[R_EDX],
245 env->regs[R_ESI],
246 env->regs[R_EDI],
247 env->regs[R_EBP],
248 0, 0);
249 if (ret == -TARGET_ERESTARTSYS) {
250 env->eip -= 2;
251 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
252 env->regs[R_EAX] = ret;
253 }
254 break;
255 #ifndef TARGET_ABI32
256 case EXCP_SYSCALL:
257 /* linux syscall from syscall instruction */
258 ret = do_syscall(env,
259 env->regs[R_EAX],
260 env->regs[R_EDI],
261 env->regs[R_ESI],
262 env->regs[R_EDX],
263 env->regs[10],
264 env->regs[8],
265 env->regs[9],
266 0, 0);
267 if (ret == -TARGET_ERESTARTSYS) {
268 env->eip -= 2;
269 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
270 env->regs[R_EAX] = ret;
271 }
272 break;
273 #endif
274 case EXCP0B_NOSEG:
275 case EXCP0C_STACK:
276 info.si_signo = TARGET_SIGBUS;
277 info.si_errno = 0;
278 info.si_code = TARGET_SI_KERNEL;
279 info._sifields._sigfault._addr = 0;
280 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
281 break;
282 case EXCP0D_GPF:
283 /* XXX: potential problem if ABI32 */
284 #ifndef TARGET_X86_64
285 if (env->eflags & VM_MASK) {
286 handle_vm86_fault(env);
287 } else
288 #endif
289 {
290 info.si_signo = TARGET_SIGSEGV;
291 info.si_errno = 0;
292 info.si_code = TARGET_SI_KERNEL;
293 info._sifields._sigfault._addr = 0;
294 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
295 }
296 break;
297 case EXCP0E_PAGE:
298 info.si_signo = TARGET_SIGSEGV;
299 info.si_errno = 0;
300 if (!(env->error_code & 1))
301 info.si_code = TARGET_SEGV_MAPERR;
302 else
303 info.si_code = TARGET_SEGV_ACCERR;
304 info._sifields._sigfault._addr = env->cr[2];
305 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
306 break;
307 case EXCP00_DIVZ:
308 #ifndef TARGET_X86_64
309 if (env->eflags & VM_MASK) {
310 handle_vm86_trap(env, trapnr);
311 } else
312 #endif
313 {
314 /* division by zero */
315 info.si_signo = TARGET_SIGFPE;
316 info.si_errno = 0;
317 info.si_code = TARGET_FPE_INTDIV;
318 info._sifields._sigfault._addr = env->eip;
319 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
320 }
321 break;
322 case EXCP01_DB:
323 case EXCP03_INT3:
324 #ifndef TARGET_X86_64
325 if (env->eflags & VM_MASK) {
326 handle_vm86_trap(env, trapnr);
327 } else
328 #endif
329 {
330 info.si_signo = TARGET_SIGTRAP;
331 info.si_errno = 0;
332 if (trapnr == EXCP01_DB) {
333 info.si_code = TARGET_TRAP_BRKPT;
334 info._sifields._sigfault._addr = env->eip;
335 } else {
336 info.si_code = TARGET_SI_KERNEL;
337 info._sifields._sigfault._addr = 0;
338 }
339 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
340 }
341 break;
342 case EXCP04_INTO:
343 case EXCP05_BOUND:
344 #ifndef TARGET_X86_64
345 if (env->eflags & VM_MASK) {
346 handle_vm86_trap(env, trapnr);
347 } else
348 #endif
349 {
350 info.si_signo = TARGET_SIGSEGV;
351 info.si_errno = 0;
352 info.si_code = TARGET_SI_KERNEL;
353 info._sifields._sigfault._addr = 0;
354 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
355 }
356 break;
357 case EXCP06_ILLOP:
358 info.si_signo = TARGET_SIGILL;
359 info.si_errno = 0;
360 info.si_code = TARGET_ILL_ILLOPN;
361 info._sifields._sigfault._addr = env->eip;
362 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
363 break;
364 case EXCP_INTERRUPT:
365 /* just indicate that signals should be handled asap */
366 break;
367 case EXCP_DEBUG:
368 {
369 int sig;
370
371 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
372 if (sig)
373 {
374 info.si_signo = sig;
375 info.si_errno = 0;
376 info.si_code = TARGET_TRAP_BRKPT;
377 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
378 }
379 }
380 break;
381 case EXCP_ATOMIC:
382 cpu_exec_step_atomic(cs);
383 break;
384 default:
385 pc = env->segs[R_CS].base + env->eip;
386 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
387 (long)pc, trapnr);
388 abort();
389 }
390 process_pending_signals(env);
391 }
392 }
393 #endif
394
395 #ifdef TARGET_ARM
396
397 #define get_user_code_u32(x, gaddr, env) \
398 ({ abi_long __r = get_user_u32((x), (gaddr)); \
399 if (!__r && bswap_code(arm_sctlr_b(env))) { \
400 (x) = bswap32(x); \
401 } \
402 __r; \
403 })
404
405 #define get_user_code_u16(x, gaddr, env) \
406 ({ abi_long __r = get_user_u16((x), (gaddr)); \
407 if (!__r && bswap_code(arm_sctlr_b(env))) { \
408 (x) = bswap16(x); \
409 } \
410 __r; \
411 })
412
413 #define get_user_data_u32(x, gaddr, env) \
414 ({ abi_long __r = get_user_u32((x), (gaddr)); \
415 if (!__r && arm_cpu_bswap_data(env)) { \
416 (x) = bswap32(x); \
417 } \
418 __r; \
419 })
420
421 #define get_user_data_u16(x, gaddr, env) \
422 ({ abi_long __r = get_user_u16((x), (gaddr)); \
423 if (!__r && arm_cpu_bswap_data(env)) { \
424 (x) = bswap16(x); \
425 } \
426 __r; \
427 })
428
429 #define put_user_data_u32(x, gaddr, env) \
430 ({ typeof(x) __x = (x); \
431 if (arm_cpu_bswap_data(env)) { \
432 __x = bswap32(__x); \
433 } \
434 put_user_u32(__x, (gaddr)); \
435 })
436
437 #define put_user_data_u16(x, gaddr, env) \
438 ({ typeof(x) __x = (x); \
439 if (arm_cpu_bswap_data(env)) { \
440 __x = bswap16(__x); \
441 } \
442 put_user_u16(__x, (gaddr)); \
443 })
444
445 #ifdef TARGET_ABI32
446 /* Commpage handling -- there is no commpage for AArch64 */
447
448 /*
449 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
450 * Input:
451 * r0 = pointer to oldval
452 * r1 = pointer to newval
453 * r2 = pointer to target value
454 *
455 * Output:
456 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
457 * C set if *ptr was changed, clear if no exchange happened
458 *
459 * Note segv's in kernel helpers are a bit tricky, we can set the
460 * data address sensibly but the PC address is just the entry point.
461 */
462 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
463 {
464 uint64_t oldval, newval, val;
465 uint32_t addr, cpsr;
466 target_siginfo_t info;
467
468 /* Based on the 32 bit code in do_kernel_trap */
469
470 /* XXX: This only works between threads, not between processes.
471 It's probably possible to implement this with native host
472 operations. However things like ldrex/strex are much harder so
473 there's not much point trying. */
474 start_exclusive();
475 cpsr = cpsr_read(env);
476 addr = env->regs[2];
477
478 if (get_user_u64(oldval, env->regs[0])) {
479 env->exception.vaddress = env->regs[0];
480 goto segv;
481 };
482
483 if (get_user_u64(newval, env->regs[1])) {
484 env->exception.vaddress = env->regs[1];
485 goto segv;
486 };
487
488 if (get_user_u64(val, addr)) {
489 env->exception.vaddress = addr;
490 goto segv;
491 }
492
493 if (val == oldval) {
494 val = newval;
495
496 if (put_user_u64(val, addr)) {
497 env->exception.vaddress = addr;
498 goto segv;
499 };
500
501 env->regs[0] = 0;
502 cpsr |= CPSR_C;
503 } else {
504 env->regs[0] = -1;
505 cpsr &= ~CPSR_C;
506 }
507 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
508 end_exclusive();
509 return;
510
511 segv:
512 end_exclusive();
513 /* We get the PC of the entry address - which is as good as anything,
514 on a real kernel what you get depends on which mode it uses. */
515 info.si_signo = TARGET_SIGSEGV;
516 info.si_errno = 0;
517 /* XXX: check env->error_code */
518 info.si_code = TARGET_SEGV_MAPERR;
519 info._sifields._sigfault._addr = env->exception.vaddress;
520 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
521 }
522
523 /* Handle a jump to the kernel code page. */
524 static int
525 do_kernel_trap(CPUARMState *env)
526 {
527 uint32_t addr;
528 uint32_t cpsr;
529 uint32_t val;
530
531 switch (env->regs[15]) {
532 case 0xffff0fa0: /* __kernel_memory_barrier */
533 /* ??? No-op. Will need to do better for SMP. */
534 break;
535 case 0xffff0fc0: /* __kernel_cmpxchg */
536 /* XXX: This only works between threads, not between processes.
537 It's probably possible to implement this with native host
538 operations. However things like ldrex/strex are much harder so
539 there's not much point trying. */
540 start_exclusive();
541 cpsr = cpsr_read(env);
542 addr = env->regs[2];
543 /* FIXME: This should SEGV if the access fails. */
544 if (get_user_u32(val, addr))
545 val = ~env->regs[0];
546 if (val == env->regs[0]) {
547 val = env->regs[1];
548 /* FIXME: Check for segfaults. */
549 put_user_u32(val, addr);
550 env->regs[0] = 0;
551 cpsr |= CPSR_C;
552 } else {
553 env->regs[0] = -1;
554 cpsr &= ~CPSR_C;
555 }
556 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
557 end_exclusive();
558 break;
559 case 0xffff0fe0: /* __kernel_get_tls */
560 env->regs[0] = cpu_get_tls(env);
561 break;
562 case 0xffff0f60: /* __kernel_cmpxchg64 */
563 arm_kernel_cmpxchg64_helper(env);
564 break;
565
566 default:
567 return 1;
568 }
569 /* Jump back to the caller. */
570 addr = env->regs[14];
571 if (addr & 1) {
572 env->thumb = 1;
573 addr &= ~1;
574 }
575 env->regs[15] = addr;
576
577 return 0;
578 }
579
580 void cpu_loop(CPUARMState *env)
581 {
582 CPUState *cs = CPU(arm_env_get_cpu(env));
583 int trapnr;
584 unsigned int n, insn;
585 target_siginfo_t info;
586 uint32_t addr;
587 abi_ulong ret;
588
589 for(;;) {
590 cpu_exec_start(cs);
591 trapnr = cpu_exec(cs);
592 cpu_exec_end(cs);
593 process_queued_cpu_work(cs);
594
595 switch(trapnr) {
596 case EXCP_UDEF:
597 case EXCP_NOCP:
598 case EXCP_INVSTATE:
599 {
600 TaskState *ts = cs->opaque;
601 uint32_t opcode;
602 int rc;
603
604 /* we handle the FPU emulation here, as Linux */
605 /* we get the opcode */
606 /* FIXME - what to do if get_user() fails? */
607 get_user_code_u32(opcode, env->regs[15], env);
608
609 rc = EmulateAll(opcode, &ts->fpa, env);
610 if (rc == 0) { /* illegal instruction */
611 info.si_signo = TARGET_SIGILL;
612 info.si_errno = 0;
613 info.si_code = TARGET_ILL_ILLOPN;
614 info._sifields._sigfault._addr = env->regs[15];
615 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
616 } else if (rc < 0) { /* FP exception */
617 int arm_fpe=0;
618
619 /* translate softfloat flags to FPSR flags */
620 if (-rc & float_flag_invalid)
621 arm_fpe |= BIT_IOC;
622 if (-rc & float_flag_divbyzero)
623 arm_fpe |= BIT_DZC;
624 if (-rc & float_flag_overflow)
625 arm_fpe |= BIT_OFC;
626 if (-rc & float_flag_underflow)
627 arm_fpe |= BIT_UFC;
628 if (-rc & float_flag_inexact)
629 arm_fpe |= BIT_IXC;
630
631 FPSR fpsr = ts->fpa.fpsr;
632 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
633
634 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
635 info.si_signo = TARGET_SIGFPE;
636 info.si_errno = 0;
637
638 /* ordered by priority, least first */
639 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
640 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
641 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
642 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
643 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
644
645 info._sifields._sigfault._addr = env->regs[15];
646 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
647 } else {
648 env->regs[15] += 4;
649 }
650
651 /* accumulate unenabled exceptions */
652 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
653 fpsr |= BIT_IXC;
654 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
655 fpsr |= BIT_UFC;
656 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
657 fpsr |= BIT_OFC;
658 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
659 fpsr |= BIT_DZC;
660 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
661 fpsr |= BIT_IOC;
662 ts->fpa.fpsr=fpsr;
663 } else { /* everything OK */
664 /* increment PC */
665 env->regs[15] += 4;
666 }
667 }
668 break;
669 case EXCP_SWI:
670 case EXCP_BKPT:
671 {
672 env->eabi = 1;
673 /* system call */
674 if (trapnr == EXCP_BKPT) {
675 if (env->thumb) {
676 /* FIXME - what to do if get_user() fails? */
677 get_user_code_u16(insn, env->regs[15], env);
678 n = insn & 0xff;
679 env->regs[15] += 2;
680 } else {
681 /* FIXME - what to do if get_user() fails? */
682 get_user_code_u32(insn, env->regs[15], env);
683 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
684 env->regs[15] += 4;
685 }
686 } else {
687 if (env->thumb) {
688 /* FIXME - what to do if get_user() fails? */
689 get_user_code_u16(insn, env->regs[15] - 2, env);
690 n = insn & 0xff;
691 } else {
692 /* FIXME - what to do if get_user() fails? */
693 get_user_code_u32(insn, env->regs[15] - 4, env);
694 n = insn & 0xffffff;
695 }
696 }
697
698 if (n == ARM_NR_cacheflush) {
699 /* nop */
700 } else if (n == ARM_NR_semihosting
701 || n == ARM_NR_thumb_semihosting) {
702 env->regs[0] = do_arm_semihosting (env);
703 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
704 /* linux syscall */
705 if (env->thumb || n == 0) {
706 n = env->regs[7];
707 } else {
708 n -= ARM_SYSCALL_BASE;
709 env->eabi = 0;
710 }
711 if ( n > ARM_NR_BASE) {
712 switch (n) {
713 case ARM_NR_cacheflush:
714 /* nop */
715 break;
716 case ARM_NR_set_tls:
717 cpu_set_tls(env, env->regs[0]);
718 env->regs[0] = 0;
719 break;
720 case ARM_NR_breakpoint:
721 env->regs[15] -= env->thumb ? 2 : 4;
722 goto excp_debug;
723 default:
724 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
725 n);
726 env->regs[0] = -TARGET_ENOSYS;
727 break;
728 }
729 } else {
730 ret = do_syscall(env,
731 n,
732 env->regs[0],
733 env->regs[1],
734 env->regs[2],
735 env->regs[3],
736 env->regs[4],
737 env->regs[5],
738 0, 0);
739 if (ret == -TARGET_ERESTARTSYS) {
740 env->regs[15] -= env->thumb ? 2 : 4;
741 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
742 env->regs[0] = ret;
743 }
744 }
745 } else {
746 goto error;
747 }
748 }
749 break;
750 case EXCP_SEMIHOST:
751 env->regs[0] = do_arm_semihosting(env);
752 break;
753 case EXCP_INTERRUPT:
754 /* just indicate that signals should be handled asap */
755 break;
756 case EXCP_PREFETCH_ABORT:
757 case EXCP_DATA_ABORT:
758 addr = env->exception.vaddress;
759 {
760 info.si_signo = TARGET_SIGSEGV;
761 info.si_errno = 0;
762 /* XXX: check env->error_code */
763 info.si_code = TARGET_SEGV_MAPERR;
764 info._sifields._sigfault._addr = addr;
765 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
766 }
767 break;
768 case EXCP_DEBUG:
769 excp_debug:
770 {
771 int sig;
772
773 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
774 if (sig)
775 {
776 info.si_signo = sig;
777 info.si_errno = 0;
778 info.si_code = TARGET_TRAP_BRKPT;
779 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
780 }
781 }
782 break;
783 case EXCP_KERNEL_TRAP:
784 if (do_kernel_trap(env))
785 goto error;
786 break;
787 case EXCP_YIELD:
788 /* nothing to do here for user-mode, just resume guest code */
789 break;
790 case EXCP_ATOMIC:
791 cpu_exec_step_atomic(cs);
792 break;
793 default:
794 error:
795 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
796 abort();
797 }
798 process_pending_signals(env);
799 }
800 }
801
802 #else
803
804 /* AArch64 main loop */
805 void cpu_loop(CPUARMState *env)
806 {
807 CPUState *cs = CPU(arm_env_get_cpu(env));
808 int trapnr, sig;
809 abi_long ret;
810 target_siginfo_t info;
811
812 for (;;) {
813 cpu_exec_start(cs);
814 trapnr = cpu_exec(cs);
815 cpu_exec_end(cs);
816 process_queued_cpu_work(cs);
817
818 switch (trapnr) {
819 case EXCP_SWI:
820 ret = do_syscall(env,
821 env->xregs[8],
822 env->xregs[0],
823 env->xregs[1],
824 env->xregs[2],
825 env->xregs[3],
826 env->xregs[4],
827 env->xregs[5],
828 0, 0);
829 if (ret == -TARGET_ERESTARTSYS) {
830 env->pc -= 4;
831 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
832 env->xregs[0] = ret;
833 }
834 break;
835 case EXCP_INTERRUPT:
836 /* just indicate that signals should be handled asap */
837 break;
838 case EXCP_UDEF:
839 info.si_signo = TARGET_SIGILL;
840 info.si_errno = 0;
841 info.si_code = TARGET_ILL_ILLOPN;
842 info._sifields._sigfault._addr = env->pc;
843 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
844 break;
845 case EXCP_PREFETCH_ABORT:
846 case EXCP_DATA_ABORT:
847 info.si_signo = TARGET_SIGSEGV;
848 info.si_errno = 0;
849 /* XXX: check env->error_code */
850 info.si_code = TARGET_SEGV_MAPERR;
851 info._sifields._sigfault._addr = env->exception.vaddress;
852 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
853 break;
854 case EXCP_DEBUG:
855 case EXCP_BKPT:
856 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
857 if (sig) {
858 info.si_signo = sig;
859 info.si_errno = 0;
860 info.si_code = TARGET_TRAP_BRKPT;
861 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
862 }
863 break;
864 case EXCP_SEMIHOST:
865 env->xregs[0] = do_arm_semihosting(env);
866 break;
867 case EXCP_YIELD:
868 /* nothing to do here for user-mode, just resume guest code */
869 break;
870 case EXCP_ATOMIC:
871 cpu_exec_step_atomic(cs);
872 break;
873 default:
874 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
875 abort();
876 }
877 process_pending_signals(env);
878 /* Exception return on AArch64 always clears the exclusive monitor,
879 * so any return to running guest code implies this.
880 */
881 env->exclusive_addr = -1;
882 }
883 }
884 #endif /* ndef TARGET_ABI32 */
885
886 #endif
887
888 #ifdef TARGET_SPARC
889 #define SPARC64_STACK_BIAS 2047
890
891 //#define DEBUG_WIN
892
893 /* WARNING: dealing with register windows _is_ complicated. More info
894 can be found at http://www.sics.se/~psm/sparcstack.html */
895 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
896 {
897 index = (index + cwp * 16) % (16 * env->nwindows);
898 /* wrap handling : if cwp is on the last window, then we use the
899 registers 'after' the end */
900 if (index < 8 && env->cwp == env->nwindows - 1)
901 index += 16 * env->nwindows;
902 return index;
903 }
904
905 /* save the register window 'cwp1' */
906 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
907 {
908 unsigned int i;
909 abi_ulong sp_ptr;
910
911 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
912 #ifdef TARGET_SPARC64
913 if (sp_ptr & 3)
914 sp_ptr += SPARC64_STACK_BIAS;
915 #endif
916 #if defined(DEBUG_WIN)
917 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
918 sp_ptr, cwp1);
919 #endif
920 for(i = 0; i < 16; i++) {
921 /* FIXME - what to do if put_user() fails? */
922 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
923 sp_ptr += sizeof(abi_ulong);
924 }
925 }
926
927 static void save_window(CPUSPARCState *env)
928 {
929 #ifndef TARGET_SPARC64
930 unsigned int new_wim;
931 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
932 ((1LL << env->nwindows) - 1);
933 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
934 env->wim = new_wim;
935 #else
936 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
937 env->cansave++;
938 env->canrestore--;
939 #endif
940 }
941
942 static void restore_window(CPUSPARCState *env)
943 {
944 #ifndef TARGET_SPARC64
945 unsigned int new_wim;
946 #endif
947 unsigned int i, cwp1;
948 abi_ulong sp_ptr;
949
950 #ifndef TARGET_SPARC64
951 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
952 ((1LL << env->nwindows) - 1);
953 #endif
954
955 /* restore the invalid window */
956 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
957 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
958 #ifdef TARGET_SPARC64
959 if (sp_ptr & 3)
960 sp_ptr += SPARC64_STACK_BIAS;
961 #endif
962 #if defined(DEBUG_WIN)
963 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
964 sp_ptr, cwp1);
965 #endif
966 for(i = 0; i < 16; i++) {
967 /* FIXME - what to do if get_user() fails? */
968 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
969 sp_ptr += sizeof(abi_ulong);
970 }
971 #ifdef TARGET_SPARC64
972 env->canrestore++;
973 if (env->cleanwin < env->nwindows - 1)
974 env->cleanwin++;
975 env->cansave--;
976 #else
977 env->wim = new_wim;
978 #endif
979 }
980
981 static void flush_windows(CPUSPARCState *env)
982 {
983 int offset, cwp1;
984
985 offset = 1;
986 for(;;) {
987 /* if restore would invoke restore_window(), then we can stop */
988 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
989 #ifndef TARGET_SPARC64
990 if (env->wim & (1 << cwp1))
991 break;
992 #else
993 if (env->canrestore == 0)
994 break;
995 env->cansave++;
996 env->canrestore--;
997 #endif
998 save_window_offset(env, cwp1);
999 offset++;
1000 }
1001 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1002 #ifndef TARGET_SPARC64
1003 /* set wim so that restore will reload the registers */
1004 env->wim = 1 << cwp1;
1005 #endif
1006 #if defined(DEBUG_WIN)
1007 printf("flush_windows: nb=%d\n", offset - 1);
1008 #endif
1009 }
1010
1011 void cpu_loop (CPUSPARCState *env)
1012 {
1013 CPUState *cs = CPU(sparc_env_get_cpu(env));
1014 int trapnr;
1015 abi_long ret;
1016 target_siginfo_t info;
1017
1018 while (1) {
1019 cpu_exec_start(cs);
1020 trapnr = cpu_exec(cs);
1021 cpu_exec_end(cs);
1022 process_queued_cpu_work(cs);
1023
1024 /* Compute PSR before exposing state. */
1025 if (env->cc_op != CC_OP_FLAGS) {
1026 cpu_get_psr(env);
1027 }
1028
1029 switch (trapnr) {
1030 #ifndef TARGET_SPARC64
1031 case 0x88:
1032 case 0x90:
1033 #else
1034 case 0x110:
1035 case 0x16d:
1036 #endif
1037 ret = do_syscall (env, env->gregs[1],
1038 env->regwptr[0], env->regwptr[1],
1039 env->regwptr[2], env->regwptr[3],
1040 env->regwptr[4], env->regwptr[5],
1041 0, 0);
1042 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1043 break;
1044 }
1045 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1046 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1047 env->xcc |= PSR_CARRY;
1048 #else
1049 env->psr |= PSR_CARRY;
1050 #endif
1051 ret = -ret;
1052 } else {
1053 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1054 env->xcc &= ~PSR_CARRY;
1055 #else
1056 env->psr &= ~PSR_CARRY;
1057 #endif
1058 }
1059 env->regwptr[0] = ret;
1060 /* next instruction */
1061 env->pc = env->npc;
1062 env->npc = env->npc + 4;
1063 break;
1064 case 0x83: /* flush windows */
1065 #ifdef TARGET_ABI32
1066 case 0x103:
1067 #endif
1068 flush_windows(env);
1069 /* next instruction */
1070 env->pc = env->npc;
1071 env->npc = env->npc + 4;
1072 break;
1073 #ifndef TARGET_SPARC64
1074 case TT_WIN_OVF: /* window overflow */
1075 save_window(env);
1076 break;
1077 case TT_WIN_UNF: /* window underflow */
1078 restore_window(env);
1079 break;
1080 case TT_TFAULT:
1081 case TT_DFAULT:
1082 {
1083 info.si_signo = TARGET_SIGSEGV;
1084 info.si_errno = 0;
1085 /* XXX: check env->error_code */
1086 info.si_code = TARGET_SEGV_MAPERR;
1087 info._sifields._sigfault._addr = env->mmuregs[4];
1088 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1089 }
1090 break;
1091 #else
1092 case TT_SPILL: /* window overflow */
1093 save_window(env);
1094 break;
1095 case TT_FILL: /* window underflow */
1096 restore_window(env);
1097 break;
1098 case TT_TFAULT:
1099 case TT_DFAULT:
1100 {
1101 info.si_signo = TARGET_SIGSEGV;
1102 info.si_errno = 0;
1103 /* XXX: check env->error_code */
1104 info.si_code = TARGET_SEGV_MAPERR;
1105 if (trapnr == TT_DFAULT)
1106 info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
1107 else
1108 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1109 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1110 }
1111 break;
1112 #ifndef TARGET_ABI32
1113 case 0x16e:
1114 flush_windows(env);
1115 sparc64_get_context(env);
1116 break;
1117 case 0x16f:
1118 flush_windows(env);
1119 sparc64_set_context(env);
1120 break;
1121 #endif
1122 #endif
1123 case EXCP_INTERRUPT:
1124 /* just indicate that signals should be handled asap */
1125 break;
1126 case TT_ILL_INSN:
1127 {
1128 info.si_signo = TARGET_SIGILL;
1129 info.si_errno = 0;
1130 info.si_code = TARGET_ILL_ILLOPC;
1131 info._sifields._sigfault._addr = env->pc;
1132 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1133 }
1134 break;
1135 case EXCP_DEBUG:
1136 {
1137 int sig;
1138
1139 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1140 if (sig)
1141 {
1142 info.si_signo = sig;
1143 info.si_errno = 0;
1144 info.si_code = TARGET_TRAP_BRKPT;
1145 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1146 }
1147 }
1148 break;
1149 case EXCP_ATOMIC:
1150 cpu_exec_step_atomic(cs);
1151 break;
1152 default:
1153 printf ("Unhandled trap: 0x%x\n", trapnr);
1154 cpu_dump_state(cs, stderr, fprintf, 0);
1155 exit(EXIT_FAILURE);
1156 }
1157 process_pending_signals (env);
1158 }
1159 }
1160
1161 #endif
1162
1163 #ifdef TARGET_PPC
1164 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1165 {
1166 return cpu_get_host_ticks();
1167 }
1168
1169 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1170 {
1171 return cpu_ppc_get_tb(env);
1172 }
1173
1174 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1175 {
1176 return cpu_ppc_get_tb(env) >> 32;
1177 }
1178
1179 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1180 {
1181 return cpu_ppc_get_tb(env);
1182 }
1183
1184 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1185 {
1186 return cpu_ppc_get_tb(env) >> 32;
1187 }
1188
1189 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1190 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1191
1192 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1193 {
1194 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1195 }
1196
1197 /* XXX: to be fixed */
1198 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1199 {
1200 return -1;
1201 }
1202
1203 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1204 {
1205 return -1;
1206 }
1207
1208 static int do_store_exclusive(CPUPPCState *env)
1209 {
1210 target_ulong addr;
1211 target_ulong page_addr;
1212 target_ulong val, val2 __attribute__((unused)) = 0;
1213 int flags;
1214 int segv = 0;
1215
1216 addr = env->reserve_ea;
1217 page_addr = addr & TARGET_PAGE_MASK;
1218 start_exclusive();
1219 mmap_lock();
1220 flags = page_get_flags(page_addr);
1221 if ((flags & PAGE_READ) == 0) {
1222 segv = 1;
1223 } else {
1224 int reg = env->reserve_info & 0x1f;
1225 int size = env->reserve_info >> 5;
1226 int stored = 0;
1227
1228 if (addr == env->reserve_addr) {
1229 switch (size) {
1230 case 1: segv = get_user_u8(val, addr); break;
1231 case 2: segv = get_user_u16(val, addr); break;
1232 case 4: segv = get_user_u32(val, addr); break;
1233 #if defined(TARGET_PPC64)
1234 case 8: segv = get_user_u64(val, addr); break;
1235 case 16: {
1236 segv = get_user_u64(val, addr);
1237 if (!segv) {
1238 segv = get_user_u64(val2, addr + 8);
1239 }
1240 break;
1241 }
1242 #endif
1243 default: abort();
1244 }
1245 if (!segv && val == env->reserve_val) {
1246 val = env->gpr[reg];
1247 switch (size) {
1248 case 1: segv = put_user_u8(val, addr); break;
1249 case 2: segv = put_user_u16(val, addr); break;
1250 case 4: segv = put_user_u32(val, addr); break;
1251 #if defined(TARGET_PPC64)
1252 case 8: segv = put_user_u64(val, addr); break;
1253 case 16: {
1254 if (val2 == env->reserve_val2) {
1255 if (msr_le) {
1256 val2 = val;
1257 val = env->gpr[reg+1];
1258 } else {
1259 val2 = env->gpr[reg+1];
1260 }
1261 segv = put_user_u64(val, addr);
1262 if (!segv) {
1263 segv = put_user_u64(val2, addr + 8);
1264 }
1265 }
1266 break;
1267 }
1268 #endif
1269 default: abort();
1270 }
1271 if (!segv) {
1272 stored = 1;
1273 }
1274 }
1275 }
1276 env->crf[0] = (stored << 1) | xer_so;
1277 env->reserve_addr = (target_ulong)-1;
1278 }
1279 if (!segv) {
1280 env->nip += 4;
1281 }
1282 mmap_unlock();
1283 end_exclusive();
1284 return segv;
1285 }
1286
1287 void cpu_loop(CPUPPCState *env)
1288 {
1289 CPUState *cs = CPU(ppc_env_get_cpu(env));
1290 target_siginfo_t info;
1291 int trapnr;
1292 target_ulong ret;
1293
1294 for(;;) {
1295 cpu_exec_start(cs);
1296 trapnr = cpu_exec(cs);
1297 cpu_exec_end(cs);
1298 process_queued_cpu_work(cs);
1299
1300 switch(trapnr) {
1301 case POWERPC_EXCP_NONE:
1302 /* Just go on */
1303 break;
1304 case POWERPC_EXCP_CRITICAL: /* Critical input */
1305 cpu_abort(cs, "Critical interrupt while in user mode. "
1306 "Aborting\n");
1307 break;
1308 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1309 cpu_abort(cs, "Machine check exception while in user mode. "
1310 "Aborting\n");
1311 break;
1312 case POWERPC_EXCP_DSI: /* Data storage exception */
1313 /* XXX: check this. Seems bugged */
1314 switch (env->error_code & 0xFF000000) {
1315 case 0x40000000:
1316 case 0x42000000:
1317 info.si_signo = TARGET_SIGSEGV;
1318 info.si_errno = 0;
1319 info.si_code = TARGET_SEGV_MAPERR;
1320 break;
1321 case 0x04000000:
1322 info.si_signo = TARGET_SIGILL;
1323 info.si_errno = 0;
1324 info.si_code = TARGET_ILL_ILLADR;
1325 break;
1326 case 0x08000000:
1327 info.si_signo = TARGET_SIGSEGV;
1328 info.si_errno = 0;
1329 info.si_code = TARGET_SEGV_ACCERR;
1330 break;
1331 default:
1332 /* Let's send a regular segfault... */
1333 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1334 env->error_code);
1335 info.si_signo = TARGET_SIGSEGV;
1336 info.si_errno = 0;
1337 info.si_code = TARGET_SEGV_MAPERR;
1338 break;
1339 }
1340 info._sifields._sigfault._addr = env->spr[SPR_DAR];
1341 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1342 break;
1343 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1344 /* XXX: check this */
1345 switch (env->error_code & 0xFF000000) {
1346 case 0x40000000:
1347 info.si_signo = TARGET_SIGSEGV;
1348 info.si_errno = 0;
1349 info.si_code = TARGET_SEGV_MAPERR;
1350 break;
1351 case 0x10000000:
1352 case 0x08000000:
1353 info.si_signo = TARGET_SIGSEGV;
1354 info.si_errno = 0;
1355 info.si_code = TARGET_SEGV_ACCERR;
1356 break;
1357 default:
1358 /* Let's send a regular segfault... */
1359 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1360 env->error_code);
1361 info.si_signo = TARGET_SIGSEGV;
1362 info.si_errno = 0;
1363 info.si_code = TARGET_SEGV_MAPERR;
1364 break;
1365 }
1366 info._sifields._sigfault._addr = env->nip - 4;
1367 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1368 break;
1369 case POWERPC_EXCP_EXTERNAL: /* External input */
1370 cpu_abort(cs, "External interrupt while in user mode. "
1371 "Aborting\n");
1372 break;
1373 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1374 /* XXX: check this */
1375 info.si_signo = TARGET_SIGBUS;
1376 info.si_errno = 0;
1377 info.si_code = TARGET_BUS_ADRALN;
1378 info._sifields._sigfault._addr = env->nip;
1379 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1380 break;
1381 case POWERPC_EXCP_PROGRAM: /* Program exception */
1382 case POWERPC_EXCP_HV_EMU: /* HV emulation */
1383 /* XXX: check this */
1384 switch (env->error_code & ~0xF) {
1385 case POWERPC_EXCP_FP:
1386 info.si_signo = TARGET_SIGFPE;
1387 info.si_errno = 0;
1388 switch (env->error_code & 0xF) {
1389 case POWERPC_EXCP_FP_OX:
1390 info.si_code = TARGET_FPE_FLTOVF;
1391 break;
1392 case POWERPC_EXCP_FP_UX:
1393 info.si_code = TARGET_FPE_FLTUND;
1394 break;
1395 case POWERPC_EXCP_FP_ZX:
1396 case POWERPC_EXCP_FP_VXZDZ:
1397 info.si_code = TARGET_FPE_FLTDIV;
1398 break;
1399 case POWERPC_EXCP_FP_XX:
1400 info.si_code = TARGET_FPE_FLTRES;
1401 break;
1402 case POWERPC_EXCP_FP_VXSOFT:
1403 info.si_code = TARGET_FPE_FLTINV;
1404 break;
1405 case POWERPC_EXCP_FP_VXSNAN:
1406 case POWERPC_EXCP_FP_VXISI:
1407 case POWERPC_EXCP_FP_VXIDI:
1408 case POWERPC_EXCP_FP_VXIMZ:
1409 case POWERPC_EXCP_FP_VXVC:
1410 case POWERPC_EXCP_FP_VXSQRT:
1411 case POWERPC_EXCP_FP_VXCVI:
1412 info.si_code = TARGET_FPE_FLTSUB;
1413 break;
1414 default:
1415 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1416 env->error_code);
1417 break;
1418 }
1419 break;
1420 case POWERPC_EXCP_INVAL:
1421 info.si_signo = TARGET_SIGILL;
1422 info.si_errno = 0;
1423 switch (env->error_code & 0xF) {
1424 case POWERPC_EXCP_INVAL_INVAL:
1425 info.si_code = TARGET_ILL_ILLOPC;
1426 break;
1427 case POWERPC_EXCP_INVAL_LSWX:
1428 info.si_code = TARGET_ILL_ILLOPN;
1429 break;
1430 case POWERPC_EXCP_INVAL_SPR:
1431 info.si_code = TARGET_ILL_PRVREG;
1432 break;
1433 case POWERPC_EXCP_INVAL_FP:
1434 info.si_code = TARGET_ILL_COPROC;
1435 break;
1436 default:
1437 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1438 env->error_code & 0xF);
1439 info.si_code = TARGET_ILL_ILLADR;
1440 break;
1441 }
1442 break;
1443 case POWERPC_EXCP_PRIV:
1444 info.si_signo = TARGET_SIGILL;
1445 info.si_errno = 0;
1446 switch (env->error_code & 0xF) {
1447 case POWERPC_EXCP_PRIV_OPC:
1448 info.si_code = TARGET_ILL_PRVOPC;
1449 break;
1450 case POWERPC_EXCP_PRIV_REG:
1451 info.si_code = TARGET_ILL_PRVREG;
1452 break;
1453 default:
1454 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1455 env->error_code & 0xF);
1456 info.si_code = TARGET_ILL_PRVOPC;
1457 break;
1458 }
1459 break;
1460 case POWERPC_EXCP_TRAP:
1461 cpu_abort(cs, "Tried to call a TRAP\n");
1462 break;
1463 default:
1464 /* Should not happen ! */
1465 cpu_abort(cs, "Unknown program exception (%02x)\n",
1466 env->error_code);
1467 break;
1468 }
1469 info._sifields._sigfault._addr = env->nip;
1470 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1471 break;
1472 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1473 info.si_signo = TARGET_SIGILL;
1474 info.si_errno = 0;
1475 info.si_code = TARGET_ILL_COPROC;
1476 info._sifields._sigfault._addr = env->nip;
1477 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1478 break;
1479 case POWERPC_EXCP_SYSCALL: /* System call exception */
1480 cpu_abort(cs, "Syscall exception while in user mode. "
1481 "Aborting\n");
1482 break;
1483 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1484 info.si_signo = TARGET_SIGILL;
1485 info.si_errno = 0;
1486 info.si_code = TARGET_ILL_COPROC;
1487 info._sifields._sigfault._addr = env->nip;
1488 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1489 break;
1490 case POWERPC_EXCP_DECR: /* Decrementer exception */
1491 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1492 "Aborting\n");
1493 break;
1494 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1495 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1496 "Aborting\n");
1497 break;
1498 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1499 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1500 "Aborting\n");
1501 break;
1502 case POWERPC_EXCP_DTLB: /* Data TLB error */
1503 cpu_abort(cs, "Data TLB exception while in user mode. "
1504 "Aborting\n");
1505 break;
1506 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1507 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1508 "Aborting\n");
1509 break;
1510 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1511 info.si_signo = TARGET_SIGILL;
1512 info.si_errno = 0;
1513 info.si_code = TARGET_ILL_COPROC;
1514 info._sifields._sigfault._addr = env->nip;
1515 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1516 break;
1517 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1518 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1519 break;
1520 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1521 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1522 break;
1523 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1524 cpu_abort(cs, "Performance monitor exception not handled\n");
1525 break;
1526 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1527 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1528 "Aborting\n");
1529 break;
1530 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1531 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1532 "Aborting\n");
1533 break;
1534 case POWERPC_EXCP_RESET: /* System reset exception */
1535 cpu_abort(cs, "Reset interrupt while in user mode. "
1536 "Aborting\n");
1537 break;
1538 case POWERPC_EXCP_DSEG: /* Data segment exception */
1539 cpu_abort(cs, "Data segment exception while in user mode. "
1540 "Aborting\n");
1541 break;
1542 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1543 cpu_abort(cs, "Instruction segment exception "
1544 "while in user mode. Aborting\n");
1545 break;
1546 /* PowerPC 64 with hypervisor mode support */
1547 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1548 cpu_abort(cs, "Hypervisor decrementer interrupt "
1549 "while in user mode. Aborting\n");
1550 break;
1551 case POWERPC_EXCP_TRACE: /* Trace exception */
1552 /* Nothing to do:
1553 * we use this exception to emulate step-by-step execution mode.
1554 */
1555 break;
1556 /* PowerPC 64 with hypervisor mode support */
1557 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1558 cpu_abort(cs, "Hypervisor data storage exception "
1559 "while in user mode. Aborting\n");
1560 break;
1561 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1562 cpu_abort(cs, "Hypervisor instruction storage exception "
1563 "while in user mode. Aborting\n");
1564 break;
1565 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1566 cpu_abort(cs, "Hypervisor data segment exception "
1567 "while in user mode. Aborting\n");
1568 break;
1569 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1570 cpu_abort(cs, "Hypervisor instruction segment exception "
1571 "while in user mode. Aborting\n");
1572 break;
1573 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1574 info.si_signo = TARGET_SIGILL;
1575 info.si_errno = 0;
1576 info.si_code = TARGET_ILL_COPROC;
1577 info._sifields._sigfault._addr = env->nip;
1578 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1579 break;
1580 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1581 cpu_abort(cs, "Programmable interval timer interrupt "
1582 "while in user mode. Aborting\n");
1583 break;
1584 case POWERPC_EXCP_IO: /* IO error exception */
1585 cpu_abort(cs, "IO error exception while in user mode. "
1586 "Aborting\n");
1587 break;
1588 case POWERPC_EXCP_RUNM: /* Run mode exception */
1589 cpu_abort(cs, "Run mode exception while in user mode. "
1590 "Aborting\n");
1591 break;
1592 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1593 cpu_abort(cs, "Emulation trap exception not handled\n");
1594 break;
1595 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1596 cpu_abort(cs, "Instruction fetch TLB exception "
1597 "while in user-mode. Aborting");
1598 break;
1599 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1600 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1601 "Aborting");
1602 break;
1603 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1604 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1605 "Aborting");
1606 break;
1607 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1608 cpu_abort(cs, "Floating-point assist exception not handled\n");
1609 break;
1610 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1611 cpu_abort(cs, "Instruction address breakpoint exception "
1612 "not handled\n");
1613 break;
1614 case POWERPC_EXCP_SMI: /* System management interrupt */
1615 cpu_abort(cs, "System management interrupt while in user mode. "
1616 "Aborting\n");
1617 break;
1618 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1619 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1620 "Aborting\n");
1621 break;
1622 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1623 cpu_abort(cs, "Performance monitor exception not handled\n");
1624 break;
1625 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1626 cpu_abort(cs, "Vector assist exception not handled\n");
1627 break;
1628 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1629 cpu_abort(cs, "Soft patch exception not handled\n");
1630 break;
1631 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1632 cpu_abort(cs, "Maintenance exception while in user mode. "
1633 "Aborting\n");
1634 break;
1635 case POWERPC_EXCP_STOP: /* stop translation */
1636 /* We did invalidate the instruction cache. Go on */
1637 break;
1638 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1639 /* We just stopped because of a branch. Go on */
1640 break;
1641 case POWERPC_EXCP_SYSCALL_USER:
1642 /* system call in user-mode emulation */
1643 /* WARNING:
1644 * PPC ABI uses overflow flag in cr0 to signal an error
1645 * in syscalls.
1646 */
1647 env->crf[0] &= ~0x1;
1648 env->nip += 4;
1649 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1650 env->gpr[5], env->gpr[6], env->gpr[7],
1651 env->gpr[8], 0, 0);
1652 if (ret == -TARGET_ERESTARTSYS) {
1653 env->nip -= 4;
1654 break;
1655 }
1656 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1657 /* Returning from a successful sigreturn syscall.
1658 Avoid corrupting register state. */
1659 break;
1660 }
1661 if (ret > (target_ulong)(-515)) {
1662 env->crf[0] |= 0x1;
1663 ret = -ret;
1664 }
1665 env->gpr[3] = ret;
1666 break;
1667 case POWERPC_EXCP_STCX:
1668 if (do_store_exclusive(env)) {
1669 info.si_signo = TARGET_SIGSEGV;
1670 info.si_errno = 0;
1671 info.si_code = TARGET_SEGV_MAPERR;
1672 info._sifields._sigfault._addr = env->nip;
1673 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1674 }
1675 break;
1676 case EXCP_DEBUG:
1677 {
1678 int sig;
1679
1680 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1681 if (sig) {
1682 info.si_signo = sig;
1683 info.si_errno = 0;
1684 info.si_code = TARGET_TRAP_BRKPT;
1685 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1686 }
1687 }
1688 break;
1689 case EXCP_INTERRUPT:
1690 /* just indicate that signals should be handled asap */
1691 break;
1692 case EXCP_ATOMIC:
1693 cpu_exec_step_atomic(cs);
1694 break;
1695 default:
1696 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
1697 break;
1698 }
1699 process_pending_signals(env);
1700 }
1701 }
1702 #endif
1703
1704 #ifdef TARGET_MIPS
1705
1706 # ifdef TARGET_ABI_MIPSO32
1707 # define MIPS_SYS(name, args) args,
1708 static const uint8_t mips_syscall_args[] = {
1709 MIPS_SYS(sys_syscall , 8) /* 4000 */
1710 MIPS_SYS(sys_exit , 1)
1711 MIPS_SYS(sys_fork , 0)
1712 MIPS_SYS(sys_read , 3)
1713 MIPS_SYS(sys_write , 3)
1714 MIPS_SYS(sys_open , 3) /* 4005 */
1715 MIPS_SYS(sys_close , 1)
1716 MIPS_SYS(sys_waitpid , 3)
1717 MIPS_SYS(sys_creat , 2)
1718 MIPS_SYS(sys_link , 2)
1719 MIPS_SYS(sys_unlink , 1) /* 4010 */
1720 MIPS_SYS(sys_execve , 0)
1721 MIPS_SYS(sys_chdir , 1)
1722 MIPS_SYS(sys_time , 1)
1723 MIPS_SYS(sys_mknod , 3)
1724 MIPS_SYS(sys_chmod , 2) /* 4015 */
1725 MIPS_SYS(sys_lchown , 3)
1726 MIPS_SYS(sys_ni_syscall , 0)
1727 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1728 MIPS_SYS(sys_lseek , 3)
1729 MIPS_SYS(sys_getpid , 0) /* 4020 */
1730 MIPS_SYS(sys_mount , 5)
1731 MIPS_SYS(sys_umount , 1)
1732 MIPS_SYS(sys_setuid , 1)
1733 MIPS_SYS(sys_getuid , 0)
1734 MIPS_SYS(sys_stime , 1) /* 4025 */
1735 MIPS_SYS(sys_ptrace , 4)
1736 MIPS_SYS(sys_alarm , 1)
1737 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1738 MIPS_SYS(sys_pause , 0)
1739 MIPS_SYS(sys_utime , 2) /* 4030 */
1740 MIPS_SYS(sys_ni_syscall , 0)
1741 MIPS_SYS(sys_ni_syscall , 0)
1742 MIPS_SYS(sys_access , 2)
1743 MIPS_SYS(sys_nice , 1)
1744 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1745 MIPS_SYS(sys_sync , 0)
1746 MIPS_SYS(sys_kill , 2)
1747 MIPS_SYS(sys_rename , 2)
1748 MIPS_SYS(sys_mkdir , 2)
1749 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1750 MIPS_SYS(sys_dup , 1)
1751 MIPS_SYS(sys_pipe , 0)
1752 MIPS_SYS(sys_times , 1)
1753 MIPS_SYS(sys_ni_syscall , 0)
1754 MIPS_SYS(sys_brk , 1) /* 4045 */
1755 MIPS_SYS(sys_setgid , 1)
1756 MIPS_SYS(sys_getgid , 0)
1757 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1758 MIPS_SYS(sys_geteuid , 0)
1759 MIPS_SYS(sys_getegid , 0) /* 4050 */
1760 MIPS_SYS(sys_acct , 0)
1761 MIPS_SYS(sys_umount2 , 2)
1762 MIPS_SYS(sys_ni_syscall , 0)
1763 MIPS_SYS(sys_ioctl , 3)
1764 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1765 MIPS_SYS(sys_ni_syscall , 2)
1766 MIPS_SYS(sys_setpgid , 2)
1767 MIPS_SYS(sys_ni_syscall , 0)
1768 MIPS_SYS(sys_olduname , 1)
1769 MIPS_SYS(sys_umask , 1) /* 4060 */
1770 MIPS_SYS(sys_chroot , 1)
1771 MIPS_SYS(sys_ustat , 2)
1772 MIPS_SYS(sys_dup2 , 2)
1773 MIPS_SYS(sys_getppid , 0)
1774 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1775 MIPS_SYS(sys_setsid , 0)
1776 MIPS_SYS(sys_sigaction , 3)
1777 MIPS_SYS(sys_sgetmask , 0)
1778 MIPS_SYS(sys_ssetmask , 1)
1779 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1780 MIPS_SYS(sys_setregid , 2)
1781 MIPS_SYS(sys_sigsuspend , 0)
1782 MIPS_SYS(sys_sigpending , 1)
1783 MIPS_SYS(sys_sethostname , 2)
1784 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1785 MIPS_SYS(sys_getrlimit , 2)
1786 MIPS_SYS(sys_getrusage , 2)
1787 MIPS_SYS(sys_gettimeofday, 2)
1788 MIPS_SYS(sys_settimeofday, 2)
1789 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1790 MIPS_SYS(sys_setgroups , 2)
1791 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1792 MIPS_SYS(sys_symlink , 2)
1793 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1794 MIPS_SYS(sys_readlink , 3) /* 4085 */
1795 MIPS_SYS(sys_uselib , 1)
1796 MIPS_SYS(sys_swapon , 2)
1797 MIPS_SYS(sys_reboot , 3)
1798 MIPS_SYS(old_readdir , 3)
1799 MIPS_SYS(old_mmap , 6) /* 4090 */
1800 MIPS_SYS(sys_munmap , 2)
1801 MIPS_SYS(sys_truncate , 2)
1802 MIPS_SYS(sys_ftruncate , 2)
1803 MIPS_SYS(sys_fchmod , 2)
1804 MIPS_SYS(sys_fchown , 3) /* 4095 */
1805 MIPS_SYS(sys_getpriority , 2)
1806 MIPS_SYS(sys_setpriority , 3)
1807 MIPS_SYS(sys_ni_syscall , 0)
1808 MIPS_SYS(sys_statfs , 2)
1809 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1810 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1811 MIPS_SYS(sys_socketcall , 2)
1812 MIPS_SYS(sys_syslog , 3)
1813 MIPS_SYS(sys_setitimer , 3)
1814 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1815 MIPS_SYS(sys_newstat , 2)
1816 MIPS_SYS(sys_newlstat , 2)
1817 MIPS_SYS(sys_newfstat , 2)
1818 MIPS_SYS(sys_uname , 1)
1819 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1820 MIPS_SYS(sys_vhangup , 0)
1821 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1822 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1823 MIPS_SYS(sys_wait4 , 4)
1824 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1825 MIPS_SYS(sys_sysinfo , 1)
1826 MIPS_SYS(sys_ipc , 6)
1827 MIPS_SYS(sys_fsync , 1)
1828 MIPS_SYS(sys_sigreturn , 0)
1829 MIPS_SYS(sys_clone , 6) /* 4120 */
1830 MIPS_SYS(sys_setdomainname, 2)
1831 MIPS_SYS(sys_newuname , 1)
1832 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1833 MIPS_SYS(sys_adjtimex , 1)
1834 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1835 MIPS_SYS(sys_sigprocmask , 3)
1836 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1837 MIPS_SYS(sys_init_module , 5)
1838 MIPS_SYS(sys_delete_module, 1)
1839 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1840 MIPS_SYS(sys_quotactl , 0)
1841 MIPS_SYS(sys_getpgid , 1)
1842 MIPS_SYS(sys_fchdir , 1)
1843 MIPS_SYS(sys_bdflush , 2)
1844 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1845 MIPS_SYS(sys_personality , 1)
1846 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1847 MIPS_SYS(sys_setfsuid , 1)
1848 MIPS_SYS(sys_setfsgid , 1)
1849 MIPS_SYS(sys_llseek , 5) /* 4140 */
1850 MIPS_SYS(sys_getdents , 3)
1851 MIPS_SYS(sys_select , 5)
1852 MIPS_SYS(sys_flock , 2)
1853 MIPS_SYS(sys_msync , 3)
1854 MIPS_SYS(sys_readv , 3) /* 4145 */
1855 MIPS_SYS(sys_writev , 3)
1856 MIPS_SYS(sys_cacheflush , 3)
1857 MIPS_SYS(sys_cachectl , 3)
1858 MIPS_SYS(sys_sysmips , 4)
1859 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1860 MIPS_SYS(sys_getsid , 1)
1861 MIPS_SYS(sys_fdatasync , 0)
1862 MIPS_SYS(sys_sysctl , 1)
1863 MIPS_SYS(sys_mlock , 2)
1864 MIPS_SYS(sys_munlock , 2) /* 4155 */
1865 MIPS_SYS(sys_mlockall , 1)
1866 MIPS_SYS(sys_munlockall , 0)
1867 MIPS_SYS(sys_sched_setparam, 2)
1868 MIPS_SYS(sys_sched_getparam, 2)
1869 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1870 MIPS_SYS(sys_sched_getscheduler, 1)
1871 MIPS_SYS(sys_sched_yield , 0)
1872 MIPS_SYS(sys_sched_get_priority_max, 1)
1873 MIPS_SYS(sys_sched_get_priority_min, 1)
1874 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1875 MIPS_SYS(sys_nanosleep, 2)
1876 MIPS_SYS(sys_mremap , 5)
1877 MIPS_SYS(sys_accept , 3)
1878 MIPS_SYS(sys_bind , 3)
1879 MIPS_SYS(sys_connect , 3) /* 4170 */
1880 MIPS_SYS(sys_getpeername , 3)
1881 MIPS_SYS(sys_getsockname , 3)
1882 MIPS_SYS(sys_getsockopt , 5)
1883 MIPS_SYS(sys_listen , 2)
1884 MIPS_SYS(sys_recv , 4) /* 4175 */
1885 MIPS_SYS(sys_recvfrom , 6)
1886 MIPS_SYS(sys_recvmsg , 3)
1887 MIPS_SYS(sys_send , 4)
1888 MIPS_SYS(sys_sendmsg , 3)
1889 MIPS_SYS(sys_sendto , 6) /* 4180 */
1890 MIPS_SYS(sys_setsockopt , 5)
1891 MIPS_SYS(sys_shutdown , 2)
1892 MIPS_SYS(sys_socket , 3)
1893 MIPS_SYS(sys_socketpair , 4)
1894 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1895 MIPS_SYS(sys_getresuid , 3)
1896 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1897 MIPS_SYS(sys_poll , 3)
1898 MIPS_SYS(sys_nfsservctl , 3)
1899 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1900 MIPS_SYS(sys_getresgid , 3)
1901 MIPS_SYS(sys_prctl , 5)
1902 MIPS_SYS(sys_rt_sigreturn, 0)
1903 MIPS_SYS(sys_rt_sigaction, 4)
1904 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1905 MIPS_SYS(sys_rt_sigpending, 2)
1906 MIPS_SYS(sys_rt_sigtimedwait, 4)
1907 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1908 MIPS_SYS(sys_rt_sigsuspend, 0)
1909 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1910 MIPS_SYS(sys_pwrite64 , 6)
1911 MIPS_SYS(sys_chown , 3)
1912 MIPS_SYS(sys_getcwd , 2)
1913 MIPS_SYS(sys_capget , 2)
1914 MIPS_SYS(sys_capset , 2) /* 4205 */
1915 MIPS_SYS(sys_sigaltstack , 2)
1916 MIPS_SYS(sys_sendfile , 4)
1917 MIPS_SYS(sys_ni_syscall , 0)
1918 MIPS_SYS(sys_ni_syscall , 0)
1919 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1920 MIPS_SYS(sys_truncate64 , 4)
1921 MIPS_SYS(sys_ftruncate64 , 4)
1922 MIPS_SYS(sys_stat64 , 2)
1923 MIPS_SYS(sys_lstat64 , 2)
1924 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1925 MIPS_SYS(sys_pivot_root , 2)
1926 MIPS_SYS(sys_mincore , 3)
1927 MIPS_SYS(sys_madvise , 3)
1928 MIPS_SYS(sys_getdents64 , 3)
1929 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1930 MIPS_SYS(sys_ni_syscall , 0)
1931 MIPS_SYS(sys_gettid , 0)
1932 MIPS_SYS(sys_readahead , 5)
1933 MIPS_SYS(sys_setxattr , 5)
1934 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1935 MIPS_SYS(sys_fsetxattr , 5)
1936 MIPS_SYS(sys_getxattr , 4)
1937 MIPS_SYS(sys_lgetxattr , 4)
1938 MIPS_SYS(sys_fgetxattr , 4)
1939 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1940 MIPS_SYS(sys_llistxattr , 3)
1941 MIPS_SYS(sys_flistxattr , 3)
1942 MIPS_SYS(sys_removexattr , 2)
1943 MIPS_SYS(sys_lremovexattr, 2)
1944 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1945 MIPS_SYS(sys_tkill , 2)
1946 MIPS_SYS(sys_sendfile64 , 5)
1947 MIPS_SYS(sys_futex , 6)
1948 MIPS_SYS(sys_sched_setaffinity, 3)
1949 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1950 MIPS_SYS(sys_io_setup , 2)
1951 MIPS_SYS(sys_io_destroy , 1)
1952 MIPS_SYS(sys_io_getevents, 5)
1953 MIPS_SYS(sys_io_submit , 3)
1954 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1955 MIPS_SYS(sys_exit_group , 1)
1956 MIPS_SYS(sys_lookup_dcookie, 3)
1957 MIPS_SYS(sys_epoll_create, 1)
1958 MIPS_SYS(sys_epoll_ctl , 4)
1959 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1960 MIPS_SYS(sys_remap_file_pages, 5)
1961 MIPS_SYS(sys_set_tid_address, 1)
1962 MIPS_SYS(sys_restart_syscall, 0)
1963 MIPS_SYS(sys_fadvise64_64, 7)
1964 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1965 MIPS_SYS(sys_fstatfs64 , 2)
1966 MIPS_SYS(sys_timer_create, 3)
1967 MIPS_SYS(sys_timer_settime, 4)
1968 MIPS_SYS(sys_timer_gettime, 2)
1969 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1970 MIPS_SYS(sys_timer_delete, 1)
1971 MIPS_SYS(sys_clock_settime, 2)
1972 MIPS_SYS(sys_clock_gettime, 2)
1973 MIPS_SYS(sys_clock_getres, 2)
1974 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1975 MIPS_SYS(sys_tgkill , 3)
1976 MIPS_SYS(sys_utimes , 2)
1977 MIPS_SYS(sys_mbind , 4)
1978 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1979 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1980 MIPS_SYS(sys_mq_open , 4)
1981 MIPS_SYS(sys_mq_unlink , 1)
1982 MIPS_SYS(sys_mq_timedsend, 5)
1983 MIPS_SYS(sys_mq_timedreceive, 5)
1984 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1985 MIPS_SYS(sys_mq_getsetattr, 3)
1986 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1987 MIPS_SYS(sys_waitid , 4)
1988 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1989 MIPS_SYS(sys_add_key , 5)
1990 MIPS_SYS(sys_request_key, 4)
1991 MIPS_SYS(sys_keyctl , 5)
1992 MIPS_SYS(sys_set_thread_area, 1)
1993 MIPS_SYS(sys_inotify_init, 0)
1994 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1995 MIPS_SYS(sys_inotify_rm_watch, 2)
1996 MIPS_SYS(sys_migrate_pages, 4)
1997 MIPS_SYS(sys_openat, 4)
1998 MIPS_SYS(sys_mkdirat, 3)
1999 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2000 MIPS_SYS(sys_fchownat, 5)
2001 MIPS_SYS(sys_futimesat, 3)
2002 MIPS_SYS(sys_fstatat64, 4)
2003 MIPS_SYS(sys_unlinkat, 3)
2004 MIPS_SYS(sys_renameat, 4) /* 4295 */
2005 MIPS_SYS(sys_linkat, 5)
2006 MIPS_SYS(sys_symlinkat, 3)
2007 MIPS_SYS(sys_readlinkat, 4)
2008 MIPS_SYS(sys_fchmodat, 3)
2009 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2010 MIPS_SYS(sys_pselect6, 6)
2011 MIPS_SYS(sys_ppoll, 5)
2012 MIPS_SYS(sys_unshare, 1)
2013 MIPS_SYS(sys_splice, 6)
2014 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2015 MIPS_SYS(sys_tee, 4)
2016 MIPS_SYS(sys_vmsplice, 4)
2017 MIPS_SYS(sys_move_pages, 6)
2018 MIPS_SYS(sys_set_robust_list, 2)
2019 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2020 MIPS_SYS(sys_kexec_load, 4)
2021 MIPS_SYS(sys_getcpu, 3)
2022 MIPS_SYS(sys_epoll_pwait, 6)
2023 MIPS_SYS(sys_ioprio_set, 3)
2024 MIPS_SYS(sys_ioprio_get, 2)
2025 MIPS_SYS(sys_utimensat, 4)
2026 MIPS_SYS(sys_signalfd, 3)
2027 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2028 MIPS_SYS(sys_eventfd, 1)
2029 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2030 MIPS_SYS(sys_timerfd_create, 2)
2031 MIPS_SYS(sys_timerfd_gettime, 2)
2032 MIPS_SYS(sys_timerfd_settime, 4)
2033 MIPS_SYS(sys_signalfd4, 4)
2034 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2035 MIPS_SYS(sys_epoll_create1, 1)
2036 MIPS_SYS(sys_dup3, 3)
2037 MIPS_SYS(sys_pipe2, 2)
2038 MIPS_SYS(sys_inotify_init1, 1)
2039 MIPS_SYS(sys_preadv, 5) /* 4330 */
2040 MIPS_SYS(sys_pwritev, 5)
2041 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2042 MIPS_SYS(sys_perf_event_open, 5)
2043 MIPS_SYS(sys_accept4, 4)
2044 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2045 MIPS_SYS(sys_fanotify_init, 2)
2046 MIPS_SYS(sys_fanotify_mark, 6)
2047 MIPS_SYS(sys_prlimit64, 4)
2048 MIPS_SYS(sys_name_to_handle_at, 5)
2049 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2050 MIPS_SYS(sys_clock_adjtime, 2)
2051 MIPS_SYS(sys_syncfs, 1)
2052 MIPS_SYS(sys_sendmmsg, 4)
2053 MIPS_SYS(sys_setns, 2)
2054 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */
2055 MIPS_SYS(sys_process_vm_writev, 6)
2056 MIPS_SYS(sys_kcmp, 5)
2057 MIPS_SYS(sys_finit_module, 3)
2058 MIPS_SYS(sys_sched_setattr, 2)
2059 MIPS_SYS(sys_sched_getattr, 3) /* 350 */
2060 MIPS_SYS(sys_renameat2, 5)
2061 MIPS_SYS(sys_seccomp, 3)
2062 MIPS_SYS(sys_getrandom, 3)
2063 MIPS_SYS(sys_memfd_create, 2)
2064 MIPS_SYS(sys_bpf, 3) /* 355 */
2065 MIPS_SYS(sys_execveat, 5)
2066 MIPS_SYS(sys_userfaultfd, 1)
2067 MIPS_SYS(sys_membarrier, 2)
2068 MIPS_SYS(sys_mlock2, 3)
2069 MIPS_SYS(sys_copy_file_range, 6) /* 360 */
2070 MIPS_SYS(sys_preadv2, 6)
2071 MIPS_SYS(sys_pwritev2, 6)
2072 };
2073 # undef MIPS_SYS
2074 # endif /* O32 */
2075
2076 static int do_store_exclusive(CPUMIPSState *env)
2077 {
2078 target_ulong addr;
2079 target_ulong page_addr;
2080 target_ulong val;
2081 int flags;
2082 int segv = 0;
2083 int reg;
2084 int d;
2085
2086 addr = env->lladdr;
2087 page_addr = addr & TARGET_PAGE_MASK;
2088 start_exclusive();
2089 mmap_lock();
2090 flags = page_get_flags(page_addr);
2091 if ((flags & PAGE_READ) == 0) {
2092 segv = 1;
2093 } else {
2094 reg = env->llreg & 0x1f;
2095 d = (env->llreg & 0x20) != 0;
2096 if (d) {
2097 segv = get_user_s64(val, addr);
2098 } else {
2099 segv = get_user_s32(val, addr);
2100 }
2101 if (!segv) {
2102 if (val != env->llval) {
2103 env->active_tc.gpr[reg] = 0;
2104 } else {
2105 if (d) {
2106 segv = put_user_u64(env->llnewval, addr);
2107 } else {
2108 segv = put_user_u32(env->llnewval, addr);
2109 }
2110 if (!segv) {
2111 env->active_tc.gpr[reg] = 1;
2112 }
2113 }
2114 }
2115 }
2116 env->lladdr = -1;
2117 if (!segv) {
2118 env->active_tc.PC += 4;
2119 }
2120 mmap_unlock();
2121 end_exclusive();
2122 return segv;
2123 }
2124
2125 /* Break codes */
2126 enum {
2127 BRK_OVERFLOW = 6,
2128 BRK_DIVZERO = 7
2129 };
2130
2131 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2132 unsigned int code)
2133 {
2134 int ret = -1;
2135
2136 switch (code) {
2137 case BRK_OVERFLOW:
2138 case BRK_DIVZERO:
2139 info->si_signo = TARGET_SIGFPE;
2140 info->si_errno = 0;
2141 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2142 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2143 ret = 0;
2144 break;
2145 default:
2146 info->si_signo = TARGET_SIGTRAP;
2147 info->si_errno = 0;
2148 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2149 ret = 0;
2150 break;
2151 }
2152
2153 return ret;
2154 }
2155
2156 void cpu_loop(CPUMIPSState *env)
2157 {
2158 CPUState *cs = CPU(mips_env_get_cpu(env));
2159 target_siginfo_t info;
2160 int trapnr;
2161 abi_long ret;
2162 # ifdef TARGET_ABI_MIPSO32
2163 unsigned int syscall_num;
2164 # endif
2165
2166 for(;;) {
2167 cpu_exec_start(cs);
2168 trapnr = cpu_exec(cs);
2169 cpu_exec_end(cs);
2170 process_queued_cpu_work(cs);
2171
2172 switch(trapnr) {
2173 case EXCP_SYSCALL:
2174 env->active_tc.PC += 4;
2175 # ifdef TARGET_ABI_MIPSO32
2176 syscall_num = env->active_tc.gpr[2] - 4000;
2177 if (syscall_num >= sizeof(mips_syscall_args)) {
2178 ret = -TARGET_ENOSYS;
2179 } else {
2180 int nb_args;
2181 abi_ulong sp_reg;
2182 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2183
2184 nb_args = mips_syscall_args[syscall_num];
2185 sp_reg = env->active_tc.gpr[29];
2186 switch (nb_args) {
2187 /* these arguments are taken from the stack */
2188 case 8:
2189 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2190 goto done_syscall;
2191 }
2192 case 7:
2193 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2194 goto done_syscall;
2195 }
2196 case 6:
2197 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2198 goto done_syscall;
2199 }
2200 case 5:
2201 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2202 goto done_syscall;
2203 }
2204 default:
2205 break;
2206 }
2207 ret = do_syscall(env, env->active_tc.gpr[2],
2208 env->active_tc.gpr[4],
2209 env->active_tc.gpr[5],
2210 env->active_tc.gpr[6],
2211 env->active_tc.gpr[7],
2212 arg5, arg6, arg7, arg8);
2213 }
2214 done_syscall:
2215 # else
2216 ret = do_syscall(env, env->active_tc.gpr[2],
2217 env->active_tc.gpr[4], env->active_tc.gpr[5],
2218 env->active_tc.gpr[6], env->active_tc.gpr[7],
2219 env->active_tc.gpr[8], env->active_tc.gpr[9],
2220 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2221 # endif /* O32 */
2222 if (ret == -TARGET_ERESTARTSYS) {
2223 env->active_tc.PC -= 4;
2224 break;
2225 }
2226 if (ret == -TARGET_QEMU_ESIGRETURN) {
2227 /* Returning from a successful sigreturn syscall.
2228 Avoid clobbering register state. */
2229 break;
2230 }
2231 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2232 env->active_tc.gpr[7] = 1; /* error flag */
2233 ret = -ret;
2234 } else {
2235 env->active_tc.gpr[7] = 0; /* error flag */
2236 }
2237 env->active_tc.gpr[2] = ret;
2238 break;
2239 case EXCP_TLBL:
2240 case EXCP_TLBS:
2241 case EXCP_AdEL:
2242 case EXCP_AdES:
2243 info.si_signo = TARGET_SIGSEGV;
2244 info.si_errno = 0;
2245 /* XXX: check env->error_code */
2246 info.si_code = TARGET_SEGV_MAPERR;
2247 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2248 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2249 break;
2250 case EXCP_CpU:
2251 case EXCP_RI:
2252 info.si_signo = TARGET_SIGILL;
2253 info.si_errno = 0;
2254 info.si_code = 0;
2255 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2256 break;
2257 case EXCP_INTERRUPT:
2258 /* just indicate that signals should be handled asap */
2259 break;
2260 case EXCP_DEBUG:
2261 {
2262 int sig;
2263
2264 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2265 if (sig)
2266 {
2267 info.si_signo = sig;
2268 info.si_errno = 0;
2269 info.si_code = TARGET_TRAP_BRKPT;
2270 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2271 }
2272 }
2273 break;
2274 case EXCP_SC:
2275 if (do_store_exclusive(env)) {
2276 info.si_signo = TARGET_SIGSEGV;
2277 info.si_errno = 0;
2278 info.si_code = TARGET_SEGV_MAPERR;
2279 info._sifields._sigfault._addr = env->active_tc.PC;
2280 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2281 }
2282 break;
2283 case EXCP_DSPDIS:
2284 info.si_signo = TARGET_SIGILL;
2285 info.si_errno = 0;
2286 info.si_code = TARGET_ILL_ILLOPC;
2287 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2288 break;
2289 /* The code below was inspired by the MIPS Linux kernel trap
2290 * handling code in arch/mips/kernel/traps.c.
2291 */
2292 case EXCP_BREAK:
2293 {
2294 abi_ulong trap_instr;
2295 unsigned int code;
2296
2297 if (env->hflags & MIPS_HFLAG_M16) {
2298 if (env->insn_flags & ASE_MICROMIPS) {
2299 /* microMIPS mode */
2300 ret = get_user_u16(trap_instr, env->active_tc.PC);
2301 if (ret != 0) {
2302 goto error;
2303 }
2304
2305 if ((trap_instr >> 10) == 0x11) {
2306 /* 16-bit instruction */
2307 code = trap_instr & 0xf;
2308 } else {
2309 /* 32-bit instruction */
2310 abi_ulong instr_lo;
2311
2312 ret = get_user_u16(instr_lo,
2313 env->active_tc.PC + 2);
2314 if (ret != 0) {
2315 goto error;
2316 }
2317 trap_instr = (trap_instr << 16) | instr_lo;
2318 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2319 /* Unfortunately, microMIPS also suffers from
2320 the old assembler bug... */
2321 if (code >= (1 << 10)) {
2322 code >>= 10;
2323 }
2324 }
2325 } else {
2326 /* MIPS16e mode */
2327 ret = get_user_u16(trap_instr, env->active_tc.PC);
2328 if (ret != 0) {
2329 goto error;
2330 }
2331 code = (trap_instr >> 6) & 0x3f;
2332 }
2333 } else {
2334 ret = get_user_u32(trap_instr, env->active_tc.PC);
2335 if (ret != 0) {
2336 goto error;
2337 }
2338
2339 /* As described in the original Linux kernel code, the
2340 * below checks on 'code' are to work around an old
2341 * assembly bug.
2342 */
2343 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2344 if (code >= (1 << 10)) {
2345 code >>= 10;
2346 }
2347 }
2348
2349 if (do_break(env, &info, code) != 0) {
2350 goto error;
2351 }
2352 }
2353 break;
2354 case EXCP_TRAP:
2355 {
2356 abi_ulong trap_instr;
2357 unsigned int code = 0;
2358
2359 if (env->hflags & MIPS_HFLAG_M16) {
2360 /* microMIPS mode */
2361 abi_ulong instr[2];
2362
2363 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2364 get_user_u16(instr[1], env->active_tc.PC + 2);
2365
2366 trap_instr = (instr[0] << 16) | instr[1];
2367 } else {
2368 ret = get_user_u32(trap_instr, env->active_tc.PC);
2369 }
2370
2371 if (ret != 0) {
2372 goto error;
2373 }
2374
2375 /* The immediate versions don't provide a code. */
2376 if (!(trap_instr & 0xFC000000)) {
2377 if (env->hflags & MIPS_HFLAG_M16) {
2378 /* microMIPS mode */
2379 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2380 } else {
2381 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2382 }
2383 }
2384
2385 if (do_break(env, &info, code) != 0) {
2386 goto error;
2387 }
2388 }
2389 break;
2390 case EXCP_ATOMIC:
2391 cpu_exec_step_atomic(cs);
2392 break;
2393 default:
2394 error:
2395 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2396 abort();
2397 }
2398 process_pending_signals(env);
2399 }
2400 }
2401 #endif
2402
2403 #ifdef TARGET_NIOS2
2404
2405 void cpu_loop(CPUNios2State *env)
2406 {
2407 CPUState *cs = ENV_GET_CPU(env);
2408 Nios2CPU *cpu = NIOS2_CPU(cs);
2409 target_siginfo_t info;
2410 int trapnr, gdbsig, ret;
2411
2412 for (;;) {
2413 cpu_exec_start(cs);
2414 trapnr = cpu_exec(cs);
2415 cpu_exec_end(cs);
2416 gdbsig = 0;
2417
2418 switch (trapnr) {
2419 case EXCP_INTERRUPT:
2420 /* just indicate that signals should be handled asap */
2421 break;
2422 case EXCP_TRAP:
2423 if (env->regs[R_AT] == 0) {
2424 abi_long ret;
2425 qemu_log_mask(CPU_LOG_INT, "\nSyscall\n");
2426
2427 ret = do_syscall(env, env->regs[2],
2428 env->regs[4], env->regs[5], env->regs[6],
2429 env->regs[7], env->regs[8], env->regs[9],
2430 0, 0);
2431
2432 if (env->regs[2] == 0) { /* FIXME: syscall 0 workaround */
2433 ret = 0;
2434 }
2435
2436 env->regs[2] = abs(ret);
2437 /* Return value is 0..4096 */
2438 env->regs[7] = (ret > 0xfffffffffffff000ULL);
2439 env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
2440 env->regs[CR_STATUS] &= ~0x3;
2441 env->regs[R_EA] = env->regs[R_PC] + 4;
2442 env->regs[R_PC] += 4;
2443 break;
2444 } else {
2445 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2446
2447 env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
2448 env->regs[CR_STATUS] &= ~0x3;
2449 env->regs[R_EA] = env->regs[R_PC] + 4;
2450 env->regs[R_PC] = cpu->exception_addr;
2451
2452 gdbsig = TARGET_SIGTRAP;
2453 break;
2454 }
2455 case 0xaa:
2456 switch (env->regs[R_PC]) {
2457 /*case 0x1000:*/ /* TODO:__kuser_helper_version */
2458 case 0x1004: /* __kuser_cmpxchg */
2459 start_exclusive();
2460 if (env->regs[4] & 0x3) {
2461 goto kuser_fail;
2462 }
2463 ret = get_user_u32(env->regs[2], env->regs[4]);
2464 if (ret) {
2465 end_exclusive();
2466 goto kuser_fail;
2467 }
2468 env->regs[2] -= env->regs[5];
2469 if (env->regs[2] == 0) {
2470 put_user_u32(env->regs[6], env->regs[4]);
2471 }
2472 end_exclusive();
2473 env->regs[R_PC] = env->regs[R_RA];
2474 break;
2475 /*case 0x1040:*/ /* TODO:__kuser_sigtramp */
2476 default:
2477 ;
2478 kuser_fail:
2479 info.si_signo = TARGET_SIGSEGV;
2480 info.si_errno = 0;
2481 /* TODO: check env->error_code */
2482 info.si_code = TARGET_SEGV_MAPERR;
2483 info._sifields._sigfault._addr = env->regs[R_PC];
2484 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2485 }
2486 break;
2487 default:
2488 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2489 trapnr);
2490 gdbsig = TARGET_SIGILL;
2491 break;
2492 }
2493 if (gdbsig) {
2494 gdb_handlesig(cs, gdbsig);
2495 if (gdbsig != TARGET_SIGTRAP) {
2496 exit(EXIT_FAILURE);
2497 }
2498 }
2499
2500 process_pending_signals(env);
2501 }
2502 }
2503
2504 #endif /* TARGET_NIOS2 */
2505
2506 #ifdef TARGET_OPENRISC
2507
2508 void cpu_loop(CPUOpenRISCState *env)
2509 {
2510 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2511 int trapnr;
2512 abi_long ret;
2513 target_siginfo_t info;
2514
2515 for (;;) {
2516 cpu_exec_start(cs);
2517 trapnr = cpu_exec(cs);
2518 cpu_exec_end(cs);
2519 process_queued_cpu_work(cs);
2520
2521 switch (trapnr) {
2522 case EXCP_SYSCALL:
2523 env->pc += 4; /* 0xc00; */
2524 ret = do_syscall(env,
2525 cpu_get_gpr(env, 11), /* return value */
2526 cpu_get_gpr(env, 3), /* r3 - r7 are params */
2527 cpu_get_gpr(env, 4),
2528 cpu_get_gpr(env, 5),
2529 cpu_get_gpr(env, 6),
2530 cpu_get_gpr(env, 7),
2531 cpu_get_gpr(env, 8), 0, 0);
2532 if (ret == -TARGET_ERESTARTSYS) {
2533 env->pc -= 4;
2534 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2535 cpu_set_gpr(env, 11, ret);
2536 }
2537 break;
2538 case EXCP_DPF:
2539 case EXCP_IPF:
2540 case EXCP_RANGE:
2541 info.si_signo = TARGET_SIGSEGV;
2542 info.si_errno = 0;
2543 info.si_code = TARGET_SEGV_MAPERR;
2544 info._sifields._sigfault._addr = env->pc;
2545 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2546 break;
2547 case EXCP_ALIGN:
2548 info.si_signo = TARGET_SIGBUS;
2549 info.si_errno = 0;
2550 info.si_code = TARGET_BUS_ADRALN;
2551 info._sifields._sigfault._addr = env->pc;
2552 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2553 break;
2554 case EXCP_ILLEGAL:
2555 info.si_signo = TARGET_SIGILL;
2556 info.si_errno = 0;
2557 info.si_code = TARGET_ILL_ILLOPC;
2558 info._sifields._sigfault._addr = env->pc;
2559 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2560 break;
2561 case EXCP_FPE:
2562 info.si_signo = TARGET_SIGFPE;
2563 info.si_errno = 0;
2564 info.si_code = 0;
2565 info._sifields._sigfault._addr = env->pc;
2566 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2567 break;
2568 case EXCP_INTERRUPT:
2569 /* We processed the pending cpu work above. */
2570 break;
2571 case EXCP_DEBUG:
2572 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
2573 if (trapnr) {
2574 info.si_signo = trapnr;
2575 info.si_errno = 0;
2576 info.si_code = TARGET_TRAP_BRKPT;
2577 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2578 }
2579 break;
2580 case EXCP_ATOMIC:
2581 cpu_exec_step_atomic(cs);
2582 break;
2583 default:
2584 g_assert_not_reached();
2585 }
2586 process_pending_signals(env);
2587 }
2588 }
2589
2590 #endif /* TARGET_OPENRISC */
2591
2592 #ifdef TARGET_SH4
2593 void cpu_loop(CPUSH4State *env)
2594 {
2595 CPUState *cs = CPU(sh_env_get_cpu(env));
2596 int trapnr, ret;
2597 target_siginfo_t info;
2598
2599 while (1) {
2600 bool arch_interrupt = true;
2601
2602 cpu_exec_start(cs);
2603 trapnr = cpu_exec(cs);
2604 cpu_exec_end(cs);
2605 process_queued_cpu_work(cs);
2606
2607 switch (trapnr) {
2608 case 0x160:
2609 env->pc += 2;
2610 ret = do_syscall(env,
2611 env->gregs[3],
2612 env->gregs[4],
2613 env->gregs[5],
2614 env->gregs[6],
2615 env->gregs[7],
2616 env->gregs[0],
2617 env->gregs[1],
2618 0, 0);
2619 if (ret == -TARGET_ERESTARTSYS) {
2620 env->pc -= 2;
2621 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2622 env->gregs[0] = ret;
2623 }
2624 break;
2625 case EXCP_INTERRUPT:
2626 /* just indicate that signals should be handled asap */
2627 break;
2628 case EXCP_DEBUG:
2629 {
2630 int sig;
2631
2632 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2633 if (sig) {
2634 info.si_signo = sig;
2635 info.si_errno = 0;
2636 info.si_code = TARGET_TRAP_BRKPT;
2637 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2638 } else {
2639 arch_interrupt = false;
2640 }
2641 }
2642 break;
2643 case 0xa0:
2644 case 0xc0:
2645 info.si_signo = TARGET_SIGSEGV;
2646 info.si_errno = 0;
2647 info.si_code = TARGET_SEGV_MAPERR;
2648 info._sifields._sigfault._addr = env->tea;
2649 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2650 break;
2651 case EXCP_ATOMIC:
2652 cpu_exec_step_atomic(cs);
2653 arch_interrupt = false;
2654 break;
2655 default:
2656 printf ("Unhandled trap: 0x%x\n", trapnr);
2657 cpu_dump_state(cs, stderr, fprintf, 0);
2658 exit(EXIT_FAILURE);
2659 }
2660 process_pending_signals (env);
2661
2662 /* Most of the traps imply an exception or interrupt, which
2663 implies an REI instruction has been executed. Which means
2664 that LDST (aka LOK_ADDR) should be cleared. But there are
2665 a few exceptions for traps internal to QEMU. */
2666 if (arch_interrupt) {
2667 env->lock_addr = -1;
2668 }
2669 }
2670 }
2671 #endif
2672
2673 #ifdef TARGET_CRIS
2674 void cpu_loop(CPUCRISState *env)
2675 {
2676 CPUState *cs = CPU(cris_env_get_cpu(env));
2677 int trapnr, ret;
2678 target_siginfo_t info;
2679
2680 while (1) {
2681 cpu_exec_start(cs);
2682 trapnr = cpu_exec(cs);
2683 cpu_exec_end(cs);
2684 process_queued_cpu_work(cs);
2685
2686 switch (trapnr) {
2687 case 0xaa:
2688 {
2689 info.si_signo = TARGET_SIGSEGV;
2690 info.si_errno = 0;
2691 /* XXX: check env->error_code */
2692 info.si_code = TARGET_SEGV_MAPERR;
2693 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2694 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2695 }
2696 break;
2697 case EXCP_INTERRUPT:
2698 /* just indicate that signals should be handled asap */
2699 break;
2700 case EXCP_BREAK:
2701 ret = do_syscall(env,
2702 env->regs[9],
2703 env->regs[10],
2704 env->regs[11],
2705 env->regs[12],
2706 env->regs[13],
2707 env->pregs[7],
2708 env->pregs[11],
2709 0, 0);
2710 if (ret == -TARGET_ERESTARTSYS) {
2711 env->pc -= 2;
2712 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2713 env->regs[10] = ret;
2714 }
2715 break;
2716 case EXCP_DEBUG:
2717 {
2718 int sig;
2719
2720 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2721 if (sig)
2722 {
2723 info.si_signo = sig;
2724 info.si_errno = 0;
2725 info.si_code = TARGET_TRAP_BRKPT;
2726 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2727 }
2728 }
2729 break;
2730 case EXCP_ATOMIC:
2731 cpu_exec_step_atomic(cs);
2732 break;
2733 default:
2734 printf ("Unhandled trap: 0x%x\n", trapnr);
2735 cpu_dump_state(cs, stderr, fprintf, 0);
2736 exit(EXIT_FAILURE);
2737 }
2738 process_pending_signals (env);
2739 }
2740 }
2741 #endif
2742
2743 #ifdef TARGET_MICROBLAZE
2744 void cpu_loop(CPUMBState *env)
2745 {
2746 CPUState *cs = CPU(mb_env_get_cpu(env));
2747 int trapnr, ret;
2748 target_siginfo_t info;
2749
2750 while (1) {
2751 cpu_exec_start(cs);
2752 trapnr = cpu_exec(cs);
2753 cpu_exec_end(cs);
2754 process_queued_cpu_work(cs);
2755
2756 switch (trapnr) {
2757 case 0xaa:
2758 {
2759 info.si_signo = TARGET_SIGSEGV;
2760 info.si_errno = 0;
2761 /* XXX: check env->error_code */
2762 info.si_code = TARGET_SEGV_MAPERR;
2763 info._sifields._sigfault._addr = 0;
2764 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2765 }
2766 break;
2767 case EXCP_INTERRUPT:
2768 /* just indicate that signals should be handled asap */
2769 break;
2770 case EXCP_BREAK:
2771 /* Return address is 4 bytes after the call. */
2772 env->regs[14] += 4;
2773 env->sregs[SR_PC] = env->regs[14];
2774 ret = do_syscall(env,
2775 env->regs[12],
2776 env->regs[5],
2777 env->regs[6],
2778 env->regs[7],
2779 env->regs[8],
2780 env->regs[9],
2781 env->regs[10],
2782 0, 0);
2783 if (ret == -TARGET_ERESTARTSYS) {
2784 /* Wind back to before the syscall. */
2785 env->sregs[SR_PC] -= 4;
2786 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2787 env->regs[3] = ret;
2788 }
2789 /* All syscall exits result in guest r14 being equal to the
2790 * PC we return to, because the kernel syscall exit "rtbd" does
2791 * this. (This is true even for sigreturn(); note that r14 is
2792 * not a userspace-usable register, as the kernel may clobber it
2793 * at any point.)
2794 */
2795 env->regs[14] = env->sregs[SR_PC];
2796 break;
2797 case EXCP_HW_EXCP:
2798 env->regs[17] = env->sregs[SR_PC] + 4;
2799 if (env->iflags & D_FLAG) {
2800 env->sregs[SR_ESR] |= 1 << 12;
2801 env->sregs[SR_PC] -= 4;
2802 /* FIXME: if branch was immed, replay the imm as well. */
2803 }
2804
2805 env->iflags &= ~(IMM_FLAG | D_FLAG);
2806
2807 switch (env->sregs[SR_ESR] & 31) {
2808 case ESR_EC_DIVZERO:
2809 info.si_signo = TARGET_SIGFPE;
2810 info.si_errno = 0;
2811 info.si_code = TARGET_FPE_FLTDIV;
2812 info._sifields._sigfault._addr = 0;
2813 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2814 break;
2815 case ESR_EC_FPU:
2816 info.si_signo = TARGET_SIGFPE;
2817 info.si_errno = 0;
2818 if (env->sregs[SR_FSR] & FSR_IO) {
2819 info.si_code = TARGET_FPE_FLTINV;
2820 }
2821 if (env->sregs[SR_FSR] & FSR_DZ) {
2822 info.si_code = TARGET_FPE_FLTDIV;
2823 }
2824 info._sifields._sigfault._addr = 0;
2825 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2826 break;
2827 default:
2828 printf ("Unhandled hw-exception: 0x%x\n",
2829 env->sregs[SR_ESR] & ESR_EC_MASK);
2830 cpu_dump_state(cs, stderr, fprintf, 0);
2831 exit(EXIT_FAILURE);
2832 break;
2833 }
2834 break;
2835 case EXCP_DEBUG:
2836 {
2837 int sig;
2838
2839 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2840 if (sig)
2841 {
2842 info.si_signo = sig;
2843 info.si_errno = 0;
2844 info.si_code = TARGET_TRAP_BRKPT;
2845 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2846 }
2847 }
2848 break;
2849 case EXCP_ATOMIC:
2850 cpu_exec_step_atomic(cs);
2851 break;
2852 default:
2853 printf ("Unhandled trap: 0x%x\n", trapnr);
2854 cpu_dump_state(cs, stderr, fprintf, 0);
2855 exit(EXIT_FAILURE);
2856 }
2857 process_pending_signals (env);
2858 }
2859 }
2860 #endif
2861
2862 #ifdef TARGET_M68K
2863
2864 void cpu_loop(CPUM68KState *env)
2865 {
2866 CPUState *cs = CPU(m68k_env_get_cpu(env));
2867 int trapnr;
2868 unsigned int n;
2869 target_siginfo_t info;
2870 TaskState *ts = cs->opaque;
2871
2872 for(;;) {
2873 cpu_exec_start(cs);
2874 trapnr = cpu_exec(cs);
2875 cpu_exec_end(cs);
2876 process_queued_cpu_work(cs);
2877
2878 switch(trapnr) {
2879 case EXCP_ILLEGAL:
2880 {
2881 if (ts->sim_syscalls) {
2882 uint16_t nr;
2883 get_user_u16(nr, env->pc + 2);
2884 env->pc += 4;
2885 do_m68k_simcall(env, nr);
2886 } else {
2887 goto do_sigill;
2888 }
2889 }
2890 break;
2891 case EXCP_HALT_INSN:
2892 /* Semihosing syscall. */
2893 env->pc += 4;
2894 do_m68k_semihosting(env, env->dregs[0]);
2895 break;
2896 case EXCP_LINEA:
2897 case EXCP_LINEF:
2898 case EXCP_UNSUPPORTED:
2899 do_sigill:
2900 info.si_signo = TARGET_SIGILL;
2901 info.si_errno = 0;
2902 info.si_code = TARGET_ILL_ILLOPN;
2903 info._sifields._sigfault._addr = env->pc;
2904 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2905 break;
2906 case EXCP_CHK:
2907 info.si_signo = TARGET_SIGFPE;
2908 info.si_errno = 0;
2909 info.si_code = TARGET_FPE_INTOVF;
2910 info._sifields._sigfault._addr = env->pc;
2911 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2912 break;
2913 case EXCP_DIV0:
2914 info.si_signo = TARGET_SIGFPE;
2915 info.si_errno = 0;
2916 info.si_code = TARGET_FPE_INTDIV;
2917 info._sifields._sigfault._addr = env->pc;
2918 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2919 break;
2920 case EXCP_TRAP0:
2921 {
2922 abi_long ret;
2923 ts->sim_syscalls = 0;
2924 n = env->dregs[0];
2925 env->pc += 2;
2926 ret = do_syscall(env,
2927 n,
2928 env->dregs[1],
2929 env->dregs[2],
2930 env->dregs[3],
2931 env->dregs[4],
2932 env->dregs[5],
2933 env->aregs[0],
2934 0, 0);
2935 if (ret == -TARGET_ERESTARTSYS) {
2936 env->pc -= 2;
2937 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2938 env->dregs[0] = ret;
2939 }
2940 }
2941 break;
2942 case EXCP_INTERRUPT:
2943 /* just indicate that signals should be handled asap */
2944 break;
2945 case EXCP_ACCESS:
2946 {
2947 info.si_signo = TARGET_SIGSEGV;
2948 info.si_errno = 0;
2949 /* XXX: check env->error_code */
2950 info.si_code = TARGET_SEGV_MAPERR;
2951 info._sifields._sigfault._addr = env->mmu.ar;
2952 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2953 }
2954 break;
2955 case EXCP_DEBUG:
2956 {
2957 int sig;
2958
2959 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2960 if (sig)
2961 {
2962 info.si_signo = sig;
2963 info.si_errno = 0;
2964 info.si_code = TARGET_TRAP_BRKPT;
2965 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2966 }
2967 }
2968 break;
2969 case EXCP_ATOMIC:
2970 cpu_exec_step_atomic(cs);
2971 break;
2972 default:
2973 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2974 abort();
2975 }
2976 process_pending_signals(env);
2977 }
2978 }
2979 #endif /* TARGET_M68K */
2980
2981 #ifdef TARGET_ALPHA
2982 void cpu_loop(CPUAlphaState *env)
2983 {
2984 CPUState *cs = CPU(alpha_env_get_cpu(env));
2985 int trapnr;
2986 target_siginfo_t info;
2987 abi_long sysret;
2988
2989 while (1) {
2990 bool arch_interrupt = true;
2991
2992 cpu_exec_start(cs);
2993 trapnr = cpu_exec(cs);
2994 cpu_exec_end(cs);
2995 process_queued_cpu_work(cs);
2996
2997 switch (trapnr) {
2998 case EXCP_RESET:
2999 fprintf(stderr, "Reset requested. Exit\n");
3000 exit(EXIT_FAILURE);
3001 break;
3002 case EXCP_MCHK:
3003 fprintf(stderr, "Machine check exception. Exit\n");
3004 exit(EXIT_FAILURE);
3005 break;
3006 case EXCP_SMP_INTERRUPT:
3007 case EXCP_CLK_INTERRUPT:
3008 case EXCP_DEV_INTERRUPT:
3009 fprintf(stderr, "External interrupt. Exit\n");
3010 exit(EXIT_FAILURE);
3011 break;
3012 case EXCP_MMFAULT:
3013 info.si_signo = TARGET_SIGSEGV;
3014 info.si_errno = 0;
3015 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3016 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3017 info._sifields._sigfault._addr = env->trap_arg0;
3018 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3019 break;
3020 case EXCP_UNALIGN:
3021 info.si_signo = TARGET_SIGBUS;
3022 info.si_errno = 0;
3023 info.si_code = TARGET_BUS_ADRALN;
3024 info._sifields._sigfault._addr = env->trap_arg0;
3025 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3026 break;
3027 case EXCP_OPCDEC:
3028 do_sigill:
3029 info.si_signo = TARGET_SIGILL;
3030 info.si_errno = 0;
3031 info.si_code = TARGET_ILL_ILLOPC;
3032 info._sifields._sigfault._addr = env->pc;
3033 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3034 break;
3035 case EXCP_ARITH:
3036 info.si_signo = TARGET_SIGFPE;
3037 info.si_errno = 0;
3038 info.si_code = TARGET_FPE_FLTINV;
3039 info._sifields._sigfault._addr = env->pc;
3040 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3041 break;
3042 case EXCP_FEN:
3043 /* No-op. Linux simply re-enables the FPU. */
3044 break;
3045 case EXCP_CALL_PAL:
3046 switch (env->error_code) {
3047 case 0x80:
3048 /* BPT */
3049 info.si_signo = TARGET_SIGTRAP;
3050 info.si_errno = 0;
3051 info.si_code = TARGET_TRAP_BRKPT;
3052 info._sifields._sigfault._addr = env->pc;
3053 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3054 break;
3055 case 0x81:
3056 /* BUGCHK */
3057 info.si_signo = TARGET_SIGTRAP;
3058 info.si_errno = 0;
3059 info.si_code = 0;
3060 info._sifields._sigfault._addr = env->pc;
3061 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3062 break;
3063 case 0x83:
3064 /* CALLSYS */
3065 trapnr = env->ir[IR_V0];
3066 sysret = do_syscall(env, trapnr,
3067 env->ir[IR_A0], env->ir[IR_A1],
3068 env->ir[IR_A2], env->ir[IR_A3],
3069 env->ir[IR_A4], env->ir[IR_A5],
3070 0, 0);
3071 if (sysret == -TARGET_ERESTARTSYS) {
3072 env->pc -= 4;
3073 break;
3074 }
3075 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3076 break;
3077 }
3078 /* Syscall writes 0 to V0 to bypass error check, similar
3079 to how this is handled internal to Linux kernel.
3080 (Ab)use trapnr temporarily as boolean indicating error. */
3081 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3082 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3083 env->ir[IR_A3] = trapnr;
3084 break;
3085 case 0x86:
3086 /* IMB */
3087 /* ??? We can probably elide the code using page_unprotect
3088 that is checking for self-modifying code. Instead we
3089 could simply call tb_flush here. Until we work out the
3090 changes required to turn off the extra write protection,
3091 this can be a no-op. */
3092 break;
3093 case 0x9E:
3094 /* RDUNIQUE */
3095 /* Handled in the translator for usermode. */
3096 abort();
3097 case 0x9F:
3098 /* WRUNIQUE */
3099 /* Handled in the translator for usermode. */
3100 abort();
3101 case 0xAA:
3102 /* GENTRAP */
3103 info.si_signo = TARGET_SIGFPE;
3104 switch (env->ir[IR_A0]) {
3105 case TARGET_GEN_INTOVF:
3106 info.si_code = TARGET_FPE_INTOVF;
3107 break;
3108 case TARGET_GEN_INTDIV:
3109 info.si_code = TARGET_FPE_INTDIV;
3110 break;
3111 case TARGET_GEN_FLTOVF:
3112 info.si_code = TARGET_FPE_FLTOVF;
3113 break;
3114 case TARGET_GEN_FLTUND:
3115 info.si_code = TARGET_FPE_FLTUND;
3116 break;
3117 case TARGET_GEN_FLTINV:
3118 info.si_code = TARGET_FPE_FLTINV;
3119 break;
3120 case TARGET_GEN_FLTINE:
3121 info.si_code = TARGET_FPE_FLTRES;
3122 break;
3123 case TARGET_GEN_ROPRAND:
3124 info.si_code = 0;
3125 break;
3126 default:
3127 info.si_signo = TARGET_SIGTRAP;
3128 info.si_code = 0;
3129 break;
3130 }
3131 info.si_errno = 0;
3132 info._sifields._sigfault._addr = env->pc;
3133 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3134 break;
3135 default:
3136 goto do_sigill;
3137 }
3138 break;
3139 case EXCP_DEBUG:
3140 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3141 if (info.si_signo) {
3142 info.si_errno = 0;
3143 info.si_code = TARGET_TRAP_BRKPT;
3144 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3145 } else {
3146 arch_interrupt = false;
3147 }
3148 break;
3149 case EXCP_INTERRUPT:
3150 /* Just indicate that signals should be handled asap. */
3151 break;
3152 case EXCP_ATOMIC:
3153 cpu_exec_step_atomic(cs);
3154 arch_interrupt = false;
3155 break;
3156 default:
3157 printf ("Unhandled trap: 0x%x\n", trapnr);
3158 cpu_dump_state(cs, stderr, fprintf, 0);
3159 exit(EXIT_FAILURE);
3160 }
3161 process_pending_signals (env);
3162
3163 /* Most of the traps imply a transition through PALcode, which
3164 implies an REI instruction has been executed. Which means
3165 that RX and LOCK_ADDR should be cleared. But there are a
3166 few exceptions for traps internal to QEMU. */
3167 if (arch_interrupt) {
3168 env->flags &= ~ENV_FLAG_RX_FLAG;
3169 env->lock_addr = -1;
3170 }
3171 }
3172 }
3173 #endif /* TARGET_ALPHA */
3174
3175 #ifdef TARGET_S390X
3176
3177 /* s390x masks the fault address it reports in si_addr for SIGSEGV and SIGBUS */
3178 #define S390X_FAIL_ADDR_MASK -4096LL
3179
3180 void cpu_loop(CPUS390XState *env)
3181 {
3182 CPUState *cs = CPU(s390_env_get_cpu(env));
3183 int trapnr, n, sig;
3184 target_siginfo_t info;
3185 target_ulong addr;
3186 abi_long ret;
3187
3188 while (1) {
3189 cpu_exec_start(cs);
3190 trapnr = cpu_exec(cs);
3191 cpu_exec_end(cs);
3192 process_queued_cpu_work(cs);
3193
3194 switch (trapnr) {
3195 case EXCP_INTERRUPT:
3196 /* Just indicate that signals should be handled asap. */
3197 break;
3198
3199 case EXCP_SVC:
3200 n = env->int_svc_code;
3201 if (!n) {
3202 /* syscalls > 255 */
3203 n = env->regs[1];
3204 }
3205 env->psw.addr += env->int_svc_ilen;
3206 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3207 env->regs[4], env->regs[5],
3208 env->regs[6], env->regs[7], 0, 0);
3209 if (ret == -TARGET_ERESTARTSYS) {
3210 env->psw.addr -= env->int_svc_ilen;
3211 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3212 env->regs[2] = ret;
3213 }
3214 break;
3215
3216 case EXCP_DEBUG:
3217 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3218 if (sig) {
3219 n = TARGET_TRAP_BRKPT;
3220 goto do_signal_pc;
3221 }
3222 break;
3223 case EXCP_PGM:
3224 n = env->int_pgm_code;
3225 switch (n) {
3226 case PGM_OPERATION:
3227 case PGM_PRIVILEGED:
3228 sig = TARGET_SIGILL;
3229 n = TARGET_ILL_ILLOPC;
3230 goto do_signal_pc;
3231 case PGM_PROTECTION:
3232 case PGM_ADDRESSING:
3233 sig = TARGET_SIGSEGV;
3234 /* XXX: check env->error_code */
3235 n = TARGET_SEGV_MAPERR;
3236 addr = env->__excp_addr & S390X_FAIL_ADDR_MASK;
3237 goto do_signal;
3238 case PGM_EXECUTE:
3239 case PGM_SPECIFICATION:
3240 case PGM_SPECIAL_OP:
3241 case PGM_OPERAND:
3242 do_sigill_opn:
3243 sig = TARGET_SIGILL;
3244 n = TARGET_ILL_ILLOPN;
3245 goto do_signal_pc;
3246
3247 case PGM_FIXPT_OVERFLOW:
3248 sig = TARGET_SIGFPE;
3249 n = TARGET_FPE_INTOVF;
3250 goto do_signal_pc;
3251 case PGM_FIXPT_DIVIDE:
3252 sig = TARGET_SIGFPE;
3253 n = TARGET_FPE_INTDIV;
3254 goto do_signal_pc;
3255
3256 case PGM_DATA:
3257 n = (env->fpc >> 8) & 0xff;
3258 if (n == 0xff) {
3259 /* compare-and-trap */
3260 goto do_sigill_opn;
3261 } else {
3262 /* An IEEE exception, simulated or otherwise. */
3263 if (n & 0x80) {
3264 n = TARGET_FPE_FLTINV;
3265 } else if (n & 0x40) {
3266 n = TARGET_FPE_FLTDIV;
3267 } else if (n & 0x20) {
3268 n = TARGET_FPE_FLTOVF;
3269 } else if (n & 0x10) {
3270 n = TARGET_FPE_FLTUND;
3271 } else if (n & 0x08) {
3272 n = TARGET_FPE_FLTRES;
3273 } else {
3274 /* ??? Quantum exception; BFP, DFP error. */
3275 goto do_sigill_opn;
3276 }
3277 sig = TARGET_SIGFPE;
3278 goto do_signal_pc;
3279 }
3280
3281 default:
3282 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3283 cpu_dump_state(cs, stderr, fprintf, 0);
3284 exit(EXIT_FAILURE);
3285 }
3286 break;
3287
3288 do_signal_pc:
3289 addr = env->psw.addr;
3290 do_signal:
3291 info.si_signo = sig;
3292 info.si_errno = 0;
3293 info.si_code = n;
3294 info._sifields._sigfault._addr = addr;
3295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3296 break;
3297
3298 case EXCP_ATOMIC:
3299 cpu_exec_step_atomic(cs);
3300 break;
3301 default:
3302 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3303 cpu_dump_state(cs, stderr, fprintf, 0);
3304 exit(EXIT_FAILURE);
3305 }
3306 process_pending_signals (env);
3307 }
3308 }
3309
3310 #endif /* TARGET_S390X */
3311
3312 #ifdef TARGET_TILEGX
3313
3314 static void gen_sigill_reg(CPUTLGState *env)
3315 {
3316 target_siginfo_t info;
3317
3318 info.si_signo = TARGET_SIGILL;
3319 info.si_errno = 0;
3320 info.si_code = TARGET_ILL_PRVREG;
3321 info._sifields._sigfault._addr = env->pc;
3322 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3323 }
3324
3325 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3326 {
3327 target_siginfo_t info;
3328
3329 info.si_signo = signo;
3330 info.si_errno = 0;
3331 info._sifields._sigfault._addr = env->pc;
3332
3333 if (signo == TARGET_SIGSEGV) {
3334 /* The passed in sigcode is a dummy; check for a page mapping
3335 and pass either MAPERR or ACCERR. */
3336 target_ulong addr = env->excaddr;
3337 info._sifields._sigfault._addr = addr;
3338 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3339 sigcode = TARGET_SEGV_MAPERR;
3340 } else {
3341 sigcode = TARGET_SEGV_ACCERR;
3342 }
3343 }
3344 info.si_code = sigcode;
3345
3346 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3347 }
3348
3349 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3350 {
3351 env->excaddr = addr;
3352 do_signal(env, TARGET_SIGSEGV, 0);
3353 }
3354
3355 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3356 {
3357 if (unlikely(reg >= TILEGX_R_COUNT)) {
3358 switch (reg) {
3359 case TILEGX_R_SN:
3360 case TILEGX_R_ZERO:
3361 return;
3362 case TILEGX_R_IDN0:
3363 case TILEGX_R_IDN1:
3364 case TILEGX_R_UDN0:
3365 case TILEGX_R_UDN1:
3366 case TILEGX_R_UDN2:
3367 case TILEGX_R_UDN3:
3368 gen_sigill_reg(env);
3369 return;
3370 default:
3371 g_assert_not_reached();
3372 }
3373 }
3374 env->regs[reg] = val;
3375 }
3376
3377 /*
3378 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3379 * memory at the address held in the first source register. If the values are
3380 * not equal, then no memory operation is performed. If the values are equal,
3381 * the 8-byte quantity from the second source register is written into memory
3382 * at the address held in the first source register. In either case, the result
3383 * of the instruction is the value read from memory. The compare and write to
3384 * memory are atomic and thus can be used for synchronization purposes. This
3385 * instruction only operates for addresses aligned to a 8-byte boundary.
3386 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3387 *
3388 * Functional Description (64-bit)
3389 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3390 * rf[Dest] = memVal;
3391 * if (memVal == SPR[CmpValueSPR])
3392 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3393 *
3394 * Functional Description (32-bit)
3395 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3396 * rf[Dest] = memVal;
3397 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3398 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3399 *
3400 *
3401 * This function also processes exch and exch4 which need not process SPR.
3402 */
3403 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3404 {
3405 target_ulong addr;
3406 target_long val, sprval;
3407
3408 start_exclusive();
3409
3410 addr = env->atomic_srca;
3411 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3412 goto sigsegv_maperr;
3413 }
3414
3415 if (cmp) {
3416 if (quad) {
3417 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3418 } else {
3419 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3420 }
3421 }
3422
3423 if (!cmp || val == sprval) {
3424 target_long valb = env->atomic_srcb;
3425 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3426 goto sigsegv_maperr;
3427 }
3428 }
3429
3430 set_regval(env, env->atomic_dstr, val);
3431 end_exclusive();
3432 return;
3433
3434 sigsegv_maperr:
3435 end_exclusive();
3436 gen_sigsegv_maperr(env, addr);
3437 }
3438
3439 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3440 {
3441 int8_t write = 1;
3442 target_ulong addr;
3443 target_long val, valb;
3444
3445 start_exclusive();
3446
3447 addr = env->atomic_srca;
3448 valb = env->atomic_srcb;
3449 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3450 goto sigsegv_maperr;
3451 }
3452
3453 switch (trapnr) {
3454 case TILEGX_EXCP_OPCODE_FETCHADD:
3455 case TILEGX_EXCP_OPCODE_FETCHADD4:
3456 valb += val;
3457 break;
3458 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3459 valb += val;
3460 if (valb < 0) {
3461 write = 0;
3462 }
3463 break;
3464 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3465 valb += val;
3466 if ((int32_t)valb < 0) {
3467 write = 0;
3468 }
3469 break;
3470 case TILEGX_EXCP_OPCODE_FETCHAND:
3471 case TILEGX_EXCP_OPCODE_FETCHAND4:
3472 valb &= val;
3473 break;
3474 case TILEGX_EXCP_OPCODE_FETCHOR:
3475 case TILEGX_EXCP_OPCODE_FETCHOR4:
3476 valb |= val;
3477 break;
3478 default:
3479 g_assert_not_reached();
3480 }
3481
3482 if (write) {
3483 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3484 goto sigsegv_maperr;
3485 }
3486 }
3487
3488 set_regval(env, env->atomic_dstr, val);
3489 end_exclusive();
3490 return;
3491
3492 sigsegv_maperr:
3493 end_exclusive();
3494 gen_sigsegv_maperr(env, addr);
3495 }
3496
3497 void cpu_loop(CPUTLGState *env)
3498 {
3499 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3500 int trapnr;
3501
3502 while (1) {
3503 cpu_exec_start(cs);
3504 trapnr = cpu_exec(cs);
3505 cpu_exec_end(cs);
3506 process_queued_cpu_work(cs);
3507
3508 switch (trapnr) {
3509 case TILEGX_EXCP_SYSCALL:
3510 {
3511 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3512 env->regs[0], env->regs[1],
3513 env->regs[2], env->regs[3],
3514 env->regs[4], env->regs[5],
3515 env->regs[6], env->regs[7]);
3516 if (ret == -TARGET_ERESTARTSYS) {
3517 env->pc -= 8;
3518 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3519 env->regs[TILEGX_R_RE] = ret;
3520 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3521 }
3522 break;
3523 }
3524 case TILEGX_EXCP_OPCODE_EXCH:
3525 do_exch(env, true, false);
3526 break;
3527 case TILEGX_EXCP_OPCODE_EXCH4:
3528 do_exch(env, false, false);
3529 break;
3530 case TILEGX_EXCP_OPCODE_CMPEXCH:
3531 do_exch(env, true, true);
3532 break;
3533 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3534 do_exch(env, false, true);
3535 break;
3536 case TILEGX_EXCP_OPCODE_FETCHADD:
3537 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3538 case TILEGX_EXCP_OPCODE_FETCHAND:
3539 case TILEGX_EXCP_OPCODE_FETCHOR:
3540 do_fetch(env, trapnr, true);
3541 break;
3542 case TILEGX_EXCP_OPCODE_FETCHADD4:
3543 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3544 case TILEGX_EXCP_OPCODE_FETCHAND4:
3545 case TILEGX_EXCP_OPCODE_FETCHOR4:
3546 do_fetch(env, trapnr, false);
3547 break;
3548 case TILEGX_EXCP_SIGNAL:
3549 do_signal(env, env->signo, env->sigcode);
3550 break;
3551 case TILEGX_EXCP_REG_IDN_ACCESS:
3552 case TILEGX_EXCP_REG_UDN_ACCESS:
3553 gen_sigill_reg(env);
3554 break;
3555 case EXCP_ATOMIC:
3556 cpu_exec_step_atomic(cs);
3557 break;
3558 default:
3559 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3560 g_assert_not_reached();
3561 }
3562 process_pending_signals(env);
3563 }
3564 }
3565
3566 #endif
3567
3568 #ifdef TARGET_RISCV
3569
3570 void cpu_loop(CPURISCVState *env)
3571 {
3572 CPUState *cs = CPU(riscv_env_get_cpu(env));
3573 int trapnr, signum, sigcode;
3574 target_ulong sigaddr;
3575 target_ulong ret;
3576
3577 for (;;) {
3578 cpu_exec_start(cs);
3579 trapnr = cpu_exec(cs);
3580 cpu_exec_end(cs);
3581 process_queued_cpu_work(cs);
3582
3583 signum = 0;
3584 sigcode = 0;
3585 sigaddr = 0;
3586
3587 switch (trapnr) {
3588 case EXCP_INTERRUPT:
3589 /* just indicate that signals should be handled asap */
3590 break;
3591 case EXCP_ATOMIC:
3592 cpu_exec_step_atomic(cs);
3593 break;
3594 case RISCV_EXCP_U_ECALL:
3595 env->pc += 4;
3596 if (env->gpr[xA7] == TARGET_NR_arch_specific_syscall + 15) {
3597 /* riscv_flush_icache_syscall is a no-op in QEMU as
3598 self-modifying code is automatically detected */
3599 ret = 0;
3600 } else {
3601 ret = do_syscall(env,
3602 env->gpr[xA7],
3603 env->gpr[xA0],
3604 env->gpr[xA1],
3605 env->gpr[xA2],
3606 env->gpr[xA3],
3607 env->gpr[xA4],
3608 env->gpr[xA5],
3609 0, 0);
3610 }
3611 if (ret == -TARGET_ERESTARTSYS) {
3612 env->pc -= 4;
3613 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3614 env->gpr[xA0] = ret;
3615 }
3616 if (cs->singlestep_enabled) {
3617 goto gdbstep;
3618 }
3619 break;
3620 case RISCV_EXCP_ILLEGAL_INST:
3621 signum = TARGET_SIGILL;
3622 sigcode = TARGET_ILL_ILLOPC;
3623 break;
3624 case RISCV_EXCP_BREAKPOINT:
3625 signum = TARGET_SIGTRAP;
3626 sigcode = TARGET_TRAP_BRKPT;
3627 sigaddr = env->pc;
3628 break;
3629 case RISCV_EXCP_INST_PAGE_FAULT:
3630 case RISCV_EXCP_LOAD_PAGE_FAULT:
3631 case RISCV_EXCP_STORE_PAGE_FAULT:
3632 signum = TARGET_SIGSEGV;
3633 sigcode = TARGET_SEGV_MAPERR;
3634 break;
3635 case EXCP_DEBUG:
3636 gdbstep:
3637 signum = gdb_handlesig(cs, TARGET_SIGTRAP);
3638 sigcode = TARGET_TRAP_BRKPT;
3639 break;
3640 default:
3641 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
3642 trapnr);
3643 exit(EXIT_FAILURE);
3644 }
3645
3646 if (signum) {
3647 target_siginfo_t info = {
3648 .si_signo = signum,
3649 .si_errno = 0,
3650 .si_code = sigcode,
3651 ._sifields._sigfault._addr = sigaddr
3652 };
3653 queue_signal(env, info.si_signo, QEMU_SI_KILL, &info);
3654 }
3655
3656 process_pending_signals(env);
3657 }
3658 }
3659
3660 #endif /* TARGET_RISCV */
3661
3662 #ifdef TARGET_HPPA
3663
3664 static abi_ulong hppa_lws(CPUHPPAState *env)
3665 {
3666 uint32_t which = env->gr[20];
3667 abi_ulong addr = env->gr[26];
3668 abi_ulong old = env->gr[25];
3669 abi_ulong new = env->gr[24];
3670 abi_ulong size, ret;
3671
3672 switch (which) {
3673 default:
3674 return -TARGET_ENOSYS;
3675
3676 case 0: /* elf32 atomic 32bit cmpxchg */
3677 if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) {
3678 return -TARGET_EFAULT;
3679 }
3680 old = tswap32(old);
3681 new = tswap32(new);
3682 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3683 ret = tswap32(ret);
3684 break;
3685
3686 case 2: /* elf32 atomic "new" cmpxchg */
3687 size = env->gr[23];
3688 if (size >= 4) {
3689 return -TARGET_ENOSYS;
3690 }
3691 if (((addr | old | new) & ((1 << size) - 1))
3692 || !access_ok(VERIFY_WRITE, addr, 1 << size)
3693 || !access_ok(VERIFY_READ, old, 1 << size)
3694 || !access_ok(VERIFY_READ, new, 1 << size)) {
3695 return -TARGET_EFAULT;
3696 }
3697 /* Note that below we use host-endian loads so that the cmpxchg
3698 can be host-endian as well. */
3699 switch (size) {
3700 case 0:
3701 old = *(uint8_t *)g2h(old);
3702 new = *(uint8_t *)g2h(new);
3703 ret = atomic_cmpxchg((uint8_t *)g2h(addr), old, new);
3704 ret = ret != old;
3705 break;
3706 case 1:
3707 old = *(uint16_t *)g2h(old);
3708 new = *(uint16_t *)g2h(new);
3709 ret = atomic_cmpxchg((uint16_t *)g2h(addr), old, new);
3710 ret = ret != old;
3711 break;
3712 case 2:
3713 old = *(uint32_t *)g2h(old);
3714 new = *(uint32_t *)g2h(new);
3715 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3716 ret = ret != old;
3717 break;
3718 case 3:
3719 {
3720 uint64_t o64, n64, r64;
3721 o64 = *(uint64_t *)g2h(old);
3722 n64 = *(uint64_t *)g2h(new);
3723 #ifdef CONFIG_ATOMIC64
3724 r64 = atomic_cmpxchg__nocheck((uint64_t *)g2h(addr), o64, n64);
3725 ret = r64 != o64;
3726 #else
3727 start_exclusive();
3728 r64 = *(uint64_t *)g2h(addr);
3729 ret = 1;
3730 if (r64 == o64) {
3731 *(uint64_t *)g2h(addr) = n64;
3732 ret = 0;
3733 }
3734 end_exclusive();
3735 #endif
3736 }
3737 break;
3738 }
3739 break;
3740 }
3741
3742 env->gr[28] = ret;
3743 return 0;
3744 }
3745
3746 void cpu_loop(CPUHPPAState *env)
3747 {
3748 CPUState *cs = CPU(hppa_env_get_cpu(env));
3749 target_siginfo_t info;
3750 abi_ulong ret;
3751 int trapnr;
3752
3753 while (1) {
3754 cpu_exec_start(cs);
3755 trapnr = cpu_exec(cs);
3756 cpu_exec_end(cs);
3757 process_queued_cpu_work(cs);
3758
3759 switch (trapnr) {
3760 case EXCP_SYSCALL:
3761 ret = do_syscall(env, env->gr[20],
3762 env->gr[26], env->gr[25],
3763 env->gr[24], env->gr[23],
3764 env->gr[22], env->gr[21], 0, 0);
3765 switch (ret) {
3766 default:
3767 env->gr[28] = ret;
3768 /* We arrived here by faking the gateway page. Return. */
3769 env->iaoq_f = env->gr[31];
3770 env->iaoq_b = env->gr[31] + 4;
3771 break;
3772 case -TARGET_ERESTARTSYS:
3773 case -TARGET_QEMU_ESIGRETURN:
3774 break;
3775 }
3776 break;
3777 case EXCP_SYSCALL_LWS:
3778 env->gr[21] = hppa_lws(env);
3779 /* We arrived here by faking the gateway page. Return. */
3780 env->iaoq_f = env->gr[31];
3781 env->iaoq_b = env->gr[31] + 4;
3782 break;
3783 case EXCP_ITLB_MISS:
3784 case EXCP_DTLB_MISS:
3785 case EXCP_NA_ITLB_MISS:
3786 case EXCP_NA_DTLB_MISS:
3787 case EXCP_IMP:
3788 case EXCP_DMP:
3789 case EXCP_DMB:
3790 case EXCP_PAGE_REF:
3791 case EXCP_DMAR:
3792 case EXCP_DMPI:
3793 info.si_signo = TARGET_SIGSEGV;
3794 info.si_errno = 0;
3795 info.si_code = TARGET_SEGV_ACCERR;
3796 info._sifields._sigfault._addr = env->cr[CR_IOR];
3797 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3798 break;
3799 case EXCP_UNALIGN:
3800 info.si_signo = TARGET_SIGBUS;
3801 info.si_errno = 0;
3802 info.si_code = 0;
3803 info._sifields._sigfault._addr = env->cr[CR_IOR];
3804 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3805 break;
3806 case EXCP_ILL:
3807 case EXCP_PRIV_OPR:
3808 case EXCP_PRIV_REG:
3809 info.si_signo = TARGET_SIGILL;
3810 info.si_errno = 0;
3811 info.si_code = TARGET_ILL_ILLOPN;
3812 info._sifields._sigfault._addr = env->iaoq_f;
3813 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3814 break;
3815 case EXCP_OVERFLOW:
3816 case EXCP_COND:
3817 case EXCP_ASSIST:
3818 info.si_signo = TARGET_SIGFPE;
3819 info.si_errno = 0;
3820 info.si_code = 0;
3821 info._sifields._sigfault._addr = env->iaoq_f;
3822 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3823 break;
3824 case EXCP_DEBUG:
3825 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
3826 if (trapnr) {
3827 info.si_signo = trapnr;
3828 info.si_errno = 0;
3829 info.si_code = TARGET_TRAP_BRKPT;
3830 queue_signal(env, trapnr, QEMU_SI_FAULT, &info);
3831 }
3832 break;
3833 case EXCP_INTERRUPT:
3834 /* just indicate that signals should be handled asap */
3835 break;
3836 default:
3837 g_assert_not_reached();
3838 }
3839 process_pending_signals(env);
3840 }
3841 }
3842
3843 #endif /* TARGET_HPPA */
3844
3845 #ifdef TARGET_XTENSA
3846
3847 static void xtensa_rfw(CPUXtensaState *env)
3848 {
3849 xtensa_restore_owb(env);
3850 env->pc = env->sregs[EPC1];
3851 }
3852
3853 static void xtensa_rfwu(CPUXtensaState *env)
3854 {
3855 env->sregs[WINDOW_START] |= (1 << env->sregs[WINDOW_BASE]);
3856 xtensa_rfw(env);
3857 }
3858
3859 static void xtensa_rfwo(CPUXtensaState *env)
3860 {
3861 env->sregs[WINDOW_START] &= ~(1 << env->sregs[WINDOW_BASE]);
3862 xtensa_rfw(env);
3863 }
3864
3865 static void xtensa_overflow4(CPUXtensaState *env)
3866 {
3867 put_user_ual(env->regs[0], env->regs[5] - 16);
3868 put_user_ual(env->regs[1], env->regs[5] - 12);
3869 put_user_ual(env->regs[2], env->regs[5] - 8);
3870 put_user_ual(env->regs[3], env->regs[5] - 4);
3871 xtensa_rfwo(env);
3872 }
3873
3874 static void xtensa_underflow4(CPUXtensaState *env)
3875 {
3876 get_user_ual(env->regs[0], env->regs[5] - 16);
3877 get_user_ual(env->regs[1], env->regs[5] - 12);
3878 get_user_ual(env->regs[2], env->regs[5] - 8);
3879 get_user_ual(env->regs[3], env->regs[5] - 4);
3880 xtensa_rfwu(env);
3881 }
3882
3883 static void xtensa_overflow8(CPUXtensaState *env)
3884 {
3885 put_user_ual(env->regs[0], env->regs[9] - 16);
3886 get_user_ual(env->regs[0], env->regs[1] - 12);
3887 put_user_ual(env->regs[1], env->regs[9] - 12);
3888 put_user_ual(env->regs[2], env->regs[9] - 8);
3889 put_user_ual(env->regs[3], env->regs[9] - 4);
3890 put_user_ual(env->regs[4], env->regs[0] - 32);
3891 put_user_ual(env->regs[5], env->regs[0] - 28);
3892 put_user_ual(env->regs[6], env->regs[0] - 24);
3893 put_user_ual(env->regs[7], env->regs[0] - 20);
3894 xtensa_rfwo(env);
3895 }
3896
3897 static void xtensa_underflow8(CPUXtensaState *env)
3898 {
3899 get_user_ual(env->regs[0], env->regs[9] - 16);
3900 get_user_ual(env->regs[1], env->regs[9] - 12);
3901 get_user_ual(env->regs[2], env->regs[9] - 8);
3902 get_user_ual(env->regs[7], env->regs[1] - 12);
3903 get_user_ual(env->regs[3], env->regs[9] - 4);
3904 get_user_ual(env->regs[4], env->regs[7] - 32);
3905 get_user_ual(env->regs[5], env->regs[7] - 28);
3906 get_user_ual(env->regs[6], env->regs[7] - 24);
3907 get_user_ual(env->regs[7], env->regs[7] - 20);
3908 xtensa_rfwu(env);
3909 }
3910
3911 static void xtensa_overflow12(CPUXtensaState *env)
3912 {
3913 put_user_ual(env->regs[0], env->regs[13] - 16);
3914 get_user_ual(env->regs[0], env->regs[1] - 12);
3915 put_user_ual(env->regs[1], env->regs[13] - 12);
3916 put_user_ual(env->regs[2], env->regs[13] - 8);
3917 put_user_ual(env->regs[3], env->regs[13] - 4);
3918 put_user_ual(env->regs[4], env->regs[0] - 48);
3919 put_user_ual(env->regs[5], env->regs[0] - 44);
3920 put_user_ual(env->regs[6], env->regs[0] - 40);
3921 put_user_ual(env->regs[7], env->regs[0] - 36);
3922 put_user_ual(env->regs[8], env->regs[0] - 32);
3923 put_user_ual(env->regs[9], env->regs[0] - 28);
3924 put_user_ual(env->regs[10], env->regs[0] - 24);
3925 put_user_ual(env->regs[11], env->regs[0] - 20);
3926 xtensa_rfwo(env);
3927 }
3928
3929 static void xtensa_underflow12(CPUXtensaState *env)
3930 {
3931 get_user_ual(env->regs[0], env->regs[13] - 16);
3932 get_user_ual(env->regs[1], env->regs[13] - 12);
3933 get_user_ual(env->regs[2], env->regs[13] - 8);
3934 get_user_ual(env->regs[11], env->regs[1] - 12);
3935 get_user_ual(env->regs[3], env->regs[13] - 4);
3936 get_user_ual(env->regs[4], env->regs[11] - 48);
3937 get_user_ual(env->regs[5], env->regs[11] - 44);
3938 get_user_ual(env->regs[6], env->regs[11] - 40);
3939 get_user_ual(env->regs[7], env->regs[11] - 36);
3940 get_user_ual(env->regs[8], env->regs[11] - 32);
3941 get_user_ual(env->regs[9], env->regs[11] - 28);
3942 get_user_ual(env->regs[10], env->regs[11] - 24);
3943 get_user_ual(env->regs[11], env->regs[11] - 20);
3944 xtensa_rfwu(env);
3945 }
3946
3947 void cpu_loop(CPUXtensaState *env)
3948 {
3949 CPUState *cs = CPU(xtensa_env_get_cpu(env));
3950 target_siginfo_t info;
3951 abi_ulong ret;
3952 int trapnr;
3953
3954 while (1) {
3955 cpu_exec_start(cs);
3956 trapnr = cpu_exec(cs);
3957 cpu_exec_end(cs);
3958 process_queued_cpu_work(cs);
3959
3960 env->sregs[PS] &= ~PS_EXCM;
3961 switch (trapnr) {
3962 case EXCP_INTERRUPT:
3963 break;
3964
3965 case EXC_WINDOW_OVERFLOW4:
3966 xtensa_overflow4(env);
3967 break;
3968 case EXC_WINDOW_UNDERFLOW4:
3969 xtensa_underflow4(env);
3970 break;
3971 case EXC_WINDOW_OVERFLOW8:
3972 xtensa_overflow8(env);
3973 break;
3974 case EXC_WINDOW_UNDERFLOW8:
3975 xtensa_underflow8(env);
3976 break;
3977 case EXC_WINDOW_OVERFLOW12:
3978 xtensa_overflow12(env);
3979 break;
3980 case EXC_WINDOW_UNDERFLOW12:
3981 xtensa_underflow12(env);
3982 break;
3983
3984 case EXC_USER:
3985 switch (env->sregs[EXCCAUSE]) {
3986 case ILLEGAL_INSTRUCTION_CAUSE:
3987 case PRIVILEGED_CAUSE:
3988 info.si_signo = TARGET_SIGILL;
3989 info.si_errno = 0;
3990 info.si_code =
3991 env->sregs[EXCCAUSE] == ILLEGAL_INSTRUCTION_CAUSE ?
3992 TARGET_ILL_ILLOPC : TARGET_ILL_PRVOPC;
3993 info._sifields._sigfault._addr = env->sregs[EPC1];
3994 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3995 break;
3996
3997 case SYSCALL_CAUSE:
3998 env->pc += 3;
3999 ret = do_syscall(env, env->regs[2],
4000 env->regs[6], env->regs[3],
4001 env->regs[4], env->regs[5],
4002 env->regs[8], env->regs[9], 0, 0);
4003 switch (ret) {
4004 default:
4005 env->regs[2] = ret;
4006 break;
4007
4008 case -TARGET_ERESTARTSYS:
4009 env->pc -= 3;
4010 break;
4011
4012 case -TARGET_QEMU_ESIGRETURN:
4013 break;
4014 }
4015 break;
4016
4017 case ALLOCA_CAUSE:
4018 env->sregs[PS] = deposit32(env->sregs[PS],
4019 PS_OWB_SHIFT,
4020 PS_OWB_LEN,
4021 env->sregs[WINDOW_BASE]);
4022
4023 switch (env->regs[0] & 0xc0000000) {
4024 case 0x00000000:
4025 case 0x40000000:
4026 xtensa_rotate_window(env, -1);
4027 xtensa_underflow4(env);
4028 break;
4029
4030 case 0x80000000:
4031 xtensa_rotate_window(env, -2);
4032 xtensa_underflow8(env);
4033 break;
4034
4035 case 0xc0000000:
4036 xtensa_rotate_window(env, -3);
4037 xtensa_underflow12(env);
4038 break;
4039 }
4040 break;
4041
4042 case INTEGER_DIVIDE_BY_ZERO_CAUSE:
4043 info.si_signo = TARGET_SIGFPE;
4044 info.si_errno = 0;
4045 info.si_code = TARGET_FPE_INTDIV;
4046 info._sifields._sigfault._addr = env->sregs[EPC1];
4047 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
4048 break;
4049
4050 case LOAD_PROHIBITED_CAUSE:
4051 case STORE_PROHIBITED_CAUSE:
4052 info.si_signo = TARGET_SIGSEGV;
4053 info.si_errno = 0;
4054 info.si_code = TARGET_SEGV_ACCERR;
4055 info._sifields._sigfault._addr = env->sregs[EXCVADDR];
4056 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
4057 break;
4058
4059 default:
4060 fprintf(stderr, "exccause = %d\n", env->sregs[EXCCAUSE]);
4061 g_assert_not_reached();
4062 }
4063 break;
4064 case EXCP_DEBUG:
4065 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
4066 if (trapnr) {
4067 info.si_signo = trapnr;
4068 info.si_errno = 0;
4069 info.si_code = TARGET_TRAP_BRKPT;
4070 queue_signal(env, trapnr, QEMU_SI_FAULT, &info);
4071 }
4072 break;
4073 case EXC_DEBUG:
4074 default:
4075 fprintf(stderr, "trapnr = %d\n", trapnr);
4076 g_assert_not_reached();
4077 }
4078 process_pending_signals(env);
4079 }
4080 }
4081
4082 #endif /* TARGET_XTENSA */
4083
4084 __thread CPUState *thread_cpu;
4085
4086 bool qemu_cpu_is_self(CPUState *cpu)
4087 {
4088 return thread_cpu == cpu;
4089 }
4090
4091 void qemu_cpu_kick(CPUState *cpu)
4092 {
4093 cpu_exit(cpu);
4094 }
4095
4096 void task_settid(TaskState *ts)
4097 {
4098 if (ts->ts_tid == 0) {
4099 ts->ts_tid = (pid_t)syscall(SYS_gettid);
4100 }
4101 }
4102
4103 void stop_all_tasks(void)
4104 {
4105 /*
4106 * We trust that when using NPTL, start_exclusive()
4107 * handles thread stopping correctly.
4108 */
4109 start_exclusive();
4110 }
4111
4112 /* Assumes contents are already zeroed. */
4113 void init_task_state(TaskState *ts)
4114 {
4115 ts->used = 1;
4116 }
4117
4118 CPUArchState *cpu_copy(CPUArchState *env)
4119 {
4120 CPUState *cpu = ENV_GET_CPU(env);
4121 CPUState *new_cpu = cpu_create(cpu_type);
4122 CPUArchState *new_env = new_cpu->env_ptr;
4123 CPUBreakpoint *bp;
4124 CPUWatchpoint *wp;
4125
4126 /* Reset non arch specific state */
4127 cpu_reset(new_cpu);
4128
4129 memcpy(new_env, env, sizeof(CPUArchState));
4130
4131 /* Clone all break/watchpoints.
4132 Note: Once we support ptrace with hw-debug register access, make sure
4133 BP_CPU break/watchpoints are handled correctly on clone. */
4134 QTAILQ_INIT(&new_cpu->breakpoints);
4135 QTAILQ_INIT(&new_cpu->watchpoints);
4136 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
4137 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
4138 }
4139 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
4140 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
4141 }
4142
4143 return new_env;
4144 }
4145
4146 static void handle_arg_help(const char *arg)
4147 {
4148 usage(EXIT_SUCCESS);
4149 }
4150
4151 static void handle_arg_log(const char *arg)
4152 {
4153 int mask;
4154
4155 mask = qemu_str_to_log_mask(arg);
4156 if (!mask) {
4157 qemu_print_log_usage(stdout);
4158 exit(EXIT_FAILURE);
4159 }
4160 qemu_log_needs_buffers();
4161 qemu_set_log(mask);
4162 }
4163
4164 static void handle_arg_dfilter(const char *arg)
4165 {
4166 qemu_set_dfilter_ranges(arg, NULL);
4167 }
4168
4169 static void handle_arg_log_filename(const char *arg)
4170 {
4171 qemu_set_log_filename(arg, &error_fatal);
4172 }
4173
4174 static void handle_arg_set_env(const char *arg)
4175 {
4176 char *r, *p, *token;
4177 r = p = strdup(arg);
4178 while ((token = strsep(&p, ",")) != NULL) {
4179 if (envlist_setenv(envlist, token) != 0) {
4180 usage(EXIT_FAILURE);
4181 }
4182 }
4183 free(r);
4184 }
4185
4186 static void handle_arg_unset_env(const char *arg)
4187 {
4188 char *r, *p, *token;
4189 r = p = strdup(arg);
4190 while ((token = strsep(&p, ",")) != NULL) {
4191 if (envlist_unsetenv(envlist, token) != 0) {
4192 usage(EXIT_FAILURE);
4193 }
4194 }
4195 free(r);
4196 }
4197
4198 static void handle_arg_argv0(const char *arg)
4199 {
4200 argv0 = strdup(arg);
4201 }
4202
4203 static void handle_arg_stack_size(const char *arg)
4204 {
4205 char *p;
4206 guest_stack_size = strtoul(arg, &p, 0);
4207 if (guest_stack_size == 0) {
4208 usage(EXIT_FAILURE);
4209 }
4210
4211 if (*p == 'M') {
4212 guest_stack_size *= 1024 * 1024;
4213 } else if (*p == 'k' || *p == 'K') {
4214 guest_stack_size *= 1024;
4215 }
4216 }
4217
4218 static void handle_arg_ld_prefix(const char *arg)
4219 {
4220 interp_prefix = strdup(arg);
4221 }
4222
4223 static void handle_arg_pagesize(const char *arg)
4224 {
4225 qemu_host_page_size = atoi(arg);
4226 if (qemu_host_page_size == 0 ||
4227 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
4228 fprintf(stderr, "page size must be a power of two\n");
4229 exit(EXIT_FAILURE);
4230 }
4231 }
4232
4233 static void handle_arg_randseed(const char *arg)
4234 {
4235 unsigned long long seed;
4236
4237 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
4238 fprintf(stderr, "Invalid seed number: %s\n", arg);
4239 exit(EXIT_FAILURE);
4240 }
4241 srand(seed);
4242 }
4243
4244 static void handle_arg_gdb(const char *arg)
4245 {
4246 gdbstub_port = atoi(arg);
4247 }
4248
4249 static void handle_arg_uname(const char *arg)
4250 {
4251 qemu_uname_release = strdup(arg);
4252 }
4253
4254 static void handle_arg_cpu(const char *arg)
4255 {
4256 cpu_model = strdup(arg);
4257 if (cpu_model == NULL || is_help_option(cpu_model)) {
4258 /* XXX: implement xxx_cpu_list for targets that still miss it */
4259 #if defined(cpu_list)
4260 cpu_list(stdout, &fprintf);
4261 #endif
4262 exit(EXIT_FAILURE);
4263 }
4264 }
4265
4266 static void handle_arg_guest_base(const char *arg)
4267 {
4268 guest_base = strtol(arg, NULL, 0);
4269 have_guest_base = 1;
4270 }
4271
4272 static void handle_arg_reserved_va(const char *arg)
4273 {
4274 char *p;
4275 int shift = 0;
4276 reserved_va = strtoul(arg, &p, 0);
4277 switch (*p) {
4278 case 'k':
4279 case 'K':
4280 shift = 10;
4281 break;
4282 case 'M':
4283 shift = 20;
4284 break;
4285 case 'G':
4286 shift = 30;
4287 break;
4288 }
4289 if (shift) {
4290 unsigned long unshifted = reserved_va;
4291 p++;
4292 reserved_va <<= shift;
4293 if (reserved_va >> shift != unshifted
4294 || (MAX_RESERVED_VA && reserved_va > MAX_RESERVED_VA)) {
4295 fprintf(stderr, "Reserved virtual address too big\n");
4296 exit(EXIT_FAILURE);
4297 }
4298 }
4299 if (*p) {
4300 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
4301 exit(EXIT_FAILURE);
4302 }
4303 }
4304
4305 static void handle_arg_singlestep(const char *arg)
4306 {
4307 singlestep = 1;
4308 }
4309
4310 static void handle_arg_strace(const char *arg)
4311 {
4312 do_strace = 1;
4313 }
4314
4315 static void handle_arg_version(const char *arg)
4316 {
4317 printf("qemu-" TARGET_NAME " version " QEMU_FULL_VERSION
4318 "\n" QEMU_COPYRIGHT "\n");
4319 exit(EXIT_SUCCESS);
4320 }
4321
4322 static char *trace_file;
4323 static void handle_arg_trace(const char *arg)
4324 {
4325 g_free(trace_file);
4326 trace_file = trace_opt_parse(arg);
4327 }
4328
4329 struct qemu_argument {
4330 const char *argv;
4331 const char *env;
4332 bool has_arg;
4333 void (*handle_opt)(const char *arg);
4334 const char *example;
4335 const char *help;
4336 };
4337
4338 static const struct qemu_argument arg_table[] = {
4339 {"h", "", false, handle_arg_help,
4340 "", "print this help"},
4341 {"help", "", false, handle_arg_help,
4342 "", ""},
4343 {"g", "QEMU_GDB", true, handle_arg_gdb,
4344 "port", "wait gdb connection to 'port'"},
4345 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4346 "path", "set the elf interpreter prefix to 'path'"},
4347 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4348 "size", "set the stack size to 'size' bytes"},
4349 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
4350 "model", "select CPU (-cpu help for list)"},
4351 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4352 "var=value", "sets targets environment variable (see below)"},
4353 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4354 "var", "unsets targets environment variable (see below)"},
4355 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4356 "argv0", "forces target process argv[0] to be 'argv0'"},
4357 {"r", "QEMU_UNAME", true, handle_arg_uname,
4358 "uname", "set qemu uname release string to 'uname'"},
4359 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4360 "address", "set guest_base address to 'address'"},
4361 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4362 "size", "reserve 'size' bytes for guest virtual address space"},
4363 {"d", "QEMU_LOG", true, handle_arg_log,
4364 "item[,...]", "enable logging of specified items "
4365 "(use '-d help' for a list of items)"},
4366 {"dfilter", "QEMU_DFILTER", true, handle_arg_dfilter,
4367 "range[,...]","filter logging based on address range"},
4368 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
4369 "logfile", "write logs to 'logfile' (default stderr)"},
4370 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4371 "pagesize", "set the host page size to 'pagesize'"},
4372 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4373 "", "run in singlestep mode"},
4374 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4375 "", "log system calls"},
4376 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4377 "", "Seed for pseudo-random number generator"},
4378 {"trace", "QEMU_TRACE", true, handle_arg_trace,
4379 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
4380 {"version", "QEMU_VERSION", false, handle_arg_version,
4381 "", "display version information and exit"},
4382 {NULL, NULL, false, NULL, NULL, NULL}
4383 };
4384
4385 static void usage(int exitcode)
4386 {
4387 const struct qemu_argument *arginfo;
4388 int maxarglen;
4389 int maxenvlen;
4390
4391 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4392 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
4393 "\n"
4394 "Options and associated environment variables:\n"
4395 "\n");
4396
4397 /* Calculate column widths. We must always have at least enough space
4398 * for the column header.
4399 */
4400 maxarglen = strlen("Argument");
4401 maxenvlen = strlen("Env-variable");
4402
4403 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4404 int arglen = strlen(arginfo->argv);
4405 if (arginfo->has_arg) {
4406 arglen += strlen(arginfo->example) + 1;
4407 }
4408 if (strlen(arginfo->env) > maxenvlen) {
4409 maxenvlen = strlen(arginfo->env);
4410 }
4411 if (arglen > maxarglen) {
4412 maxarglen = arglen;
4413 }
4414 }
4415
4416 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4417 maxenvlen, "Env-variable");
4418
4419 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4420 if (arginfo->has_arg) {
4421 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4422 (int)(maxarglen - strlen(arginfo->argv) - 1),
4423 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4424 } else {
4425 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4426 maxenvlen, arginfo->env,
4427 arginfo->help);
4428 }
4429 }
4430
4431 printf("\n"
4432 "Defaults:\n"
4433 "QEMU_LD_PREFIX = %s\n"
4434 "QEMU_STACK_SIZE = %ld byte\n",
4435 interp_prefix,
4436 guest_stack_size);
4437
4438 printf("\n"
4439 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4440 "QEMU_UNSET_ENV environment variables to set and unset\n"
4441 "environment variables for the target process.\n"
4442 "It is possible to provide several variables by separating them\n"
4443 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4444 "provide the -E and -U options multiple times.\n"
4445 "The following lines are equivalent:\n"
4446 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4447 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4448 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4449 "Note that if you provide several changes to a single variable\n"
4450 "the last change will stay in effect.\n"
4451 "\n"
4452 QEMU_HELP_BOTTOM "\n");
4453
4454 exit(exitcode);
4455 }
4456
4457 static int parse_args(int argc, char **argv)
4458 {
4459 const char *r;
4460 int optind;
4461 const struct qemu_argument *arginfo;
4462
4463 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4464 if (arginfo->env == NULL) {
4465 continue;
4466 }
4467
4468 r = getenv(arginfo->env);
4469 if (r != NULL) {
4470 arginfo->handle_opt(r);
4471 }
4472 }
4473
4474 optind = 1;
4475 for (;;) {
4476 if (optind >= argc) {
4477 break;
4478 }
4479 r = argv[optind];
4480 if (r[0] != '-') {
4481 break;
4482 }
4483 optind++;
4484 r++;
4485 if (!strcmp(r, "-")) {
4486 break;
4487 }
4488 /* Treat --foo the same as -foo. */
4489 if (r[0] == '-') {
4490 r++;
4491 }
4492
4493 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4494 if (!strcmp(r, arginfo->argv)) {
4495 if (arginfo->has_arg) {
4496 if (optind >= argc) {
4497 (void) fprintf(stderr,
4498 "qemu: missing argument for option '%s'\n", r);
4499 exit(EXIT_FAILURE);
4500 }
4501 arginfo->handle_opt(argv[optind]);
4502 optind++;
4503 } else {
4504 arginfo->handle_opt(NULL);
4505 }
4506 break;
4507 }
4508 }
4509
4510 /* no option matched the current argv */
4511 if (arginfo->handle_opt == NULL) {
4512 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4513 exit(EXIT_FAILURE);
4514 }
4515 }
4516
4517 if (optind >= argc) {
4518 (void) fprintf(stderr, "qemu: no user program specified\n");
4519 exit(EXIT_FAILURE);
4520 }
4521
4522 filename = argv[optind];
4523 exec_path = argv[optind];
4524
4525 return optind;
4526 }
4527
4528 int main(int argc, char **argv, char **envp)
4529 {
4530 struct target_pt_regs regs1, *regs = &regs1;
4531 struct image_info info1, *info = &info1;
4532 struct linux_binprm bprm;
4533 TaskState *ts;
4534 CPUArchState *env;
4535 CPUState *cpu;
4536 int optind;
4537 char **target_environ, **wrk;
4538 char **target_argv;
4539 int target_argc;
4540 int i;
4541 int ret;
4542 int execfd;
4543
4544 module_call_init(MODULE_INIT_TRACE);
4545 qemu_init_cpu_list();
4546 module_call_init(MODULE_INIT_QOM);
4547
4548 envlist = envlist_create();
4549
4550 /* add current environment into the list */
4551 for (wrk = environ; *wrk != NULL; wrk++) {
4552 (void) envlist_setenv(envlist, *wrk);
4553 }
4554
4555 /* Read the stack limit from the kernel. If it's "unlimited",
4556 then we can do little else besides use the default. */
4557 {
4558 struct rlimit lim;
4559 if (getrlimit(RLIMIT_STACK, &lim) == 0
4560 && lim.rlim_cur != RLIM_INFINITY
4561 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4562 guest_stack_size = lim.rlim_cur;
4563 }
4564 }
4565
4566 cpu_model = NULL;
4567
4568 srand(time(NULL));
4569
4570 qemu_add_opts(&qemu_trace_opts);
4571
4572 optind = parse_args(argc, argv);
4573
4574 if (!trace_init_backends()) {
4575 exit(1);
4576 }
4577 trace_init_file(trace_file);
4578
4579 /* Zero out regs */
4580 memset(regs, 0, sizeof(struct target_pt_regs));
4581
4582 /* Zero out image_info */
4583 memset(info, 0, sizeof(struct image_info));
4584
4585 memset(&bprm, 0, sizeof (bprm));
4586
4587 /* Scan interp_prefix dir for replacement files. */
4588 init_paths(interp_prefix);
4589
4590 init_qemu_uname_release();
4591
4592 execfd = qemu_getauxval(AT_EXECFD);
4593 if (execfd == 0) {
4594 execfd = open(filename, O_RDONLY);
4595 if (execfd < 0) {
4596 printf("Error while loading %s: %s\n", filename, strerror(errno));
4597 _exit(EXIT_FAILURE);
4598 }
4599 }
4600
4601 if (cpu_model == NULL) {
4602 cpu_model = cpu_get_model(get_elf_eflags(execfd));
4603 }
4604 cpu_type = parse_cpu_model(cpu_model);
4605
4606 tcg_exec_init(0);
4607 /* NOTE: we need to init the CPU at this stage to get
4608 qemu_host_page_size */
4609
4610 cpu = cpu_create(cpu_type);
4611 env = cpu->env_ptr;
4612 cpu_reset(cpu);
4613
4614 thread_cpu = cpu;
4615
4616 if (getenv("QEMU_STRACE")) {
4617 do_strace = 1;
4618 }
4619
4620 if (getenv("QEMU_RAND_SEED")) {
4621 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4622 }
4623
4624 target_environ = envlist_to_environ(envlist, NULL);
4625 envlist_free(envlist);
4626
4627 /*
4628 * Now that page sizes are configured in cpu_init() we can do
4629 * proper page alignment for guest_base.
4630 */
4631 guest_base = HOST_PAGE_ALIGN(guest_base);
4632
4633 if (reserved_va || have_guest_base) {
4634 guest_base = init_guest_space(guest_base, reserved_va, 0,
4635 have_guest_base);
4636 if (guest_base == (unsigned long)-1) {
4637 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4638 "space for use as guest address space (check your virtual "
4639 "memory ulimit setting or reserve less using -R option)\n",
4640 reserved_va);
4641 exit(EXIT_FAILURE);
4642 }
4643
4644 if (reserved_va) {
4645 mmap_next_start = reserved_va;
4646 }
4647 }
4648
4649 /*
4650 * Read in mmap_min_addr kernel parameter. This value is used
4651 * When loading the ELF image to determine whether guest_base
4652 * is needed. It is also used in mmap_find_vma.
4653 */
4654 {
4655 FILE *fp;
4656
4657 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4658 unsigned long tmp;
4659 if (fscanf(fp, "%lu", &tmp) == 1) {
4660 mmap_min_addr = tmp;
4661 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4662 }
4663 fclose(fp);
4664 }
4665 }
4666
4667 /*
4668 * Prepare copy of argv vector for target.
4669 */
4670 target_argc = argc - optind;
4671 target_argv = calloc(target_argc + 1, sizeof (char *));
4672 if (target_argv == NULL) {
4673 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4674 exit(EXIT_FAILURE);
4675 }
4676
4677 /*
4678 * If argv0 is specified (using '-0' switch) we replace
4679 * argv[0] pointer with the given one.
4680 */
4681 i = 0;
4682 if (argv0 != NULL) {
4683 target_argv[i++] = strdup(argv0);
4684 }
4685 for (; i < target_argc; i++) {
4686 target_argv[i] = strdup(argv[optind + i]);
4687 }
4688 target_argv[target_argc] = NULL;
4689
4690 ts = g_new0(TaskState, 1);
4691 init_task_state(ts);
4692 /* build Task State */
4693 ts->info = info;
4694 ts->bprm = &bprm;
4695 cpu->opaque = ts;
4696 task_settid(ts);
4697
4698 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4699 info, &bprm);
4700 if (ret != 0) {
4701 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4702 _exit(EXIT_FAILURE);
4703 }
4704
4705 for (wrk = target_environ; *wrk; wrk++) {
4706 g_free(*wrk);
4707 }
4708
4709 g_free(target_environ);
4710
4711 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4712 qemu_log("guest_base 0x%lx\n", guest_base);
4713 log_page_dump();
4714
4715 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4716 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4717 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", info->start_code);
4718 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", info->start_data);
4719 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4720 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", info->start_stack);
4721 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4722 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4723 qemu_log("argv_start 0x" TARGET_ABI_FMT_lx "\n", info->arg_start);
4724 qemu_log("env_start 0x" TARGET_ABI_FMT_lx "\n",
4725 info->arg_end + (abi_ulong)sizeof(abi_ulong));
4726 qemu_log("auxv_start 0x" TARGET_ABI_FMT_lx "\n", info->saved_auxv);
4727 }
4728
4729 target_set_brk(info->brk);
4730 syscall_init();
4731 signal_init();
4732
4733 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4734 generating the prologue until now so that the prologue can take
4735 the real value of GUEST_BASE into account. */
4736 tcg_prologue_init(tcg_ctx);
4737 tcg_region_init();
4738
4739 #if defined(TARGET_I386)
4740 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4741 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4742 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4743 env->cr[4] |= CR4_OSFXSR_MASK;
4744 env->hflags |= HF_OSFXSR_MASK;
4745 }
4746 #ifndef TARGET_ABI32
4747 /* enable 64 bit mode if possible */
4748 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4749 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4750 exit(EXIT_FAILURE);
4751 }
4752 env->cr[4] |= CR4_PAE_MASK;
4753 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4754 env->hflags |= HF_LMA_MASK;
4755 #endif
4756
4757 /* flags setup : we activate the IRQs by default as in user mode */
4758 env->eflags |= IF_MASK;
4759
4760 /* linux register setup */
4761 #ifndef TARGET_ABI32
4762 env->regs[R_EAX] = regs->rax;
4763 env->regs[R_EBX] = regs->rbx;
4764 env->regs[R_ECX] = regs->rcx;
4765 env->regs[R_EDX] = regs->rdx;
4766 env->regs[R_ESI] = regs->rsi;
4767 env->regs[R_EDI] = regs->rdi;
4768 env->regs[R_EBP] = regs->rbp;
4769 env->regs[R_ESP] = regs->rsp;
4770 env->eip = regs->rip;
4771 #else
4772 env->regs[R_EAX] = regs->eax;
4773 env->regs[R_EBX] = regs->ebx;
4774 env->regs[R_ECX] = regs->ecx;
4775 env->regs[R_EDX] = regs->edx;
4776 env->regs[R_ESI] = regs->esi;
4777 env->regs[R_EDI] = regs->edi;
4778 env->regs[R_EBP] = regs->ebp;
4779 env->regs[R_ESP] = regs->esp;
4780 env->eip = regs->eip;
4781 #endif
4782
4783 /* linux interrupt setup */
4784 #ifndef TARGET_ABI32
4785 env->idt.limit = 511;
4786 #else
4787 env->idt.limit = 255;
4788 #endif
4789 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4790 PROT_READ|PROT_WRITE,
4791 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4792 idt_table = g2h(env->idt.base);
4793 set_idt(0, 0);
4794 set_idt(1, 0);
4795 set_idt(2, 0);
4796 set_idt(3, 3);
4797 set_idt(4, 3);
4798 set_idt(5, 0);
4799 set_idt(6, 0);
4800 set_idt(7, 0);
4801 set_idt(8, 0);
4802 set_idt(9, 0);
4803 set_idt(10, 0);
4804 set_idt(11, 0);
4805 set_idt(12, 0);
4806 set_idt(13, 0);
4807 set_idt(14, 0);
4808 set_idt(15, 0);
4809 set_idt(16, 0);
4810 set_idt(17, 0);
4811 set_idt(18, 0);
4812 set_idt(19, 0);
4813 set_idt(0x80, 3);
4814
4815 /* linux segment setup */
4816 {
4817 uint64_t *gdt_table;
4818 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4819 PROT_READ|PROT_WRITE,
4820 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4821 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4822 gdt_table = g2h(env->gdt.base);
4823 #ifdef TARGET_ABI32
4824 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4825 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4826 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4827 #else
4828 /* 64 bit code segment */
4829 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4830 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4831 DESC_L_MASK |
4832 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4833 #endif
4834 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4835 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4836 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4837 }
4838 cpu_x86_load_seg(env, R_CS, __USER_CS);
4839 cpu_x86_load_seg(env, R_SS, __USER_DS);
4840 #ifdef TARGET_ABI32
4841 cpu_x86_load_seg(env, R_DS, __USER_DS);
4842 cpu_x86_load_seg(env, R_ES, __USER_DS);
4843 cpu_x86_load_seg(env, R_FS, __USER_DS);
4844 cpu_x86_load_seg(env, R_GS, __USER_DS);
4845 /* This hack makes Wine work... */
4846 env->segs[R_FS].selector = 0;
4847 #else
4848 cpu_x86_load_seg(env, R_DS, 0);
4849 cpu_x86_load_seg(env, R_ES, 0);
4850 cpu_x86_load_seg(env, R_FS, 0);
4851 cpu_x86_load_seg(env, R_GS, 0);
4852 #endif
4853 #elif defined(TARGET_AARCH64)
4854 {
4855 int i;
4856
4857 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4858 fprintf(stderr,
4859 "The selected ARM CPU does not support 64 bit mode\n");
4860 exit(EXIT_FAILURE);
4861 }
4862
4863 for (i = 0; i < 31; i++) {
4864 env->xregs[i] = regs->regs[i];
4865 }
4866 env->pc = regs->pc;
4867 env->xregs[31] = regs->sp;
4868 #ifdef TARGET_WORDS_BIGENDIAN
4869 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4870 for (i = 1; i < 4; ++i) {
4871 env->cp15.sctlr_el[i] |= SCTLR_EE;
4872 }
4873 #endif
4874 }
4875 #elif defined(TARGET_ARM)
4876 {
4877 int i;
4878 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4879 CPSRWriteByInstr);
4880 for(i = 0; i < 16; i++) {
4881 env->regs[i] = regs->uregs[i];
4882 }
4883 #ifdef TARGET_WORDS_BIGENDIAN
4884 /* Enable BE8. */
4885 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4886 && (info->elf_flags & EF_ARM_BE8)) {
4887 env->uncached_cpsr |= CPSR_E;
4888 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4889 } else {
4890 env->cp15.sctlr_el[1] |= SCTLR_B;
4891 }
4892 #endif
4893 }
4894 #elif defined(TARGET_SPARC)
4895 {
4896 int i;
4897 env->pc = regs->pc;
4898 env->npc = regs->npc;
4899 env->y = regs->y;
4900 for(i = 0; i < 8; i++)
4901 env->gregs[i] = regs->u_regs[i];
4902 for(i = 0; i < 8; i++)
4903 env->regwptr[i] = regs->u_regs[i + 8];
4904 }
4905 #elif defined(TARGET_PPC)
4906 {
4907 int i;
4908
4909 #if defined(TARGET_PPC64)
4910 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
4911 #if defined(TARGET_ABI32)
4912 env->msr &= ~((target_ulong)1 << flag);
4913 #else
4914 env->msr |= (target_ulong)1 << flag;
4915 #endif
4916 #endif
4917 env->nip = regs->nip;
4918 for(i = 0; i < 32; i++) {
4919 env->gpr[i] = regs->gpr[i];
4920 }
4921 }
4922 #elif defined(TARGET_M68K)
4923 {
4924 env->pc = regs->pc;
4925 env->dregs[0] = regs->d0;
4926 env->dregs[1] = regs->d1;
4927 env->dregs[2] = regs->d2;
4928 env->dregs[3] = regs->d3;
4929 env->dregs[4] = regs->d4;
4930 env->dregs[5] = regs->d5;
4931 env->dregs[6] = regs->d6;
4932 env->dregs[7] = regs->d7;
4933 env->aregs[0] = regs->a0;
4934 env->aregs[1] = regs->a1;
4935 env->aregs[2] = regs->a2;
4936 env->aregs[3] = regs->a3;
4937 env->aregs[4] = regs->a4;
4938 env->aregs[5] = regs->a5;
4939 env->aregs[6] = regs->a6;
4940 env->aregs[7] = regs->usp;
4941 env->sr = regs->sr;
4942 ts->sim_syscalls = 1;
4943 }
4944 #elif defined(TARGET_MICROBLAZE)
4945 {
4946 env->regs[0] = regs->r0;
4947 env->regs[1] = regs->r1;
4948 env->regs[2] = regs->r2;
4949 env->regs[3] = regs->r3;
4950 env->regs[4] = regs->r4;
4951 env->regs[5] = regs->r5;
4952 env->regs[6] = regs->r6;
4953 env->regs[7] = regs->r7;
4954 env->regs[8] = regs->r8;
4955 env->regs[9] = regs->r9;
4956 env->regs[10] = regs->r10;
4957 env->regs[11] = regs->r11;
4958 env->regs[12] = regs->r12;
4959 env->regs[13] = regs->r13;
4960 env->regs[14] = regs->r14;
4961 env->regs[15] = regs->r15;
4962 env->regs[16] = regs->r16;
4963 env->regs[17] = regs->r17;
4964 env->regs[18] = regs->r18;
4965 env->regs[19] = regs->r19;
4966 env->regs[20] = regs->r20;
4967 env->regs[21] = regs->r21;
4968 env->regs[22] = regs->r22;
4969 env->regs[23] = regs->r23;
4970 env->regs[24] = regs->r24;
4971 env->regs[25] = regs->r25;
4972 env->regs[26] = regs->r26;
4973 env->regs[27] = regs->r27;
4974 env->regs[28] = regs->r28;
4975 env->regs[29] = regs->r29;
4976 env->regs[30] = regs->r30;
4977 env->regs[31] = regs->r31;
4978 env->sregs[SR_PC] = regs->pc;
4979 }
4980 #elif defined(TARGET_MIPS)
4981 {
4982 int i;
4983
4984 for(i = 0; i < 32; i++) {
4985 env->active_tc.gpr[i] = regs->regs[i];
4986 }
4987 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4988 if (regs->cp0_epc & 1) {
4989 env->hflags |= MIPS_HFLAG_M16;
4990 }
4991 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4992 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4993 if ((env->active_fpu.fcr31_rw_bitmask &
4994 (1 << FCR31_NAN2008)) == 0) {
4995 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4996 exit(1);
4997 }
4998 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4999 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
5000 } else {
5001 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
5002 }
5003 restore_snan_bit_mode(env);
5004 }
5005 }
5006 #elif defined(TARGET_NIOS2)
5007 {
5008 env->regs[0] = 0;
5009 env->regs[1] = regs->r1;
5010 env->regs[2] = regs->r2;
5011 env->regs[3] = regs->r3;
5012 env->regs[4] = regs->r4;
5013 env->regs[5] = regs->r5;
5014 env->regs[6] = regs->r6;
5015 env->regs[7] = regs->r7;
5016 env->regs[8] = regs->r8;
5017 env->regs[9] = regs->r9;
5018 env->regs[10] = regs->r10;
5019 env->regs[11] = regs->r11;
5020 env->regs[12] = regs->r12;
5021 env->regs[13] = regs->r13;
5022 env->regs[14] = regs->r14;
5023 env->regs[15] = regs->r15;
5024 /* TODO: unsigned long orig_r2; */
5025 env->regs[R_RA] = regs->ra;
5026 env->regs[R_FP] = regs->fp;
5027 env->regs[R_SP] = regs->sp;
5028 env->regs[R_GP] = regs->gp;
5029 env->regs[CR_ESTATUS] = regs->estatus;
5030 env->regs[R_EA] = regs->ea;
5031 /* TODO: unsigned long orig_r7; */
5032
5033 /* Emulate eret when starting thread. */
5034 env->regs[R_PC] = regs->ea;
5035 }
5036 #elif defined(TARGET_OPENRISC)
5037 {
5038 int i;
5039
5040 for (i = 0; i < 32; i++) {
5041 cpu_set_gpr(env, i, regs->gpr[i]);
5042 }
5043 env->pc = regs->pc;
5044 cpu_set_sr(env, regs->sr);
5045 }
5046 #elif defined(TARGET_RISCV)
5047 {
5048 env->pc = regs->sepc;
5049 env->gpr[xSP] = regs->sp;
5050 }
5051 #elif defined(TARGET_SH4)
5052 {
5053 int i;
5054
5055 for(i = 0; i < 16; i++) {
5056 env->gregs[i] = regs->regs[i];
5057 }
5058 env->pc = regs->pc;
5059 }
5060 #elif defined(TARGET_ALPHA)
5061 {
5062 int i;
5063
5064 for(i = 0; i < 28; i++) {
5065 env->ir[i] = ((abi_ulong *)regs)[i];
5066 }
5067 env->ir[IR_SP] = regs->usp;
5068 env->pc = regs->pc;
5069 }
5070 #elif defined(TARGET_CRIS)
5071 {
5072 env->regs[0] = regs->r0;
5073 env->regs[1] = regs->r1;
5074 env->regs[2] = regs->r2;
5075 env->regs[3] = regs->r3;
5076 env->regs[4] = regs->r4;
5077 env->regs[5] = regs->r5;
5078 env->regs[6] = regs->r6;
5079 env->regs[7] = regs->r7;
5080 env->regs[8] = regs->r8;
5081 env->regs[9] = regs->r9;
5082 env->regs[10] = regs->r10;
5083 env->regs[11] = regs->r11;
5084 env->regs[12] = regs->r12;
5085 env->regs[13] = regs->r13;
5086 env->regs[14] = info->start_stack;
5087 env->regs[15] = regs->acr;
5088 env->pc = regs->erp;
5089 }
5090 #elif defined(TARGET_S390X)
5091 {
5092 int i;
5093 for (i = 0; i < 16; i++) {
5094 env->regs[i] = regs->gprs[i];
5095 }
5096 env->psw.mask = regs->psw.mask;
5097 env->psw.addr = regs->psw.addr;
5098 }
5099 #elif defined(TARGET_TILEGX)
5100 {
5101 int i;
5102 for (i = 0; i < TILEGX_R_COUNT; i++) {
5103 env->regs[i] = regs->regs[i];
5104 }
5105 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
5106 env->spregs[i] = 0;
5107 }
5108 env->pc = regs->pc;
5109 }
5110 #elif defined(TARGET_HPPA)
5111 {
5112 int i;
5113 for (i = 1; i < 32; i++) {
5114 env->gr[i] = regs->gr[i];
5115 }
5116 env->iaoq_f = regs->iaoq[0];
5117 env->iaoq_b = regs->iaoq[1];
5118 }
5119 #elif defined(TARGET_XTENSA)
5120 {
5121 int i;
5122 for (i = 0; i < 16; ++i) {
5123 env->regs[i] = regs->areg[i];
5124 }
5125 env->sregs[WINDOW_START] = regs->windowstart;
5126 env->pc = regs->pc;
5127 }
5128 #else
5129 #error unsupported target CPU
5130 #endif
5131
5132 #if defined(TARGET_ARM) || defined(TARGET_M68K)
5133 ts->stack_base = info->start_stack;
5134 ts->heap_base = info->brk;
5135 /* This will be filled in on the first SYS_HEAPINFO call. */
5136 ts->heap_limit = 0;
5137 #endif
5138
5139 if (gdbstub_port) {
5140 if (gdbserver_start(gdbstub_port) < 0) {
5141 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
5142 gdbstub_port);
5143 exit(EXIT_FAILURE);
5144 }
5145 gdb_handlesig(cpu, 0);
5146 }
5147 cpu_loop(env);
5148 /* never exits */
5149 return 0;
5150 }
QEmu