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Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210316' into staging
[qemu.git] / hw / block / m25p80.c
blob5f9471d83c6a4005cc48fc8c8c29466bfa17b8cc
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/units.h"
26 #include "sysemu/block-backend.h"
27 #include "hw/qdev-properties.h"
28 #include "hw/qdev-properties-system.h"
29 #include "hw/ssi/ssi.h"
30 #include "migration/vmstate.h"
31 #include "qemu/bitops.h"
32 #include "qemu/log.h"
33 #include "qemu/module.h"
34 #include "qemu/error-report.h"
35 #include "qapi/error.h"
36 #include "trace.h"
37 #include "qom/object.h"
38
39 /* Fields for FlashPartInfo->flags */
40
41 /* erase capabilities */
42 #define ER_4K 1
43 #define ER_32K 2
44 /* set to allow the page program command to write 0s back to 1. Useful for
45 * modelling EEPROM with SPI flash command set
46 */
47 #define EEPROM 0x100
48
49 /* 16 MiB max in 3 byte address mode */
50 #define MAX_3BYTES_SIZE 0x1000000
51
52 #define SPI_NOR_MAX_ID_LEN 6
53
54 typedef struct FlashPartInfo {
55 const char *part_name;
56 /*
57 * This array stores the ID bytes.
58 * The first three bytes are the JEDIC ID.
59 * JEDEC ID zero means "no ID" (mostly older chips).
60 */
61 uint8_t id[SPI_NOR_MAX_ID_LEN];
62 uint8_t id_len;
63 /* there is confusion between manufacturers as to what a sector is. In this
64 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
65 * command (opcode 0xd8).
66 */
67 uint32_t sector_size;
68 uint32_t n_sectors;
69 uint32_t page_size;
70 uint16_t flags;
71 /*
72 * Big sized spi nor are often stacked devices, thus sometime
73 * replace chip erase with die erase.
74 * This field inform how many die is in the chip.
75 */
76 uint8_t die_cnt;
77 } FlashPartInfo;
78
79 /* adapted from linux */
80 /* Used when the "_ext_id" is two bytes at most */
81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
82 .part_name = _part_name,\
83 .id = {\
84 ((_jedec_id) >> 16) & 0xff,\
85 ((_jedec_id) >> 8) & 0xff,\
86 (_jedec_id) & 0xff,\
87 ((_ext_id) >> 8) & 0xff,\
88 (_ext_id) & 0xff,\
89 },\
90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
91 .sector_size = (_sector_size),\
92 .n_sectors = (_n_sectors),\
93 .page_size = 256,\
94 .flags = (_flags),\
95 .die_cnt = 0
96
97 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
98 .part_name = _part_name,\
99 .id = {\
100 ((_jedec_id) >> 16) & 0xff,\
101 ((_jedec_id) >> 8) & 0xff,\
102 (_jedec_id) & 0xff,\
103 ((_ext_id) >> 16) & 0xff,\
104 ((_ext_id) >> 8) & 0xff,\
105 (_ext_id) & 0xff,\
106 },\
107 .id_len = 6,\
108 .sector_size = (_sector_size),\
109 .n_sectors = (_n_sectors),\
110 .page_size = 256,\
111 .flags = (_flags),\
112 .die_cnt = 0
113
114 #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\
115 _flags, _die_cnt)\
116 .part_name = _part_name,\
117 .id = {\
118 ((_jedec_id) >> 16) & 0xff,\
119 ((_jedec_id) >> 8) & 0xff,\
120 (_jedec_id) & 0xff,\
121 ((_ext_id) >> 8) & 0xff,\
122 (_ext_id) & 0xff,\
123 },\
124 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
125 .sector_size = (_sector_size),\
126 .n_sectors = (_n_sectors),\
127 .page_size = 256,\
128 .flags = (_flags),\
129 .die_cnt = _die_cnt
130
131 #define JEDEC_NUMONYX 0x20
132 #define JEDEC_WINBOND 0xEF
133 #define JEDEC_SPANSION 0x01
134
135 /* Numonyx (Micron) Configuration register macros */
136 #define VCFG_DUMMY 0x1
137 #define VCFG_WRAP_SEQUENTIAL 0x2
138 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
139 #define NVCFG_XIP_MODE_MASK (7 << 9)
140 #define VCFG_XIP_MODE_DISABLED (1 << 3)
141 #define CFG_DUMMY_CLK_LEN 4
142 #define NVCFG_DUMMY_CLK_POS 12
143 #define VCFG_DUMMY_CLK_POS 4
144 #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7
145 #define EVCFG_VPP_ACCELERATOR (1 << 3)
146 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
147 #define NVCFG_DUAL_IO_MASK (1 << 2)
148 #define EVCFG_DUAL_IO_DISABLED (1 << 6)
149 #define NVCFG_QUAD_IO_MASK (1 << 3)
150 #define EVCFG_QUAD_IO_DISABLED (1 << 7)
151 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
152 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
153
154 /* Numonyx (Micron) Flag Status Register macros */
155 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
156 #define FSR_FLASH_READY (1 << 7)
157
158 /* Spansion configuration registers macros. */
159 #define SPANSION_QUAD_CFG_POS 0
160 #define SPANSION_QUAD_CFG_LEN 1
161 #define SPANSION_DUMMY_CLK_POS 0
162 #define SPANSION_DUMMY_CLK_LEN 4
163 #define SPANSION_ADDR_LEN_POS 7
164 #define SPANSION_ADDR_LEN_LEN 1
165
166 /*
167 * Spansion read mode command length in bytes,
168 * the mode is currently not supported.
169 */
170
171 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
172 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
173
174 static const FlashPartInfo known_devices[] = {
175 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
176 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
177 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
178
179 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
180 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
181 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
182
183 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
184 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
185 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
186 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
187
188 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
189
190 /* Atmel EEPROMS - it is assumed, that don't care bit in command
191 * is set to 0. Block protection is not supported.
192 */
193 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
194 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
195
196 /* EON -- en25xxx */
197 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
198 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
199 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
200 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
201 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
202
203 /* GigaDevice */
204 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
205 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
206
207 /* Intel/Numonyx -- xxxs33b */
208 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
209 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
210 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
211 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
212
213 /* ISSI */
214 { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) },
215 { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) },
216 { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) },
217 { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) },
218 { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) },
219 { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) },
220 { INFO("is25lp256", 0x9d6019, 0, 64 << 10, 512, ER_4K) },
221 { INFO("is25wp032", 0x9d7016, 0, 64 << 10, 64, ER_4K) },
222 { INFO("is25wp064", 0x9d7017, 0, 64 << 10, 128, ER_4K) },
223 { INFO("is25wp128", 0x9d7018, 0, 64 << 10, 256, ER_4K) },
224 { INFO("is25wp256", 0x9d7019, 0, 64 << 10, 512, ER_4K) },
225
226 /* Macronix */
227 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
228 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
229 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
230 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
231 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
232 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
233 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
234 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
235 { INFO6("mx25l25635e", 0xc22019, 0xc22019, 64 << 10, 512, 0) },
236 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
237 { INFO("mx66l51235f", 0xc2201a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
238 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
239 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
240 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
241
242 /* Micron */
243 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
244 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
245 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
246 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
247 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
248 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
249 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
250 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
251 { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) },
252 { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
253 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
254 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
255 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
256 { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) },
257 { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
258 { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
259 { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) },
260 { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
261 { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) },
262
263 /* Spansion -- single (large) sector size only, at least
264 * for the chips listed here (without boot sectors).
265 */
266 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
267 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
268 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
269 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
270 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
271 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
272 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
273 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
274 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
275 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
276 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
277 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
278 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
279 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
280 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
281 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
282 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
283
284 /* Spansion -- boot sectors support */
285 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
286 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
287
288 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
289 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
290 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
291 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
292 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
293 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
294 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
295 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
296 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
297 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
298
299 /* ST Microelectronics -- newer production may have feature updates */
300 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
301 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
302 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
303 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
304 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
305 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
306 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
307 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
308 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
309 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
310
311 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
312 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
313 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
314
315 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
316 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
317 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
318
319 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
320 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
321 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
322 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
323
324 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
325 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
326 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
327 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
328 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
329 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
330 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
331 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
332 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
333 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
334 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
335 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
336 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
337 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
338 { INFO("w25q512jv", 0xef4020, 0, 64 << 10, 1024, ER_4K) },
339 };
340
341 typedef enum {
342 NOP = 0,
343 WRSR = 0x1,
344 WRDI = 0x4,
345 RDSR = 0x5,
346 WREN = 0x6,
347 BRRD = 0x16,
348 BRWR = 0x17,
349 JEDEC_READ = 0x9f,
350 BULK_ERASE_60 = 0x60,
351 BULK_ERASE = 0xc7,
352 READ_FSR = 0x70,
353 RDCR = 0x15,
354
355 READ = 0x03,
356 READ4 = 0x13,
357 FAST_READ = 0x0b,
358 FAST_READ4 = 0x0c,
359 DOR = 0x3b,
360 DOR4 = 0x3c,
361 QOR = 0x6b,
362 QOR4 = 0x6c,
363 DIOR = 0xbb,
364 DIOR4 = 0xbc,
365 QIOR = 0xeb,
366 QIOR4 = 0xec,
367
368 PP = 0x02,
369 PP4 = 0x12,
370 PP4_4 = 0x3e,
371 DPP = 0xa2,
372 QPP = 0x32,
373 QPP_4 = 0x34,
374 RDID_90 = 0x90,
375 RDID_AB = 0xab,
376 AAI_WP = 0xad,
377
378 ERASE_4K = 0x20,
379 ERASE4_4K = 0x21,
380 ERASE_32K = 0x52,
381 ERASE4_32K = 0x5c,
382 ERASE_SECTOR = 0xd8,
383 ERASE4_SECTOR = 0xdc,
384
385 EN_4BYTE_ADDR = 0xB7,
386 EX_4BYTE_ADDR = 0xE9,
387
388 EXTEND_ADDR_READ = 0xC8,
389 EXTEND_ADDR_WRITE = 0xC5,
390
391 RESET_ENABLE = 0x66,
392 RESET_MEMORY = 0x99,
393
394 /*
395 * Micron: 0x35 - enable QPI
396 * Spansion: 0x35 - read control register
397 */
398 RDCR_EQIO = 0x35,
399 RSTQIO = 0xf5,
400
401 RNVCR = 0xB5,
402 WNVCR = 0xB1,
403
404 RVCR = 0x85,
405 WVCR = 0x81,
406
407 REVCR = 0x65,
408 WEVCR = 0x61,
409
410 DIE_ERASE = 0xC4,
411 } FlashCMD;
412
413 typedef enum {
414 STATE_IDLE,
415 STATE_PAGE_PROGRAM,
416 STATE_READ,
417 STATE_COLLECTING_DATA,
418 STATE_COLLECTING_VAR_LEN_DATA,
419 STATE_READING_DATA,
420 } CMDState;
421
422 typedef enum {
423 MAN_SPANSION,
424 MAN_MACRONIX,
425 MAN_NUMONYX,
426 MAN_WINBOND,
427 MAN_SST,
428 MAN_ISSI,
429 MAN_GENERIC,
430 } Manufacturer;
431
432 typedef enum {
433 MODE_STD = 0,
434 MODE_DIO = 1,
435 MODE_QIO = 2
436 } SPIMode;
437
438 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
439
440 struct Flash {
441 SSIPeripheral parent_obj;
442
443 BlockBackend *blk;
444
445 uint8_t *storage;
446 uint32_t size;
447 int page_size;
448
449 uint8_t state;
450 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
451 uint32_t len;
452 uint32_t pos;
453 bool data_read_loop;
454 uint8_t needed_bytes;
455 uint8_t cmd_in_progress;
456 uint32_t cur_addr;
457 uint32_t nonvolatile_cfg;
458 /* Configuration register for Macronix */
459 uint32_t volatile_cfg;
460 uint32_t enh_volatile_cfg;
461 /* Spansion cfg registers. */
462 uint8_t spansion_cr1nv;
463 uint8_t spansion_cr2nv;
464 uint8_t spansion_cr3nv;
465 uint8_t spansion_cr4nv;
466 uint8_t spansion_cr1v;
467 uint8_t spansion_cr2v;
468 uint8_t spansion_cr3v;
469 uint8_t spansion_cr4v;
470 bool write_enable;
471 bool four_bytes_address_mode;
472 bool reset_enable;
473 bool quad_enable;
474 bool aai_enable;
475 uint8_t ear;
476
477 int64_t dirty_page;
478
479 const FlashPartInfo *pi;
480
481 };
482
483 struct M25P80Class {
484 SSIPeripheralClass parent_class;
485 FlashPartInfo *pi;
486 };
487
488 #define TYPE_M25P80 "m25p80-generic"
489 OBJECT_DECLARE_TYPE(Flash, M25P80Class, M25P80)
490
491 static inline Manufacturer get_man(Flash *s)
492 {
493 switch (s->pi->id[0]) {
494 case 0x20:
495 return MAN_NUMONYX;
496 case 0xEF:
497 return MAN_WINBOND;
498 case 0x01:
499 return MAN_SPANSION;
500 case 0xC2:
501 return MAN_MACRONIX;
502 case 0xBF:
503 return MAN_SST;
504 case 0x9D:
505 return MAN_ISSI;
506 default:
507 return MAN_GENERIC;
508 }
509 }
510
511 static void blk_sync_complete(void *opaque, int ret)
512 {
513 QEMUIOVector *iov = opaque;
514
515 qemu_iovec_destroy(iov);
516 g_free(iov);
517
518 /* do nothing. Masters do not directly interact with the backing store,
519 * only the working copy so no mutexing required.
520 */
521 }
522
523 static void flash_sync_page(Flash *s, int page)
524 {
525 QEMUIOVector *iov;
526
527 if (!s->blk || !blk_is_writable(s->blk)) {
528 return;
529 }
530
531 iov = g_new(QEMUIOVector, 1);
532 qemu_iovec_init(iov, 1);
533 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
534 s->pi->page_size);
535 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
536 blk_sync_complete, iov);
537 }
538
539 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
540 {
541 QEMUIOVector *iov;
542
543 if (!s->blk || !blk_is_writable(s->blk)) {
544 return;
545 }
546
547 assert(!(len % BDRV_SECTOR_SIZE));
548 iov = g_new(QEMUIOVector, 1);
549 qemu_iovec_init(iov, 1);
550 qemu_iovec_add(iov, s->storage + off, len);
551 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
552 }
553
554 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
555 {
556 uint32_t len;
557 uint8_t capa_to_assert = 0;
558
559 switch (cmd) {
560 case ERASE_4K:
561 case ERASE4_4K:
562 len = 4 * KiB;
563 capa_to_assert = ER_4K;
564 break;
565 case ERASE_32K:
566 case ERASE4_32K:
567 len = 32 * KiB;
568 capa_to_assert = ER_32K;
569 break;
570 case ERASE_SECTOR:
571 case ERASE4_SECTOR:
572 len = s->pi->sector_size;
573 break;
574 case BULK_ERASE:
575 len = s->size;
576 break;
577 case DIE_ERASE:
578 if (s->pi->die_cnt) {
579 len = s->size / s->pi->die_cnt;
580 offset = offset & (~(len - 1));
581 } else {
582 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported"
583 " by device\n");
584 return;
585 }
586 break;
587 default:
588 abort();
589 }
590
591 trace_m25p80_flash_erase(s, offset, len);
592
593 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
594 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
595 " device\n", len);
596 }
597
598 if (!s->write_enable) {
599 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
600 return;
601 }
602 memset(s->storage + offset, 0xff, len);
603 flash_sync_area(s, offset, len);
604 }
605
606 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
607 {
608 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
609 flash_sync_page(s, s->dirty_page);
610 s->dirty_page = newpage;
611 }
612 }
613
614 static inline
615 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
616 {
617 uint32_t page = addr / s->pi->page_size;
618 uint8_t prev = s->storage[s->cur_addr];
619
620 if (!s->write_enable) {
621 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
622 return;
623 }
624
625 if ((prev ^ data) & data) {
626 trace_m25p80_programming_zero_to_one(s, addr, prev, data);
627 }
628
629 if (s->pi->flags & EEPROM) {
630 s->storage[s->cur_addr] = data;
631 } else {
632 s->storage[s->cur_addr] &= data;
633 }
634
635 flash_sync_dirty(s, page);
636 s->dirty_page = page;
637 }
638
639 static inline int get_addr_length(Flash *s)
640 {
641 /* check if eeprom is in use */
642 if (s->pi->flags == EEPROM) {
643 return 2;
644 }
645
646 switch (s->cmd_in_progress) {
647 case PP4:
648 case PP4_4:
649 case QPP_4:
650 case READ4:
651 case QIOR4:
652 case ERASE4_4K:
653 case ERASE4_32K:
654 case ERASE4_SECTOR:
655 case FAST_READ4:
656 case DOR4:
657 case QOR4:
658 case DIOR4:
659 return 4;
660 default:
661 return s->four_bytes_address_mode ? 4 : 3;
662 }
663 }
664
665 static void complete_collecting_data(Flash *s)
666 {
667 int i, n;
668
669 n = get_addr_length(s);
670 s->cur_addr = (n == 3 ? s->ear : 0);
671 for (i = 0; i < n; ++i) {
672 s->cur_addr <<= 8;
673 s->cur_addr |= s->data[i];
674 }
675
676 s->cur_addr &= s->size - 1;
677
678 s->state = STATE_IDLE;
679
680 trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
681 s->cur_addr);
682
683 switch (s->cmd_in_progress) {
684 case DPP:
685 case QPP:
686 case QPP_4:
687 case PP:
688 case PP4:
689 case PP4_4:
690 s->state = STATE_PAGE_PROGRAM;
691 break;
692 case AAI_WP:
693 /* AAI programming starts from the even address */
694 s->cur_addr &= ~BIT(0);
695 s->state = STATE_PAGE_PROGRAM;
696 break;
697 case READ:
698 case READ4:
699 case FAST_READ:
700 case FAST_READ4:
701 case DOR:
702 case DOR4:
703 case QOR:
704 case QOR4:
705 case DIOR:
706 case DIOR4:
707 case QIOR:
708 case QIOR4:
709 s->state = STATE_READ;
710 break;
711 case ERASE_4K:
712 case ERASE4_4K:
713 case ERASE_32K:
714 case ERASE4_32K:
715 case ERASE_SECTOR:
716 case ERASE4_SECTOR:
717 case DIE_ERASE:
718 flash_erase(s, s->cur_addr, s->cmd_in_progress);
719 break;
720 case WRSR:
721 switch (get_man(s)) {
722 case MAN_SPANSION:
723 s->quad_enable = !!(s->data[1] & 0x02);
724 break;
725 case MAN_ISSI:
726 s->quad_enable = extract32(s->data[0], 6, 1);
727 break;
728 case MAN_MACRONIX:
729 s->quad_enable = extract32(s->data[0], 6, 1);
730 if (s->len > 1) {
731 s->volatile_cfg = s->data[1];
732 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
733 }
734 break;
735 default:
736 break;
737 }
738 if (s->write_enable) {
739 s->write_enable = false;
740 }
741 break;
742 case BRWR:
743 case EXTEND_ADDR_WRITE:
744 s->ear = s->data[0];
745 break;
746 case WNVCR:
747 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
748 break;
749 case WVCR:
750 s->volatile_cfg = s->data[0];
751 break;
752 case WEVCR:
753 s->enh_volatile_cfg = s->data[0];
754 break;
755 case RDID_90:
756 case RDID_AB:
757 if (get_man(s) == MAN_SST) {
758 if (s->cur_addr <= 1) {
759 if (s->cur_addr) {
760 s->data[0] = s->pi->id[2];
761 s->data[1] = s->pi->id[0];
762 } else {
763 s->data[0] = s->pi->id[0];
764 s->data[1] = s->pi->id[2];
765 }
766 s->pos = 0;
767 s->len = 2;
768 s->data_read_loop = true;
769 s->state = STATE_READING_DATA;
770 } else {
771 qemu_log_mask(LOG_GUEST_ERROR,
772 "M25P80: Invalid read id address\n");
773 }
774 } else {
775 qemu_log_mask(LOG_GUEST_ERROR,
776 "M25P80: Read id (command 0x90/0xAB) is not supported"
777 " by device\n");
778 }
779 break;
780 default:
781 break;
782 }
783 }
784
785 static void reset_memory(Flash *s)
786 {
787 s->cmd_in_progress = NOP;
788 s->cur_addr = 0;
789 s->ear = 0;
790 s->four_bytes_address_mode = false;
791 s->len = 0;
792 s->needed_bytes = 0;
793 s->pos = 0;
794 s->state = STATE_IDLE;
795 s->write_enable = false;
796 s->reset_enable = false;
797 s->quad_enable = false;
798 s->aai_enable = false;
799
800 switch (get_man(s)) {
801 case MAN_NUMONYX:
802 s->volatile_cfg = 0;
803 s->volatile_cfg |= VCFG_DUMMY;
804 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
805 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
806 == NVCFG_XIP_MODE_DISABLED) {
807 s->volatile_cfg |= VCFG_XIP_MODE_DISABLED;
808 }
809 s->volatile_cfg |= deposit32(s->volatile_cfg,
810 VCFG_DUMMY_CLK_POS,
811 CFG_DUMMY_CLK_LEN,
812 extract32(s->nonvolatile_cfg,
813 NVCFG_DUMMY_CLK_POS,
814 CFG_DUMMY_CLK_LEN)
815 );
816
817 s->enh_volatile_cfg = 0;
818 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF;
819 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
820 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
821 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
822 s->enh_volatile_cfg |= EVCFG_DUAL_IO_DISABLED;
823 }
824 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
825 s->enh_volatile_cfg |= EVCFG_QUAD_IO_DISABLED;
826 }
827 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
828 s->four_bytes_address_mode = true;
829 }
830 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
831 s->ear = s->size / MAX_3BYTES_SIZE - 1;
832 }
833 break;
834 case MAN_MACRONIX:
835 s->volatile_cfg = 0x7;
836 break;
837 case MAN_SPANSION:
838 s->spansion_cr1v = s->spansion_cr1nv;
839 s->spansion_cr2v = s->spansion_cr2nv;
840 s->spansion_cr3v = s->spansion_cr3nv;
841 s->spansion_cr4v = s->spansion_cr4nv;
842 s->quad_enable = extract32(s->spansion_cr1v,
843 SPANSION_QUAD_CFG_POS,
844 SPANSION_QUAD_CFG_LEN
845 );
846 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
847 SPANSION_ADDR_LEN_POS,
848 SPANSION_ADDR_LEN_LEN
849 );
850 break;
851 default:
852 break;
853 }
854
855 trace_m25p80_reset_done(s);
856 }
857
858 static uint8_t numonyx_mode(Flash *s)
859 {
860 if (!(s->enh_volatile_cfg & EVCFG_QUAD_IO_DISABLED)) {
861 return MODE_QIO;
862 } else if (!(s->enh_volatile_cfg & EVCFG_DUAL_IO_DISABLED)) {
863 return MODE_DIO;
864 } else {
865 return MODE_STD;
866 }
867 }
868
869 static uint8_t numonyx_extract_cfg_num_dummies(Flash *s)
870 {
871 uint8_t num_dummies;
872 uint8_t mode;
873 assert(get_man(s) == MAN_NUMONYX);
874
875 mode = numonyx_mode(s);
876 num_dummies = extract32(s->volatile_cfg, 4, 4);
877
878 if (num_dummies == 0x0 || num_dummies == 0xf) {
879 switch (s->cmd_in_progress) {
880 case QIOR:
881 case QIOR4:
882 num_dummies = 10;
883 break;
884 default:
885 num_dummies = (mode == MODE_QIO) ? 10 : 8;
886 break;
887 }
888 }
889
890 return num_dummies;
891 }
892
893 static void decode_fast_read_cmd(Flash *s)
894 {
895 s->needed_bytes = get_addr_length(s);
896 switch (get_man(s)) {
897 /* Dummy cycles - modeled with bytes writes instead of bits */
898 case MAN_WINBOND:
899 s->needed_bytes += 8;
900 break;
901 case MAN_NUMONYX:
902 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
903 break;
904 case MAN_MACRONIX:
905 if (extract32(s->volatile_cfg, 6, 2) == 1) {
906 s->needed_bytes += 6;
907 } else {
908 s->needed_bytes += 8;
909 }
910 break;
911 case MAN_SPANSION:
912 s->needed_bytes += extract32(s->spansion_cr2v,
913 SPANSION_DUMMY_CLK_POS,
914 SPANSION_DUMMY_CLK_LEN
915 );
916 break;
917 case MAN_ISSI:
918 /*
919 * The Fast Read instruction code is followed by address bytes and
920 * dummy cycles, transmitted via the SI line.
921 *
922 * The number of dummy cycles is configurable but this is currently
923 * unmodeled, hence the default value 8 is used.
924 *
925 * QPI (Quad Peripheral Interface) mode has different default value
926 * of dummy cycles, but this is unsupported at the time being.
927 */
928 s->needed_bytes += 1;
929 break;
930 default:
931 break;
932 }
933 s->pos = 0;
934 s->len = 0;
935 s->state = STATE_COLLECTING_DATA;
936 }
937
938 static void decode_dio_read_cmd(Flash *s)
939 {
940 s->needed_bytes = get_addr_length(s);
941 /* Dummy cycles modeled with bytes writes instead of bits */
942 switch (get_man(s)) {
943 case MAN_WINBOND:
944 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
945 break;
946 case MAN_SPANSION:
947 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
948 s->needed_bytes += extract32(s->spansion_cr2v,
949 SPANSION_DUMMY_CLK_POS,
950 SPANSION_DUMMY_CLK_LEN
951 );
952 break;
953 case MAN_NUMONYX:
954 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
955 break;
956 case MAN_MACRONIX:
957 switch (extract32(s->volatile_cfg, 6, 2)) {
958 case 1:
959 s->needed_bytes += 6;
960 break;
961 case 2:
962 s->needed_bytes += 8;
963 break;
964 default:
965 s->needed_bytes += 4;
966 break;
967 }
968 break;
969 case MAN_ISSI:
970 /*
971 * The Fast Read Dual I/O instruction code is followed by address bytes
972 * and dummy cycles, transmitted via the IO1 and IO0 line.
973 *
974 * The number of dummy cycles is configurable but this is currently
975 * unmodeled, hence the default value 4 is used.
976 */
977 s->needed_bytes += 1;
978 break;
979 default:
980 break;
981 }
982 s->pos = 0;
983 s->len = 0;
984 s->state = STATE_COLLECTING_DATA;
985 }
986
987 static void decode_qio_read_cmd(Flash *s)
988 {
989 s->needed_bytes = get_addr_length(s);
990 /* Dummy cycles modeled with bytes writes instead of bits */
991 switch (get_man(s)) {
992 case MAN_WINBOND:
993 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
994 s->needed_bytes += 4;
995 break;
996 case MAN_SPANSION:
997 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
998 s->needed_bytes += extract32(s->spansion_cr2v,
999 SPANSION_DUMMY_CLK_POS,
1000 SPANSION_DUMMY_CLK_LEN
1001 );
1002 break;
1003 case MAN_NUMONYX:
1004 s->needed_bytes += numonyx_extract_cfg_num_dummies(s);
1005 break;
1006 case MAN_MACRONIX:
1007 switch (extract32(s->volatile_cfg, 6, 2)) {
1008 case 1:
1009 s->needed_bytes += 4;
1010 break;
1011 case 2:
1012 s->needed_bytes += 8;
1013 break;
1014 default:
1015 s->needed_bytes += 6;
1016 break;
1017 }
1018 break;
1019 case MAN_ISSI:
1020 /*
1021 * The Fast Read Quad I/O instruction code is followed by address bytes
1022 * and dummy cycles, transmitted via the IO3, IO2, IO1 and IO0 line.
1023 *
1024 * The number of dummy cycles is configurable but this is currently
1025 * unmodeled, hence the default value 6 is used.
1026 *
1027 * QPI (Quad Peripheral Interface) mode has different default value
1028 * of dummy cycles, but this is unsupported at the time being.
1029 */
1030 s->needed_bytes += 3;
1031 break;
1032 default:
1033 break;
1034 }
1035 s->pos = 0;
1036 s->len = 0;
1037 s->state = STATE_COLLECTING_DATA;
1038 }
1039
1040 static bool is_valid_aai_cmd(uint32_t cmd)
1041 {
1042 return cmd == AAI_WP || cmd == WRDI || cmd == RDSR;
1043 }
1044
1045 static void decode_new_cmd(Flash *s, uint32_t value)
1046 {
1047 int i;
1048
1049 s->cmd_in_progress = value;
1050 trace_m25p80_command_decoded(s, value);
1051
1052 if (value != RESET_MEMORY) {
1053 s->reset_enable = false;
1054 }
1055
1056 if (get_man(s) == MAN_SST && s->aai_enable && !is_valid_aai_cmd(value)) {
1057 qemu_log_mask(LOG_GUEST_ERROR,
1058 "M25P80: Invalid cmd within AAI programming sequence");
1059 }
1060
1061 switch (value) {
1062
1063 case ERASE_4K:
1064 case ERASE4_4K:
1065 case ERASE_32K:
1066 case ERASE4_32K:
1067 case ERASE_SECTOR:
1068 case ERASE4_SECTOR:
1069 case PP:
1070 case PP4:
1071 case DIE_ERASE:
1072 case RDID_90:
1073 case RDID_AB:
1074 s->needed_bytes = get_addr_length(s);
1075 s->pos = 0;
1076 s->len = 0;
1077 s->state = STATE_COLLECTING_DATA;
1078 break;
1079 case READ:
1080 case READ4:
1081 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1082 s->needed_bytes = get_addr_length(s);
1083 s->pos = 0;
1084 s->len = 0;
1085 s->state = STATE_COLLECTING_DATA;
1086 } else {
1087 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1088 "DIO or QIO mode\n", s->cmd_in_progress);
1089 }
1090 break;
1091 case DPP:
1092 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1093 s->needed_bytes = get_addr_length(s);
1094 s->pos = 0;
1095 s->len = 0;
1096 s->state = STATE_COLLECTING_DATA;
1097 } else {
1098 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1099 "QIO mode\n", s->cmd_in_progress);
1100 }
1101 break;
1102 case QPP:
1103 case QPP_4:
1104 case PP4_4:
1105 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1106 s->needed_bytes = get_addr_length(s);
1107 s->pos = 0;
1108 s->len = 0;
1109 s->state = STATE_COLLECTING_DATA;
1110 } else {
1111 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1112 "DIO mode\n", s->cmd_in_progress);
1113 }
1114 break;
1115
1116 case FAST_READ:
1117 case FAST_READ4:
1118 decode_fast_read_cmd(s);
1119 break;
1120 case DOR:
1121 case DOR4:
1122 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1123 decode_fast_read_cmd(s);
1124 } else {
1125 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1126 "QIO mode\n", s->cmd_in_progress);
1127 }
1128 break;
1129 case QOR:
1130 case QOR4:
1131 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1132 decode_fast_read_cmd(s);
1133 } else {
1134 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1135 "DIO mode\n", s->cmd_in_progress);
1136 }
1137 break;
1138
1139 case DIOR:
1140 case DIOR4:
1141 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_QIO) {
1142 decode_dio_read_cmd(s);
1143 } else {
1144 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1145 "QIO mode\n", s->cmd_in_progress);
1146 }
1147 break;
1148
1149 case QIOR:
1150 case QIOR4:
1151 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) != MODE_DIO) {
1152 decode_qio_read_cmd(s);
1153 } else {
1154 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute cmd %x in "
1155 "DIO mode\n", s->cmd_in_progress);
1156 }
1157 break;
1158
1159 case WRSR:
1160 if (s->write_enable) {
1161 switch (get_man(s)) {
1162 case MAN_SPANSION:
1163 s->needed_bytes = 2;
1164 s->state = STATE_COLLECTING_DATA;
1165 break;
1166 case MAN_MACRONIX:
1167 s->needed_bytes = 2;
1168 s->state = STATE_COLLECTING_VAR_LEN_DATA;
1169 break;
1170 default:
1171 s->needed_bytes = 1;
1172 s->state = STATE_COLLECTING_DATA;
1173 }
1174 s->pos = 0;
1175 }
1176 break;
1177
1178 case WRDI:
1179 s->write_enable = false;
1180 if (get_man(s) == MAN_SST) {
1181 s->aai_enable = false;
1182 }
1183 break;
1184 case WREN:
1185 s->write_enable = true;
1186 break;
1187
1188 case RDSR:
1189 s->data[0] = (!!s->write_enable) << 1;
1190 if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {
1191 s->data[0] |= (!!s->quad_enable) << 6;
1192 }
1193 if (get_man(s) == MAN_SST) {
1194 s->data[0] |= (!!s->aai_enable) << 6;
1195 }
1196
1197 s->pos = 0;
1198 s->len = 1;
1199 s->data_read_loop = true;
1200 s->state = STATE_READING_DATA;
1201 break;
1202
1203 case READ_FSR:
1204 s->data[0] = FSR_FLASH_READY;
1205 if (s->four_bytes_address_mode) {
1206 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
1207 }
1208 s->pos = 0;
1209 s->len = 1;
1210 s->data_read_loop = true;
1211 s->state = STATE_READING_DATA;
1212 break;
1213
1214 case JEDEC_READ:
1215 if (get_man(s) != MAN_NUMONYX || numonyx_mode(s) == MODE_STD) {
1216 trace_m25p80_populated_jedec(s);
1217 for (i = 0; i < s->pi->id_len; i++) {
1218 s->data[i] = s->pi->id[i];
1219 }
1220 for (; i < SPI_NOR_MAX_ID_LEN; i++) {
1221 s->data[i] = 0;
1222 }
1223
1224 s->len = SPI_NOR_MAX_ID_LEN;
1225 s->pos = 0;
1226 s->state = STATE_READING_DATA;
1227 } else {
1228 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Cannot execute JEDEC read "
1229 "in DIO or QIO mode\n");
1230 }
1231 break;
1232
1233 case RDCR:
1234 s->data[0] = s->volatile_cfg & 0xFF;
1235 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
1236 s->pos = 0;
1237 s->len = 1;
1238 s->state = STATE_READING_DATA;
1239 break;
1240
1241 case BULK_ERASE_60:
1242 case BULK_ERASE:
1243 if (s->write_enable) {
1244 trace_m25p80_chip_erase(s);
1245 flash_erase(s, 0, BULK_ERASE);
1246 } else {
1247 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
1248 "protect!\n");
1249 }
1250 break;
1251 case NOP:
1252 break;
1253 case EN_4BYTE_ADDR:
1254 s->four_bytes_address_mode = true;
1255 break;
1256 case EX_4BYTE_ADDR:
1257 s->four_bytes_address_mode = false;
1258 break;
1259 case BRRD:
1260 case EXTEND_ADDR_READ:
1261 s->data[0] = s->ear;
1262 s->pos = 0;
1263 s->len = 1;
1264 s->state = STATE_READING_DATA;
1265 break;
1266 case BRWR:
1267 case EXTEND_ADDR_WRITE:
1268 if (s->write_enable) {
1269 s->needed_bytes = 1;
1270 s->pos = 0;
1271 s->len = 0;
1272 s->state = STATE_COLLECTING_DATA;
1273 }
1274 break;
1275 case RNVCR:
1276 s->data[0] = s->nonvolatile_cfg & 0xFF;
1277 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1278 s->pos = 0;
1279 s->len = 2;
1280 s->state = STATE_READING_DATA;
1281 break;
1282 case WNVCR:
1283 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1284 s->needed_bytes = 2;
1285 s->pos = 0;
1286 s->len = 0;
1287 s->state = STATE_COLLECTING_DATA;
1288 }
1289 break;
1290 case RVCR:
1291 s->data[0] = s->volatile_cfg & 0xFF;
1292 s->pos = 0;
1293 s->len = 1;
1294 s->state = STATE_READING_DATA;
1295 break;
1296 case WVCR:
1297 if (s->write_enable) {
1298 s->needed_bytes = 1;
1299 s->pos = 0;
1300 s->len = 0;
1301 s->state = STATE_COLLECTING_DATA;
1302 }
1303 break;
1304 case REVCR:
1305 s->data[0] = s->enh_volatile_cfg & 0xFF;
1306 s->pos = 0;
1307 s->len = 1;
1308 s->state = STATE_READING_DATA;
1309 break;
1310 case WEVCR:
1311 if (s->write_enable) {
1312 s->needed_bytes = 1;
1313 s->pos = 0;
1314 s->len = 0;
1315 s->state = STATE_COLLECTING_DATA;
1316 }
1317 break;
1318 case RESET_ENABLE:
1319 s->reset_enable = true;
1320 break;
1321 case RESET_MEMORY:
1322 if (s->reset_enable) {
1323 reset_memory(s);
1324 }
1325 break;
1326 case RDCR_EQIO:
1327 switch (get_man(s)) {
1328 case MAN_SPANSION:
1329 s->data[0] = (!!s->quad_enable) << 1;
1330 s->pos = 0;
1331 s->len = 1;
1332 s->state = STATE_READING_DATA;
1333 break;
1334 case MAN_MACRONIX:
1335 s->quad_enable = true;
1336 break;
1337 default:
1338 break;
1339 }
1340 break;
1341 case RSTQIO:
1342 s->quad_enable = false;
1343 break;
1344 case AAI_WP:
1345 if (get_man(s) == MAN_SST) {
1346 if (s->write_enable) {
1347 if (s->aai_enable) {
1348 s->state = STATE_PAGE_PROGRAM;
1349 } else {
1350 s->aai_enable = true;
1351 s->needed_bytes = get_addr_length(s);
1352 s->state = STATE_COLLECTING_DATA;
1353 }
1354 } else {
1355 qemu_log_mask(LOG_GUEST_ERROR,
1356 "M25P80: AAI_WP with write protect\n");
1357 }
1358 } else {
1359 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1360 }
1361 break;
1362 default:
1363 s->pos = 0;
1364 s->len = 1;
1365 s->state = STATE_READING_DATA;
1366 s->data_read_loop = true;
1367 s->data[0] = 0;
1368 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1369 break;
1370 }
1371 }
1372
1373 static int m25p80_cs(SSIPeripheral *ss, bool select)
1374 {
1375 Flash *s = M25P80(ss);
1376
1377 if (select) {
1378 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1379 complete_collecting_data(s);
1380 }
1381 s->len = 0;
1382 s->pos = 0;
1383 s->state = STATE_IDLE;
1384 flash_sync_dirty(s, -1);
1385 s->data_read_loop = false;
1386 }
1387
1388 trace_m25p80_select(s, select ? "de" : "");
1389
1390 return 0;
1391 }
1392
1393 static uint32_t m25p80_transfer8(SSIPeripheral *ss, uint32_t tx)
1394 {
1395 Flash *s = M25P80(ss);
1396 uint32_t r = 0;
1397
1398 trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
1399 s->cur_addr, (uint8_t)tx);
1400
1401 switch (s->state) {
1402
1403 case STATE_PAGE_PROGRAM:
1404 trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
1405 flash_write8(s, s->cur_addr, (uint8_t)tx);
1406 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1407
1408 if (get_man(s) == MAN_SST && s->aai_enable && s->cur_addr == 0) {
1409 /*
1410 * There is no wrap mode during AAI programming once the highest
1411 * unprotected memory address is reached. The Write-Enable-Latch
1412 * bit is automatically reset, and AAI programming mode aborts.
1413 */
1414 s->write_enable = false;
1415 s->aai_enable = false;
1416 }
1417
1418 break;
1419
1420 case STATE_READ:
1421 r = s->storage[s->cur_addr];
1422 trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
1423 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1424 break;
1425
1426 case STATE_COLLECTING_DATA:
1427 case STATE_COLLECTING_VAR_LEN_DATA:
1428
1429 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1430 qemu_log_mask(LOG_GUEST_ERROR,
1431 "M25P80: Write overrun internal data buffer. "
1432 "SPI controller (QEMU emulator or guest driver) "
1433 "is misbehaving\n");
1434 s->len = s->pos = 0;
1435 s->state = STATE_IDLE;
1436 break;
1437 }
1438
1439 s->data[s->len] = (uint8_t)tx;
1440 s->len++;
1441
1442 if (s->len == s->needed_bytes) {
1443 complete_collecting_data(s);
1444 }
1445 break;
1446
1447 case STATE_READING_DATA:
1448
1449 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1450 qemu_log_mask(LOG_GUEST_ERROR,
1451 "M25P80: Read overrun internal data buffer. "
1452 "SPI controller (QEMU emulator or guest driver) "
1453 "is misbehaving\n");
1454 s->len = s->pos = 0;
1455 s->state = STATE_IDLE;
1456 break;
1457 }
1458
1459 r = s->data[s->pos];
1460 trace_m25p80_read_data(s, s->pos, (uint8_t)r);
1461 s->pos++;
1462 if (s->pos == s->len) {
1463 s->pos = 0;
1464 if (!s->data_read_loop) {
1465 s->state = STATE_IDLE;
1466 }
1467 }
1468 break;
1469
1470 default:
1471 case STATE_IDLE:
1472 decode_new_cmd(s, (uint8_t)tx);
1473 break;
1474 }
1475
1476 return r;
1477 }
1478
1479 static void m25p80_realize(SSIPeripheral *ss, Error **errp)
1480 {
1481 Flash *s = M25P80(ss);
1482 M25P80Class *mc = M25P80_GET_CLASS(s);
1483 int ret;
1484
1485 s->pi = mc->pi;
1486
1487 s->size = s->pi->sector_size * s->pi->n_sectors;
1488 s->dirty_page = -1;
1489
1490 if (s->blk) {
1491 uint64_t perm = BLK_PERM_CONSISTENT_READ |
1492 (blk_supports_write_perm(s->blk) ? BLK_PERM_WRITE : 0);
1493 ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp);
1494 if (ret < 0) {
1495 return;
1496 }
1497
1498 trace_m25p80_binding(s);
1499 s->storage = blk_blockalign(s->blk, s->size);
1500
1501 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1502 error_setg(errp, "failed to read the initial flash content");
1503 return;
1504 }
1505 } else {
1506 trace_m25p80_binding_no_bdrv(s);
1507 s->storage = blk_blockalign(NULL, s->size);
1508 memset(s->storage, 0xFF, s->size);
1509 }
1510 }
1511
1512 static void m25p80_reset(DeviceState *d)
1513 {
1514 Flash *s = M25P80(d);
1515
1516 reset_memory(s);
1517 }
1518
1519 static int m25p80_pre_save(void *opaque)
1520 {
1521 flash_sync_dirty((Flash *)opaque, -1);
1522
1523 return 0;
1524 }
1525
1526 static Property m25p80_properties[] = {
1527 /* This is default value for Micron flash */
1528 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1529 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1530 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1531 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1532 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1533 DEFINE_PROP_DRIVE("drive", Flash, blk),
1534 DEFINE_PROP_END_OF_LIST(),
1535 };
1536
1537 static int m25p80_pre_load(void *opaque)
1538 {
1539 Flash *s = (Flash *)opaque;
1540
1541 s->data_read_loop = false;
1542 return 0;
1543 }
1544
1545 static bool m25p80_data_read_loop_needed(void *opaque)
1546 {
1547 Flash *s = (Flash *)opaque;
1548
1549 return s->data_read_loop;
1550 }
1551
1552 static const VMStateDescription vmstate_m25p80_data_read_loop = {
1553 .name = "m25p80/data_read_loop",
1554 .version_id = 1,
1555 .minimum_version_id = 1,
1556 .needed = m25p80_data_read_loop_needed,
1557 .fields = (VMStateField[]) {
1558 VMSTATE_BOOL(data_read_loop, Flash),
1559 VMSTATE_END_OF_LIST()
1560 }
1561 };
1562
1563 static bool m25p80_aai_enable_needed(void *opaque)
1564 {
1565 Flash *s = (Flash *)opaque;
1566
1567 return s->aai_enable;
1568 }
1569
1570 static const VMStateDescription vmstate_m25p80_aai_enable = {
1571 .name = "m25p80/aai_enable",
1572 .version_id = 1,
1573 .minimum_version_id = 1,
1574 .needed = m25p80_aai_enable_needed,
1575 .fields = (VMStateField[]) {
1576 VMSTATE_BOOL(aai_enable, Flash),
1577 VMSTATE_END_OF_LIST()
1578 }
1579 };
1580
1581 static const VMStateDescription vmstate_m25p80 = {
1582 .name = "m25p80",
1583 .version_id = 0,
1584 .minimum_version_id = 0,
1585 .pre_save = m25p80_pre_save,
1586 .pre_load = m25p80_pre_load,
1587 .fields = (VMStateField[]) {
1588 VMSTATE_UINT8(state, Flash),
1589 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1590 VMSTATE_UINT32(len, Flash),
1591 VMSTATE_UINT32(pos, Flash),
1592 VMSTATE_UINT8(needed_bytes, Flash),
1593 VMSTATE_UINT8(cmd_in_progress, Flash),
1594 VMSTATE_UINT32(cur_addr, Flash),
1595 VMSTATE_BOOL(write_enable, Flash),
1596 VMSTATE_BOOL(reset_enable, Flash),
1597 VMSTATE_UINT8(ear, Flash),
1598 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1599 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1600 VMSTATE_UINT32(volatile_cfg, Flash),
1601 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1602 VMSTATE_BOOL(quad_enable, Flash),
1603 VMSTATE_UINT8(spansion_cr1nv, Flash),
1604 VMSTATE_UINT8(spansion_cr2nv, Flash),
1605 VMSTATE_UINT8(spansion_cr3nv, Flash),
1606 VMSTATE_UINT8(spansion_cr4nv, Flash),
1607 VMSTATE_END_OF_LIST()
1608 },
1609 .subsections = (const VMStateDescription * []) {
1610 &vmstate_m25p80_data_read_loop,
1611 &vmstate_m25p80_aai_enable,
1612 NULL
1613 }
1614 };
1615
1616 static void m25p80_class_init(ObjectClass *klass, void *data)
1617 {
1618 DeviceClass *dc = DEVICE_CLASS(klass);
1619 SSIPeripheralClass *k = SSI_PERIPHERAL_CLASS(klass);
1620 M25P80Class *mc = M25P80_CLASS(klass);
1621
1622 k->realize = m25p80_realize;
1623 k->transfer = m25p80_transfer8;
1624 k->set_cs = m25p80_cs;
1625 k->cs_polarity = SSI_CS_LOW;
1626 dc->vmsd = &vmstate_m25p80;
1627 device_class_set_props(dc, m25p80_properties);
1628 dc->reset = m25p80_reset;
1629 mc->pi = data;
1630 }
1631
1632 static const TypeInfo m25p80_info = {
1633 .name = TYPE_M25P80,
1634 .parent = TYPE_SSI_PERIPHERAL,
1635 .instance_size = sizeof(Flash),
1636 .class_size = sizeof(M25P80Class),
1637 .abstract = true,
1638 };
1639
1640 static void m25p80_register_types(void)
1641 {
1642 int i;
1643
1644 type_register_static(&m25p80_info);
1645 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1646 TypeInfo ti = {
1647 .name = known_devices[i].part_name,
1648 .parent = TYPE_M25P80,
1649 .class_init = m25p80_class_init,
1650 .class_data = (void *)&known_devices[i],
1651 };
1652 type_register(&ti);
1653 }
1654 }
1655
1656 type_init(m25p80_register_types)
QEmu