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target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEF
[qemu.git] / target-arm / translate.c
blobbe25c8f33ae689993adb4a0a438b77a600fd999a
1 /*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include <stdarg.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <string.h>
25 #include <inttypes.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "qemu-log.h"
32
33 #include "helpers.h"
34 #define GEN_HELPER 1
35 #include "helpers.h"
36
37 #define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T)
38 #define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5)
39 /* currently all emulated v5 cores are also v5TE, so don't bother */
40 #define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5)
41 #define ENABLE_ARCH_5J 0
42 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
43 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
44 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
45 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
46
47 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
48
49 /* internal defines */
50 typedef struct DisasContext {
51 target_ulong pc;
52 int is_jmp;
53 /* Nonzero if this instruction has been conditionally skipped. */
54 int condjmp;
55 /* The label that will be jumped to when the instruction is skipped. */
56 int condlabel;
57 /* Thumb-2 condtional execution bits. */
58 int condexec_mask;
59 int condexec_cond;
60 struct TranslationBlock *tb;
61 int singlestep_enabled;
62 int thumb;
63 #if !defined(CONFIG_USER_ONLY)
64 int user;
65 #endif
66 int vfp_enabled;
67 int vec_len;
68 int vec_stride;
69 } DisasContext;
70
71 static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
72
73 #if defined(CONFIG_USER_ONLY)
74 #define IS_USER(s) 1
75 #else
76 #define IS_USER(s) (s->user)
77 #endif
78
79 /* These instructions trap after executing, so defer them until after the
80 conditional executions state has been updated. */
81 #define DISAS_WFI 4
82 #define DISAS_SWI 5
83
84 static TCGv_ptr cpu_env;
85 /* We reuse the same 64-bit temporaries for efficiency. */
86 static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
87 static TCGv_i32 cpu_R[16];
88 static TCGv_i32 cpu_exclusive_addr;
89 static TCGv_i32 cpu_exclusive_val;
90 static TCGv_i32 cpu_exclusive_high;
91 #ifdef CONFIG_USER_ONLY
92 static TCGv_i32 cpu_exclusive_test;
93 static TCGv_i32 cpu_exclusive_info;
94 #endif
95
96 /* FIXME: These should be removed. */
97 static TCGv cpu_F0s, cpu_F1s;
98 static TCGv_i64 cpu_F0d, cpu_F1d;
99
100 #include "gen-icount.h"
101
102 static const char *regnames[] =
103 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
105
106 /* initialize TCG globals. */
107 void arm_translate_init(void)
108 {
109 int i;
110
111 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
112
113 for (i = 0; i < 16; i++) {
114 cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
115 offsetof(CPUState, regs[i]),
116 regnames[i]);
117 }
118 cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
119 offsetof(CPUState, exclusive_addr), "exclusive_addr");
120 cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
121 offsetof(CPUState, exclusive_val), "exclusive_val");
122 cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
123 offsetof(CPUState, exclusive_high), "exclusive_high");
124 #ifdef CONFIG_USER_ONLY
125 cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
126 offsetof(CPUState, exclusive_test), "exclusive_test");
127 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
128 offsetof(CPUState, exclusive_info), "exclusive_info");
129 #endif
130
131 #define GEN_HELPER 2
132 #include "helpers.h"
133 }
134
135 static inline TCGv load_cpu_offset(int offset)
136 {
137 TCGv tmp = tcg_temp_new_i32();
138 tcg_gen_ld_i32(tmp, cpu_env, offset);
139 return tmp;
140 }
141
142 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
143
144 static inline void store_cpu_offset(TCGv var, int offset)
145 {
146 tcg_gen_st_i32(var, cpu_env, offset);
147 tcg_temp_free_i32(var);
148 }
149
150 #define store_cpu_field(var, name) \
151 store_cpu_offset(var, offsetof(CPUState, name))
152
153 /* Set a variable to the value of a CPU register. */
154 static void load_reg_var(DisasContext *s, TCGv var, int reg)
155 {
156 if (reg == 15) {
157 uint32_t addr;
158 /* normaly, since we updated PC, we need only to add one insn */
159 if (s->thumb)
160 addr = (long)s->pc + 2;
161 else
162 addr = (long)s->pc + 4;
163 tcg_gen_movi_i32(var, addr);
164 } else {
165 tcg_gen_mov_i32(var, cpu_R[reg]);
166 }
167 }
168
169 /* Create a new temporary and set it to the value of a CPU register. */
170 static inline TCGv load_reg(DisasContext *s, int reg)
171 {
172 TCGv tmp = tcg_temp_new_i32();
173 load_reg_var(s, tmp, reg);
174 return tmp;
175 }
176
177 /* Set a CPU register. The source must be a temporary and will be
178 marked as dead. */
179 static void store_reg(DisasContext *s, int reg, TCGv var)
180 {
181 if (reg == 15) {
182 tcg_gen_andi_i32(var, var, ~1);
183 s->is_jmp = DISAS_JUMP;
184 }
185 tcg_gen_mov_i32(cpu_R[reg], var);
186 tcg_temp_free_i32(var);
187 }
188
189 /* Value extensions. */
190 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
191 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
192 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
193 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
194
195 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
196 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
197
198
199 static inline void gen_set_cpsr(TCGv var, uint32_t mask)
200 {
201 TCGv tmp_mask = tcg_const_i32(mask);
202 gen_helper_cpsr_write(var, tmp_mask);
203 tcg_temp_free_i32(tmp_mask);
204 }
205 /* Set NZCV flags from the high 4 bits of var. */
206 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
207
208 static void gen_exception(int excp)
209 {
210 TCGv tmp = tcg_temp_new_i32();
211 tcg_gen_movi_i32(tmp, excp);
212 gen_helper_exception(tmp);
213 tcg_temp_free_i32(tmp);
214 }
215
216 static void gen_smul_dual(TCGv a, TCGv b)
217 {
218 TCGv tmp1 = tcg_temp_new_i32();
219 TCGv tmp2 = tcg_temp_new_i32();
220 tcg_gen_ext16s_i32(tmp1, a);
221 tcg_gen_ext16s_i32(tmp2, b);
222 tcg_gen_mul_i32(tmp1, tmp1, tmp2);
223 tcg_temp_free_i32(tmp2);
224 tcg_gen_sari_i32(a, a, 16);
225 tcg_gen_sari_i32(b, b, 16);
226 tcg_gen_mul_i32(b, b, a);
227 tcg_gen_mov_i32(a, tmp1);
228 tcg_temp_free_i32(tmp1);
229 }
230
231 /* Byteswap each halfword. */
232 static void gen_rev16(TCGv var)
233 {
234 TCGv tmp = tcg_temp_new_i32();
235 tcg_gen_shri_i32(tmp, var, 8);
236 tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
237 tcg_gen_shli_i32(var, var, 8);
238 tcg_gen_andi_i32(var, var, 0xff00ff00);
239 tcg_gen_or_i32(var, var, tmp);
240 tcg_temp_free_i32(tmp);
241 }
242
243 /* Byteswap low halfword and sign extend. */
244 static void gen_revsh(TCGv var)
245 {
246 tcg_gen_ext16u_i32(var, var);
247 tcg_gen_bswap16_i32(var, var);
248 tcg_gen_ext16s_i32(var, var);
249 }
250
251 /* Unsigned bitfield extract. */
252 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
253 {
254 if (shift)
255 tcg_gen_shri_i32(var, var, shift);
256 tcg_gen_andi_i32(var, var, mask);
257 }
258
259 /* Signed bitfield extract. */
260 static void gen_sbfx(TCGv var, int shift, int width)
261 {
262 uint32_t signbit;
263
264 if (shift)
265 tcg_gen_sari_i32(var, var, shift);
266 if (shift + width < 32) {
267 signbit = 1u << (width - 1);
268 tcg_gen_andi_i32(var, var, (1u << width) - 1);
269 tcg_gen_xori_i32(var, var, signbit);
270 tcg_gen_subi_i32(var, var, signbit);
271 }
272 }
273
274 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
275 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
276 {
277 tcg_gen_andi_i32(val, val, mask);
278 tcg_gen_shli_i32(val, val, shift);
279 tcg_gen_andi_i32(base, base, ~(mask << shift));
280 tcg_gen_or_i32(dest, base, val);
281 }
282
283 /* Return (b << 32) + a. Mark inputs as dead */
284 static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv b)
285 {
286 TCGv_i64 tmp64 = tcg_temp_new_i64();
287
288 tcg_gen_extu_i32_i64(tmp64, b);
289 tcg_temp_free_i32(b);
290 tcg_gen_shli_i64(tmp64, tmp64, 32);
291 tcg_gen_add_i64(a, tmp64, a);
292
293 tcg_temp_free_i64(tmp64);
294 return a;
295 }
296
297 /* Return (b << 32) - a. Mark inputs as dead. */
298 static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv b)
299 {
300 TCGv_i64 tmp64 = tcg_temp_new_i64();
301
302 tcg_gen_extu_i32_i64(tmp64, b);
303 tcg_temp_free_i32(b);
304 tcg_gen_shli_i64(tmp64, tmp64, 32);
305 tcg_gen_sub_i64(a, tmp64, a);
306
307 tcg_temp_free_i64(tmp64);
308 return a;
309 }
310
311 /* FIXME: Most targets have native widening multiplication.
312 It would be good to use that instead of a full wide multiply. */
313 /* 32x32->64 multiply. Marks inputs as dead. */
314 static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b)
315 {
316 TCGv_i64 tmp1 = tcg_temp_new_i64();
317 TCGv_i64 tmp2 = tcg_temp_new_i64();
318
319 tcg_gen_extu_i32_i64(tmp1, a);
320 tcg_temp_free_i32(a);
321 tcg_gen_extu_i32_i64(tmp2, b);
322 tcg_temp_free_i32(b);
323 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
324 tcg_temp_free_i64(tmp2);
325 return tmp1;
326 }
327
328 static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b)
329 {
330 TCGv_i64 tmp1 = tcg_temp_new_i64();
331 TCGv_i64 tmp2 = tcg_temp_new_i64();
332
333 tcg_gen_ext_i32_i64(tmp1, a);
334 tcg_temp_free_i32(a);
335 tcg_gen_ext_i32_i64(tmp2, b);
336 tcg_temp_free_i32(b);
337 tcg_gen_mul_i64(tmp1, tmp1, tmp2);
338 tcg_temp_free_i64(tmp2);
339 return tmp1;
340 }
341
342 /* Swap low and high halfwords. */
343 static void gen_swap_half(TCGv var)
344 {
345 TCGv tmp = tcg_temp_new_i32();
346 tcg_gen_shri_i32(tmp, var, 16);
347 tcg_gen_shli_i32(var, var, 16);
348 tcg_gen_or_i32(var, var, tmp);
349 tcg_temp_free_i32(tmp);
350 }
351
352 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
353 tmp = (t0 ^ t1) & 0x8000;
354 t0 &= ~0x8000;
355 t1 &= ~0x8000;
356 t0 = (t0 + t1) ^ tmp;
357 */
358
359 static void gen_add16(TCGv t0, TCGv t1)
360 {
361 TCGv tmp = tcg_temp_new_i32();
362 tcg_gen_xor_i32(tmp, t0, t1);
363 tcg_gen_andi_i32(tmp, tmp, 0x8000);
364 tcg_gen_andi_i32(t0, t0, ~0x8000);
365 tcg_gen_andi_i32(t1, t1, ~0x8000);
366 tcg_gen_add_i32(t0, t0, t1);
367 tcg_gen_xor_i32(t0, t0, tmp);
368 tcg_temp_free_i32(tmp);
369 tcg_temp_free_i32(t1);
370 }
371
372 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
373
374 /* Set CF to the top bit of var. */
375 static void gen_set_CF_bit31(TCGv var)
376 {
377 TCGv tmp = tcg_temp_new_i32();
378 tcg_gen_shri_i32(tmp, var, 31);
379 gen_set_CF(tmp);
380 tcg_temp_free_i32(tmp);
381 }
382
383 /* Set N and Z flags from var. */
384 static inline void gen_logic_CC(TCGv var)
385 {
386 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
387 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
388 }
389
390 /* T0 += T1 + CF. */
391 static void gen_adc(TCGv t0, TCGv t1)
392 {
393 TCGv tmp;
394 tcg_gen_add_i32(t0, t0, t1);
395 tmp = load_cpu_field(CF);
396 tcg_gen_add_i32(t0, t0, tmp);
397 tcg_temp_free_i32(tmp);
398 }
399
400 /* dest = T0 + T1 + CF. */
401 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
402 {
403 TCGv tmp;
404 tcg_gen_add_i32(dest, t0, t1);
405 tmp = load_cpu_field(CF);
406 tcg_gen_add_i32(dest, dest, tmp);
407 tcg_temp_free_i32(tmp);
408 }
409
410 /* dest = T0 - T1 + CF - 1. */
411 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
412 {
413 TCGv tmp;
414 tcg_gen_sub_i32(dest, t0, t1);
415 tmp = load_cpu_field(CF);
416 tcg_gen_add_i32(dest, dest, tmp);
417 tcg_gen_subi_i32(dest, dest, 1);
418 tcg_temp_free_i32(tmp);
419 }
420
421 /* FIXME: Implement this natively. */
422 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
423
424 static void shifter_out_im(TCGv var, int shift)
425 {
426 TCGv tmp = tcg_temp_new_i32();
427 if (shift == 0) {
428 tcg_gen_andi_i32(tmp, var, 1);
429 } else {
430 tcg_gen_shri_i32(tmp, var, shift);
431 if (shift != 31)
432 tcg_gen_andi_i32(tmp, tmp, 1);
433 }
434 gen_set_CF(tmp);
435 tcg_temp_free_i32(tmp);
436 }
437
438 /* Shift by immediate. Includes special handling for shift == 0. */
439 static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags)
440 {
441 switch (shiftop) {
442 case 0: /* LSL */
443 if (shift != 0) {
444 if (flags)
445 shifter_out_im(var, 32 - shift);
446 tcg_gen_shli_i32(var, var, shift);
447 }
448 break;
449 case 1: /* LSR */
450 if (shift == 0) {
451 if (flags) {
452 tcg_gen_shri_i32(var, var, 31);
453 gen_set_CF(var);
454 }
455 tcg_gen_movi_i32(var, 0);
456 } else {
457 if (flags)
458 shifter_out_im(var, shift - 1);
459 tcg_gen_shri_i32(var, var, shift);
460 }
461 break;
462 case 2: /* ASR */
463 if (shift == 0)
464 shift = 32;
465 if (flags)
466 shifter_out_im(var, shift - 1);
467 if (shift == 32)
468 shift = 31;
469 tcg_gen_sari_i32(var, var, shift);
470 break;
471 case 3: /* ROR/RRX */
472 if (shift != 0) {
473 if (flags)
474 shifter_out_im(var, shift - 1);
475 tcg_gen_rotri_i32(var, var, shift); break;
476 } else {
477 TCGv tmp = load_cpu_field(CF);
478 if (flags)
479 shifter_out_im(var, 0);
480 tcg_gen_shri_i32(var, var, 1);
481 tcg_gen_shli_i32(tmp, tmp, 31);
482 tcg_gen_or_i32(var, var, tmp);
483 tcg_temp_free_i32(tmp);
484 }
485 }
486 };
487
488 static inline void gen_arm_shift_reg(TCGv var, int shiftop,
489 TCGv shift, int flags)
490 {
491 if (flags) {
492 switch (shiftop) {
493 case 0: gen_helper_shl_cc(var, var, shift); break;
494 case 1: gen_helper_shr_cc(var, var, shift); break;
495 case 2: gen_helper_sar_cc(var, var, shift); break;
496 case 3: gen_helper_ror_cc(var, var, shift); break;
497 }
498 } else {
499 switch (shiftop) {
500 case 0: gen_helper_shl(var, var, shift); break;
501 case 1: gen_helper_shr(var, var, shift); break;
502 case 2: gen_helper_sar(var, var, shift); break;
503 case 3: tcg_gen_andi_i32(shift, shift, 0x1f);
504 tcg_gen_rotr_i32(var, var, shift); break;
505 }
506 }
507 tcg_temp_free_i32(shift);
508 }
509
510 #define PAS_OP(pfx) \
511 switch (op2) { \
512 case 0: gen_pas_helper(glue(pfx,add16)); break; \
513 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
514 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
515 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
516 case 4: gen_pas_helper(glue(pfx,add8)); break; \
517 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
518 }
519 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
520 {
521 TCGv_ptr tmp;
522
523 switch (op1) {
524 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
525 case 1:
526 tmp = tcg_temp_new_ptr();
527 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
528 PAS_OP(s)
529 tcg_temp_free_ptr(tmp);
530 break;
531 case 5:
532 tmp = tcg_temp_new_ptr();
533 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
534 PAS_OP(u)
535 tcg_temp_free_ptr(tmp);
536 break;
537 #undef gen_pas_helper
538 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
539 case 2:
540 PAS_OP(q);
541 break;
542 case 3:
543 PAS_OP(sh);
544 break;
545 case 6:
546 PAS_OP(uq);
547 break;
548 case 7:
549 PAS_OP(uh);
550 break;
551 #undef gen_pas_helper
552 }
553 }
554 #undef PAS_OP
555
556 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
557 #define PAS_OP(pfx) \
558 switch (op1) { \
559 case 0: gen_pas_helper(glue(pfx,add8)); break; \
560 case 1: gen_pas_helper(glue(pfx,add16)); break; \
561 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
562 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
563 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
564 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
565 }
566 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
567 {
568 TCGv_ptr tmp;
569
570 switch (op2) {
571 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
572 case 0:
573 tmp = tcg_temp_new_ptr();
574 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
575 PAS_OP(s)
576 tcg_temp_free_ptr(tmp);
577 break;
578 case 4:
579 tmp = tcg_temp_new_ptr();
580 tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
581 PAS_OP(u)
582 tcg_temp_free_ptr(tmp);
583 break;
584 #undef gen_pas_helper
585 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
586 case 1:
587 PAS_OP(q);
588 break;
589 case 2:
590 PAS_OP(sh);
591 break;
592 case 5:
593 PAS_OP(uq);
594 break;
595 case 6:
596 PAS_OP(uh);
597 break;
598 #undef gen_pas_helper
599 }
600 }
601 #undef PAS_OP
602
603 static void gen_test_cc(int cc, int label)
604 {
605 TCGv tmp;
606 TCGv tmp2;
607 int inv;
608
609 switch (cc) {
610 case 0: /* eq: Z */
611 tmp = load_cpu_field(ZF);
612 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
613 break;
614 case 1: /* ne: !Z */
615 tmp = load_cpu_field(ZF);
616 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
617 break;
618 case 2: /* cs: C */
619 tmp = load_cpu_field(CF);
620 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
621 break;
622 case 3: /* cc: !C */
623 tmp = load_cpu_field(CF);
624 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
625 break;
626 case 4: /* mi: N */
627 tmp = load_cpu_field(NF);
628 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
629 break;
630 case 5: /* pl: !N */
631 tmp = load_cpu_field(NF);
632 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
633 break;
634 case 6: /* vs: V */
635 tmp = load_cpu_field(VF);
636 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
637 break;
638 case 7: /* vc: !V */
639 tmp = load_cpu_field(VF);
640 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
641 break;
642 case 8: /* hi: C && !Z */
643 inv = gen_new_label();
644 tmp = load_cpu_field(CF);
645 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
646 tcg_temp_free_i32(tmp);
647 tmp = load_cpu_field(ZF);
648 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label);
649 gen_set_label(inv);
650 break;
651 case 9: /* ls: !C || Z */
652 tmp = load_cpu_field(CF);
653 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
654 tcg_temp_free_i32(tmp);
655 tmp = load_cpu_field(ZF);
656 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
657 break;
658 case 10: /* ge: N == V -> N ^ V == 0 */
659 tmp = load_cpu_field(VF);
660 tmp2 = load_cpu_field(NF);
661 tcg_gen_xor_i32(tmp, tmp, tmp2);
662 tcg_temp_free_i32(tmp2);
663 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
664 break;
665 case 11: /* lt: N != V -> N ^ V != 0 */
666 tmp = load_cpu_field(VF);
667 tmp2 = load_cpu_field(NF);
668 tcg_gen_xor_i32(tmp, tmp, tmp2);
669 tcg_temp_free_i32(tmp2);
670 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
671 break;
672 case 12: /* gt: !Z && N == V */
673 inv = gen_new_label();
674 tmp = load_cpu_field(ZF);
675 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv);
676 tcg_temp_free_i32(tmp);
677 tmp = load_cpu_field(VF);
678 tmp2 = load_cpu_field(NF);
679 tcg_gen_xor_i32(tmp, tmp, tmp2);
680 tcg_temp_free_i32(tmp2);
681 tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label);
682 gen_set_label(inv);
683 break;
684 case 13: /* le: Z || N != V */
685 tmp = load_cpu_field(ZF);
686 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
687 tcg_temp_free_i32(tmp);
688 tmp = load_cpu_field(VF);
689 tmp2 = load_cpu_field(NF);
690 tcg_gen_xor_i32(tmp, tmp, tmp2);
691 tcg_temp_free_i32(tmp2);
692 tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label);
693 break;
694 default:
695 fprintf(stderr, "Bad condition code 0x%x\n", cc);
696 abort();
697 }
698 tcg_temp_free_i32(tmp);
699 }
700
701 static const uint8_t table_logic_cc[16] = {
702 1, /* and */
703 1, /* xor */
704 0, /* sub */
705 0, /* rsb */
706 0, /* add */
707 0, /* adc */
708 0, /* sbc */
709 0, /* rsc */
710 1, /* andl */
711 1, /* xorl */
712 0, /* cmp */
713 0, /* cmn */
714 1, /* orr */
715 1, /* mov */
716 1, /* bic */
717 1, /* mvn */
718 };
719
720 /* Set PC and Thumb state from an immediate address. */
721 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
722 {
723 TCGv tmp;
724
725 s->is_jmp = DISAS_UPDATE;
726 if (s->thumb != (addr & 1)) {
727 tmp = tcg_temp_new_i32();
728 tcg_gen_movi_i32(tmp, addr & 1);
729 tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
730 tcg_temp_free_i32(tmp);
731 }
732 tcg_gen_movi_i32(cpu_R[15], addr & ~1);
733 }
734
735 /* Set PC and Thumb state from var. var is marked as dead. */
736 static inline void gen_bx(DisasContext *s, TCGv var)
737 {
738 s->is_jmp = DISAS_UPDATE;
739 tcg_gen_andi_i32(cpu_R[15], var, ~1);
740 tcg_gen_andi_i32(var, var, 1);
741 store_cpu_field(var, thumb);
742 }
743
744 /* Variant of store_reg which uses branch&exchange logic when storing
745 to r15 in ARM architecture v7 and above. The source must be a temporary
746 and will be marked as dead. */
747 static inline void store_reg_bx(CPUState *env, DisasContext *s,
748 int reg, TCGv var)
749 {
750 if (reg == 15 && ENABLE_ARCH_7) {
751 gen_bx(s, var);
752 } else {
753 store_reg(s, reg, var);
754 }
755 }
756
757 /* Variant of store_reg which uses branch&exchange logic when storing
758 * to r15 in ARM architecture v5T and above. This is used for storing
759 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
760 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
761 static inline void store_reg_from_load(CPUState *env, DisasContext *s,
762 int reg, TCGv var)
763 {
764 if (reg == 15 && ENABLE_ARCH_5) {
765 gen_bx(s, var);
766 } else {
767 store_reg(s, reg, var);
768 }
769 }
770
771 static inline TCGv gen_ld8s(TCGv addr, int index)
772 {
773 TCGv tmp = tcg_temp_new_i32();
774 tcg_gen_qemu_ld8s(tmp, addr, index);
775 return tmp;
776 }
777 static inline TCGv gen_ld8u(TCGv addr, int index)
778 {
779 TCGv tmp = tcg_temp_new_i32();
780 tcg_gen_qemu_ld8u(tmp, addr, index);
781 return tmp;
782 }
783 static inline TCGv gen_ld16s(TCGv addr, int index)
784 {
785 TCGv tmp = tcg_temp_new_i32();
786 tcg_gen_qemu_ld16s(tmp, addr, index);
787 return tmp;
788 }
789 static inline TCGv gen_ld16u(TCGv addr, int index)
790 {
791 TCGv tmp = tcg_temp_new_i32();
792 tcg_gen_qemu_ld16u(tmp, addr, index);
793 return tmp;
794 }
795 static inline TCGv gen_ld32(TCGv addr, int index)
796 {
797 TCGv tmp = tcg_temp_new_i32();
798 tcg_gen_qemu_ld32u(tmp, addr, index);
799 return tmp;
800 }
801 static inline TCGv_i64 gen_ld64(TCGv addr, int index)
802 {
803 TCGv_i64 tmp = tcg_temp_new_i64();
804 tcg_gen_qemu_ld64(tmp, addr, index);
805 return tmp;
806 }
807 static inline void gen_st8(TCGv val, TCGv addr, int index)
808 {
809 tcg_gen_qemu_st8(val, addr, index);
810 tcg_temp_free_i32(val);
811 }
812 static inline void gen_st16(TCGv val, TCGv addr, int index)
813 {
814 tcg_gen_qemu_st16(val, addr, index);
815 tcg_temp_free_i32(val);
816 }
817 static inline void gen_st32(TCGv val, TCGv addr, int index)
818 {
819 tcg_gen_qemu_st32(val, addr, index);
820 tcg_temp_free_i32(val);
821 }
822 static inline void gen_st64(TCGv_i64 val, TCGv addr, int index)
823 {
824 tcg_gen_qemu_st64(val, addr, index);
825 tcg_temp_free_i64(val);
826 }
827
828 static inline void gen_set_pc_im(uint32_t val)
829 {
830 tcg_gen_movi_i32(cpu_R[15], val);
831 }
832
833 /* Force a TB lookup after an instruction that changes the CPU state. */
834 static inline void gen_lookup_tb(DisasContext *s)
835 {
836 tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
837 s->is_jmp = DISAS_UPDATE;
838 }
839
840 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
841 TCGv var)
842 {
843 int val, rm, shift, shiftop;
844 TCGv offset;
845
846 if (!(insn & (1 << 25))) {
847 /* immediate */
848 val = insn & 0xfff;
849 if (!(insn & (1 << 23)))
850 val = -val;
851 if (val != 0)
852 tcg_gen_addi_i32(var, var, val);
853 } else {
854 /* shift/register */
855 rm = (insn) & 0xf;
856 shift = (insn >> 7) & 0x1f;
857 shiftop = (insn >> 5) & 3;
858 offset = load_reg(s, rm);
859 gen_arm_shift_im(offset, shiftop, shift, 0);
860 if (!(insn & (1 << 23)))
861 tcg_gen_sub_i32(var, var, offset);
862 else
863 tcg_gen_add_i32(var, var, offset);
864 tcg_temp_free_i32(offset);
865 }
866 }
867
868 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
869 int extra, TCGv var)
870 {
871 int val, rm;
872 TCGv offset;
873
874 if (insn & (1 << 22)) {
875 /* immediate */
876 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
877 if (!(insn & (1 << 23)))
878 val = -val;
879 val += extra;
880 if (val != 0)
881 tcg_gen_addi_i32(var, var, val);
882 } else {
883 /* register */
884 if (extra)
885 tcg_gen_addi_i32(var, var, extra);
886 rm = (insn) & 0xf;
887 offset = load_reg(s, rm);
888 if (!(insn & (1 << 23)))
889 tcg_gen_sub_i32(var, var, offset);
890 else
891 tcg_gen_add_i32(var, var, offset);
892 tcg_temp_free_i32(offset);
893 }
894 }
895
896 #define VFP_OP2(name) \
897 static inline void gen_vfp_##name(int dp) \
898 { \
899 if (dp) \
900 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
901 else \
902 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
903 }
904
905 VFP_OP2(add)
906 VFP_OP2(sub)
907 VFP_OP2(mul)
908 VFP_OP2(div)
909
910 #undef VFP_OP2
911
912 static inline void gen_vfp_abs(int dp)
913 {
914 if (dp)
915 gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
916 else
917 gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
918 }
919
920 static inline void gen_vfp_neg(int dp)
921 {
922 if (dp)
923 gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
924 else
925 gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
926 }
927
928 static inline void gen_vfp_sqrt(int dp)
929 {
930 if (dp)
931 gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env);
932 else
933 gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env);
934 }
935
936 static inline void gen_vfp_cmp(int dp)
937 {
938 if (dp)
939 gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env);
940 else
941 gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env);
942 }
943
944 static inline void gen_vfp_cmpe(int dp)
945 {
946 if (dp)
947 gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env);
948 else
949 gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env);
950 }
951
952 static inline void gen_vfp_F1_ld0(int dp)
953 {
954 if (dp)
955 tcg_gen_movi_i64(cpu_F1d, 0);
956 else
957 tcg_gen_movi_i32(cpu_F1s, 0);
958 }
959
960 static inline void gen_vfp_uito(int dp)
961 {
962 if (dp)
963 gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env);
964 else
965 gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env);
966 }
967
968 static inline void gen_vfp_sito(int dp)
969 {
970 if (dp)
971 gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env);
972 else
973 gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env);
974 }
975
976 static inline void gen_vfp_toui(int dp)
977 {
978 if (dp)
979 gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env);
980 else
981 gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env);
982 }
983
984 static inline void gen_vfp_touiz(int dp)
985 {
986 if (dp)
987 gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env);
988 else
989 gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env);
990 }
991
992 static inline void gen_vfp_tosi(int dp)
993 {
994 if (dp)
995 gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env);
996 else
997 gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env);
998 }
999
1000 static inline void gen_vfp_tosiz(int dp)
1001 {
1002 if (dp)
1003 gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env);
1004 else
1005 gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env);
1006 }
1007
1008 #define VFP_GEN_FIX(name) \
1009 static inline void gen_vfp_##name(int dp, int shift) \
1010 { \
1011 TCGv tmp_shift = tcg_const_i32(shift); \
1012 if (dp) \
1013 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1014 else \
1015 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1016 tcg_temp_free_i32(tmp_shift); \
1017 }
1018 VFP_GEN_FIX(tosh)
1019 VFP_GEN_FIX(tosl)
1020 VFP_GEN_FIX(touh)
1021 VFP_GEN_FIX(toul)
1022 VFP_GEN_FIX(shto)
1023 VFP_GEN_FIX(slto)
1024 VFP_GEN_FIX(uhto)
1025 VFP_GEN_FIX(ulto)
1026 #undef VFP_GEN_FIX
1027
1028 static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv addr)
1029 {
1030 if (dp)
1031 tcg_gen_qemu_ld64(cpu_F0d, addr, IS_USER(s));
1032 else
1033 tcg_gen_qemu_ld32u(cpu_F0s, addr, IS_USER(s));
1034 }
1035
1036 static inline void gen_vfp_st(DisasContext *s, int dp, TCGv addr)
1037 {
1038 if (dp)
1039 tcg_gen_qemu_st64(cpu_F0d, addr, IS_USER(s));
1040 else
1041 tcg_gen_qemu_st32(cpu_F0s, addr, IS_USER(s));
1042 }
1043
1044 static inline long
1045 vfp_reg_offset (int dp, int reg)
1046 {
1047 if (dp)
1048 return offsetof(CPUARMState, vfp.regs[reg]);
1049 else if (reg & 1) {
1050 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1051 + offsetof(CPU_DoubleU, l.upper);
1052 } else {
1053 return offsetof(CPUARMState, vfp.regs[reg >> 1])
1054 + offsetof(CPU_DoubleU, l.lower);
1055 }
1056 }
1057
1058 /* Return the offset of a 32-bit piece of a NEON register.
1059 zero is the least significant end of the register. */
1060 static inline long
1061 neon_reg_offset (int reg, int n)
1062 {
1063 int sreg;
1064 sreg = reg * 2 + n;
1065 return vfp_reg_offset(0, sreg);
1066 }
1067
1068 static TCGv neon_load_reg(int reg, int pass)
1069 {
1070 TCGv tmp = tcg_temp_new_i32();
1071 tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
1072 return tmp;
1073 }
1074
1075 static void neon_store_reg(int reg, int pass, TCGv var)
1076 {
1077 tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
1078 tcg_temp_free_i32(var);
1079 }
1080
1081 static inline void neon_load_reg64(TCGv_i64 var, int reg)
1082 {
1083 tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg));
1084 }
1085
1086 static inline void neon_store_reg64(TCGv_i64 var, int reg)
1087 {
1088 tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
1089 }
1090
1091 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1092 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1093 #define tcg_gen_st_f32 tcg_gen_st_i32
1094 #define tcg_gen_st_f64 tcg_gen_st_i64
1095
1096 static inline void gen_mov_F0_vreg(int dp, int reg)
1097 {
1098 if (dp)
1099 tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1100 else
1101 tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1102 }
1103
1104 static inline void gen_mov_F1_vreg(int dp, int reg)
1105 {
1106 if (dp)
1107 tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg));
1108 else
1109 tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg));
1110 }
1111
1112 static inline void gen_mov_vreg_F0(int dp, int reg)
1113 {
1114 if (dp)
1115 tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg));
1116 else
1117 tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg));
1118 }
1119
1120 #define ARM_CP_RW_BIT (1 << 20)
1121
1122 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
1123 {
1124 tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1125 }
1126
1127 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
1128 {
1129 tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
1130 }
1131
1132 static inline TCGv iwmmxt_load_creg(int reg)
1133 {
1134 TCGv var = tcg_temp_new_i32();
1135 tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1136 return var;
1137 }
1138
1139 static inline void iwmmxt_store_creg(int reg, TCGv var)
1140 {
1141 tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
1142 tcg_temp_free_i32(var);
1143 }
1144
1145 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn)
1146 {
1147 iwmmxt_store_reg(cpu_M0, rn);
1148 }
1149
1150 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn)
1151 {
1152 iwmmxt_load_reg(cpu_M0, rn);
1153 }
1154
1155 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn)
1156 {
1157 iwmmxt_load_reg(cpu_V1, rn);
1158 tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1);
1159 }
1160
1161 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn)
1162 {
1163 iwmmxt_load_reg(cpu_V1, rn);
1164 tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1);
1165 }
1166
1167 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn)
1168 {
1169 iwmmxt_load_reg(cpu_V1, rn);
1170 tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1);
1171 }
1172
1173 #define IWMMXT_OP(name) \
1174 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1175 { \
1176 iwmmxt_load_reg(cpu_V1, rn); \
1177 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1178 }
1179
1180 #define IWMMXT_OP_SIZE(name) \
1181 IWMMXT_OP(name##b) \
1182 IWMMXT_OP(name##w) \
1183 IWMMXT_OP(name##l)
1184
1185 #define IWMMXT_OP_1(name) \
1186 static inline void gen_op_iwmmxt_##name##_M0(void) \
1187 { \
1188 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0); \
1189 }
1190
1191 IWMMXT_OP(maddsq)
1192 IWMMXT_OP(madduq)
1193 IWMMXT_OP(sadb)
1194 IWMMXT_OP(sadw)
1195 IWMMXT_OP(mulslw)
1196 IWMMXT_OP(mulshw)
1197 IWMMXT_OP(mululw)
1198 IWMMXT_OP(muluhw)
1199 IWMMXT_OP(macsw)
1200 IWMMXT_OP(macuw)
1201
1202 IWMMXT_OP_SIZE(unpackl)
1203 IWMMXT_OP_SIZE(unpackh)
1204
1205 IWMMXT_OP_1(unpacklub)
1206 IWMMXT_OP_1(unpackluw)
1207 IWMMXT_OP_1(unpacklul)
1208 IWMMXT_OP_1(unpackhub)
1209 IWMMXT_OP_1(unpackhuw)
1210 IWMMXT_OP_1(unpackhul)
1211 IWMMXT_OP_1(unpacklsb)
1212 IWMMXT_OP_1(unpacklsw)
1213 IWMMXT_OP_1(unpacklsl)
1214 IWMMXT_OP_1(unpackhsb)
1215 IWMMXT_OP_1(unpackhsw)
1216 IWMMXT_OP_1(unpackhsl)
1217
1218 IWMMXT_OP_SIZE(cmpeq)
1219 IWMMXT_OP_SIZE(cmpgtu)
1220 IWMMXT_OP_SIZE(cmpgts)
1221
1222 IWMMXT_OP_SIZE(mins)
1223 IWMMXT_OP_SIZE(minu)
1224 IWMMXT_OP_SIZE(maxs)
1225 IWMMXT_OP_SIZE(maxu)
1226
1227 IWMMXT_OP_SIZE(subn)
1228 IWMMXT_OP_SIZE(addn)
1229 IWMMXT_OP_SIZE(subu)
1230 IWMMXT_OP_SIZE(addu)
1231 IWMMXT_OP_SIZE(subs)
1232 IWMMXT_OP_SIZE(adds)
1233
1234 IWMMXT_OP(avgb0)
1235 IWMMXT_OP(avgb1)
1236 IWMMXT_OP(avgw0)
1237 IWMMXT_OP(avgw1)
1238
1239 IWMMXT_OP(msadb)
1240
1241 IWMMXT_OP(packuw)
1242 IWMMXT_OP(packul)
1243 IWMMXT_OP(packuq)
1244 IWMMXT_OP(packsw)
1245 IWMMXT_OP(packsl)
1246 IWMMXT_OP(packsq)
1247
1248 static void gen_op_iwmmxt_set_mup(void)
1249 {
1250 TCGv tmp;
1251 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1252 tcg_gen_ori_i32(tmp, tmp, 2);
1253 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1254 }
1255
1256 static void gen_op_iwmmxt_set_cup(void)
1257 {
1258 TCGv tmp;
1259 tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]);
1260 tcg_gen_ori_i32(tmp, tmp, 1);
1261 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]);
1262 }
1263
1264 static void gen_op_iwmmxt_setpsr_nz(void)
1265 {
1266 TCGv tmp = tcg_temp_new_i32();
1267 gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0);
1268 store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]);
1269 }
1270
1271 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn)
1272 {
1273 iwmmxt_load_reg(cpu_V1, rn);
1274 tcg_gen_ext32u_i64(cpu_V1, cpu_V1);
1275 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1276 }
1277
1278 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, TCGv dest)
1279 {
1280 int rd;
1281 uint32_t offset;
1282 TCGv tmp;
1283
1284 rd = (insn >> 16) & 0xf;
1285 tmp = load_reg(s, rd);
1286
1287 offset = (insn & 0xff) << ((insn >> 7) & 2);
1288 if (insn & (1 << 24)) {
1289 /* Pre indexed */
1290 if (insn & (1 << 23))
1291 tcg_gen_addi_i32(tmp, tmp, offset);
1292 else
1293 tcg_gen_addi_i32(tmp, tmp, -offset);
1294 tcg_gen_mov_i32(dest, tmp);
1295 if (insn & (1 << 21))
1296 store_reg(s, rd, tmp);
1297 else
1298 tcg_temp_free_i32(tmp);
1299 } else if (insn & (1 << 21)) {
1300 /* Post indexed */
1301 tcg_gen_mov_i32(dest, tmp);
1302 if (insn & (1 << 23))
1303 tcg_gen_addi_i32(tmp, tmp, offset);
1304 else
1305 tcg_gen_addi_i32(tmp, tmp, -offset);
1306 store_reg(s, rd, tmp);
1307 } else if (!(insn & (1 << 23)))
1308 return 1;
1309 return 0;
1310 }
1311
1312 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
1313 {
1314 int rd = (insn >> 0) & 0xf;
1315 TCGv tmp;
1316
1317 if (insn & (1 << 8)) {
1318 if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) {
1319 return 1;
1320 } else {
1321 tmp = iwmmxt_load_creg(rd);
1322 }
1323 } else {
1324 tmp = tcg_temp_new_i32();
1325 iwmmxt_load_reg(cpu_V0, rd);
1326 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
1327 }
1328 tcg_gen_andi_i32(tmp, tmp, mask);
1329 tcg_gen_mov_i32(dest, tmp);
1330 tcg_temp_free_i32(tmp);
1331 return 0;
1332 }
1333
1334 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1335 (ie. an undefined instruction). */
1336 static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1337 {
1338 int rd, wrd;
1339 int rdhi, rdlo, rd0, rd1, i;
1340 TCGv addr;
1341 TCGv tmp, tmp2, tmp3;
1342
1343 if ((insn & 0x0e000e00) == 0x0c000000) {
1344 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1345 wrd = insn & 0xf;
1346 rdlo = (insn >> 12) & 0xf;
1347 rdhi = (insn >> 16) & 0xf;
1348 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1349 iwmmxt_load_reg(cpu_V0, wrd);
1350 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
1351 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
1352 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
1353 } else { /* TMCRR */
1354 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
1355 iwmmxt_store_reg(cpu_V0, wrd);
1356 gen_op_iwmmxt_set_mup();
1357 }
1358 return 0;
1359 }
1360
1361 wrd = (insn >> 12) & 0xf;
1362 addr = tcg_temp_new_i32();
1363 if (gen_iwmmxt_address(s, insn, addr)) {
1364 tcg_temp_free_i32(addr);
1365 return 1;
1366 }
1367 if (insn & ARM_CP_RW_BIT) {
1368 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1369 tmp = tcg_temp_new_i32();
1370 tcg_gen_qemu_ld32u(tmp, addr, IS_USER(s));
1371 iwmmxt_store_creg(wrd, tmp);
1372 } else {
1373 i = 1;
1374 if (insn & (1 << 8)) {
1375 if (insn & (1 << 22)) { /* WLDRD */
1376 tcg_gen_qemu_ld64(cpu_M0, addr, IS_USER(s));
1377 i = 0;
1378 } else { /* WLDRW wRd */
1379 tmp = gen_ld32(addr, IS_USER(s));
1380 }
1381 } else {
1382 if (insn & (1 << 22)) { /* WLDRH */
1383 tmp = gen_ld16u(addr, IS_USER(s));
1384 } else { /* WLDRB */
1385 tmp = gen_ld8u(addr, IS_USER(s));
1386 }
1387 }
1388 if (i) {
1389 tcg_gen_extu_i32_i64(cpu_M0, tmp);
1390 tcg_temp_free_i32(tmp);
1391 }
1392 gen_op_iwmmxt_movq_wRn_M0(wrd);
1393 }
1394 } else {
1395 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1396 tmp = iwmmxt_load_creg(wrd);
1397 gen_st32(tmp, addr, IS_USER(s));
1398 } else {
1399 gen_op_iwmmxt_movq_M0_wRn(wrd);
1400 tmp = tcg_temp_new_i32();
1401 if (insn & (1 << 8)) {
1402 if (insn & (1 << 22)) { /* WSTRD */
1403 tcg_temp_free_i32(tmp);
1404 tcg_gen_qemu_st64(cpu_M0, addr, IS_USER(s));
1405 } else { /* WSTRW wRd */
1406 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1407 gen_st32(tmp, addr, IS_USER(s));
1408 }
1409 } else {
1410 if (insn & (1 << 22)) { /* WSTRH */
1411 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1412 gen_st16(tmp, addr, IS_USER(s));
1413 } else { /* WSTRB */
1414 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1415 gen_st8(tmp, addr, IS_USER(s));
1416 }
1417 }
1418 }
1419 }
1420 tcg_temp_free_i32(addr);
1421 return 0;
1422 }
1423
1424 if ((insn & 0x0f000000) != 0x0e000000)
1425 return 1;
1426
1427 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1428 case 0x000: /* WOR */
1429 wrd = (insn >> 12) & 0xf;
1430 rd0 = (insn >> 0) & 0xf;
1431 rd1 = (insn >> 16) & 0xf;
1432 gen_op_iwmmxt_movq_M0_wRn(rd0);
1433 gen_op_iwmmxt_orq_M0_wRn(rd1);
1434 gen_op_iwmmxt_setpsr_nz();
1435 gen_op_iwmmxt_movq_wRn_M0(wrd);
1436 gen_op_iwmmxt_set_mup();
1437 gen_op_iwmmxt_set_cup();
1438 break;
1439 case 0x011: /* TMCR */
1440 if (insn & 0xf)
1441 return 1;
1442 rd = (insn >> 12) & 0xf;
1443 wrd = (insn >> 16) & 0xf;
1444 switch (wrd) {
1445 case ARM_IWMMXT_wCID:
1446 case ARM_IWMMXT_wCASF:
1447 break;
1448 case ARM_IWMMXT_wCon:
1449 gen_op_iwmmxt_set_cup();
1450 /* Fall through. */
1451 case ARM_IWMMXT_wCSSF:
1452 tmp = iwmmxt_load_creg(wrd);
1453 tmp2 = load_reg(s, rd);
1454 tcg_gen_andc_i32(tmp, tmp, tmp2);
1455 tcg_temp_free_i32(tmp2);
1456 iwmmxt_store_creg(wrd, tmp);
1457 break;
1458 case ARM_IWMMXT_wCGR0:
1459 case ARM_IWMMXT_wCGR1:
1460 case ARM_IWMMXT_wCGR2:
1461 case ARM_IWMMXT_wCGR3:
1462 gen_op_iwmmxt_set_cup();
1463 tmp = load_reg(s, rd);
1464 iwmmxt_store_creg(wrd, tmp);
1465 break;
1466 default:
1467 return 1;
1468 }
1469 break;
1470 case 0x100: /* WXOR */
1471 wrd = (insn >> 12) & 0xf;
1472 rd0 = (insn >> 0) & 0xf;
1473 rd1 = (insn >> 16) & 0xf;
1474 gen_op_iwmmxt_movq_M0_wRn(rd0);
1475 gen_op_iwmmxt_xorq_M0_wRn(rd1);
1476 gen_op_iwmmxt_setpsr_nz();
1477 gen_op_iwmmxt_movq_wRn_M0(wrd);
1478 gen_op_iwmmxt_set_mup();
1479 gen_op_iwmmxt_set_cup();
1480 break;
1481 case 0x111: /* TMRC */
1482 if (insn & 0xf)
1483 return 1;
1484 rd = (insn >> 12) & 0xf;
1485 wrd = (insn >> 16) & 0xf;
1486 tmp = iwmmxt_load_creg(wrd);
1487 store_reg(s, rd, tmp);
1488 break;
1489 case 0x300: /* WANDN */
1490 wrd = (insn >> 12) & 0xf;
1491 rd0 = (insn >> 0) & 0xf;
1492 rd1 = (insn >> 16) & 0xf;
1493 gen_op_iwmmxt_movq_M0_wRn(rd0);
1494 tcg_gen_neg_i64(cpu_M0, cpu_M0);
1495 gen_op_iwmmxt_andq_M0_wRn(rd1);
1496 gen_op_iwmmxt_setpsr_nz();
1497 gen_op_iwmmxt_movq_wRn_M0(wrd);
1498 gen_op_iwmmxt_set_mup();
1499 gen_op_iwmmxt_set_cup();
1500 break;
1501 case 0x200: /* WAND */
1502 wrd = (insn >> 12) & 0xf;
1503 rd0 = (insn >> 0) & 0xf;
1504 rd1 = (insn >> 16) & 0xf;
1505 gen_op_iwmmxt_movq_M0_wRn(rd0);
1506 gen_op_iwmmxt_andq_M0_wRn(rd1);
1507 gen_op_iwmmxt_setpsr_nz();
1508 gen_op_iwmmxt_movq_wRn_M0(wrd);
1509 gen_op_iwmmxt_set_mup();
1510 gen_op_iwmmxt_set_cup();
1511 break;
1512 case 0x810: case 0xa10: /* WMADD */
1513 wrd = (insn >> 12) & 0xf;
1514 rd0 = (insn >> 0) & 0xf;
1515 rd1 = (insn >> 16) & 0xf;
1516 gen_op_iwmmxt_movq_M0_wRn(rd0);
1517 if (insn & (1 << 21))
1518 gen_op_iwmmxt_maddsq_M0_wRn(rd1);
1519 else
1520 gen_op_iwmmxt_madduq_M0_wRn(rd1);
1521 gen_op_iwmmxt_movq_wRn_M0(wrd);
1522 gen_op_iwmmxt_set_mup();
1523 break;
1524 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1525 wrd = (insn >> 12) & 0xf;
1526 rd0 = (insn >> 16) & 0xf;
1527 rd1 = (insn >> 0) & 0xf;
1528 gen_op_iwmmxt_movq_M0_wRn(rd0);
1529 switch ((insn >> 22) & 3) {
1530 case 0:
1531 gen_op_iwmmxt_unpacklb_M0_wRn(rd1);
1532 break;
1533 case 1:
1534 gen_op_iwmmxt_unpacklw_M0_wRn(rd1);
1535 break;
1536 case 2:
1537 gen_op_iwmmxt_unpackll_M0_wRn(rd1);
1538 break;
1539 case 3:
1540 return 1;
1541 }
1542 gen_op_iwmmxt_movq_wRn_M0(wrd);
1543 gen_op_iwmmxt_set_mup();
1544 gen_op_iwmmxt_set_cup();
1545 break;
1546 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1547 wrd = (insn >> 12) & 0xf;
1548 rd0 = (insn >> 16) & 0xf;
1549 rd1 = (insn >> 0) & 0xf;
1550 gen_op_iwmmxt_movq_M0_wRn(rd0);
1551 switch ((insn >> 22) & 3) {
1552 case 0:
1553 gen_op_iwmmxt_unpackhb_M0_wRn(rd1);
1554 break;
1555 case 1:
1556 gen_op_iwmmxt_unpackhw_M0_wRn(rd1);
1557 break;
1558 case 2:
1559 gen_op_iwmmxt_unpackhl_M0_wRn(rd1);
1560 break;
1561 case 3:
1562 return 1;
1563 }
1564 gen_op_iwmmxt_movq_wRn_M0(wrd);
1565 gen_op_iwmmxt_set_mup();
1566 gen_op_iwmmxt_set_cup();
1567 break;
1568 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1569 wrd = (insn >> 12) & 0xf;
1570 rd0 = (insn >> 16) & 0xf;
1571 rd1 = (insn >> 0) & 0xf;
1572 gen_op_iwmmxt_movq_M0_wRn(rd0);
1573 if (insn & (1 << 22))
1574 gen_op_iwmmxt_sadw_M0_wRn(rd1);
1575 else
1576 gen_op_iwmmxt_sadb_M0_wRn(rd1);
1577 if (!(insn & (1 << 20)))
1578 gen_op_iwmmxt_addl_M0_wRn(wrd);
1579 gen_op_iwmmxt_movq_wRn_M0(wrd);
1580 gen_op_iwmmxt_set_mup();
1581 break;
1582 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1583 wrd = (insn >> 12) & 0xf;
1584 rd0 = (insn >> 16) & 0xf;
1585 rd1 = (insn >> 0) & 0xf;
1586 gen_op_iwmmxt_movq_M0_wRn(rd0);
1587 if (insn & (1 << 21)) {
1588 if (insn & (1 << 20))
1589 gen_op_iwmmxt_mulshw_M0_wRn(rd1);
1590 else
1591 gen_op_iwmmxt_mulslw_M0_wRn(rd1);
1592 } else {
1593 if (insn & (1 << 20))
1594 gen_op_iwmmxt_muluhw_M0_wRn(rd1);
1595 else
1596 gen_op_iwmmxt_mululw_M0_wRn(rd1);
1597 }
1598 gen_op_iwmmxt_movq_wRn_M0(wrd);
1599 gen_op_iwmmxt_set_mup();
1600 break;
1601 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1602 wrd = (insn >> 12) & 0xf;
1603 rd0 = (insn >> 16) & 0xf;
1604 rd1 = (insn >> 0) & 0xf;
1605 gen_op_iwmmxt_movq_M0_wRn(rd0);
1606 if (insn & (1 << 21))
1607 gen_op_iwmmxt_macsw_M0_wRn(rd1);
1608 else
1609 gen_op_iwmmxt_macuw_M0_wRn(rd1);
1610 if (!(insn & (1 << 20))) {
1611 iwmmxt_load_reg(cpu_V1, wrd);
1612 tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1);
1613 }
1614 gen_op_iwmmxt_movq_wRn_M0(wrd);
1615 gen_op_iwmmxt_set_mup();
1616 break;
1617 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1618 wrd = (insn >> 12) & 0xf;
1619 rd0 = (insn >> 16) & 0xf;
1620 rd1 = (insn >> 0) & 0xf;
1621 gen_op_iwmmxt_movq_M0_wRn(rd0);
1622 switch ((insn >> 22) & 3) {
1623 case 0:
1624 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1);
1625 break;
1626 case 1:
1627 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1);
1628 break;
1629 case 2:
1630 gen_op_iwmmxt_cmpeql_M0_wRn(rd1);
1631 break;
1632 case 3:
1633 return 1;
1634 }
1635 gen_op_iwmmxt_movq_wRn_M0(wrd);
1636 gen_op_iwmmxt_set_mup();
1637 gen_op_iwmmxt_set_cup();
1638 break;
1639 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1640 wrd = (insn >> 12) & 0xf;
1641 rd0 = (insn >> 16) & 0xf;
1642 rd1 = (insn >> 0) & 0xf;
1643 gen_op_iwmmxt_movq_M0_wRn(rd0);
1644 if (insn & (1 << 22)) {
1645 if (insn & (1 << 20))
1646 gen_op_iwmmxt_avgw1_M0_wRn(rd1);
1647 else
1648 gen_op_iwmmxt_avgw0_M0_wRn(rd1);
1649 } else {
1650 if (insn & (1 << 20))
1651 gen_op_iwmmxt_avgb1_M0_wRn(rd1);
1652 else
1653 gen_op_iwmmxt_avgb0_M0_wRn(rd1);
1654 }
1655 gen_op_iwmmxt_movq_wRn_M0(wrd);
1656 gen_op_iwmmxt_set_mup();
1657 gen_op_iwmmxt_set_cup();
1658 break;
1659 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1660 wrd = (insn >> 12) & 0xf;
1661 rd0 = (insn >> 16) & 0xf;
1662 rd1 = (insn >> 0) & 0xf;
1663 gen_op_iwmmxt_movq_M0_wRn(rd0);
1664 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1665 tcg_gen_andi_i32(tmp, tmp, 7);
1666 iwmmxt_load_reg(cpu_V1, rd1);
1667 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
1668 tcg_temp_free_i32(tmp);
1669 gen_op_iwmmxt_movq_wRn_M0(wrd);
1670 gen_op_iwmmxt_set_mup();
1671 break;
1672 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1673 if (((insn >> 6) & 3) == 3)
1674 return 1;
1675 rd = (insn >> 12) & 0xf;
1676 wrd = (insn >> 16) & 0xf;
1677 tmp = load_reg(s, rd);
1678 gen_op_iwmmxt_movq_M0_wRn(wrd);
1679 switch ((insn >> 6) & 3) {
1680 case 0:
1681 tmp2 = tcg_const_i32(0xff);
1682 tmp3 = tcg_const_i32((insn & 7) << 3);
1683 break;
1684 case 1:
1685 tmp2 = tcg_const_i32(0xffff);
1686 tmp3 = tcg_const_i32((insn & 3) << 4);
1687 break;
1688 case 2:
1689 tmp2 = tcg_const_i32(0xffffffff);
1690 tmp3 = tcg_const_i32((insn & 1) << 5);
1691 break;
1692 default:
1693 TCGV_UNUSED(tmp2);
1694 TCGV_UNUSED(tmp3);
1695 }
1696 gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
1697 tcg_temp_free(tmp3);
1698 tcg_temp_free(tmp2);
1699 tcg_temp_free_i32(tmp);
1700 gen_op_iwmmxt_movq_wRn_M0(wrd);
1701 gen_op_iwmmxt_set_mup();
1702 break;
1703 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1704 rd = (insn >> 12) & 0xf;
1705 wrd = (insn >> 16) & 0xf;
1706 if (rd == 15 || ((insn >> 22) & 3) == 3)
1707 return 1;
1708 gen_op_iwmmxt_movq_M0_wRn(wrd);
1709 tmp = tcg_temp_new_i32();
1710 switch ((insn >> 22) & 3) {
1711 case 0:
1712 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3);
1713 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1714 if (insn & 8) {
1715 tcg_gen_ext8s_i32(tmp, tmp);
1716 } else {
1717 tcg_gen_andi_i32(tmp, tmp, 0xff);
1718 }
1719 break;
1720 case 1:
1721 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4);
1722 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1723 if (insn & 8) {
1724 tcg_gen_ext16s_i32(tmp, tmp);
1725 } else {
1726 tcg_gen_andi_i32(tmp, tmp, 0xffff);
1727 }
1728 break;
1729 case 2:
1730 tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5);
1731 tcg_gen_trunc_i64_i32(tmp, cpu_M0);
1732 break;
1733 }
1734 store_reg(s, rd, tmp);
1735 break;
1736 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1737 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1738 return 1;
1739 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1740 switch ((insn >> 22) & 3) {
1741 case 0:
1742 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0);
1743 break;
1744 case 1:
1745 tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4);
1746 break;
1747 case 2:
1748 tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12);
1749 break;
1750 }
1751 tcg_gen_shli_i32(tmp, tmp, 28);
1752 gen_set_nzcv(tmp);
1753 tcg_temp_free_i32(tmp);
1754 break;
1755 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1756 if (((insn >> 6) & 3) == 3)
1757 return 1;
1758 rd = (insn >> 12) & 0xf;
1759 wrd = (insn >> 16) & 0xf;
1760 tmp = load_reg(s, rd);
1761 switch ((insn >> 6) & 3) {
1762 case 0:
1763 gen_helper_iwmmxt_bcstb(cpu_M0, tmp);
1764 break;
1765 case 1:
1766 gen_helper_iwmmxt_bcstw(cpu_M0, tmp);
1767 break;
1768 case 2:
1769 gen_helper_iwmmxt_bcstl(cpu_M0, tmp);
1770 break;
1771 }
1772 tcg_temp_free_i32(tmp);
1773 gen_op_iwmmxt_movq_wRn_M0(wrd);
1774 gen_op_iwmmxt_set_mup();
1775 break;
1776 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1777 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1778 return 1;
1779 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1780 tmp2 = tcg_temp_new_i32();
1781 tcg_gen_mov_i32(tmp2, tmp);
1782 switch ((insn >> 22) & 3) {
1783 case 0:
1784 for (i = 0; i < 7; i ++) {
1785 tcg_gen_shli_i32(tmp2, tmp2, 4);
1786 tcg_gen_and_i32(tmp, tmp, tmp2);
1787 }
1788 break;
1789 case 1:
1790 for (i = 0; i < 3; i ++) {
1791 tcg_gen_shli_i32(tmp2, tmp2, 8);
1792 tcg_gen_and_i32(tmp, tmp, tmp2);
1793 }
1794 break;
1795 case 2:
1796 tcg_gen_shli_i32(tmp2, tmp2, 16);
1797 tcg_gen_and_i32(tmp, tmp, tmp2);
1798 break;
1799 }
1800 gen_set_nzcv(tmp);
1801 tcg_temp_free_i32(tmp2);
1802 tcg_temp_free_i32(tmp);
1803 break;
1804 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1805 wrd = (insn >> 12) & 0xf;
1806 rd0 = (insn >> 16) & 0xf;
1807 gen_op_iwmmxt_movq_M0_wRn(rd0);
1808 switch ((insn >> 22) & 3) {
1809 case 0:
1810 gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0);
1811 break;
1812 case 1:
1813 gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0);
1814 break;
1815 case 2:
1816 gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0);
1817 break;
1818 case 3:
1819 return 1;
1820 }
1821 gen_op_iwmmxt_movq_wRn_M0(wrd);
1822 gen_op_iwmmxt_set_mup();
1823 break;
1824 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1825 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3)
1826 return 1;
1827 tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF);
1828 tmp2 = tcg_temp_new_i32();
1829 tcg_gen_mov_i32(tmp2, tmp);
1830 switch ((insn >> 22) & 3) {
1831 case 0:
1832 for (i = 0; i < 7; i ++) {
1833 tcg_gen_shli_i32(tmp2, tmp2, 4);
1834 tcg_gen_or_i32(tmp, tmp, tmp2);
1835 }
1836 break;
1837 case 1:
1838 for (i = 0; i < 3; i ++) {
1839 tcg_gen_shli_i32(tmp2, tmp2, 8);
1840 tcg_gen_or_i32(tmp, tmp, tmp2);
1841 }
1842 break;
1843 case 2:
1844 tcg_gen_shli_i32(tmp2, tmp2, 16);
1845 tcg_gen_or_i32(tmp, tmp, tmp2);
1846 break;
1847 }
1848 gen_set_nzcv(tmp);
1849 tcg_temp_free_i32(tmp2);
1850 tcg_temp_free_i32(tmp);
1851 break;
1852 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1853 rd = (insn >> 12) & 0xf;
1854 rd0 = (insn >> 16) & 0xf;
1855 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
1856 return 1;
1857 gen_op_iwmmxt_movq_M0_wRn(rd0);
1858 tmp = tcg_temp_new_i32();
1859 switch ((insn >> 22) & 3) {
1860 case 0:
1861 gen_helper_iwmmxt_msbb(tmp, cpu_M0);
1862 break;
1863 case 1:
1864 gen_helper_iwmmxt_msbw(tmp, cpu_M0);
1865 break;
1866 case 2:
1867 gen_helper_iwmmxt_msbl(tmp, cpu_M0);
1868 break;
1869 }
1870 store_reg(s, rd, tmp);
1871 break;
1872 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1873 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1874 wrd = (insn >> 12) & 0xf;
1875 rd0 = (insn >> 16) & 0xf;
1876 rd1 = (insn >> 0) & 0xf;
1877 gen_op_iwmmxt_movq_M0_wRn(rd0);
1878 switch ((insn >> 22) & 3) {
1879 case 0:
1880 if (insn & (1 << 21))
1881 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1);
1882 else
1883 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1);
1884 break;
1885 case 1:
1886 if (insn & (1 << 21))
1887 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1);
1888 else
1889 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1);
1890 break;
1891 case 2:
1892 if (insn & (1 << 21))
1893 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1);
1894 else
1895 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1);
1896 break;
1897 case 3:
1898 return 1;
1899 }
1900 gen_op_iwmmxt_movq_wRn_M0(wrd);
1901 gen_op_iwmmxt_set_mup();
1902 gen_op_iwmmxt_set_cup();
1903 break;
1904 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1905 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1906 wrd = (insn >> 12) & 0xf;
1907 rd0 = (insn >> 16) & 0xf;
1908 gen_op_iwmmxt_movq_M0_wRn(rd0);
1909 switch ((insn >> 22) & 3) {
1910 case 0:
1911 if (insn & (1 << 21))
1912 gen_op_iwmmxt_unpacklsb_M0();
1913 else
1914 gen_op_iwmmxt_unpacklub_M0();
1915 break;
1916 case 1:
1917 if (insn & (1 << 21))
1918 gen_op_iwmmxt_unpacklsw_M0();
1919 else
1920 gen_op_iwmmxt_unpackluw_M0();
1921 break;
1922 case 2:
1923 if (insn & (1 << 21))
1924 gen_op_iwmmxt_unpacklsl_M0();
1925 else
1926 gen_op_iwmmxt_unpacklul_M0();
1927 break;
1928 case 3:
1929 return 1;
1930 }
1931 gen_op_iwmmxt_movq_wRn_M0(wrd);
1932 gen_op_iwmmxt_set_mup();
1933 gen_op_iwmmxt_set_cup();
1934 break;
1935 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1936 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1937 wrd = (insn >> 12) & 0xf;
1938 rd0 = (insn >> 16) & 0xf;
1939 gen_op_iwmmxt_movq_M0_wRn(rd0);
1940 switch ((insn >> 22) & 3) {
1941 case 0:
1942 if (insn & (1 << 21))
1943 gen_op_iwmmxt_unpackhsb_M0();
1944 else
1945 gen_op_iwmmxt_unpackhub_M0();
1946 break;
1947 case 1:
1948 if (insn & (1 << 21))
1949 gen_op_iwmmxt_unpackhsw_M0();
1950 else
1951 gen_op_iwmmxt_unpackhuw_M0();
1952 break;
1953 case 2:
1954 if (insn & (1 << 21))
1955 gen_op_iwmmxt_unpackhsl_M0();
1956 else
1957 gen_op_iwmmxt_unpackhul_M0();
1958 break;
1959 case 3:
1960 return 1;
1961 }
1962 gen_op_iwmmxt_movq_wRn_M0(wrd);
1963 gen_op_iwmmxt_set_mup();
1964 gen_op_iwmmxt_set_cup();
1965 break;
1966 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1967 case 0x214: case 0x614: case 0xa14: case 0xe14:
1968 if (((insn >> 22) & 3) == 0)
1969 return 1;
1970 wrd = (insn >> 12) & 0xf;
1971 rd0 = (insn >> 16) & 0xf;
1972 gen_op_iwmmxt_movq_M0_wRn(rd0);
1973 tmp = tcg_temp_new_i32();
1974 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
1975 tcg_temp_free_i32(tmp);
1976 return 1;
1977 }
1978 switch ((insn >> 22) & 3) {
1979 case 1:
1980 gen_helper_iwmmxt_srlw(cpu_M0, cpu_M0, tmp);
1981 break;
1982 case 2:
1983 gen_helper_iwmmxt_srll(cpu_M0, cpu_M0, tmp);
1984 break;
1985 case 3:
1986 gen_helper_iwmmxt_srlq(cpu_M0, cpu_M0, tmp);
1987 break;
1988 }
1989 tcg_temp_free_i32(tmp);
1990 gen_op_iwmmxt_movq_wRn_M0(wrd);
1991 gen_op_iwmmxt_set_mup();
1992 gen_op_iwmmxt_set_cup();
1993 break;
1994 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1995 case 0x014: case 0x414: case 0x814: case 0xc14:
1996 if (((insn >> 22) & 3) == 0)
1997 return 1;
1998 wrd = (insn >> 12) & 0xf;
1999 rd0 = (insn >> 16) & 0xf;
2000 gen_op_iwmmxt_movq_M0_wRn(rd0);
2001 tmp = tcg_temp_new_i32();
2002 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2003 tcg_temp_free_i32(tmp);
2004 return 1;
2005 }
2006 switch ((insn >> 22) & 3) {
2007 case 1:
2008 gen_helper_iwmmxt_sraw(cpu_M0, cpu_M0, tmp);
2009 break;
2010 case 2:
2011 gen_helper_iwmmxt_sral(cpu_M0, cpu_M0, tmp);
2012 break;
2013 case 3:
2014 gen_helper_iwmmxt_sraq(cpu_M0, cpu_M0, tmp);
2015 break;
2016 }
2017 tcg_temp_free_i32(tmp);
2018 gen_op_iwmmxt_movq_wRn_M0(wrd);
2019 gen_op_iwmmxt_set_mup();
2020 gen_op_iwmmxt_set_cup();
2021 break;
2022 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2023 case 0x114: case 0x514: case 0x914: case 0xd14:
2024 if (((insn >> 22) & 3) == 0)
2025 return 1;
2026 wrd = (insn >> 12) & 0xf;
2027 rd0 = (insn >> 16) & 0xf;
2028 gen_op_iwmmxt_movq_M0_wRn(rd0);
2029 tmp = tcg_temp_new_i32();
2030 if (gen_iwmmxt_shift(insn, 0xff, tmp)) {
2031 tcg_temp_free_i32(tmp);
2032 return 1;
2033 }
2034 switch ((insn >> 22) & 3) {
2035 case 1:
2036 gen_helper_iwmmxt_sllw(cpu_M0, cpu_M0, tmp);
2037 break;
2038 case 2:
2039 gen_helper_iwmmxt_slll(cpu_M0, cpu_M0, tmp);
2040 break;
2041 case 3:
2042 gen_helper_iwmmxt_sllq(cpu_M0, cpu_M0, tmp);
2043 break;
2044 }
2045 tcg_temp_free_i32(tmp);
2046 gen_op_iwmmxt_movq_wRn_M0(wrd);
2047 gen_op_iwmmxt_set_mup();
2048 gen_op_iwmmxt_set_cup();
2049 break;
2050 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2051 case 0x314: case 0x714: case 0xb14: case 0xf14:
2052 if (((insn >> 22) & 3) == 0)
2053 return 1;
2054 wrd = (insn >> 12) & 0xf;
2055 rd0 = (insn >> 16) & 0xf;
2056 gen_op_iwmmxt_movq_M0_wRn(rd0);
2057 tmp = tcg_temp_new_i32();
2058 switch ((insn >> 22) & 3) {
2059 case 1:
2060 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2061 tcg_temp_free_i32(tmp);
2062 return 1;
2063 }
2064 gen_helper_iwmmxt_rorw(cpu_M0, cpu_M0, tmp);
2065 break;
2066 case 2:
2067 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) {
2068 tcg_temp_free_i32(tmp);
2069 return 1;
2070 }
2071 gen_helper_iwmmxt_rorl(cpu_M0, cpu_M0, tmp);
2072 break;
2073 case 3:
2074 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) {
2075 tcg_temp_free_i32(tmp);
2076 return 1;
2077 }
2078 gen_helper_iwmmxt_rorq(cpu_M0, cpu_M0, tmp);
2079 break;
2080 }
2081 tcg_temp_free_i32(tmp);
2082 gen_op_iwmmxt_movq_wRn_M0(wrd);
2083 gen_op_iwmmxt_set_mup();
2084 gen_op_iwmmxt_set_cup();
2085 break;
2086 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2087 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2088 wrd = (insn >> 12) & 0xf;
2089 rd0 = (insn >> 16) & 0xf;
2090 rd1 = (insn >> 0) & 0xf;
2091 gen_op_iwmmxt_movq_M0_wRn(rd0);
2092 switch ((insn >> 22) & 3) {
2093 case 0:
2094 if (insn & (1 << 21))
2095 gen_op_iwmmxt_minsb_M0_wRn(rd1);
2096 else
2097 gen_op_iwmmxt_minub_M0_wRn(rd1);
2098 break;
2099 case 1:
2100 if (insn & (1 << 21))
2101 gen_op_iwmmxt_minsw_M0_wRn(rd1);
2102 else
2103 gen_op_iwmmxt_minuw_M0_wRn(rd1);
2104 break;
2105 case 2:
2106 if (insn & (1 << 21))
2107 gen_op_iwmmxt_minsl_M0_wRn(rd1);
2108 else
2109 gen_op_iwmmxt_minul_M0_wRn(rd1);
2110 break;
2111 case 3:
2112 return 1;
2113 }
2114 gen_op_iwmmxt_movq_wRn_M0(wrd);
2115 gen_op_iwmmxt_set_mup();
2116 break;
2117 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2118 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2119 wrd = (insn >> 12) & 0xf;
2120 rd0 = (insn >> 16) & 0xf;
2121 rd1 = (insn >> 0) & 0xf;
2122 gen_op_iwmmxt_movq_M0_wRn(rd0);
2123 switch ((insn >> 22) & 3) {
2124 case 0:
2125 if (insn & (1 << 21))
2126 gen_op_iwmmxt_maxsb_M0_wRn(rd1);
2127 else
2128 gen_op_iwmmxt_maxub_M0_wRn(rd1);
2129 break;
2130 case 1:
2131 if (insn & (1 << 21))
2132 gen_op_iwmmxt_maxsw_M0_wRn(rd1);
2133 else
2134 gen_op_iwmmxt_maxuw_M0_wRn(rd1);
2135 break;
2136 case 2:
2137 if (insn & (1 << 21))
2138 gen_op_iwmmxt_maxsl_M0_wRn(rd1);
2139 else
2140 gen_op_iwmmxt_maxul_M0_wRn(rd1);
2141 break;
2142 case 3:
2143 return 1;
2144 }
2145 gen_op_iwmmxt_movq_wRn_M0(wrd);
2146 gen_op_iwmmxt_set_mup();
2147 break;
2148 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2149 case 0x402: case 0x502: case 0x602: case 0x702:
2150 wrd = (insn >> 12) & 0xf;
2151 rd0 = (insn >> 16) & 0xf;
2152 rd1 = (insn >> 0) & 0xf;
2153 gen_op_iwmmxt_movq_M0_wRn(rd0);
2154 tmp = tcg_const_i32((insn >> 20) & 3);
2155 iwmmxt_load_reg(cpu_V1, rd1);
2156 gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp);
2157 tcg_temp_free(tmp);
2158 gen_op_iwmmxt_movq_wRn_M0(wrd);
2159 gen_op_iwmmxt_set_mup();
2160 break;
2161 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2162 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2163 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2164 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2165 wrd = (insn >> 12) & 0xf;
2166 rd0 = (insn >> 16) & 0xf;
2167 rd1 = (insn >> 0) & 0xf;
2168 gen_op_iwmmxt_movq_M0_wRn(rd0);
2169 switch ((insn >> 20) & 0xf) {
2170 case 0x0:
2171 gen_op_iwmmxt_subnb_M0_wRn(rd1);
2172 break;
2173 case 0x1:
2174 gen_op_iwmmxt_subub_M0_wRn(rd1);
2175 break;
2176 case 0x3:
2177 gen_op_iwmmxt_subsb_M0_wRn(rd1);
2178 break;
2179 case 0x4:
2180 gen_op_iwmmxt_subnw_M0_wRn(rd1);
2181 break;
2182 case 0x5:
2183 gen_op_iwmmxt_subuw_M0_wRn(rd1);
2184 break;
2185 case 0x7:
2186 gen_op_iwmmxt_subsw_M0_wRn(rd1);
2187 break;
2188 case 0x8:
2189 gen_op_iwmmxt_subnl_M0_wRn(rd1);
2190 break;
2191 case 0x9:
2192 gen_op_iwmmxt_subul_M0_wRn(rd1);
2193 break;
2194 case 0xb:
2195 gen_op_iwmmxt_subsl_M0_wRn(rd1);
2196 break;
2197 default:
2198 return 1;
2199 }
2200 gen_op_iwmmxt_movq_wRn_M0(wrd);
2201 gen_op_iwmmxt_set_mup();
2202 gen_op_iwmmxt_set_cup();
2203 break;
2204 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2205 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2206 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2207 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2208 wrd = (insn >> 12) & 0xf;
2209 rd0 = (insn >> 16) & 0xf;
2210 gen_op_iwmmxt_movq_M0_wRn(rd0);
2211 tmp = tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f));
2212 gen_helper_iwmmxt_shufh(cpu_M0, cpu_M0, tmp);
2213 tcg_temp_free(tmp);
2214 gen_op_iwmmxt_movq_wRn_M0(wrd);
2215 gen_op_iwmmxt_set_mup();
2216 gen_op_iwmmxt_set_cup();
2217 break;
2218 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2219 case 0x418: case 0x518: case 0x618: case 0x718:
2220 case 0x818: case 0x918: case 0xa18: case 0xb18:
2221 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2222 wrd = (insn >> 12) & 0xf;
2223 rd0 = (insn >> 16) & 0xf;
2224 rd1 = (insn >> 0) & 0xf;
2225 gen_op_iwmmxt_movq_M0_wRn(rd0);
2226 switch ((insn >> 20) & 0xf) {
2227 case 0x0:
2228 gen_op_iwmmxt_addnb_M0_wRn(rd1);
2229 break;
2230 case 0x1:
2231 gen_op_iwmmxt_addub_M0_wRn(rd1);
2232 break;
2233 case 0x3:
2234 gen_op_iwmmxt_addsb_M0_wRn(rd1);
2235 break;
2236 case 0x4:
2237 gen_op_iwmmxt_addnw_M0_wRn(rd1);
2238 break;
2239 case 0x5:
2240 gen_op_iwmmxt_adduw_M0_wRn(rd1);
2241 break;
2242 case 0x7:
2243 gen_op_iwmmxt_addsw_M0_wRn(rd1);
2244 break;
2245 case 0x8:
2246 gen_op_iwmmxt_addnl_M0_wRn(rd1);
2247 break;
2248 case 0x9:
2249 gen_op_iwmmxt_addul_M0_wRn(rd1);
2250 break;
2251 case 0xb:
2252 gen_op_iwmmxt_addsl_M0_wRn(rd1);
2253 break;
2254 default:
2255 return 1;
2256 }
2257 gen_op_iwmmxt_movq_wRn_M0(wrd);
2258 gen_op_iwmmxt_set_mup();
2259 gen_op_iwmmxt_set_cup();
2260 break;
2261 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2262 case 0x408: case 0x508: case 0x608: case 0x708:
2263 case 0x808: case 0x908: case 0xa08: case 0xb08:
2264 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2265 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0)
2266 return 1;
2267 wrd = (insn >> 12) & 0xf;
2268 rd0 = (insn >> 16) & 0xf;
2269 rd1 = (insn >> 0) & 0xf;
2270 gen_op_iwmmxt_movq_M0_wRn(rd0);
2271 switch ((insn >> 22) & 3) {
2272 case 1:
2273 if (insn & (1 << 21))
2274 gen_op_iwmmxt_packsw_M0_wRn(rd1);
2275 else
2276 gen_op_iwmmxt_packuw_M0_wRn(rd1);
2277 break;
2278 case 2:
2279 if (insn & (1 << 21))
2280 gen_op_iwmmxt_packsl_M0_wRn(rd1);
2281 else
2282 gen_op_iwmmxt_packul_M0_wRn(rd1);
2283 break;
2284 case 3:
2285 if (insn & (1 << 21))
2286 gen_op_iwmmxt_packsq_M0_wRn(rd1);
2287 else
2288 gen_op_iwmmxt_packuq_M0_wRn(rd1);
2289 break;
2290 }
2291 gen_op_iwmmxt_movq_wRn_M0(wrd);
2292 gen_op_iwmmxt_set_mup();
2293 gen_op_iwmmxt_set_cup();
2294 break;
2295 case 0x201: case 0x203: case 0x205: case 0x207:
2296 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2297 case 0x211: case 0x213: case 0x215: case 0x217:
2298 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2299 wrd = (insn >> 5) & 0xf;
2300 rd0 = (insn >> 12) & 0xf;
2301 rd1 = (insn >> 0) & 0xf;
2302 if (rd0 == 0xf || rd1 == 0xf)
2303 return 1;
2304 gen_op_iwmmxt_movq_M0_wRn(wrd);
2305 tmp = load_reg(s, rd0);
2306 tmp2 = load_reg(s, rd1);
2307 switch ((insn >> 16) & 0xf) {
2308 case 0x0: /* TMIA */
2309 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2310 break;
2311 case 0x8: /* TMIAPH */
2312 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2313 break;
2314 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2315 if (insn & (1 << 16))
2316 tcg_gen_shri_i32(tmp, tmp, 16);
2317 if (insn & (1 << 17))
2318 tcg_gen_shri_i32(tmp2, tmp2, 16);
2319 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2320 break;
2321 default:
2322 tcg_temp_free_i32(tmp2);
2323 tcg_temp_free_i32(tmp);
2324 return 1;
2325 }
2326 tcg_temp_free_i32(tmp2);
2327 tcg_temp_free_i32(tmp);
2328 gen_op_iwmmxt_movq_wRn_M0(wrd);
2329 gen_op_iwmmxt_set_mup();
2330 break;
2331 default:
2332 return 1;
2333 }
2334
2335 return 0;
2336 }
2337
2338 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2339 (ie. an undefined instruction). */
2340 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2341 {
2342 int acc, rd0, rd1, rdhi, rdlo;
2343 TCGv tmp, tmp2;
2344
2345 if ((insn & 0x0ff00f10) == 0x0e200010) {
2346 /* Multiply with Internal Accumulate Format */
2347 rd0 = (insn >> 12) & 0xf;
2348 rd1 = insn & 0xf;
2349 acc = (insn >> 5) & 7;
2350
2351 if (acc != 0)
2352 return 1;
2353
2354 tmp = load_reg(s, rd0);
2355 tmp2 = load_reg(s, rd1);
2356 switch ((insn >> 16) & 0xf) {
2357 case 0x0: /* MIA */
2358 gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2);
2359 break;
2360 case 0x8: /* MIAPH */
2361 gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2);
2362 break;
2363 case 0xc: /* MIABB */
2364 case 0xd: /* MIABT */
2365 case 0xe: /* MIATB */
2366 case 0xf: /* MIATT */
2367 if (insn & (1 << 16))
2368 tcg_gen_shri_i32(tmp, tmp, 16);
2369 if (insn & (1 << 17))
2370 tcg_gen_shri_i32(tmp2, tmp2, 16);
2371 gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2);
2372 break;
2373 default:
2374 return 1;
2375 }
2376 tcg_temp_free_i32(tmp2);
2377 tcg_temp_free_i32(tmp);
2378
2379 gen_op_iwmmxt_movq_wRn_M0(acc);
2380 return 0;
2381 }
2382
2383 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2384 /* Internal Accumulator Access Format */
2385 rdhi = (insn >> 16) & 0xf;
2386 rdlo = (insn >> 12) & 0xf;
2387 acc = insn & 7;
2388
2389 if (acc != 0)
2390 return 1;
2391
2392 if (insn & ARM_CP_RW_BIT) { /* MRA */
2393 iwmmxt_load_reg(cpu_V0, acc);
2394 tcg_gen_trunc_i64_i32(cpu_R[rdlo], cpu_V0);
2395 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
2396 tcg_gen_trunc_i64_i32(cpu_R[rdhi], cpu_V0);
2397 tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
2398 } else { /* MAR */
2399 tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
2400 iwmmxt_store_reg(cpu_V0, acc);
2401 }
2402 return 0;
2403 }
2404
2405 return 1;
2406 }
2407
2408 /* Disassemble system coprocessor instruction. Return nonzero if
2409 instruction is not defined. */
2410 static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2411 {
2412 TCGv tmp, tmp2;
2413 uint32_t rd = (insn >> 12) & 0xf;
2414 uint32_t cp = (insn >> 8) & 0xf;
2415 if (IS_USER(s)) {
2416 return 1;
2417 }
2418
2419 if (insn & ARM_CP_RW_BIT) {
2420 if (!env->cp[cp].cp_read)
2421 return 1;
2422 gen_set_pc_im(s->pc);
2423 tmp = tcg_temp_new_i32();
2424 tmp2 = tcg_const_i32(insn);
2425 gen_helper_get_cp(tmp, cpu_env, tmp2);
2426 tcg_temp_free(tmp2);
2427 store_reg(s, rd, tmp);
2428 } else {
2429 if (!env->cp[cp].cp_write)
2430 return 1;
2431 gen_set_pc_im(s->pc);
2432 tmp = load_reg(s, rd);
2433 tmp2 = tcg_const_i32(insn);
2434 gen_helper_set_cp(cpu_env, tmp2, tmp);
2435 tcg_temp_free(tmp2);
2436 tcg_temp_free_i32(tmp);
2437 }
2438 return 0;
2439 }
2440
2441 static int cp15_user_ok(uint32_t insn)
2442 {
2443 int cpn = (insn >> 16) & 0xf;
2444 int cpm = insn & 0xf;
2445 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2446
2447 if (cpn == 13 && cpm == 0) {
2448 /* TLS register. */
2449 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2450 return 1;
2451 }
2452 if (cpn == 7) {
2453 /* ISB, DSB, DMB. */
2454 if ((cpm == 5 && op == 4)
2455 || (cpm == 10 && (op == 4 || op == 5)))
2456 return 1;
2457 }
2458 return 0;
2459 }
2460
2461 static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
2462 {
2463 TCGv tmp;
2464 int cpn = (insn >> 16) & 0xf;
2465 int cpm = insn & 0xf;
2466 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2467
2468 if (!arm_feature(env, ARM_FEATURE_V6K))
2469 return 0;
2470
2471 if (!(cpn == 13 && cpm == 0))
2472 return 0;
2473
2474 if (insn & ARM_CP_RW_BIT) {
2475 switch (op) {
2476 case 2:
2477 tmp = load_cpu_field(cp15.c13_tls1);
2478 break;
2479 case 3:
2480 tmp = load_cpu_field(cp15.c13_tls2);
2481 break;
2482 case 4:
2483 tmp = load_cpu_field(cp15.c13_tls3);
2484 break;
2485 default:
2486 return 0;
2487 }
2488 store_reg(s, rd, tmp);
2489
2490 } else {
2491 tmp = load_reg(s, rd);
2492 switch (op) {
2493 case 2:
2494 store_cpu_field(tmp, cp15.c13_tls1);
2495 break;
2496 case 3:
2497 store_cpu_field(tmp, cp15.c13_tls2);
2498 break;
2499 case 4:
2500 store_cpu_field(tmp, cp15.c13_tls3);
2501 break;
2502 default:
2503 tcg_temp_free_i32(tmp);
2504 return 0;
2505 }
2506 }
2507 return 1;
2508 }
2509
2510 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2511 instruction is not defined. */
2512 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
2513 {
2514 uint32_t rd;
2515 TCGv tmp, tmp2;
2516
2517 /* M profile cores use memory mapped registers instead of cp15. */
2518 if (arm_feature(env, ARM_FEATURE_M))
2519 return 1;
2520
2521 if ((insn & (1 << 25)) == 0) {
2522 if (insn & (1 << 20)) {
2523 /* mrrc */
2524 return 1;
2525 }
2526 /* mcrr. Used for block cache operations, so implement as no-op. */
2527 return 0;
2528 }
2529 if ((insn & (1 << 4)) == 0) {
2530 /* cdp */
2531 return 1;
2532 }
2533 if (IS_USER(s) && !cp15_user_ok(insn)) {
2534 return 1;
2535 }
2536
2537 /* Pre-v7 versions of the architecture implemented WFI via coprocessor
2538 * instructions rather than a separate instruction.
2539 */
2540 if ((insn & 0x0fff0fff) == 0x0e070f90) {
2541 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2542 * In v7, this must NOP.
2543 */
2544 if (!arm_feature(env, ARM_FEATURE_V7)) {
2545 /* Wait for interrupt. */
2546 gen_set_pc_im(s->pc);
2547 s->is_jmp = DISAS_WFI;
2548 }
2549 return 0;
2550 }
2551
2552 if ((insn & 0x0fff0fff) == 0x0e070f58) {
2553 /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
2554 * so this is slightly over-broad.
2555 */
2556 if (!arm_feature(env, ARM_FEATURE_V6)) {
2557 /* Wait for interrupt. */
2558 gen_set_pc_im(s->pc);
2559 s->is_jmp = DISAS_WFI;
2560 return 0;
2561 }
2562 /* Otherwise fall through to handle via helper function.
2563 * In particular, on v7 and some v6 cores this is one of
2564 * the VA-PA registers.
2565 */
2566 }
2567
2568 rd = (insn >> 12) & 0xf;
2569
2570 if (cp15_tls_load_store(env, s, insn, rd))
2571 return 0;
2572
2573 tmp2 = tcg_const_i32(insn);
2574 if (insn & ARM_CP_RW_BIT) {
2575 tmp = tcg_temp_new_i32();
2576 gen_helper_get_cp15(tmp, cpu_env, tmp2);
2577 /* If the destination register is r15 then sets condition codes. */
2578 if (rd != 15)
2579 store_reg(s, rd, tmp);
2580 else
2581 tcg_temp_free_i32(tmp);
2582 } else {
2583 tmp = load_reg(s, rd);
2584 gen_helper_set_cp15(cpu_env, tmp2, tmp);
2585 tcg_temp_free_i32(tmp);
2586 /* Normally we would always end the TB here, but Linux
2587 * arch/arm/mach-pxa/sleep.S expects two instructions following
2588 * an MMU enable to execute from cache. Imitate this behaviour. */
2589 if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
2590 (insn & 0x0fff0fff) != 0x0e010f10)
2591 gen_lookup_tb(s);
2592 }
2593 tcg_temp_free_i32(tmp2);
2594 return 0;
2595 }
2596
2597 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2598 #define VFP_SREG(insn, bigbit, smallbit) \
2599 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2600 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2601 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2602 reg = (((insn) >> (bigbit)) & 0x0f) \
2603 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2604 } else { \
2605 if (insn & (1 << (smallbit))) \
2606 return 1; \
2607 reg = ((insn) >> (bigbit)) & 0x0f; \
2608 }} while (0)
2609
2610 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2611 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2612 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2613 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2614 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2615 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2616
2617 /* Move between integer and VFP cores. */
2618 static TCGv gen_vfp_mrs(void)
2619 {
2620 TCGv tmp = tcg_temp_new_i32();
2621 tcg_gen_mov_i32(tmp, cpu_F0s);
2622 return tmp;
2623 }
2624
2625 static void gen_vfp_msr(TCGv tmp)
2626 {
2627 tcg_gen_mov_i32(cpu_F0s, tmp);
2628 tcg_temp_free_i32(tmp);
2629 }
2630
2631 static void gen_neon_dup_u8(TCGv var, int shift)
2632 {
2633 TCGv tmp = tcg_temp_new_i32();
2634 if (shift)
2635 tcg_gen_shri_i32(var, var, shift);
2636 tcg_gen_ext8u_i32(var, var);
2637 tcg_gen_shli_i32(tmp, var, 8);
2638 tcg_gen_or_i32(var, var, tmp);
2639 tcg_gen_shli_i32(tmp, var, 16);
2640 tcg_gen_or_i32(var, var, tmp);
2641 tcg_temp_free_i32(tmp);
2642 }
2643
2644 static void gen_neon_dup_low16(TCGv var)
2645 {
2646 TCGv tmp = tcg_temp_new_i32();
2647 tcg_gen_ext16u_i32(var, var);
2648 tcg_gen_shli_i32(tmp, var, 16);
2649 tcg_gen_or_i32(var, var, tmp);
2650 tcg_temp_free_i32(tmp);
2651 }
2652
2653 static void gen_neon_dup_high16(TCGv var)
2654 {
2655 TCGv tmp = tcg_temp_new_i32();
2656 tcg_gen_andi_i32(var, var, 0xffff0000);
2657 tcg_gen_shri_i32(tmp, var, 16);
2658 tcg_gen_or_i32(var, var, tmp);
2659 tcg_temp_free_i32(tmp);
2660 }
2661
2662 static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size)
2663 {
2664 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2665 TCGv tmp;
2666 switch (size) {
2667 case 0:
2668 tmp = gen_ld8u(addr, IS_USER(s));
2669 gen_neon_dup_u8(tmp, 0);
2670 break;
2671 case 1:
2672 tmp = gen_ld16u(addr, IS_USER(s));
2673 gen_neon_dup_low16(tmp);
2674 break;
2675 case 2:
2676 tmp = gen_ld32(addr, IS_USER(s));
2677 break;
2678 default: /* Avoid compiler warnings. */
2679 abort();
2680 }
2681 return tmp;
2682 }
2683
2684 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2685 (ie. an undefined instruction). */
2686 static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2687 {
2688 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
2689 int dp, veclen;
2690 TCGv addr;
2691 TCGv tmp;
2692 TCGv tmp2;
2693
2694 if (!arm_feature(env, ARM_FEATURE_VFP))
2695 return 1;
2696
2697 if (!s->vfp_enabled) {
2698 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2699 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2700 return 1;
2701 rn = (insn >> 16) & 0xf;
2702 if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC
2703 && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0)
2704 return 1;
2705 }
2706 dp = ((insn & 0xf00) == 0xb00);
2707 switch ((insn >> 24) & 0xf) {
2708 case 0xe:
2709 if (insn & (1 << 4)) {
2710 /* single register transfer */
2711 rd = (insn >> 12) & 0xf;
2712 if (dp) {
2713 int size;
2714 int pass;
2715
2716 VFP_DREG_N(rn, insn);
2717 if (insn & 0xf)
2718 return 1;
2719 if (insn & 0x00c00060
2720 && !arm_feature(env, ARM_FEATURE_NEON))
2721 return 1;
2722
2723 pass = (insn >> 21) & 1;
2724 if (insn & (1 << 22)) {
2725 size = 0;
2726 offset = ((insn >> 5) & 3) * 8;
2727 } else if (insn & (1 << 5)) {
2728 size = 1;
2729 offset = (insn & (1 << 6)) ? 16 : 0;
2730 } else {
2731 size = 2;
2732 offset = 0;
2733 }
2734 if (insn & ARM_CP_RW_BIT) {
2735 /* vfp->arm */
2736 tmp = neon_load_reg(rn, pass);
2737 switch (size) {
2738 case 0:
2739 if (offset)
2740 tcg_gen_shri_i32(tmp, tmp, offset);
2741 if (insn & (1 << 23))
2742 gen_uxtb(tmp);
2743 else
2744 gen_sxtb(tmp);
2745 break;
2746 case 1:
2747 if (insn & (1 << 23)) {
2748 if (offset) {
2749 tcg_gen_shri_i32(tmp, tmp, 16);
2750 } else {
2751 gen_uxth(tmp);
2752 }
2753 } else {
2754 if (offset) {
2755 tcg_gen_sari_i32(tmp, tmp, 16);
2756 } else {
2757 gen_sxth(tmp);
2758 }
2759 }
2760 break;
2761 case 2:
2762 break;
2763 }
2764 store_reg(s, rd, tmp);
2765 } else {
2766 /* arm->vfp */
2767 tmp = load_reg(s, rd);
2768 if (insn & (1 << 23)) {
2769 /* VDUP */
2770 if (size == 0) {
2771 gen_neon_dup_u8(tmp, 0);
2772 } else if (size == 1) {
2773 gen_neon_dup_low16(tmp);
2774 }
2775 for (n = 0; n <= pass * 2; n++) {
2776 tmp2 = tcg_temp_new_i32();
2777 tcg_gen_mov_i32(tmp2, tmp);
2778 neon_store_reg(rn, n, tmp2);
2779 }
2780 neon_store_reg(rn, n, tmp);
2781 } else {
2782 /* VMOV */
2783 switch (size) {
2784 case 0:
2785 tmp2 = neon_load_reg(rn, pass);
2786 gen_bfi(tmp, tmp2, tmp, offset, 0xff);
2787 tcg_temp_free_i32(tmp2);
2788 break;
2789 case 1:
2790 tmp2 = neon_load_reg(rn, pass);
2791 gen_bfi(tmp, tmp2, tmp, offset, 0xffff);
2792 tcg_temp_free_i32(tmp2);
2793 break;
2794 case 2:
2795 break;
2796 }
2797 neon_store_reg(rn, pass, tmp);
2798 }
2799 }
2800 } else { /* !dp */
2801 if ((insn & 0x6f) != 0x00)
2802 return 1;
2803 rn = VFP_SREG_N(insn);
2804 if (insn & ARM_CP_RW_BIT) {
2805 /* vfp->arm */
2806 if (insn & (1 << 21)) {
2807 /* system register */
2808 rn >>= 1;
2809
2810 switch (rn) {
2811 case ARM_VFP_FPSID:
2812 /* VFP2 allows access to FSID from userspace.
2813 VFP3 restricts all id registers to privileged
2814 accesses. */
2815 if (IS_USER(s)
2816 && arm_feature(env, ARM_FEATURE_VFP3))
2817 return 1;
2818 tmp = load_cpu_field(vfp.xregs[rn]);
2819 break;
2820 case ARM_VFP_FPEXC:
2821 if (IS_USER(s))
2822 return 1;
2823 tmp = load_cpu_field(vfp.xregs[rn]);
2824 break;
2825 case ARM_VFP_FPINST:
2826 case ARM_VFP_FPINST2:
2827 /* Not present in VFP3. */
2828 if (IS_USER(s)
2829 || arm_feature(env, ARM_FEATURE_VFP3))
2830 return 1;
2831 tmp = load_cpu_field(vfp.xregs[rn]);
2832 break;
2833 case ARM_VFP_FPSCR:
2834 if (rd == 15) {
2835 tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
2836 tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
2837 } else {
2838 tmp = tcg_temp_new_i32();
2839 gen_helper_vfp_get_fpscr(tmp, cpu_env);
2840 }
2841 break;
2842 case ARM_VFP_MVFR0:
2843 case ARM_VFP_MVFR1:
2844 if (IS_USER(s)
2845 || !arm_feature(env, ARM_FEATURE_VFP3))
2846 return 1;
2847 tmp = load_cpu_field(vfp.xregs[rn]);
2848 break;
2849 default:
2850 return 1;
2851 }
2852 } else {
2853 gen_mov_F0_vreg(0, rn);
2854 tmp = gen_vfp_mrs();
2855 }
2856 if (rd == 15) {
2857 /* Set the 4 flag bits in the CPSR. */
2858 gen_set_nzcv(tmp);
2859 tcg_temp_free_i32(tmp);
2860 } else {
2861 store_reg(s, rd, tmp);
2862 }
2863 } else {
2864 /* arm->vfp */
2865 tmp = load_reg(s, rd);
2866 if (insn & (1 << 21)) {
2867 rn >>= 1;
2868 /* system register */
2869 switch (rn) {
2870 case ARM_VFP_FPSID:
2871 case ARM_VFP_MVFR0:
2872 case ARM_VFP_MVFR1:
2873 /* Writes are ignored. */
2874 break;
2875 case ARM_VFP_FPSCR:
2876 gen_helper_vfp_set_fpscr(cpu_env, tmp);
2877 tcg_temp_free_i32(tmp);
2878 gen_lookup_tb(s);
2879 break;
2880 case ARM_VFP_FPEXC:
2881 if (IS_USER(s))
2882 return 1;
2883 /* TODO: VFP subarchitecture support.
2884 * For now, keep the EN bit only */
2885 tcg_gen_andi_i32(tmp, tmp, 1 << 30);
2886 store_cpu_field(tmp, vfp.xregs[rn]);
2887 gen_lookup_tb(s);
2888 break;
2889 case ARM_VFP_FPINST:
2890 case ARM_VFP_FPINST2:
2891 store_cpu_field(tmp, vfp.xregs[rn]);
2892 break;
2893 default:
2894 return 1;
2895 }
2896 } else {
2897 gen_vfp_msr(tmp);
2898 gen_mov_vreg_F0(0, rn);
2899 }
2900 }
2901 }
2902 } else {
2903 /* data processing */
2904 /* The opcode is in bits 23, 21, 20 and 6. */
2905 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2906 if (dp) {
2907 if (op == 15) {
2908 /* rn is opcode */
2909 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2910 } else {
2911 /* rn is register number */
2912 VFP_DREG_N(rn, insn);
2913 }
2914
2915 if (op == 15 && (rn == 15 || ((rn & 0x1c) == 0x18))) {
2916 /* Integer or single precision destination. */
2917 rd = VFP_SREG_D(insn);
2918 } else {
2919 VFP_DREG_D(rd, insn);
2920 }
2921 if (op == 15 &&
2922 (((rn & 0x1c) == 0x10) || ((rn & 0x14) == 0x14))) {
2923 /* VCVT from int is always from S reg regardless of dp bit.
2924 * VCVT with immediate frac_bits has same format as SREG_M
2925 */
2926 rm = VFP_SREG_M(insn);
2927 } else {
2928 VFP_DREG_M(rm, insn);
2929 }
2930 } else {
2931 rn = VFP_SREG_N(insn);
2932 if (op == 15 && rn == 15) {
2933 /* Double precision destination. */
2934 VFP_DREG_D(rd, insn);
2935 } else {
2936 rd = VFP_SREG_D(insn);
2937 }
2938 /* NB that we implicitly rely on the encoding for the frac_bits
2939 * in VCVT of fixed to float being the same as that of an SREG_M
2940 */
2941 rm = VFP_SREG_M(insn);
2942 }
2943
2944 veclen = s->vec_len;
2945 if (op == 15 && rn > 3)
2946 veclen = 0;
2947
2948 /* Shut up compiler warnings. */
2949 delta_m = 0;
2950 delta_d = 0;
2951 bank_mask = 0;
2952
2953 if (veclen > 0) {
2954 if (dp)
2955 bank_mask = 0xc;
2956 else
2957 bank_mask = 0x18;
2958
2959 /* Figure out what type of vector operation this is. */
2960 if ((rd & bank_mask) == 0) {
2961 /* scalar */
2962 veclen = 0;
2963 } else {
2964 if (dp)
2965 delta_d = (s->vec_stride >> 1) + 1;
2966 else
2967 delta_d = s->vec_stride + 1;
2968
2969 if ((rm & bank_mask) == 0) {
2970 /* mixed scalar/vector */
2971 delta_m = 0;
2972 } else {
2973 /* vector */
2974 delta_m = delta_d;
2975 }
2976 }
2977 }
2978
2979 /* Load the initial operands. */
2980 if (op == 15) {
2981 switch (rn) {
2982 case 16:
2983 case 17:
2984 /* Integer source */
2985 gen_mov_F0_vreg(0, rm);
2986 break;
2987 case 8:
2988 case 9:
2989 /* Compare */
2990 gen_mov_F0_vreg(dp, rd);
2991 gen_mov_F1_vreg(dp, rm);
2992 break;
2993 case 10:
2994 case 11:
2995 /* Compare with zero */
2996 gen_mov_F0_vreg(dp, rd);
2997 gen_vfp_F1_ld0(dp);
2998 break;
2999 case 20:
3000 case 21:
3001 case 22:
3002 case 23:
3003 case 28:
3004 case 29:
3005 case 30:
3006 case 31:
3007 /* Source and destination the same. */
3008 gen_mov_F0_vreg(dp, rd);
3009 break;
3010 default:
3011 /* One source operand. */
3012 gen_mov_F0_vreg(dp, rm);
3013 break;
3014 }
3015 } else {
3016 /* Two source operands. */
3017 gen_mov_F0_vreg(dp, rn);
3018 gen_mov_F1_vreg(dp, rm);
3019 }
3020
3021 for (;;) {
3022 /* Perform the calculation. */
3023 switch (op) {
3024 case 0: /* mac: fd + (fn * fm) */
3025 gen_vfp_mul(dp);
3026 gen_mov_F1_vreg(dp, rd);
3027 gen_vfp_add(dp);
3028 break;
3029 case 1: /* nmac: fd - (fn * fm) */
3030 gen_vfp_mul(dp);
3031 gen_vfp_neg(dp);
3032 gen_mov_F1_vreg(dp, rd);
3033 gen_vfp_add(dp);
3034 break;
3035 case 2: /* msc: -fd + (fn * fm) */
3036 gen_vfp_mul(dp);
3037 gen_mov_F1_vreg(dp, rd);
3038 gen_vfp_sub(dp);
3039 break;
3040 case 3: /* nmsc: -fd - (fn * fm) */
3041 gen_vfp_mul(dp);
3042 gen_vfp_neg(dp);
3043 gen_mov_F1_vreg(dp, rd);
3044 gen_vfp_sub(dp);
3045 break;
3046 case 4: /* mul: fn * fm */
3047 gen_vfp_mul(dp);
3048 break;
3049 case 5: /* nmul: -(fn * fm) */
3050 gen_vfp_mul(dp);
3051 gen_vfp_neg(dp);
3052 break;
3053 case 6: /* add: fn + fm */
3054 gen_vfp_add(dp);
3055 break;
3056 case 7: /* sub: fn - fm */
3057 gen_vfp_sub(dp);
3058 break;
3059 case 8: /* div: fn / fm */
3060 gen_vfp_div(dp);
3061 break;
3062 case 14: /* fconst */
3063 if (!arm_feature(env, ARM_FEATURE_VFP3))
3064 return 1;
3065
3066 n = (insn << 12) & 0x80000000;
3067 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3068 if (dp) {
3069 if (i & 0x40)
3070 i |= 0x3f80;
3071 else
3072 i |= 0x4000;
3073 n |= i << 16;
3074 tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32);
3075 } else {
3076 if (i & 0x40)
3077 i |= 0x780;
3078 else
3079 i |= 0x800;
3080 n |= i << 19;
3081 tcg_gen_movi_i32(cpu_F0s, n);
3082 }
3083 break;
3084 case 15: /* extension space */
3085 switch (rn) {
3086 case 0: /* cpy */
3087 /* no-op */
3088 break;
3089 case 1: /* abs */
3090 gen_vfp_abs(dp);
3091 break;
3092 case 2: /* neg */
3093 gen_vfp_neg(dp);
3094 break;
3095 case 3: /* sqrt */
3096 gen_vfp_sqrt(dp);
3097 break;
3098 case 4: /* vcvtb.f32.f16 */
3099 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3100 return 1;
3101 tmp = gen_vfp_mrs();
3102 tcg_gen_ext16u_i32(tmp, tmp);
3103 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3104 tcg_temp_free_i32(tmp);
3105 break;
3106 case 5: /* vcvtt.f32.f16 */
3107 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3108 return 1;
3109 tmp = gen_vfp_mrs();
3110 tcg_gen_shri_i32(tmp, tmp, 16);
3111 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp, cpu_env);
3112 tcg_temp_free_i32(tmp);
3113 break;
3114 case 6: /* vcvtb.f16.f32 */
3115 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3116 return 1;
3117 tmp = tcg_temp_new_i32();
3118 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3119 gen_mov_F0_vreg(0, rd);
3120 tmp2 = gen_vfp_mrs();
3121 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
3122 tcg_gen_or_i32(tmp, tmp, tmp2);
3123 tcg_temp_free_i32(tmp2);
3124 gen_vfp_msr(tmp);
3125 break;
3126 case 7: /* vcvtt.f16.f32 */
3127 if (!arm_feature(env, ARM_FEATURE_VFP_FP16))
3128 return 1;
3129 tmp = tcg_temp_new_i32();
3130 gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
3131 tcg_gen_shli_i32(tmp, tmp, 16);
3132 gen_mov_F0_vreg(0, rd);
3133 tmp2 = gen_vfp_mrs();
3134 tcg_gen_ext16u_i32(tmp2, tmp2);
3135 tcg_gen_or_i32(tmp, tmp, tmp2);
3136 tcg_temp_free_i32(tmp2);
3137 gen_vfp_msr(tmp);
3138 break;
3139 case 8: /* cmp */
3140 gen_vfp_cmp(dp);
3141 break;
3142 case 9: /* cmpe */
3143 gen_vfp_cmpe(dp);
3144 break;
3145 case 10: /* cmpz */
3146 gen_vfp_cmp(dp);
3147 break;
3148 case 11: /* cmpez */
3149 gen_vfp_F1_ld0(dp);
3150 gen_vfp_cmpe(dp);
3151 break;
3152 case 15: /* single<->double conversion */
3153 if (dp)
3154 gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env);
3155 else
3156 gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env);
3157 break;
3158 case 16: /* fuito */
3159 gen_vfp_uito(dp);
3160 break;
3161 case 17: /* fsito */
3162 gen_vfp_sito(dp);
3163 break;
3164 case 20: /* fshto */
3165 if (!arm_feature(env, ARM_FEATURE_VFP3))
3166 return 1;
3167 gen_vfp_shto(dp, 16 - rm);
3168 break;
3169 case 21: /* fslto */
3170 if (!arm_feature(env, ARM_FEATURE_VFP3))
3171 return 1;
3172 gen_vfp_slto(dp, 32 - rm);
3173 break;
3174 case 22: /* fuhto */
3175 if (!arm_feature(env, ARM_FEATURE_VFP3))
3176 return 1;
3177 gen_vfp_uhto(dp, 16 - rm);
3178 break;
3179 case 23: /* fulto */
3180 if (!arm_feature(env, ARM_FEATURE_VFP3))
3181 return 1;
3182 gen_vfp_ulto(dp, 32 - rm);
3183 break;
3184 case 24: /* ftoui */
3185 gen_vfp_toui(dp);
3186 break;
3187 case 25: /* ftouiz */
3188 gen_vfp_touiz(dp);
3189 break;
3190 case 26: /* ftosi */
3191 gen_vfp_tosi(dp);
3192 break;
3193 case 27: /* ftosiz */
3194 gen_vfp_tosiz(dp);
3195 break;
3196 case 28: /* ftosh */
3197 if (!arm_feature(env, ARM_FEATURE_VFP3))
3198 return 1;
3199 gen_vfp_tosh(dp, 16 - rm);
3200 break;
3201 case 29: /* ftosl */
3202 if (!arm_feature(env, ARM_FEATURE_VFP3))
3203 return 1;
3204 gen_vfp_tosl(dp, 32 - rm);
3205 break;
3206 case 30: /* ftouh */
3207 if (!arm_feature(env, ARM_FEATURE_VFP3))
3208 return 1;
3209 gen_vfp_touh(dp, 16 - rm);
3210 break;
3211 case 31: /* ftoul */
3212 if (!arm_feature(env, ARM_FEATURE_VFP3))
3213 return 1;
3214 gen_vfp_toul(dp, 32 - rm);
3215 break;
3216 default: /* undefined */
3217 printf ("rn:%d\n", rn);
3218 return 1;
3219 }
3220 break;
3221 default: /* undefined */
3222 printf ("op:%d\n", op);
3223 return 1;
3224 }
3225
3226 /* Write back the result. */
3227 if (op == 15 && (rn >= 8 && rn <= 11))
3228 ; /* Comparison, do nothing. */
3229 else if (op == 15 && dp && ((rn & 0x1c) == 0x18))
3230 /* VCVT double to int: always integer result. */
3231 gen_mov_vreg_F0(0, rd);
3232 else if (op == 15 && rn == 15)
3233 /* conversion */
3234 gen_mov_vreg_F0(!dp, rd);
3235 else
3236 gen_mov_vreg_F0(dp, rd);
3237
3238 /* break out of the loop if we have finished */
3239 if (veclen == 0)
3240 break;
3241
3242 if (op == 15 && delta_m == 0) {
3243 /* single source one-many */
3244 while (veclen--) {
3245 rd = ((rd + delta_d) & (bank_mask - 1))
3246 | (rd & bank_mask);
3247 gen_mov_vreg_F0(dp, rd);
3248 }
3249 break;
3250 }
3251 /* Setup the next operands. */
3252 veclen--;
3253 rd = ((rd + delta_d) & (bank_mask - 1))
3254 | (rd & bank_mask);
3255
3256 if (op == 15) {
3257 /* One source operand. */
3258 rm = ((rm + delta_m) & (bank_mask - 1))
3259 | (rm & bank_mask);
3260 gen_mov_F0_vreg(dp, rm);
3261 } else {
3262 /* Two source operands. */
3263 rn = ((rn + delta_d) & (bank_mask - 1))
3264 | (rn & bank_mask);
3265 gen_mov_F0_vreg(dp, rn);
3266 if (delta_m) {
3267 rm = ((rm + delta_m) & (bank_mask - 1))
3268 | (rm & bank_mask);
3269 gen_mov_F1_vreg(dp, rm);
3270 }
3271 }
3272 }
3273 }
3274 break;
3275 case 0xc:
3276 case 0xd:
3277 if ((insn & 0x03e00000) == 0x00400000) {
3278 /* two-register transfer */
3279 rn = (insn >> 16) & 0xf;
3280 rd = (insn >> 12) & 0xf;
3281 if (dp) {
3282 VFP_DREG_M(rm, insn);
3283 } else {
3284 rm = VFP_SREG_M(insn);
3285 }
3286
3287 if (insn & ARM_CP_RW_BIT) {
3288 /* vfp->arm */
3289 if (dp) {
3290 gen_mov_F0_vreg(0, rm * 2);
3291 tmp = gen_vfp_mrs();
3292 store_reg(s, rd, tmp);
3293 gen_mov_F0_vreg(0, rm * 2 + 1);
3294 tmp = gen_vfp_mrs();
3295 store_reg(s, rn, tmp);
3296 } else {
3297 gen_mov_F0_vreg(0, rm);
3298 tmp = gen_vfp_mrs();
3299 store_reg(s, rd, tmp);
3300 gen_mov_F0_vreg(0, rm + 1);
3301 tmp = gen_vfp_mrs();
3302 store_reg(s, rn, tmp);
3303 }
3304 } else {
3305 /* arm->vfp */
3306 if (dp) {
3307 tmp = load_reg(s, rd);
3308 gen_vfp_msr(tmp);
3309 gen_mov_vreg_F0(0, rm * 2);
3310 tmp = load_reg(s, rn);
3311 gen_vfp_msr(tmp);
3312 gen_mov_vreg_F0(0, rm * 2 + 1);
3313 } else {
3314 tmp = load_reg(s, rd);
3315 gen_vfp_msr(tmp);
3316 gen_mov_vreg_F0(0, rm);
3317 tmp = load_reg(s, rn);
3318 gen_vfp_msr(tmp);
3319 gen_mov_vreg_F0(0, rm + 1);
3320 }
3321 }
3322 } else {
3323 /* Load/store */
3324 rn = (insn >> 16) & 0xf;
3325 if (dp)
3326 VFP_DREG_D(rd, insn);
3327 else
3328 rd = VFP_SREG_D(insn);
3329 if (s->thumb && rn == 15) {
3330 addr = tcg_temp_new_i32();
3331 tcg_gen_movi_i32(addr, s->pc & ~2);
3332 } else {
3333 addr = load_reg(s, rn);
3334 }
3335 if ((insn & 0x01200000) == 0x01000000) {
3336 /* Single load/store */
3337 offset = (insn & 0xff) << 2;
3338 if ((insn & (1 << 23)) == 0)
3339 offset = -offset;
3340 tcg_gen_addi_i32(addr, addr, offset);
3341 if (insn & (1 << 20)) {
3342 gen_vfp_ld(s, dp, addr);
3343 gen_mov_vreg_F0(dp, rd);
3344 } else {
3345 gen_mov_F0_vreg(dp, rd);
3346 gen_vfp_st(s, dp, addr);
3347 }
3348 tcg_temp_free_i32(addr);
3349 } else {
3350 /* load/store multiple */
3351 if (dp)
3352 n = (insn >> 1) & 0x7f;
3353 else
3354 n = insn & 0xff;
3355
3356 if (insn & (1 << 24)) /* pre-decrement */
3357 tcg_gen_addi_i32(addr, addr, -((insn & 0xff) << 2));
3358
3359 if (dp)
3360 offset = 8;
3361 else
3362 offset = 4;
3363 for (i = 0; i < n; i++) {
3364 if (insn & ARM_CP_RW_BIT) {
3365 /* load */
3366 gen_vfp_ld(s, dp, addr);
3367 gen_mov_vreg_F0(dp, rd + i);
3368 } else {
3369 /* store */
3370 gen_mov_F0_vreg(dp, rd + i);
3371 gen_vfp_st(s, dp, addr);
3372 }
3373 tcg_gen_addi_i32(addr, addr, offset);
3374 }
3375 if (insn & (1 << 21)) {
3376 /* writeback */
3377 if (insn & (1 << 24))
3378 offset = -offset * n;
3379 else if (dp && (insn & 1))
3380 offset = 4;
3381 else
3382 offset = 0;
3383
3384 if (offset != 0)
3385 tcg_gen_addi_i32(addr, addr, offset);
3386 store_reg(s, rn, addr);
3387 } else {
3388 tcg_temp_free_i32(addr);
3389 }
3390 }
3391 }
3392 break;
3393 default:
3394 /* Should never happen. */
3395 return 1;
3396 }
3397 return 0;
3398 }
3399
3400 static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
3401 {
3402 TranslationBlock *tb;
3403
3404 tb = s->tb;
3405 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3406 tcg_gen_goto_tb(n);
3407 gen_set_pc_im(dest);
3408 tcg_gen_exit_tb((tcg_target_long)tb + n);
3409 } else {
3410 gen_set_pc_im(dest);
3411 tcg_gen_exit_tb(0);
3412 }
3413 }
3414
3415 static inline void gen_jmp (DisasContext *s, uint32_t dest)
3416 {
3417 if (unlikely(s->singlestep_enabled)) {
3418 /* An indirect jump so that we still trigger the debug exception. */
3419 if (s->thumb)
3420 dest |= 1;
3421 gen_bx_im(s, dest);
3422 } else {
3423 gen_goto_tb(s, 0, dest);
3424 s->is_jmp = DISAS_TB_JUMP;
3425 }
3426 }
3427
3428 static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
3429 {
3430 if (x)
3431 tcg_gen_sari_i32(t0, t0, 16);
3432 else
3433 gen_sxth(t0);
3434 if (y)
3435 tcg_gen_sari_i32(t1, t1, 16);
3436 else
3437 gen_sxth(t1);
3438 tcg_gen_mul_i32(t0, t0, t1);
3439 }
3440
3441 /* Return the mask of PSR bits set by a MSR instruction. */
3442 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
3443 uint32_t mask;
3444
3445 mask = 0;
3446 if (flags & (1 << 0))
3447 mask |= 0xff;
3448 if (flags & (1 << 1))
3449 mask |= 0xff00;
3450 if (flags & (1 << 2))
3451 mask |= 0xff0000;
3452 if (flags & (1 << 3))
3453 mask |= 0xff000000;
3454
3455 /* Mask out undefined bits. */
3456 mask &= ~CPSR_RESERVED;
3457 if (!arm_feature(env, ARM_FEATURE_V4T))
3458 mask &= ~CPSR_T;
3459 if (!arm_feature(env, ARM_FEATURE_V5))
3460 mask &= ~CPSR_Q; /* V5TE in reality*/
3461 if (!arm_feature(env, ARM_FEATURE_V6))
3462 mask &= ~(CPSR_E | CPSR_GE);
3463 if (!arm_feature(env, ARM_FEATURE_THUMB2))
3464 mask &= ~CPSR_IT;
3465 /* Mask out execution state bits. */
3466 if (!spsr)
3467 mask &= ~CPSR_EXEC;
3468 /* Mask out privileged bits. */
3469 if (IS_USER(s))
3470 mask &= CPSR_USER;
3471 return mask;
3472 }
3473
3474 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3475 static int gen_set_psr(DisasContext *s, uint32_t mask, int spsr, TCGv t0)
3476 {
3477 TCGv tmp;
3478 if (spsr) {
3479 /* ??? This is also undefined in system mode. */
3480 if (IS_USER(s))
3481 return 1;
3482
3483 tmp = load_cpu_field(spsr);
3484 tcg_gen_andi_i32(tmp, tmp, ~mask);
3485 tcg_gen_andi_i32(t0, t0, mask);
3486 tcg_gen_or_i32(tmp, tmp, t0);
3487 store_cpu_field(tmp, spsr);
3488 } else {
3489 gen_set_cpsr(t0, mask);
3490 }
3491 tcg_temp_free_i32(t0);
3492 gen_lookup_tb(s);
3493 return 0;
3494 }
3495
3496 /* Returns nonzero if access to the PSR is not permitted. */
3497 static int gen_set_psr_im(DisasContext *s, uint32_t mask, int spsr, uint32_t val)
3498 {
3499 TCGv tmp;
3500 tmp = tcg_temp_new_i32();
3501 tcg_gen_movi_i32(tmp, val);
3502 return gen_set_psr(s, mask, spsr, tmp);
3503 }
3504
3505 /* Generate an old-style exception return. Marks pc as dead. */
3506 static void gen_exception_return(DisasContext *s, TCGv pc)
3507 {
3508 TCGv tmp;
3509 store_reg(s, 15, pc);
3510 tmp = load_cpu_field(spsr);
3511 gen_set_cpsr(tmp, 0xffffffff);
3512 tcg_temp_free_i32(tmp);
3513 s->is_jmp = DISAS_UPDATE;
3514 }
3515
3516 /* Generate a v6 exception return. Marks both values as dead. */
3517 static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr)
3518 {
3519 gen_set_cpsr(cpsr, 0xffffffff);
3520 tcg_temp_free_i32(cpsr);
3521 store_reg(s, 15, pc);
3522 s->is_jmp = DISAS_UPDATE;
3523 }
3524
3525 static inline void
3526 gen_set_condexec (DisasContext *s)
3527 {
3528 if (s->condexec_mask) {
3529 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3530 TCGv tmp = tcg_temp_new_i32();
3531 tcg_gen_movi_i32(tmp, val);
3532 store_cpu_field(tmp, condexec_bits);
3533 }
3534 }
3535
3536 static void gen_exception_insn(DisasContext *s, int offset, int excp)
3537 {
3538 gen_set_condexec(s);
3539 gen_set_pc_im(s->pc - offset);
3540 gen_exception(excp);
3541 s->is_jmp = DISAS_JUMP;
3542 }
3543
3544 static void gen_nop_hint(DisasContext *s, int val)
3545 {
3546 switch (val) {
3547 case 3: /* wfi */
3548 gen_set_pc_im(s->pc);
3549 s->is_jmp = DISAS_WFI;
3550 break;
3551 case 2: /* wfe */
3552 case 4: /* sev */
3553 /* TODO: Implement SEV and WFE. May help SMP performance. */
3554 default: /* nop */
3555 break;
3556 }
3557 }
3558
3559 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3560
3561 static inline void gen_neon_add(int size, TCGv t0, TCGv t1)
3562 {
3563 switch (size) {
3564 case 0: gen_helper_neon_add_u8(t0, t0, t1); break;
3565 case 1: gen_helper_neon_add_u16(t0, t0, t1); break;
3566 case 2: tcg_gen_add_i32(t0, t0, t1); break;
3567 default: abort();
3568 }
3569 }
3570
3571 static inline void gen_neon_rsb(int size, TCGv t0, TCGv t1)
3572 {
3573 switch (size) {
3574 case 0: gen_helper_neon_sub_u8(t0, t1, t0); break;
3575 case 1: gen_helper_neon_sub_u16(t0, t1, t0); break;
3576 case 2: tcg_gen_sub_i32(t0, t1, t0); break;
3577 default: return;
3578 }
3579 }
3580
3581 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3582 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3583 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3584 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3585 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3586
3587 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3588 switch ((size << 1) | u) { \
3589 case 0: \
3590 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3591 break; \
3592 case 1: \
3593 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3594 break; \
3595 case 2: \
3596 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3597 break; \
3598 case 3: \
3599 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3600 break; \
3601 case 4: \
3602 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3603 break; \
3604 case 5: \
3605 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3606 break; \
3607 default: return 1; \
3608 }} while (0)
3609
3610 #define GEN_NEON_INTEGER_OP(name) do { \
3611 switch ((size << 1) | u) { \
3612 case 0: \
3613 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3614 break; \
3615 case 1: \
3616 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3617 break; \
3618 case 2: \
3619 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3620 break; \
3621 case 3: \
3622 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3623 break; \
3624 case 4: \
3625 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3626 break; \
3627 case 5: \
3628 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3629 break; \
3630 default: return 1; \
3631 }} while (0)
3632
3633 static TCGv neon_load_scratch(int scratch)
3634 {
3635 TCGv tmp = tcg_temp_new_i32();
3636 tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3637 return tmp;
3638 }
3639
3640 static void neon_store_scratch(int scratch, TCGv var)
3641 {
3642 tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
3643 tcg_temp_free_i32(var);
3644 }
3645
3646 static inline TCGv neon_get_scalar(int size, int reg)
3647 {
3648 TCGv tmp;
3649 if (size == 1) {
3650 tmp = neon_load_reg(reg & 7, reg >> 4);
3651 if (reg & 8) {
3652 gen_neon_dup_high16(tmp);
3653 } else {
3654 gen_neon_dup_low16(tmp);
3655 }
3656 } else {
3657 tmp = neon_load_reg(reg & 15, reg >> 4);
3658 }
3659 return tmp;
3660 }
3661
3662 static int gen_neon_unzip(int rd, int rm, int size, int q)
3663 {
3664 TCGv tmp, tmp2;
3665 if (!q && size == 2) {
3666 return 1;
3667 }
3668 tmp = tcg_const_i32(rd);
3669 tmp2 = tcg_const_i32(rm);
3670 if (q) {
3671 switch (size) {
3672 case 0:
3673 gen_helper_neon_qunzip8(tmp, tmp2);
3674 break;
3675 case 1:
3676 gen_helper_neon_qunzip16(tmp, tmp2);
3677 break;
3678 case 2:
3679 gen_helper_neon_qunzip32(tmp, tmp2);
3680 break;
3681 default:
3682 abort();
3683 }
3684 } else {
3685 switch (size) {
3686 case 0:
3687 gen_helper_neon_unzip8(tmp, tmp2);
3688 break;
3689 case 1:
3690 gen_helper_neon_unzip16(tmp, tmp2);
3691 break;
3692 default:
3693 abort();
3694 }
3695 }
3696 tcg_temp_free_i32(tmp);
3697 tcg_temp_free_i32(tmp2);
3698 return 0;
3699 }
3700
3701 static int gen_neon_zip(int rd, int rm, int size, int q)
3702 {
3703 TCGv tmp, tmp2;
3704 if (!q && size == 2) {
3705 return 1;
3706 }
3707 tmp = tcg_const_i32(rd);
3708 tmp2 = tcg_const_i32(rm);
3709 if (q) {
3710 switch (size) {
3711 case 0:
3712 gen_helper_neon_qzip8(tmp, tmp2);
3713 break;
3714 case 1:
3715 gen_helper_neon_qzip16(tmp, tmp2);
3716 break;
3717 case 2:
3718 gen_helper_neon_qzip32(tmp, tmp2);
3719 break;
3720 default:
3721 abort();
3722 }
3723 } else {
3724 switch (size) {
3725 case 0:
3726 gen_helper_neon_zip8(tmp, tmp2);
3727 break;
3728 case 1:
3729 gen_helper_neon_zip16(tmp, tmp2);
3730 break;
3731 default:
3732 abort();
3733 }
3734 }
3735 tcg_temp_free_i32(tmp);
3736 tcg_temp_free_i32(tmp2);
3737 return 0;
3738 }
3739
3740 static void gen_neon_trn_u8(TCGv t0, TCGv t1)
3741 {
3742 TCGv rd, tmp;
3743
3744 rd = tcg_temp_new_i32();
3745 tmp = tcg_temp_new_i32();
3746
3747 tcg_gen_shli_i32(rd, t0, 8);
3748 tcg_gen_andi_i32(rd, rd, 0xff00ff00);
3749 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
3750 tcg_gen_or_i32(rd, rd, tmp);
3751
3752 tcg_gen_shri_i32(t1, t1, 8);
3753 tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
3754 tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
3755 tcg_gen_or_i32(t1, t1, tmp);
3756 tcg_gen_mov_i32(t0, rd);
3757
3758 tcg_temp_free_i32(tmp);
3759 tcg_temp_free_i32(rd);
3760 }
3761
3762 static void gen_neon_trn_u16(TCGv t0, TCGv t1)
3763 {
3764 TCGv rd, tmp;
3765
3766 rd = tcg_temp_new_i32();
3767 tmp = tcg_temp_new_i32();
3768
3769 tcg_gen_shli_i32(rd, t0, 16);
3770 tcg_gen_andi_i32(tmp, t1, 0xffff);
3771 tcg_gen_or_i32(rd, rd, tmp);
3772 tcg_gen_shri_i32(t1, t1, 16);
3773 tcg_gen_andi_i32(tmp, t0, 0xffff0000);
3774 tcg_gen_or_i32(t1, t1, tmp);
3775 tcg_gen_mov_i32(t0, rd);
3776
3777 tcg_temp_free_i32(tmp);
3778 tcg_temp_free_i32(rd);
3779 }
3780
3781
3782 static struct {
3783 int nregs;
3784 int interleave;
3785 int spacing;
3786 } neon_ls_element_type[11] = {
3787 {4, 4, 1},
3788 {4, 4, 2},
3789 {4, 1, 1},
3790 {4, 2, 1},
3791 {3, 3, 1},
3792 {3, 3, 2},
3793 {3, 1, 1},
3794 {1, 1, 1},
3795 {2, 2, 1},
3796 {2, 2, 2},
3797 {2, 1, 1}
3798 };
3799
3800 /* Translate a NEON load/store element instruction. Return nonzero if the
3801 instruction is invalid. */
3802 static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3803 {
3804 int rd, rn, rm;
3805 int op;
3806 int nregs;
3807 int interleave;
3808 int spacing;
3809 int stride;
3810 int size;
3811 int reg;
3812 int pass;
3813 int load;
3814 int shift;
3815 int n;
3816 TCGv addr;
3817 TCGv tmp;
3818 TCGv tmp2;
3819 TCGv_i64 tmp64;
3820
3821 if (!s->vfp_enabled)
3822 return 1;
3823 VFP_DREG_D(rd, insn);
3824 rn = (insn >> 16) & 0xf;
3825 rm = insn & 0xf;
3826 load = (insn & (1 << 21)) != 0;
3827 if ((insn & (1 << 23)) == 0) {
3828 /* Load store all elements. */
3829 op = (insn >> 8) & 0xf;
3830 size = (insn >> 6) & 3;
3831 if (op > 10)
3832 return 1;
3833 nregs = neon_ls_element_type[op].nregs;
3834 interleave = neon_ls_element_type[op].interleave;
3835 spacing = neon_ls_element_type[op].spacing;
3836 if (size == 3 && (interleave | spacing) != 1)
3837 return 1;
3838 addr = tcg_temp_new_i32();
3839 load_reg_var(s, addr, rn);
3840 stride = (1 << size) * interleave;
3841 for (reg = 0; reg < nregs; reg++) {
3842 if (interleave > 2 || (interleave == 2 && nregs == 2)) {
3843 load_reg_var(s, addr, rn);
3844 tcg_gen_addi_i32(addr, addr, (1 << size) * reg);
3845 } else if (interleave == 2 && nregs == 4 && reg == 2) {
3846 load_reg_var(s, addr, rn);
3847 tcg_gen_addi_i32(addr, addr, 1 << size);
3848 }
3849 if (size == 3) {
3850 if (load) {
3851 tmp64 = gen_ld64(addr, IS_USER(s));
3852 neon_store_reg64(tmp64, rd);
3853 tcg_temp_free_i64(tmp64);
3854 } else {
3855 tmp64 = tcg_temp_new_i64();
3856 neon_load_reg64(tmp64, rd);
3857 gen_st64(tmp64, addr, IS_USER(s));
3858 }
3859 tcg_gen_addi_i32(addr, addr, stride);
3860 } else {
3861 for (pass = 0; pass < 2; pass++) {
3862 if (size == 2) {
3863 if (load) {
3864 tmp = gen_ld32(addr, IS_USER(s));
3865 neon_store_reg(rd, pass, tmp);
3866 } else {
3867 tmp = neon_load_reg(rd, pass);
3868 gen_st32(tmp, addr, IS_USER(s));
3869 }
3870 tcg_gen_addi_i32(addr, addr, stride);
3871 } else if (size == 1) {
3872 if (load) {
3873 tmp = gen_ld16u(addr, IS_USER(s));
3874 tcg_gen_addi_i32(addr, addr, stride);
3875 tmp2 = gen_ld16u(addr, IS_USER(s));
3876 tcg_gen_addi_i32(addr, addr, stride);
3877 tcg_gen_shli_i32(tmp2, tmp2, 16);
3878 tcg_gen_or_i32(tmp, tmp, tmp2);
3879 tcg_temp_free_i32(tmp2);
3880 neon_store_reg(rd, pass, tmp);
3881 } else {
3882 tmp = neon_load_reg(rd, pass);
3883 tmp2 = tcg_temp_new_i32();
3884 tcg_gen_shri_i32(tmp2, tmp, 16);
3885 gen_st16(tmp, addr, IS_USER(s));
3886 tcg_gen_addi_i32(addr, addr, stride);
3887 gen_st16(tmp2, addr, IS_USER(s));
3888 tcg_gen_addi_i32(addr, addr, stride);
3889 }
3890 } else /* size == 0 */ {
3891 if (load) {
3892 TCGV_UNUSED(tmp2);
3893 for (n = 0; n < 4; n++) {
3894 tmp = gen_ld8u(addr, IS_USER(s));
3895 tcg_gen_addi_i32(addr, addr, stride);
3896 if (n == 0) {
3897 tmp2 = tmp;
3898 } else {
3899 tcg_gen_shli_i32(tmp, tmp, n * 8);
3900 tcg_gen_or_i32(tmp2, tmp2, tmp);
3901 tcg_temp_free_i32(tmp);
3902 }
3903 }
3904 neon_store_reg(rd, pass, tmp2);
3905 } else {
3906 tmp2 = neon_load_reg(rd, pass);
3907 for (n = 0; n < 4; n++) {
3908 tmp = tcg_temp_new_i32();
3909 if (n == 0) {
3910 tcg_gen_mov_i32(tmp, tmp2);
3911 } else {
3912 tcg_gen_shri_i32(tmp, tmp2, n * 8);
3913 }
3914 gen_st8(tmp, addr, IS_USER(s));
3915 tcg_gen_addi_i32(addr, addr, stride);
3916 }
3917 tcg_temp_free_i32(tmp2);
3918 }
3919 }
3920 }
3921 }
3922 rd += spacing;
3923 }
3924 tcg_temp_free_i32(addr);
3925 stride = nregs * 8;
3926 } else {
3927 size = (insn >> 10) & 3;
3928 if (size == 3) {
3929 /* Load single element to all lanes. */
3930 int a = (insn >> 4) & 1;
3931 if (!load) {
3932 return 1;
3933 }
3934 size = (insn >> 6) & 3;
3935 nregs = ((insn >> 8) & 3) + 1;
3936
3937 if (size == 3) {
3938 if (nregs != 4 || a == 0) {
3939 return 1;
3940 }
3941 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
3942 size = 2;
3943 }
3944 if (nregs == 1 && a == 1 && size == 0) {
3945 return 1;
3946 }
3947 if (nregs == 3 && a == 1) {
3948 return 1;
3949 }
3950 addr = tcg_temp_new_i32();
3951 load_reg_var(s, addr, rn);
3952 if (nregs == 1) {
3953 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
3954 tmp = gen_load_and_replicate(s, addr, size);
3955 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3956 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3957 if (insn & (1 << 5)) {
3958 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 0));
3959 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd + 1, 1));
3960 }
3961 tcg_temp_free_i32(tmp);
3962 } else {
3963 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
3964 stride = (insn & (1 << 5)) ? 2 : 1;
3965 for (reg = 0; reg < nregs; reg++) {
3966 tmp = gen_load_and_replicate(s, addr, size);
3967 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 0));
3968 tcg_gen_st_i32(tmp, cpu_env, neon_reg_offset(rd, 1));
3969 tcg_temp_free_i32(tmp);
3970 tcg_gen_addi_i32(addr, addr, 1 << size);
3971 rd += stride;
3972 }
3973 }
3974 tcg_temp_free_i32(addr);
3975 stride = (1 << size) * nregs;
3976 } else {
3977 /* Single element. */
3978 pass = (insn >> 7) & 1;
3979 switch (size) {
3980 case 0:
3981 shift = ((insn >> 5) & 3) * 8;
3982 stride = 1;
3983 break;
3984 case 1:
3985 shift = ((insn >> 6) & 1) * 16;
3986 stride = (insn & (1 << 5)) ? 2 : 1;
3987 break;
3988 case 2:
3989 shift = 0;
3990 stride = (insn & (1 << 6)) ? 2 : 1;
3991 break;
3992 default:
3993 abort();
3994 }
3995 nregs = ((insn >> 8) & 3) + 1;
3996 addr = tcg_temp_new_i32();
3997 load_reg_var(s, addr, rn);
3998 for (reg = 0; reg < nregs; reg++) {
3999 if (load) {
4000 switch (size) {
4001 case 0:
4002 tmp = gen_ld8u(addr, IS_USER(s));
4003 break;
4004 case 1:
4005 tmp = gen_ld16u(addr, IS_USER(s));
4006 break;
4007 case 2:
4008 tmp = gen_ld32(addr, IS_USER(s));
4009 break;
4010 default: /* Avoid compiler warnings. */
4011 abort();
4012 }
4013 if (size != 2) {
4014 tmp2 = neon_load_reg(rd, pass);
4015 gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff);
4016 tcg_temp_free_i32(tmp2);
4017 }
4018 neon_store_reg(rd, pass, tmp);
4019 } else { /* Store */
4020 tmp = neon_load_reg(rd, pass);
4021 if (shift)
4022 tcg_gen_shri_i32(tmp, tmp, shift);
4023 switch (size) {
4024 case 0:
4025 gen_st8(tmp, addr, IS_USER(s));
4026 break;
4027 case 1:
4028 gen_st16(tmp, addr, IS_USER(s));
4029 break;
4030 case 2:
4031 gen_st32(tmp, addr, IS_USER(s));
4032 break;
4033 }
4034 }
4035 rd += stride;
4036 tcg_gen_addi_i32(addr, addr, 1 << size);
4037 }
4038 tcg_temp_free_i32(addr);
4039 stride = nregs * (1 << size);
4040 }
4041 }
4042 if (rm != 15) {
4043 TCGv base;
4044
4045 base = load_reg(s, rn);
4046 if (rm == 13) {
4047 tcg_gen_addi_i32(base, base, stride);
4048 } else {
4049 TCGv index;
4050 index = load_reg(s, rm);
4051 tcg_gen_add_i32(base, base, index);
4052 tcg_temp_free_i32(index);
4053 }
4054 store_reg(s, rn, base);
4055 }
4056 return 0;
4057 }
4058
4059 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4060 static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c)
4061 {
4062 tcg_gen_and_i32(t, t, c);
4063 tcg_gen_andc_i32(f, f, c);
4064 tcg_gen_or_i32(dest, t, f);
4065 }
4066
4067 static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src)
4068 {
4069 switch (size) {
4070 case 0: gen_helper_neon_narrow_u8(dest, src); break;
4071 case 1: gen_helper_neon_narrow_u16(dest, src); break;
4072 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
4073 default: abort();
4074 }
4075 }
4076
4077 static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src)
4078 {
4079 switch (size) {
4080 case 0: gen_helper_neon_narrow_sat_s8(dest, src); break;
4081 case 1: gen_helper_neon_narrow_sat_s16(dest, src); break;
4082 case 2: gen_helper_neon_narrow_sat_s32(dest, src); break;
4083 default: abort();
4084 }
4085 }
4086
4087 static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src)
4088 {
4089 switch (size) {
4090 case 0: gen_helper_neon_narrow_sat_u8(dest, src); break;
4091 case 1: gen_helper_neon_narrow_sat_u16(dest, src); break;
4092 case 2: gen_helper_neon_narrow_sat_u32(dest, src); break;
4093 default: abort();
4094 }
4095 }
4096
4097 static inline void gen_neon_unarrow_sats(int size, TCGv dest, TCGv_i64 src)
4098 {
4099 switch (size) {
4100 case 0: gen_helper_neon_unarrow_sat8(dest, src); break;
4101 case 1: gen_helper_neon_unarrow_sat16(dest, src); break;
4102 case 2: gen_helper_neon_unarrow_sat32(dest, src); break;
4103 default: abort();
4104 }
4105 }
4106
4107 static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift,
4108 int q, int u)
4109 {
4110 if (q) {
4111 if (u) {
4112 switch (size) {
4113 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4114 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4115 default: abort();
4116 }
4117 } else {
4118 switch (size) {
4119 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
4120 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4121 default: abort();
4122 }
4123 }
4124 } else {
4125 if (u) {
4126 switch (size) {
4127 case 1: gen_helper_neon_shl_u16(var, var, shift); break;
4128 case 2: gen_helper_neon_shl_u32(var, var, shift); break;
4129 default: abort();
4130 }
4131 } else {
4132 switch (size) {
4133 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4134 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4135 default: abort();
4136 }
4137 }
4138 }
4139 }
4140
4141 static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u)
4142 {
4143 if (u) {
4144 switch (size) {
4145 case 0: gen_helper_neon_widen_u8(dest, src); break;
4146 case 1: gen_helper_neon_widen_u16(dest, src); break;
4147 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4148 default: abort();
4149 }
4150 } else {
4151 switch (size) {
4152 case 0: gen_helper_neon_widen_s8(dest, src); break;
4153 case 1: gen_helper_neon_widen_s16(dest, src); break;
4154 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4155 default: abort();
4156 }
4157 }
4158 tcg_temp_free_i32(src);
4159 }
4160
4161 static inline void gen_neon_addl(int size)
4162 {
4163 switch (size) {
4164 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4165 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4166 case 2: tcg_gen_add_i64(CPU_V001); break;
4167 default: abort();
4168 }
4169 }
4170
4171 static inline void gen_neon_subl(int size)
4172 {
4173 switch (size) {
4174 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4175 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4176 case 2: tcg_gen_sub_i64(CPU_V001); break;
4177 default: abort();
4178 }
4179 }
4180
4181 static inline void gen_neon_negl(TCGv_i64 var, int size)
4182 {
4183 switch (size) {
4184 case 0: gen_helper_neon_negl_u16(var, var); break;
4185 case 1: gen_helper_neon_negl_u32(var, var); break;
4186 case 2: gen_helper_neon_negl_u64(var, var); break;
4187 default: abort();
4188 }
4189 }
4190
4191 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4192 {
4193 switch (size) {
4194 case 1: gen_helper_neon_addl_saturate_s32(op0, op0, op1); break;
4195 case 2: gen_helper_neon_addl_saturate_s64(op0, op0, op1); break;
4196 default: abort();
4197 }
4198 }
4199
4200 static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u)
4201 {
4202 TCGv_i64 tmp;
4203
4204 switch ((size << 1) | u) {
4205 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4206 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4207 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4208 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4209 case 4:
4210 tmp = gen_muls_i64_i32(a, b);
4211 tcg_gen_mov_i64(dest, tmp);
4212 tcg_temp_free_i64(tmp);
4213 break;
4214 case 5:
4215 tmp = gen_mulu_i64_i32(a, b);
4216 tcg_gen_mov_i64(dest, tmp);
4217 tcg_temp_free_i64(tmp);
4218 break;
4219 default: abort();
4220 }
4221
4222 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4223 Don't forget to clean them now. */
4224 if (size < 2) {
4225 tcg_temp_free_i32(a);
4226 tcg_temp_free_i32(b);
4227 }
4228 }
4229
4230 static void gen_neon_narrow_op(int op, int u, int size, TCGv dest, TCGv_i64 src)
4231 {
4232 if (op) {
4233 if (u) {
4234 gen_neon_unarrow_sats(size, dest, src);
4235 } else {
4236 gen_neon_narrow(size, dest, src);
4237 }
4238 } else {
4239 if (u) {
4240 gen_neon_narrow_satu(size, dest, src);
4241 } else {
4242 gen_neon_narrow_sats(size, dest, src);
4243 }
4244 }
4245 }
4246
4247 /* Symbolic constants for op fields for Neon 3-register same-length.
4248 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
4249 * table A7-9.
4250 */
4251 #define NEON_3R_VHADD 0
4252 #define NEON_3R_VQADD 1
4253 #define NEON_3R_VRHADD 2
4254 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
4255 #define NEON_3R_VHSUB 4
4256 #define NEON_3R_VQSUB 5
4257 #define NEON_3R_VCGT 6
4258 #define NEON_3R_VCGE 7
4259 #define NEON_3R_VSHL 8
4260 #define NEON_3R_VQSHL 9
4261 #define NEON_3R_VRSHL 10
4262 #define NEON_3R_VQRSHL 11
4263 #define NEON_3R_VMAX 12
4264 #define NEON_3R_VMIN 13
4265 #define NEON_3R_VABD 14
4266 #define NEON_3R_VABA 15
4267 #define NEON_3R_VADD_VSUB 16
4268 #define NEON_3R_VTST_VCEQ 17
4269 #define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
4270 #define NEON_3R_VMUL 19
4271 #define NEON_3R_VPMAX 20
4272 #define NEON_3R_VPMIN 21
4273 #define NEON_3R_VQDMULH_VQRDMULH 22
4274 #define NEON_3R_VPADD 23
4275 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
4276 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
4277 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
4278 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
4279 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
4280 #define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */
4281
4282 static const uint8_t neon_3r_sizes[] = {
4283 [NEON_3R_VHADD] = 0x7,
4284 [NEON_3R_VQADD] = 0xf,
4285 [NEON_3R_VRHADD] = 0x7,
4286 [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
4287 [NEON_3R_VHSUB] = 0x7,
4288 [NEON_3R_VQSUB] = 0xf,
4289 [NEON_3R_VCGT] = 0x7,
4290 [NEON_3R_VCGE] = 0x7,
4291 [NEON_3R_VSHL] = 0xf,
4292 [NEON_3R_VQSHL] = 0xf,
4293 [NEON_3R_VRSHL] = 0xf,
4294 [NEON_3R_VQRSHL] = 0xf,
4295 [NEON_3R_VMAX] = 0x7,
4296 [NEON_3R_VMIN] = 0x7,
4297 [NEON_3R_VABD] = 0x7,
4298 [NEON_3R_VABA] = 0x7,
4299 [NEON_3R_VADD_VSUB] = 0xf,
4300 [NEON_3R_VTST_VCEQ] = 0x7,
4301 [NEON_3R_VML] = 0x7,
4302 [NEON_3R_VMUL] = 0x7,
4303 [NEON_3R_VPMAX] = 0x7,
4304 [NEON_3R_VPMIN] = 0x7,
4305 [NEON_3R_VQDMULH_VQRDMULH] = 0x6,
4306 [NEON_3R_VPADD] = 0x7,
4307 [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
4308 [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
4309 [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
4310 [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
4311 [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
4312 [NEON_3R_VRECPS_VRSQRTS] = 0x5, /* size bit 1 encodes op */
4313 };
4314
4315 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
4316 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
4317 * table A7-13.
4318 */
4319 #define NEON_2RM_VREV64 0
4320 #define NEON_2RM_VREV32 1
4321 #define NEON_2RM_VREV16 2
4322 #define NEON_2RM_VPADDL 4
4323 #define NEON_2RM_VPADDL_U 5
4324 #define NEON_2RM_VCLS 8
4325 #define NEON_2RM_VCLZ 9
4326 #define NEON_2RM_VCNT 10
4327 #define NEON_2RM_VMVN 11
4328 #define NEON_2RM_VPADAL 12
4329 #define NEON_2RM_VPADAL_U 13
4330 #define NEON_2RM_VQABS 14
4331 #define NEON_2RM_VQNEG 15
4332 #define NEON_2RM_VCGT0 16
4333 #define NEON_2RM_VCGE0 17
4334 #define NEON_2RM_VCEQ0 18
4335 #define NEON_2RM_VCLE0 19
4336 #define NEON_2RM_VCLT0 20
4337 #define NEON_2RM_VABS 22
4338 #define NEON_2RM_VNEG 23
4339 #define NEON_2RM_VCGT0_F 24
4340 #define NEON_2RM_VCGE0_F 25
4341 #define NEON_2RM_VCEQ0_F 26
4342 #define NEON_2RM_VCLE0_F 27
4343 #define NEON_2RM_VCLT0_F 28
4344 #define NEON_2RM_VABS_F 30
4345 #define NEON_2RM_VNEG_F 31
4346 #define NEON_2RM_VSWP 32
4347 #define NEON_2RM_VTRN 33
4348 #define NEON_2RM_VUZP 34
4349 #define NEON_2RM_VZIP 35
4350 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
4351 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
4352 #define NEON_2RM_VSHLL 38
4353 #define NEON_2RM_VCVT_F16_F32 44
4354 #define NEON_2RM_VCVT_F32_F16 46
4355 #define NEON_2RM_VRECPE 56
4356 #define NEON_2RM_VRSQRTE 57
4357 #define NEON_2RM_VRECPE_F 58
4358 #define NEON_2RM_VRSQRTE_F 59
4359 #define NEON_2RM_VCVT_FS 60
4360 #define NEON_2RM_VCVT_FU 61
4361 #define NEON_2RM_VCVT_SF 62
4362 #define NEON_2RM_VCVT_UF 63
4363
4364 static int neon_2rm_is_float_op(int op)
4365 {
4366 /* Return true if this neon 2reg-misc op is float-to-float */
4367 return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
4368 op >= NEON_2RM_VRECPE_F);
4369 }
4370
4371 /* Each entry in this array has bit n set if the insn allows
4372 * size value n (otherwise it will UNDEF). Since unallocated
4373 * op values will have no bits set they always UNDEF.
4374 */
4375 static const uint8_t neon_2rm_sizes[] = {
4376 [NEON_2RM_VREV64] = 0x7,
4377 [NEON_2RM_VREV32] = 0x3,
4378 [NEON_2RM_VREV16] = 0x1,
4379 [NEON_2RM_VPADDL] = 0x7,
4380 [NEON_2RM_VPADDL_U] = 0x7,
4381 [NEON_2RM_VCLS] = 0x7,
4382 [NEON_2RM_VCLZ] = 0x7,
4383 [NEON_2RM_VCNT] = 0x1,
4384 [NEON_2RM_VMVN] = 0x1,
4385 [NEON_2RM_VPADAL] = 0x7,
4386 [NEON_2RM_VPADAL_U] = 0x7,
4387 [NEON_2RM_VQABS] = 0x7,
4388 [NEON_2RM_VQNEG] = 0x7,
4389 [NEON_2RM_VCGT0] = 0x7,
4390 [NEON_2RM_VCGE0] = 0x7,
4391 [NEON_2RM_VCEQ0] = 0x7,
4392 [NEON_2RM_VCLE0] = 0x7,
4393 [NEON_2RM_VCLT0] = 0x7,
4394 [NEON_2RM_VABS] = 0x7,
4395 [NEON_2RM_VNEG] = 0x7,
4396 [NEON_2RM_VCGT0_F] = 0x4,
4397 [NEON_2RM_VCGE0_F] = 0x4,
4398 [NEON_2RM_VCEQ0_F] = 0x4,
4399 [NEON_2RM_VCLE0_F] = 0x4,
4400 [NEON_2RM_VCLT0_F] = 0x4,
4401 [NEON_2RM_VABS_F] = 0x4,
4402 [NEON_2RM_VNEG_F] = 0x4,
4403 [NEON_2RM_VSWP] = 0x1,
4404 [NEON_2RM_VTRN] = 0x7,
4405 [NEON_2RM_VUZP] = 0x7,
4406 [NEON_2RM_VZIP] = 0x7,
4407 [NEON_2RM_VMOVN] = 0x7,
4408 [NEON_2RM_VQMOVN] = 0x7,
4409 [NEON_2RM_VSHLL] = 0x7,
4410 [NEON_2RM_VCVT_F16_F32] = 0x2,
4411 [NEON_2RM_VCVT_F32_F16] = 0x2,
4412 [NEON_2RM_VRECPE] = 0x4,
4413 [NEON_2RM_VRSQRTE] = 0x4,
4414 [NEON_2RM_VRECPE_F] = 0x4,
4415 [NEON_2RM_VRSQRTE_F] = 0x4,
4416 [NEON_2RM_VCVT_FS] = 0x4,
4417 [NEON_2RM_VCVT_FU] = 0x4,
4418 [NEON_2RM_VCVT_SF] = 0x4,
4419 [NEON_2RM_VCVT_UF] = 0x4,
4420 };
4421
4422 /* Translate a NEON data processing instruction. Return nonzero if the
4423 instruction is invalid.
4424 We process data in a mixture of 32-bit and 64-bit chunks.
4425 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4426
4427 static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4428 {
4429 int op;
4430 int q;
4431 int rd, rn, rm;
4432 int size;
4433 int shift;
4434 int pass;
4435 int count;
4436 int pairwise;
4437 int u;
4438 uint32_t imm, mask;
4439 TCGv tmp, tmp2, tmp3, tmp4, tmp5;
4440 TCGv_i64 tmp64;
4441
4442 if (!s->vfp_enabled)
4443 return 1;
4444 q = (insn & (1 << 6)) != 0;
4445 u = (insn >> 24) & 1;
4446 VFP_DREG_D(rd, insn);
4447 VFP_DREG_N(rn, insn);
4448 VFP_DREG_M(rm, insn);
4449 size = (insn >> 20) & 3;
4450 if ((insn & (1 << 23)) == 0) {
4451 /* Three register same length. */
4452 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4453 /* Catch invalid op and bad size combinations: UNDEF */
4454 if ((neon_3r_sizes[op] & (1 << size)) == 0) {
4455 return 1;
4456 }
4457 /* All insns of this form UNDEF for either this condition or the
4458 * superset of cases "Q==1"; we catch the latter later.
4459 */
4460 if (q && ((rd | rn | rm) & 1)) {
4461 return 1;
4462 }
4463 if (size == 3 && op != NEON_3R_LOGIC) {
4464 /* 64-bit element instructions. */
4465 for (pass = 0; pass < (q ? 2 : 1); pass++) {
4466 neon_load_reg64(cpu_V0, rn + pass);
4467 neon_load_reg64(cpu_V1, rm + pass);
4468 switch (op) {
4469 case NEON_3R_VQADD:
4470 if (u) {
4471 gen_helper_neon_qadd_u64(cpu_V0, cpu_V0, cpu_V1);
4472 } else {
4473 gen_helper_neon_qadd_s64(cpu_V0, cpu_V0, cpu_V1);
4474 }
4475 break;
4476 case NEON_3R_VQSUB:
4477 if (u) {
4478 gen_helper_neon_qsub_u64(cpu_V0, cpu_V0, cpu_V1);
4479 } else {
4480 gen_helper_neon_qsub_s64(cpu_V0, cpu_V0, cpu_V1);
4481 }
4482 break;
4483 case NEON_3R_VSHL:
4484 if (u) {
4485 gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0);
4486 } else {
4487 gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0);
4488 }
4489 break;
4490 case NEON_3R_VQSHL:
4491 if (u) {
4492 gen_helper_neon_qshl_u64(cpu_V0, cpu_V1, cpu_V0);
4493 } else {
4494 gen_helper_neon_qshl_s64(cpu_V0, cpu_V1, cpu_V0);
4495 }
4496 break;
4497 case NEON_3R_VRSHL:
4498 if (u) {
4499 gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0);
4500 } else {
4501 gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0);
4502 }
4503 break;
4504 case NEON_3R_VQRSHL:
4505 if (u) {
4506 gen_helper_neon_qrshl_u64(cpu_V0, cpu_V1, cpu_V0);
4507 } else {
4508 gen_helper_neon_qrshl_s64(cpu_V0, cpu_V1, cpu_V0);
4509 }
4510 break;
4511 case NEON_3R_VADD_VSUB:
4512 if (u) {
4513 tcg_gen_sub_i64(CPU_V001);
4514 } else {
4515 tcg_gen_add_i64(CPU_V001);
4516 }
4517 break;
4518 default:
4519 abort();
4520 }
4521 neon_store_reg64(cpu_V0, rd + pass);
4522 }
4523 return 0;
4524 }
4525 pairwise = 0;
4526 switch (op) {
4527 case NEON_3R_VSHL:
4528 case NEON_3R_VQSHL:
4529 case NEON_3R_VRSHL:
4530 case NEON_3R_VQRSHL:
4531 {
4532 int rtmp;
4533 /* Shift instruction operands are reversed. */
4534 rtmp = rn;
4535 rn = rm;
4536 rm = rtmp;
4537 }
4538 break;
4539 case NEON_3R_VPADD:
4540 if (u) {
4541 return 1;
4542 }
4543 /* Fall through */
4544 case NEON_3R_VPMAX:
4545 case NEON_3R_VPMIN:
4546 pairwise = 1;
4547 break;
4548 case NEON_3R_FLOAT_ARITH:
4549 pairwise = (u && size < 2); /* if VPADD (float) */
4550 break;
4551 case NEON_3R_FLOAT_MINMAX:
4552 pairwise = u; /* if VPMIN/VPMAX (float) */
4553 break;
4554 case NEON_3R_FLOAT_CMP:
4555 if (!u && size) {
4556 /* no encoding for U=0 C=1x */
4557 return 1;
4558 }
4559 break;
4560 case NEON_3R_FLOAT_ACMP:
4561 if (!u) {
4562 return 1;
4563 }
4564 break;
4565 case NEON_3R_VRECPS_VRSQRTS:
4566 if (u) {
4567 return 1;
4568 }
4569 break;
4570 case NEON_3R_VMUL:
4571 if (u && (size != 0)) {
4572 /* UNDEF on invalid size for polynomial subcase */
4573 return 1;
4574 }
4575 break;
4576 default:
4577 break;
4578 }
4579
4580 if (pairwise && q) {
4581 /* All the pairwise insns UNDEF if Q is set */
4582 return 1;
4583 }
4584
4585 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4586
4587 if (pairwise) {
4588 /* Pairwise. */
4589 if (pass < 1) {
4590 tmp = neon_load_reg(rn, 0);
4591 tmp2 = neon_load_reg(rn, 1);
4592 } else {
4593 tmp = neon_load_reg(rm, 0);
4594 tmp2 = neon_load_reg(rm, 1);
4595 }
4596 } else {
4597 /* Elementwise. */
4598 tmp = neon_load_reg(rn, pass);
4599 tmp2 = neon_load_reg(rm, pass);
4600 }
4601 switch (op) {
4602 case NEON_3R_VHADD:
4603 GEN_NEON_INTEGER_OP(hadd);
4604 break;
4605 case NEON_3R_VQADD:
4606 GEN_NEON_INTEGER_OP(qadd);
4607 break;
4608 case NEON_3R_VRHADD:
4609 GEN_NEON_INTEGER_OP(rhadd);
4610 break;
4611 case NEON_3R_LOGIC: /* Logic ops. */
4612 switch ((u << 2) | size) {
4613 case 0: /* VAND */
4614 tcg_gen_and_i32(tmp, tmp, tmp2);
4615 break;
4616 case 1: /* BIC */
4617 tcg_gen_andc_i32(tmp, tmp, tmp2);
4618 break;
4619 case 2: /* VORR */
4620 tcg_gen_or_i32(tmp, tmp, tmp2);
4621 break;
4622 case 3: /* VORN */
4623 tcg_gen_orc_i32(tmp, tmp, tmp2);
4624 break;
4625 case 4: /* VEOR */
4626 tcg_gen_xor_i32(tmp, tmp, tmp2);
4627 break;
4628 case 5: /* VBSL */
4629 tmp3 = neon_load_reg(rd, pass);
4630 gen_neon_bsl(tmp, tmp, tmp2, tmp3);
4631 tcg_temp_free_i32(tmp3);
4632 break;
4633 case 6: /* VBIT */
4634 tmp3 = neon_load_reg(rd, pass);
4635 gen_neon_bsl(tmp, tmp, tmp3, tmp2);
4636 tcg_temp_free_i32(tmp3);
4637 break;
4638 case 7: /* VBIF */
4639 tmp3 = neon_load_reg(rd, pass);
4640 gen_neon_bsl(tmp, tmp3, tmp, tmp2);
4641 tcg_temp_free_i32(tmp3);
4642 break;
4643 }
4644 break;
4645 case NEON_3R_VHSUB:
4646 GEN_NEON_INTEGER_OP(hsub);
4647 break;
4648 case NEON_3R_VQSUB:
4649 GEN_NEON_INTEGER_OP(qsub);
4650 break;
4651 case NEON_3R_VCGT:
4652 GEN_NEON_INTEGER_OP(cgt);
4653 break;
4654 case NEON_3R_VCGE:
4655 GEN_NEON_INTEGER_OP(cge);
4656 break;
4657 case NEON_3R_VSHL:
4658 GEN_NEON_INTEGER_OP(shl);
4659 break;
4660 case NEON_3R_VQSHL:
4661 GEN_NEON_INTEGER_OP(qshl);
4662 break;
4663 case NEON_3R_VRSHL:
4664 GEN_NEON_INTEGER_OP(rshl);
4665 break;
4666 case NEON_3R_VQRSHL:
4667 GEN_NEON_INTEGER_OP(qrshl);
4668 break;
4669 case NEON_3R_VMAX:
4670 GEN_NEON_INTEGER_OP(max);
4671 break;
4672 case NEON_3R_VMIN:
4673 GEN_NEON_INTEGER_OP(min);
4674 break;
4675 case NEON_3R_VABD:
4676 GEN_NEON_INTEGER_OP(abd);
4677 break;
4678 case NEON_3R_VABA:
4679 GEN_NEON_INTEGER_OP(abd);
4680 tcg_temp_free_i32(tmp2);
4681 tmp2 = neon_load_reg(rd, pass);
4682 gen_neon_add(size, tmp, tmp2);
4683 break;
4684 case NEON_3R_VADD_VSUB:
4685 if (!u) { /* VADD */
4686 gen_neon_add(size, tmp, tmp2);
4687 } else { /* VSUB */
4688 switch (size) {
4689 case 0: gen_helper_neon_sub_u8(tmp, tmp, tmp2); break;
4690 case 1: gen_helper_neon_sub_u16(tmp, tmp, tmp2); break;
4691 case 2: tcg_gen_sub_i32(tmp, tmp, tmp2); break;
4692 default: abort();
4693 }
4694 }
4695 break;
4696 case NEON_3R_VTST_VCEQ:
4697 if (!u) { /* VTST */
4698 switch (size) {
4699 case 0: gen_helper_neon_tst_u8(tmp, tmp, tmp2); break;
4700 case 1: gen_helper_neon_tst_u16(tmp, tmp, tmp2); break;
4701 case 2: gen_helper_neon_tst_u32(tmp, tmp, tmp2); break;
4702 default: abort();
4703 }
4704 } else { /* VCEQ */
4705 switch (size) {
4706 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
4707 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
4708 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
4709 default: abort();
4710 }
4711 }
4712 break;
4713 case NEON_3R_VML: /* VMLA, VMLAL, VMLS,VMLSL */
4714 switch (size) {
4715 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4716 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4717 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4718 default: abort();
4719 }
4720 tcg_temp_free_i32(tmp2);
4721 tmp2 = neon_load_reg(rd, pass);
4722 if (u) { /* VMLS */
4723 gen_neon_rsb(size, tmp, tmp2);
4724 } else { /* VMLA */
4725 gen_neon_add(size, tmp, tmp2);
4726 }
4727 break;
4728 case NEON_3R_VMUL:
4729 if (u) { /* polynomial */
4730 gen_helper_neon_mul_p8(tmp, tmp, tmp2);
4731 } else { /* Integer */
4732 switch (size) {
4733 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
4734 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
4735 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
4736 default: abort();
4737 }
4738 }
4739 break;
4740 case NEON_3R_VPMAX:
4741 GEN_NEON_INTEGER_OP(pmax);
4742 break;
4743 case NEON_3R_VPMIN:
4744 GEN_NEON_INTEGER_OP(pmin);
4745 break;
4746 case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
4747 if (!u) { /* VQDMULH */
4748 switch (size) {
4749 case 1: gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2); break;
4750 case 2: gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2); break;
4751 default: abort();
4752 }
4753 } else { /* VQRDMULH */
4754 switch (size) {
4755 case 1: gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2); break;
4756 case 2: gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2); break;
4757 default: abort();
4758 }
4759 }
4760 break;
4761 case NEON_3R_VPADD:
4762 switch (size) {
4763 case 0: gen_helper_neon_padd_u8(tmp, tmp, tmp2); break;
4764 case 1: gen_helper_neon_padd_u16(tmp, tmp, tmp2); break;
4765 case 2: tcg_gen_add_i32(tmp, tmp, tmp2); break;
4766 default: abort();
4767 }
4768 break;
4769 case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
4770 switch ((u << 2) | size) {
4771 case 0: /* VADD */
4772 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4773 break;
4774 case 2: /* VSUB */
4775 gen_helper_neon_sub_f32(tmp, tmp, tmp2);
4776 break;
4777 case 4: /* VPADD */
4778 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4779 break;
4780 case 6: /* VABD */
4781 gen_helper_neon_abd_f32(tmp, tmp, tmp2);
4782 break;
4783 default:
4784 abort();
4785 }
4786 break;
4787 case NEON_3R_FLOAT_MULTIPLY:
4788 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
4789 if (!u) {
4790 tcg_temp_free_i32(tmp2);
4791 tmp2 = neon_load_reg(rd, pass);
4792 if (size == 0) {
4793 gen_helper_neon_add_f32(tmp, tmp, tmp2);
4794 } else {
4795 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
4796 }
4797 }
4798 break;
4799 case NEON_3R_FLOAT_CMP:
4800 if (!u) {
4801 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
4802 } else {
4803 if (size == 0)
4804 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
4805 else
4806 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
4807 }
4808 break;
4809 case NEON_3R_FLOAT_ACMP:
4810 if (size == 0)
4811 gen_helper_neon_acge_f32(tmp, tmp, tmp2);
4812 else
4813 gen_helper_neon_acgt_f32(tmp, tmp, tmp2);
4814 break;
4815 case NEON_3R_FLOAT_MINMAX:
4816 if (size == 0)
4817 gen_helper_neon_max_f32(tmp, tmp, tmp2);
4818 else
4819 gen_helper_neon_min_f32(tmp, tmp, tmp2);
4820 break;
4821 case NEON_3R_VRECPS_VRSQRTS:
4822 if (size == 0)
4823 gen_helper_recps_f32(tmp, tmp, tmp2, cpu_env);
4824 else
4825 gen_helper_rsqrts_f32(tmp, tmp, tmp2, cpu_env);
4826 break;
4827 default:
4828 abort();
4829 }
4830 tcg_temp_free_i32(tmp2);
4831
4832 /* Save the result. For elementwise operations we can put it
4833 straight into the destination register. For pairwise operations
4834 we have to be careful to avoid clobbering the source operands. */
4835 if (pairwise && rd == rm) {
4836 neon_store_scratch(pass, tmp);
4837 } else {
4838 neon_store_reg(rd, pass, tmp);
4839 }
4840
4841 } /* for pass */
4842 if (pairwise && rd == rm) {
4843 for (pass = 0; pass < (q ? 4 : 2); pass++) {
4844 tmp = neon_load_scratch(pass);
4845 neon_store_reg(rd, pass, tmp);
4846 }
4847 }
4848 /* End of 3 register same size operations. */
4849 } else if (insn & (1 << 4)) {
4850 if ((insn & 0x00380080) != 0) {
4851 /* Two registers and shift. */
4852 op = (insn >> 8) & 0xf;
4853 if (insn & (1 << 7)) {
4854 /* 64-bit shift. */
4855 if (op > 7) {
4856 return 1;
4857 }
4858 size = 3;
4859 } else {
4860 size = 2;
4861 while ((insn & (1 << (size + 19))) == 0)
4862 size--;
4863 }
4864 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4865 /* To avoid excessive dumplication of ops we implement shift
4866 by immediate using the variable shift operations. */
4867 if (op < 8) {
4868 /* Shift by immediate:
4869 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4870 if (q && ((rd | rm) & 1)) {
4871 return 1;
4872 }
4873 if (!u && (op == 4 || op == 6)) {
4874 return 1;
4875 }
4876 /* Right shifts are encoded as N - shift, where N is the
4877 element size in bits. */
4878 if (op <= 4)
4879 shift = shift - (1 << (size + 3));
4880 if (size == 3) {
4881 count = q + 1;
4882 } else {
4883 count = q ? 4: 2;
4884 }
4885 switch (size) {
4886 case 0:
4887 imm = (uint8_t) shift;
4888 imm |= imm << 8;
4889 imm |= imm << 16;
4890 break;
4891 case 1:
4892 imm = (uint16_t) shift;
4893 imm |= imm << 16;
4894 break;
4895 case 2:
4896 case 3:
4897 imm = shift;
4898 break;
4899 default:
4900 abort();
4901 }
4902
4903 for (pass = 0; pass < count; pass++) {
4904 if (size == 3) {
4905 neon_load_reg64(cpu_V0, rm + pass);
4906 tcg_gen_movi_i64(cpu_V1, imm);
4907 switch (op) {
4908 case 0: /* VSHR */
4909 case 1: /* VSRA */
4910 if (u)
4911 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4912 else
4913 gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1);
4914 break;
4915 case 2: /* VRSHR */
4916 case 3: /* VRSRA */
4917 if (u)
4918 gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1);
4919 else
4920 gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1);
4921 break;
4922 case 4: /* VSRI */
4923 case 5: /* VSHL, VSLI */
4924 gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1);
4925 break;
4926 case 6: /* VQSHLU */
4927 gen_helper_neon_qshlu_s64(cpu_V0, cpu_V0, cpu_V1);
4928 break;
4929 case 7: /* VQSHL */
4930 if (u) {
4931 gen_helper_neon_qshl_u64(cpu_V0,
4932 cpu_V0, cpu_V1);
4933 } else {
4934 gen_helper_neon_qshl_s64(cpu_V0,
4935 cpu_V0, cpu_V1);
4936 }
4937 break;
4938 }
4939 if (op == 1 || op == 3) {
4940 /* Accumulate. */
4941 neon_load_reg64(cpu_V1, rd + pass);
4942 tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1);
4943 } else if (op == 4 || (op == 5 && u)) {
4944 /* Insert */
4945 neon_load_reg64(cpu_V1, rd + pass);
4946 uint64_t mask;
4947 if (shift < -63 || shift > 63) {
4948 mask = 0;
4949 } else {
4950 if (op == 4) {
4951 mask = 0xffffffffffffffffull >> -shift;
4952 } else {
4953 mask = 0xffffffffffffffffull << shift;
4954 }
4955 }
4956 tcg_gen_andi_i64(cpu_V1, cpu_V1, ~mask);
4957 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
4958 }
4959 neon_store_reg64(cpu_V0, rd + pass);
4960 } else { /* size < 3 */
4961 /* Operands in T0 and T1. */
4962 tmp = neon_load_reg(rm, pass);
4963 tmp2 = tcg_temp_new_i32();
4964 tcg_gen_movi_i32(tmp2, imm);
4965 switch (op) {
4966 case 0: /* VSHR */
4967 case 1: /* VSRA */
4968 GEN_NEON_INTEGER_OP(shl);
4969 break;
4970 case 2: /* VRSHR */
4971 case 3: /* VRSRA */
4972 GEN_NEON_INTEGER_OP(rshl);
4973 break;
4974 case 4: /* VSRI */
4975 case 5: /* VSHL, VSLI */
4976 switch (size) {
4977 case 0: gen_helper_neon_shl_u8(tmp, tmp, tmp2); break;
4978 case 1: gen_helper_neon_shl_u16(tmp, tmp, tmp2); break;
4979 case 2: gen_helper_neon_shl_u32(tmp, tmp, tmp2); break;
4980 default: abort();
4981 }
4982 break;
4983 case 6: /* VQSHLU */
4984 switch (size) {
4985 case 0:
4986 gen_helper_neon_qshlu_s8(tmp, tmp, tmp2);
4987 break;
4988 case 1:
4989 gen_helper_neon_qshlu_s16(tmp, tmp, tmp2);
4990 break;
4991 case 2:
4992 gen_helper_neon_qshlu_s32(tmp, tmp, tmp2);
4993 break;
4994 default:
4995 abort();
4996 }
4997 break;
4998 case 7: /* VQSHL */
4999 GEN_NEON_INTEGER_OP(qshl);
5000 break;
5001 }
5002 tcg_temp_free_i32(tmp2);
5003
5004 if (op == 1 || op == 3) {
5005 /* Accumulate. */
5006 tmp2 = neon_load_reg(rd, pass);
5007 gen_neon_add(size, tmp, tmp2);
5008 tcg_temp_free_i32(tmp2);
5009 } else if (op == 4 || (op == 5 && u)) {
5010 /* Insert */
5011 switch (size) {
5012 case 0:
5013 if (op == 4)
5014 mask = 0xff >> -shift;
5015 else
5016 mask = (uint8_t)(0xff << shift);
5017 mask |= mask << 8;
5018 mask |= mask << 16;
5019 break;
5020 case 1:
5021 if (op == 4)
5022 mask = 0xffff >> -shift;
5023 else
5024 mask = (uint16_t)(0xffff << shift);
5025 mask |= mask << 16;
5026 break;
5027 case 2:
5028 if (shift < -31 || shift > 31) {
5029 mask = 0;
5030 } else {
5031 if (op == 4)
5032 mask = 0xffffffffu >> -shift;
5033 else
5034 mask = 0xffffffffu << shift;
5035 }
5036 break;
5037 default:
5038 abort();
5039 }
5040 tmp2 = neon_load_reg(rd, pass);
5041 tcg_gen_andi_i32(tmp, tmp, mask);
5042 tcg_gen_andi_i32(tmp2, tmp2, ~mask);
5043 tcg_gen_or_i32(tmp, tmp, tmp2);
5044 tcg_temp_free_i32(tmp2);
5045 }
5046 neon_store_reg(rd, pass, tmp);
5047 }
5048 } /* for pass */
5049 } else if (op < 10) {
5050 /* Shift by immediate and narrow:
5051 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
5052 int input_unsigned = (op == 8) ? !u : u;
5053 if (rm & 1) {
5054 return 1;
5055 }
5056 shift = shift - (1 << (size + 3));
5057 size++;
5058 if (size == 3) {
5059 tmp64 = tcg_const_i64(shift);
5060 neon_load_reg64(cpu_V0, rm);
5061 neon_load_reg64(cpu_V1, rm + 1);
5062 for (pass = 0; pass < 2; pass++) {
5063 TCGv_i64 in;
5064 if (pass == 0) {
5065 in = cpu_V0;
5066 } else {
5067 in = cpu_V1;
5068 }
5069 if (q) {
5070 if (input_unsigned) {
5071 gen_helper_neon_rshl_u64(cpu_V0, in, tmp64);
5072 } else {
5073 gen_helper_neon_rshl_s64(cpu_V0, in, tmp64);
5074 }
5075 } else {
5076 if (input_unsigned) {
5077 gen_helper_neon_shl_u64(cpu_V0, in, tmp64);
5078 } else {
5079 gen_helper_neon_shl_s64(cpu_V0, in, tmp64);
5080 }
5081 }
5082 tmp = tcg_temp_new_i32();
5083 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5084 neon_store_reg(rd, pass, tmp);
5085 } /* for pass */
5086 tcg_temp_free_i64(tmp64);
5087 } else {
5088 if (size == 1) {
5089 imm = (uint16_t)shift;
5090 imm |= imm << 16;
5091 } else {
5092 /* size == 2 */
5093 imm = (uint32_t)shift;
5094 }
5095 tmp2 = tcg_const_i32(imm);
5096 tmp4 = neon_load_reg(rm + 1, 0);
5097 tmp5 = neon_load_reg(rm + 1, 1);
5098 for (pass = 0; pass < 2; pass++) {
5099 if (pass == 0) {
5100 tmp = neon_load_reg(rm, 0);
5101 } else {
5102 tmp = tmp4;
5103 }
5104 gen_neon_shift_narrow(size, tmp, tmp2, q,
5105 input_unsigned);
5106 if (pass == 0) {
5107 tmp3 = neon_load_reg(rm, 1);
5108 } else {
5109 tmp3 = tmp5;
5110 }
5111 gen_neon_shift_narrow(size, tmp3, tmp2, q,
5112 input_unsigned);
5113 tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3);
5114 tcg_temp_free_i32(tmp);
5115 tcg_temp_free_i32(tmp3);
5116 tmp = tcg_temp_new_i32();
5117 gen_neon_narrow_op(op == 8, u, size - 1, tmp, cpu_V0);
5118 neon_store_reg(rd, pass, tmp);
5119 } /* for pass */
5120 tcg_temp_free_i32(tmp2);
5121 }
5122 } else if (op == 10) {
5123 /* VSHLL, VMOVL */
5124 if (q || (rd & 1)) {
5125 return 1;
5126 }
5127 tmp = neon_load_reg(rm, 0);
5128 tmp2 = neon_load_reg(rm, 1);
5129 for (pass = 0; pass < 2; pass++) {
5130 if (pass == 1)
5131 tmp = tmp2;
5132
5133 gen_neon_widen(cpu_V0, tmp, size, u);
5134
5135 if (shift != 0) {
5136 /* The shift is less than the width of the source
5137 type, so we can just shift the whole register. */
5138 tcg_gen_shli_i64(cpu_V0, cpu_V0, shift);
5139 /* Widen the result of shift: we need to clear
5140 * the potential overflow bits resulting from
5141 * left bits of the narrow input appearing as
5142 * right bits of left the neighbour narrow
5143 * input. */
5144 if (size < 2 || !u) {
5145 uint64_t imm64;
5146 if (size == 0) {
5147 imm = (0xffu >> (8 - shift));
5148 imm |= imm << 16;
5149 } else if (size == 1) {
5150 imm = 0xffff >> (16 - shift);
5151 } else {
5152 /* size == 2 */
5153 imm = 0xffffffff >> (32 - shift);
5154 }
5155 if (size < 2) {
5156 imm64 = imm | (((uint64_t)imm) << 32);
5157 } else {
5158 imm64 = imm;
5159 }
5160 tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64);
5161 }
5162 }
5163 neon_store_reg64(cpu_V0, rd + pass);
5164 }
5165 } else if (op >= 14) {
5166 /* VCVT fixed-point. */
5167 if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
5168 return 1;
5169 }
5170 /* We have already masked out the must-be-1 top bit of imm6,
5171 * hence this 32-shift where the ARM ARM has 64-imm6.
5172 */
5173 shift = 32 - shift;
5174 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5175 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
5176 if (!(op & 1)) {
5177 if (u)
5178 gen_vfp_ulto(0, shift);
5179 else
5180 gen_vfp_slto(0, shift);
5181 } else {
5182 if (u)
5183 gen_vfp_toul(0, shift);
5184 else
5185 gen_vfp_tosl(0, shift);
5186 }
5187 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
5188 }
5189 } else {
5190 return 1;
5191 }
5192 } else { /* (insn & 0x00380080) == 0 */
5193 int invert;
5194 if (q && (rd & 1)) {
5195 return 1;
5196 }
5197
5198 op = (insn >> 8) & 0xf;
5199 /* One register and immediate. */
5200 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
5201 invert = (insn & (1 << 5)) != 0;
5202 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
5203 * We choose to not special-case this and will behave as if a
5204 * valid constant encoding of 0 had been given.
5205 */
5206 switch (op) {
5207 case 0: case 1:
5208 /* no-op */
5209 break;
5210 case 2: case 3:
5211 imm <<= 8;
5212 break;
5213 case 4: case 5:
5214 imm <<= 16;
5215 break;
5216 case 6: case 7:
5217 imm <<= 24;
5218 break;
5219 case 8: case 9:
5220 imm |= imm << 16;
5221 break;
5222 case 10: case 11:
5223 imm = (imm << 8) | (imm << 24);
5224 break;
5225 case 12:
5226 imm = (imm << 8) | 0xff;
5227 break;
5228 case 13:
5229 imm = (imm << 16) | 0xffff;
5230 break;
5231 case 14:
5232 imm |= (imm << 8) | (imm << 16) | (imm << 24);
5233 if (invert)
5234 imm = ~imm;
5235 break;
5236 case 15:
5237 if (invert) {
5238 return 1;
5239 }
5240 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
5241 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
5242 break;
5243 }
5244 if (invert)
5245 imm = ~imm;
5246
5247 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5248 if (op & 1 && op < 12) {
5249 tmp = neon_load_reg(rd, pass);
5250 if (invert) {
5251 /* The immediate value has already been inverted, so
5252 BIC becomes AND. */
5253 tcg_gen_andi_i32(tmp, tmp, imm);
5254 } else {
5255 tcg_gen_ori_i32(tmp, tmp, imm);
5256 }
5257 } else {
5258 /* VMOV, VMVN. */
5259 tmp = tcg_temp_new_i32();
5260 if (op == 14 && invert) {
5261 int n;
5262 uint32_t val;
5263 val = 0;
5264 for (n = 0; n < 4; n++) {
5265 if (imm & (1 << (n + (pass & 1) * 4)))
5266 val |= 0xff << (n * 8);
5267 }
5268 tcg_gen_movi_i32(tmp, val);
5269 } else {
5270 tcg_gen_movi_i32(tmp, imm);
5271 }
5272 }
5273 neon_store_reg(rd, pass, tmp);
5274 }
5275 }
5276 } else { /* (insn & 0x00800010 == 0x00800000) */
5277 if (size != 3) {
5278 op = (insn >> 8) & 0xf;
5279 if ((insn & (1 << 6)) == 0) {
5280 /* Three registers of different lengths. */
5281 int src1_wide;
5282 int src2_wide;
5283 int prewiden;
5284 /* undefreq: bit 0 : UNDEF if size != 0
5285 * bit 1 : UNDEF if size == 0
5286 * bit 2 : UNDEF if U == 1
5287 * Note that [1:0] set implies 'always UNDEF'
5288 */
5289 int undefreq;
5290 /* prewiden, src1_wide, src2_wide, undefreq */
5291 static const int neon_3reg_wide[16][4] = {
5292 {1, 0, 0, 0}, /* VADDL */
5293 {1, 1, 0, 0}, /* VADDW */
5294 {1, 0, 0, 0}, /* VSUBL */
5295 {1, 1, 0, 0}, /* VSUBW */
5296 {0, 1, 1, 0}, /* VADDHN */
5297 {0, 0, 0, 0}, /* VABAL */
5298 {0, 1, 1, 0}, /* VSUBHN */
5299 {0, 0, 0, 0}, /* VABDL */
5300 {0, 0, 0, 0}, /* VMLAL */
5301 {0, 0, 0, 6}, /* VQDMLAL */
5302 {0, 0, 0, 0}, /* VMLSL */
5303 {0, 0, 0, 6}, /* VQDMLSL */
5304 {0, 0, 0, 0}, /* Integer VMULL */
5305 {0, 0, 0, 2}, /* VQDMULL */
5306 {0, 0, 0, 5}, /* Polynomial VMULL */
5307 {0, 0, 0, 3}, /* Reserved: always UNDEF */
5308 };
5309
5310 prewiden = neon_3reg_wide[op][0];
5311 src1_wide = neon_3reg_wide[op][1];
5312 src2_wide = neon_3reg_wide[op][2];
5313 undefreq = neon_3reg_wide[op][3];
5314
5315 if (((undefreq & 1) && (size != 0)) ||
5316 ((undefreq & 2) && (size == 0)) ||
5317 ((undefreq & 4) && u)) {
5318 return 1;
5319 }
5320 if ((src1_wide && (rn & 1)) ||
5321 (src2_wide && (rm & 1)) ||
5322 (!src2_wide && (rd & 1))) {
5323 return 1;
5324 }
5325
5326 /* Avoid overlapping operands. Wide source operands are
5327 always aligned so will never overlap with wide
5328 destinations in problematic ways. */
5329 if (rd == rm && !src2_wide) {
5330 tmp = neon_load_reg(rm, 1);
5331 neon_store_scratch(2, tmp);
5332 } else if (rd == rn && !src1_wide) {
5333 tmp = neon_load_reg(rn, 1);
5334 neon_store_scratch(2, tmp);
5335 }
5336 TCGV_UNUSED(tmp3);
5337 for (pass = 0; pass < 2; pass++) {
5338 if (src1_wide) {
5339 neon_load_reg64(cpu_V0, rn + pass);
5340 TCGV_UNUSED(tmp);
5341 } else {
5342 if (pass == 1 && rd == rn) {
5343 tmp = neon_load_scratch(2);
5344 } else {
5345 tmp = neon_load_reg(rn, pass);
5346 }
5347 if (prewiden) {
5348 gen_neon_widen(cpu_V0, tmp, size, u);
5349 }
5350 }
5351 if (src2_wide) {
5352 neon_load_reg64(cpu_V1, rm + pass);
5353 TCGV_UNUSED(tmp2);
5354 } else {
5355 if (pass == 1 && rd == rm) {
5356 tmp2 = neon_load_scratch(2);
5357 } else {
5358 tmp2 = neon_load_reg(rm, pass);
5359 }
5360 if (prewiden) {
5361 gen_neon_widen(cpu_V1, tmp2, size, u);
5362 }
5363 }
5364 switch (op) {
5365 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5366 gen_neon_addl(size);
5367 break;
5368 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5369 gen_neon_subl(size);
5370 break;
5371 case 5: case 7: /* VABAL, VABDL */
5372 switch ((size << 1) | u) {
5373 case 0:
5374 gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2);
5375 break;
5376 case 1:
5377 gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2);
5378 break;
5379 case 2:
5380 gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2);
5381 break;
5382 case 3:
5383 gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2);
5384 break;
5385 case 4:
5386 gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2);
5387 break;
5388 case 5:
5389 gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2);
5390 break;
5391 default: abort();
5392 }
5393 tcg_temp_free_i32(tmp2);
5394 tcg_temp_free_i32(tmp);
5395 break;
5396 case 8: case 9: case 10: case 11: case 12: case 13:
5397 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5398 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5399 break;
5400 case 14: /* Polynomial VMULL */
5401 gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2);
5402 tcg_temp_free_i32(tmp2);
5403 tcg_temp_free_i32(tmp);
5404 break;
5405 default: /* 15 is RESERVED: caught earlier */
5406 abort();
5407 }
5408 if (op == 13) {
5409 /* VQDMULL */
5410 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5411 neon_store_reg64(cpu_V0, rd + pass);
5412 } else if (op == 5 || (op >= 8 && op <= 11)) {
5413 /* Accumulate. */
5414 neon_load_reg64(cpu_V1, rd + pass);
5415 switch (op) {
5416 case 10: /* VMLSL */
5417 gen_neon_negl(cpu_V0, size);
5418 /* Fall through */
5419 case 5: case 8: /* VABAL, VMLAL */
5420 gen_neon_addl(size);
5421 break;
5422 case 9: case 11: /* VQDMLAL, VQDMLSL */
5423 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5424 if (op == 11) {
5425 gen_neon_negl(cpu_V0, size);
5426 }
5427 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5428 break;
5429 default:
5430 abort();
5431 }
5432 neon_store_reg64(cpu_V0, rd + pass);
5433 } else if (op == 4 || op == 6) {
5434 /* Narrowing operation. */
5435 tmp = tcg_temp_new_i32();
5436 if (!u) {
5437 switch (size) {
5438 case 0:
5439 gen_helper_neon_narrow_high_u8(tmp, cpu_V0);
5440 break;
5441 case 1:
5442 gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
5443 break;
5444 case 2:
5445 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5446 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5447 break;
5448 default: abort();
5449 }
5450 } else {
5451 switch (size) {
5452 case 0:
5453 gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0);
5454 break;
5455 case 1:
5456 gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0);
5457 break;
5458 case 2:
5459 tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
5460 tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
5461 tcg_gen_trunc_i64_i32(tmp, cpu_V0);
5462 break;
5463 default: abort();
5464 }
5465 }
5466 if (pass == 0) {
5467 tmp3 = tmp;
5468 } else {
5469 neon_store_reg(rd, 0, tmp3);
5470 neon_store_reg(rd, 1, tmp);
5471 }
5472 } else {
5473 /* Write back the result. */
5474 neon_store_reg64(cpu_V0, rd + pass);
5475 }
5476 }
5477 } else {
5478 /* Two registers and a scalar. NB that for ops of this form
5479 * the ARM ARM labels bit 24 as Q, but it is in our variable
5480 * 'u', not 'q'.
5481 */
5482 if (size == 0) {
5483 return 1;
5484 }
5485 switch (op) {
5486 case 1: /* Float VMLA scalar */
5487 case 5: /* Floating point VMLS scalar */
5488 case 9: /* Floating point VMUL scalar */
5489 if (size == 1) {
5490 return 1;
5491 }
5492 /* fall through */
5493 case 0: /* Integer VMLA scalar */
5494 case 4: /* Integer VMLS scalar */
5495 case 8: /* Integer VMUL scalar */
5496 case 12: /* VQDMULH scalar */
5497 case 13: /* VQRDMULH scalar */
5498 if (u && ((rd | rn) & 1)) {
5499 return 1;
5500 }
5501 tmp = neon_get_scalar(size, rm);
5502 neon_store_scratch(0, tmp);
5503 for (pass = 0; pass < (u ? 4 : 2); pass++) {
5504 tmp = neon_load_scratch(0);
5505 tmp2 = neon_load_reg(rn, pass);
5506 if (op == 12) {
5507 if (size == 1) {
5508 gen_helper_neon_qdmulh_s16(tmp, tmp, tmp2);
5509 } else {
5510 gen_helper_neon_qdmulh_s32(tmp, tmp, tmp2);
5511 }
5512 } else if (op == 13) {
5513 if (size == 1) {
5514 gen_helper_neon_qrdmulh_s16(tmp, tmp, tmp2);
5515 } else {
5516 gen_helper_neon_qrdmulh_s32(tmp, tmp, tmp2);
5517 }
5518 } else if (op & 1) {
5519 gen_helper_neon_mul_f32(tmp, tmp, tmp2);
5520 } else {
5521 switch (size) {
5522 case 0: gen_helper_neon_mul_u8(tmp, tmp, tmp2); break;
5523 case 1: gen_helper_neon_mul_u16(tmp, tmp, tmp2); break;
5524 case 2: tcg_gen_mul_i32(tmp, tmp, tmp2); break;
5525 default: abort();
5526 }
5527 }
5528 tcg_temp_free_i32(tmp2);
5529 if (op < 8) {
5530 /* Accumulate. */
5531 tmp2 = neon_load_reg(rd, pass);
5532 switch (op) {
5533 case 0:
5534 gen_neon_add(size, tmp, tmp2);
5535 break;
5536 case 1:
5537 gen_helper_neon_add_f32(tmp, tmp, tmp2);
5538 break;
5539 case 4:
5540 gen_neon_rsb(size, tmp, tmp2);
5541 break;
5542 case 5:
5543 gen_helper_neon_sub_f32(tmp, tmp2, tmp);
5544 break;
5545 default:
5546 abort();
5547 }
5548 tcg_temp_free_i32(tmp2);
5549 }
5550 neon_store_reg(rd, pass, tmp);
5551 }
5552 break;
5553 case 3: /* VQDMLAL scalar */
5554 case 7: /* VQDMLSL scalar */
5555 case 11: /* VQDMULL scalar */
5556 if (u == 1) {
5557 return 1;
5558 }
5559 /* fall through */
5560 case 2: /* VMLAL sclar */
5561 case 6: /* VMLSL scalar */
5562 case 10: /* VMULL scalar */
5563 if (rd & 1) {
5564 return 1;
5565 }
5566 tmp2 = neon_get_scalar(size, rm);
5567 /* We need a copy of tmp2 because gen_neon_mull
5568 * deletes it during pass 0. */
5569 tmp4 = tcg_temp_new_i32();
5570 tcg_gen_mov_i32(tmp4, tmp2);
5571 tmp3 = neon_load_reg(rn, 1);
5572
5573 for (pass = 0; pass < 2; pass++) {
5574 if (pass == 0) {
5575 tmp = neon_load_reg(rn, 0);
5576 } else {
5577 tmp = tmp3;
5578 tmp2 = tmp4;
5579 }
5580 gen_neon_mull(cpu_V0, tmp, tmp2, size, u);
5581 if (op != 11) {
5582 neon_load_reg64(cpu_V1, rd + pass);
5583 }
5584 switch (op) {
5585 case 6:
5586 gen_neon_negl(cpu_V0, size);
5587 /* Fall through */
5588 case 2:
5589 gen_neon_addl(size);
5590 break;
5591 case 3: case 7:
5592 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5593 if (op == 7) {
5594 gen_neon_negl(cpu_V0, size);
5595 }
5596 gen_neon_addl_saturate(cpu_V0, cpu_V1, size);
5597 break;
5598 case 10:
5599 /* no-op */
5600 break;
5601 case 11:
5602 gen_neon_addl_saturate(cpu_V0, cpu_V0, size);
5603 break;
5604 default:
5605 abort();
5606 }
5607 neon_store_reg64(cpu_V0, rd + pass);
5608 }
5609
5610
5611 break;
5612 default: /* 14 and 15 are RESERVED */
5613 return 1;
5614 }
5615 }
5616 } else { /* size == 3 */
5617 if (!u) {
5618 /* Extract. */
5619 imm = (insn >> 8) & 0xf;
5620
5621 if (imm > 7 && !q)
5622 return 1;
5623
5624 if (q && ((rd | rn | rm) & 1)) {
5625 return 1;
5626 }
5627
5628 if (imm == 0) {
5629 neon_load_reg64(cpu_V0, rn);
5630 if (q) {
5631 neon_load_reg64(cpu_V1, rn + 1);
5632 }
5633 } else if (imm == 8) {
5634 neon_load_reg64(cpu_V0, rn + 1);
5635 if (q) {
5636 neon_load_reg64(cpu_V1, rm);
5637 }
5638 } else if (q) {
5639 tmp64 = tcg_temp_new_i64();
5640 if (imm < 8) {
5641 neon_load_reg64(cpu_V0, rn);
5642 neon_load_reg64(tmp64, rn + 1);
5643 } else {
5644 neon_load_reg64(cpu_V0, rn + 1);
5645 neon_load_reg64(tmp64, rm);
5646 }
5647 tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8);
5648 tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8));
5649 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5650 if (imm < 8) {
5651 neon_load_reg64(cpu_V1, rm);
5652 } else {
5653 neon_load_reg64(cpu_V1, rm + 1);
5654 imm -= 8;
5655 }
5656 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5657 tcg_gen_shri_i64(tmp64, tmp64, imm * 8);
5658 tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64);
5659 tcg_temp_free_i64(tmp64);
5660 } else {
5661 /* BUGFIX */
5662 neon_load_reg64(cpu_V0, rn);
5663 tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8);
5664 neon_load_reg64(cpu_V1, rm);
5665 tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8));
5666 tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1);
5667 }
5668 neon_store_reg64(cpu_V0, rd);
5669 if (q) {
5670 neon_store_reg64(cpu_V1, rd + 1);
5671 }
5672 } else if ((insn & (1 << 11)) == 0) {
5673 /* Two register misc. */
5674 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5675 size = (insn >> 18) & 3;
5676 /* UNDEF for unknown op values and bad op-size combinations */
5677 if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
5678 return 1;
5679 }
5680 if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
5681 q && ((rm | rd) & 1)) {
5682 return 1;
5683 }
5684 switch (op) {
5685 case NEON_2RM_VREV64:
5686 for (pass = 0; pass < (q ? 2 : 1); pass++) {
5687 tmp = neon_load_reg(rm, pass * 2);
5688 tmp2 = neon_load_reg(rm, pass * 2 + 1);
5689 switch (size) {
5690 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5691 case 1: gen_swap_half(tmp); break;
5692 case 2: /* no-op */ break;
5693 default: abort();
5694 }
5695 neon_store_reg(rd, pass * 2 + 1, tmp);
5696 if (size == 2) {
5697 neon_store_reg(rd, pass * 2, tmp2);
5698 } else {
5699 switch (size) {
5700 case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break;
5701 case 1: gen_swap_half(tmp2); break;
5702 default: abort();
5703 }
5704 neon_store_reg(rd, pass * 2, tmp2);
5705 }
5706 }
5707 break;
5708 case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
5709 case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
5710 for (pass = 0; pass < q + 1; pass++) {
5711 tmp = neon_load_reg(rm, pass * 2);
5712 gen_neon_widen(cpu_V0, tmp, size, op & 1);
5713 tmp = neon_load_reg(rm, pass * 2 + 1);
5714 gen_neon_widen(cpu_V1, tmp, size, op & 1);
5715 switch (size) {
5716 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5717 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5718 case 2: tcg_gen_add_i64(CPU_V001); break;
5719 default: abort();
5720 }
5721 if (op >= NEON_2RM_VPADAL) {
5722 /* Accumulate. */
5723 neon_load_reg64(cpu_V1, rd + pass);
5724 gen_neon_addl(size);
5725 }
5726 neon_store_reg64(cpu_V0, rd + pass);
5727 }
5728 break;
5729 case NEON_2RM_VTRN:
5730 if (size == 2) {
5731 int n;
5732 for (n = 0; n < (q ? 4 : 2); n += 2) {
5733 tmp = neon_load_reg(rm, n);
5734 tmp2 = neon_load_reg(rd, n + 1);
5735 neon_store_reg(rm, n, tmp2);
5736 neon_store_reg(rd, n + 1, tmp);
5737 }
5738 } else {
5739 goto elementwise;
5740 }
5741 break;
5742 case NEON_2RM_VUZP:
5743 if (gen_neon_unzip(rd, rm, size, q)) {
5744 return 1;
5745 }
5746 break;
5747 case NEON_2RM_VZIP:
5748 if (gen_neon_zip(rd, rm, size, q)) {
5749 return 1;
5750 }
5751 break;
5752 case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
5753 /* also VQMOVUN; op field and mnemonics don't line up */
5754 if (rm & 1) {
5755 return 1;
5756 }
5757 TCGV_UNUSED(tmp2);
5758 for (pass = 0; pass < 2; pass++) {
5759 neon_load_reg64(cpu_V0, rm + pass);
5760 tmp = tcg_temp_new_i32();
5761 gen_neon_narrow_op(op == NEON_2RM_VMOVN, q, size,
5762 tmp, cpu_V0);
5763 if (pass == 0) {
5764 tmp2 = tmp;
5765 } else {
5766 neon_store_reg(rd, 0, tmp2);
5767 neon_store_reg(rd, 1, tmp);
5768 }
5769 }
5770 break;
5771 case NEON_2RM_VSHLL:
5772 if (q || (rd & 1)) {
5773 return 1;
5774 }
5775 tmp = neon_load_reg(rm, 0);
5776 tmp2 = neon_load_reg(rm, 1);
5777 for (pass = 0; pass < 2; pass++) {
5778 if (pass == 1)
5779 tmp = tmp2;
5780 gen_neon_widen(cpu_V0, tmp, size, 1);
5781 tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size);
5782 neon_store_reg64(cpu_V0, rd + pass);
5783 }
5784 break;
5785 case NEON_2RM_VCVT_F16_F32:
5786 if (!arm_feature(env, ARM_FEATURE_VFP_FP16) ||
5787 q || (rm & 1)) {
5788 return 1;
5789 }
5790 tmp = tcg_temp_new_i32();
5791 tmp2 = tcg_temp_new_i32();
5792 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
5793 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5794 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
5795 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5796 tcg_gen_shli_i32(tmp2, tmp2, 16);
5797 tcg_gen_or_i32(tmp2, tmp2, tmp);
5798 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
5799 gen_helper_neon_fcvt_f32_to_f16(tmp, cpu_F0s, cpu_env);
5800 tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
5801 neon_store_reg(rd, 0, tmp2);
5802 tmp2 = tcg_temp_new_i32();
5803 gen_helper_neon_fcvt_f32_to_f16(tmp2, cpu_F0s, cpu_env);
5804 tcg_gen_shli_i32(tmp2, tmp2, 16);
5805 tcg_gen_or_i32(tmp2, tmp2, tmp);
5806 neon_store_reg(rd, 1, tmp2);
5807 tcg_temp_free_i32(tmp);
5808 break;
5809 case NEON_2RM_VCVT_F32_F16:
5810 if (!arm_feature(env, ARM_FEATURE_VFP_FP16) ||
5811 q || (rd & 1)) {
5812 return 1;
5813 }
5814 tmp3 = tcg_temp_new_i32();
5815 tmp = neon_load_reg(rm, 0);
5816 tmp2 = neon_load_reg(rm, 1);
5817 tcg_gen_ext16u_i32(tmp3, tmp);
5818 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5819 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
5820 tcg_gen_shri_i32(tmp3, tmp, 16);
5821 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5822 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
5823 tcg_temp_free_i32(tmp);
5824 tcg_gen_ext16u_i32(tmp3, tmp2);
5825 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5826 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
5827 tcg_gen_shri_i32(tmp3, tmp2, 16);
5828 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s, tmp3, cpu_env);
5829 tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
5830 tcg_temp_free_i32(tmp2);
5831 tcg_temp_free_i32(tmp3);
5832 break;
5833 default:
5834 elementwise:
5835 for (pass = 0; pass < (q ? 4 : 2); pass++) {
5836 if (neon_2rm_is_float_op(op)) {
5837 tcg_gen_ld_f32(cpu_F0s, cpu_env,
5838 neon_reg_offset(rm, pass));
5839 TCGV_UNUSED(tmp);
5840 } else {
5841 tmp = neon_load_reg(rm, pass);
5842 }
5843 switch (op) {
5844 case NEON_2RM_VREV32:
5845 switch (size) {
5846 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
5847 case 1: gen_swap_half(tmp); break;
5848 default: abort();
5849 }
5850 break;
5851 case NEON_2RM_VREV16:
5852 gen_rev16(tmp);
5853 break;
5854 case NEON_2RM_VCLS:
5855 switch (size) {
5856 case 0: gen_helper_neon_cls_s8(tmp, tmp); break;
5857 case 1: gen_helper_neon_cls_s16(tmp, tmp); break;
5858 case 2: gen_helper_neon_cls_s32(tmp, tmp); break;
5859 default: abort();
5860 }
5861 break;
5862 case NEON_2RM_VCLZ:
5863 switch (size) {
5864 case 0: gen_helper_neon_clz_u8(tmp, tmp); break;
5865 case 1: gen_helper_neon_clz_u16(tmp, tmp); break;
5866 case 2: gen_helper_clz(tmp, tmp); break;
5867 default: abort();
5868 }
5869 break;
5870 case NEON_2RM_VCNT:
5871 gen_helper_neon_cnt_u8(tmp, tmp);
5872 break;
5873 case NEON_2RM_VMVN:
5874 tcg_gen_not_i32(tmp, tmp);
5875 break;
5876 case NEON_2RM_VQABS:
5877 switch (size) {
5878 case 0: gen_helper_neon_qabs_s8(tmp, tmp); break;
5879 case 1: gen_helper_neon_qabs_s16(tmp, tmp); break;
5880 case 2: gen_helper_neon_qabs_s32(tmp, tmp); break;
5881 default: abort();
5882 }
5883 break;
5884 case NEON_2RM_VQNEG:
5885 switch (size) {
5886 case 0: gen_helper_neon_qneg_s8(tmp, tmp); break;
5887 case 1: gen_helper_neon_qneg_s16(tmp, tmp); break;
5888 case 2: gen_helper_neon_qneg_s32(tmp, tmp); break;
5889 default: abort();
5890 }
5891 break;
5892 case NEON_2RM_VCGT0: case NEON_2RM_VCLE0:
5893 tmp2 = tcg_const_i32(0);
5894 switch(size) {
5895 case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2); break;
5896 case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2); break;
5897 case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2); break;
5898 default: abort();
5899 }
5900 tcg_temp_free(tmp2);
5901 if (op == NEON_2RM_VCLE0) {
5902 tcg_gen_not_i32(tmp, tmp);
5903 }
5904 break;
5905 case NEON_2RM_VCGE0: case NEON_2RM_VCLT0:
5906 tmp2 = tcg_const_i32(0);
5907 switch(size) {
5908 case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2); break;
5909 case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2); break;
5910 case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2); break;
5911 default: abort();
5912 }
5913 tcg_temp_free(tmp2);
5914 if (op == NEON_2RM_VCLT0) {
5915 tcg_gen_not_i32(tmp, tmp);
5916 }
5917 break;
5918 case NEON_2RM_VCEQ0:
5919 tmp2 = tcg_const_i32(0);
5920 switch(size) {
5921 case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2); break;
5922 case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2); break;
5923 case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2); break;
5924 default: abort();
5925 }
5926 tcg_temp_free(tmp2);
5927 break;
5928 case NEON_2RM_VABS:
5929 switch(size) {
5930 case 0: gen_helper_neon_abs_s8(tmp, tmp); break;
5931 case 1: gen_helper_neon_abs_s16(tmp, tmp); break;
5932 case 2: tcg_gen_abs_i32(tmp, tmp); break;
5933 default: abort();
5934 }
5935 break;
5936 case NEON_2RM_VNEG:
5937 tmp2 = tcg_const_i32(0);
5938 gen_neon_rsb(size, tmp, tmp2);
5939 tcg_temp_free(tmp2);
5940 break;
5941 case NEON_2RM_VCGT0_F:
5942 tmp2 = tcg_const_i32(0);
5943 gen_helper_neon_cgt_f32(tmp, tmp, tmp2);
5944 tcg_temp_free(tmp2);
5945 break;
5946 case NEON_2RM_VCGE0_F:
5947 tmp2 = tcg_const_i32(0);
5948 gen_helper_neon_cge_f32(tmp, tmp, tmp2);
5949 tcg_temp_free(tmp2);
5950 break;
5951 case NEON_2RM_VCEQ0_F:
5952 tmp2 = tcg_const_i32(0);
5953 gen_helper_neon_ceq_f32(tmp, tmp, tmp2);
5954 tcg_temp_free(tmp2);
5955 break;
5956 case NEON_2RM_VCLE0_F:
5957 tmp2 = tcg_const_i32(0);
5958 gen_helper_neon_cge_f32(tmp, tmp2, tmp);
5959 tcg_temp_free(tmp2);
5960 break;
5961 case NEON_2RM_VCLT0_F:
5962 tmp2 = tcg_const_i32(0);
5963 gen_helper_neon_cgt_f32(tmp, tmp2, tmp);
5964 tcg_temp_free(tmp2);
5965 break;
5966 case NEON_2RM_VABS_F:
5967 gen_vfp_abs(0);
5968 break;
5969 case NEON_2RM_VNEG_F:
5970 gen_vfp_neg(0);
5971 break;
5972 case NEON_2RM_VSWP:
5973 tmp2 = neon_load_reg(rd, pass);
5974 neon_store_reg(rm, pass, tmp2);
5975 break;
5976 case NEON_2RM_VTRN:
5977 tmp2 = neon_load_reg(rd, pass);
5978 switch (size) {
5979 case 0: gen_neon_trn_u8(tmp, tmp2); break;
5980 case 1: gen_neon_trn_u16(tmp, tmp2); break;
5981 default: abort();
5982 }
5983 neon_store_reg(rm, pass, tmp2);
5984 break;
5985 case NEON_2RM_VRECPE:
5986 gen_helper_recpe_u32(tmp, tmp, cpu_env);
5987 break;
5988 case NEON_2RM_VRSQRTE:
5989 gen_helper_rsqrte_u32(tmp, tmp, cpu_env);
5990 break;
5991 case NEON_2RM_VRECPE_F:
5992 gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env);
5993 break;
5994 case NEON_2RM_VRSQRTE_F:
5995 gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env);
5996 break;
5997 case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */
5998 gen_vfp_sito(0);
5999 break;
6000 case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */
6001 gen_vfp_uito(0);
6002 break;
6003 case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */
6004 gen_vfp_tosiz(0);
6005 break;
6006 case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */
6007 gen_vfp_touiz(0);
6008 break;
6009 default:
6010 /* Reserved op values were caught by the
6011 * neon_2rm_sizes[] check earlier.
6012 */
6013 abort();
6014 }
6015 if (neon_2rm_is_float_op(op)) {
6016 tcg_gen_st_f32(cpu_F0s, cpu_env,
6017 neon_reg_offset(rd, pass));
6018 } else {
6019 neon_store_reg(rd, pass, tmp);
6020 }
6021 }
6022 break;
6023 }
6024 } else if ((insn & (1 << 10)) == 0) {
6025 /* VTBL, VTBX. */
6026 int n = ((insn >> 8) & 3) + 1;
6027 if ((rn + n) > 32) {
6028 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
6029 * helper function running off the end of the register file.
6030 */
6031 return 1;
6032 }
6033 n <<= 3;
6034 if (insn & (1 << 6)) {
6035 tmp = neon_load_reg(rd, 0);
6036 } else {
6037 tmp = tcg_temp_new_i32();
6038 tcg_gen_movi_i32(tmp, 0);
6039 }
6040 tmp2 = neon_load_reg(rm, 0);
6041 tmp4 = tcg_const_i32(rn);
6042 tmp5 = tcg_const_i32(n);
6043 gen_helper_neon_tbl(tmp2, tmp2, tmp, tmp4, tmp5);
6044 tcg_temp_free_i32(tmp);
6045 if (insn & (1 << 6)) {
6046 tmp = neon_load_reg(rd, 1);
6047 } else {
6048 tmp = tcg_temp_new_i32();
6049 tcg_gen_movi_i32(tmp, 0);
6050 }
6051 tmp3 = neon_load_reg(rm, 1);
6052 gen_helper_neon_tbl(tmp3, tmp3, tmp, tmp4, tmp5);
6053 tcg_temp_free_i32(tmp5);
6054 tcg_temp_free_i32(tmp4);
6055 neon_store_reg(rd, 0, tmp2);
6056 neon_store_reg(rd, 1, tmp3);
6057 tcg_temp_free_i32(tmp);
6058 } else if ((insn & 0x380) == 0) {
6059 /* VDUP */
6060 if (insn & (1 << 19)) {
6061 tmp = neon_load_reg(rm, 1);
6062 } else {
6063 tmp = neon_load_reg(rm, 0);
6064 }
6065 if (insn & (1 << 16)) {
6066 gen_neon_dup_u8(tmp, ((insn >> 17) & 3) * 8);
6067 } else if (insn & (1 << 17)) {
6068 if ((insn >> 18) & 1)
6069 gen_neon_dup_high16(tmp);
6070 else
6071 gen_neon_dup_low16(tmp);
6072 }
6073 for (pass = 0; pass < (q ? 4 : 2); pass++) {
6074 tmp2 = tcg_temp_new_i32();
6075 tcg_gen_mov_i32(tmp2, tmp);
6076 neon_store_reg(rd, pass, tmp2);
6077 }
6078 tcg_temp_free_i32(tmp);
6079 } else {
6080 return 1;
6081 }
6082 }
6083 }
6084 return 0;
6085 }
6086
6087 static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
6088 {
6089 int crn = (insn >> 16) & 0xf;
6090 int crm = insn & 0xf;
6091 int op1 = (insn >> 21) & 7;
6092 int op2 = (insn >> 5) & 7;
6093 int rt = (insn >> 12) & 0xf;
6094 TCGv tmp;
6095
6096 /* Minimal set of debug registers, since we don't support debug */
6097 if (op1 == 0 && crn == 0 && op2 == 0) {
6098 switch (crm) {
6099 case 0:
6100 /* DBGDIDR: just RAZ. In particular this means the
6101 * "debug architecture version" bits will read as
6102 * a reserved value, which should cause Linux to
6103 * not try to use the debug hardware.
6104 */
6105 tmp = tcg_const_i32(0);
6106 store_reg(s, rt, tmp);
6107 return 0;
6108 case 1:
6109 case 2:
6110 /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
6111 * don't implement memory mapped debug components
6112 */
6113 if (ENABLE_ARCH_7) {
6114 tmp = tcg_const_i32(0);
6115 store_reg(s, rt, tmp);
6116 return 0;
6117 }
6118 break;
6119 default:
6120 break;
6121 }
6122 }
6123
6124 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
6125 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
6126 /* TEECR */
6127 if (IS_USER(s))
6128 return 1;
6129 tmp = load_cpu_field(teecr);
6130 store_reg(s, rt, tmp);
6131 return 0;
6132 }
6133 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
6134 /* TEEHBR */
6135 if (IS_USER(s) && (env->teecr & 1))
6136 return 1;
6137 tmp = load_cpu_field(teehbr);
6138 store_reg(s, rt, tmp);
6139 return 0;
6140 }
6141 }
6142 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
6143 op1, crn, crm, op2);
6144 return 1;
6145 }
6146
6147 static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
6148 {
6149 int crn = (insn >> 16) & 0xf;
6150 int crm = insn & 0xf;
6151 int op1 = (insn >> 21) & 7;
6152 int op2 = (insn >> 5) & 7;
6153 int rt = (insn >> 12) & 0xf;
6154 TCGv tmp;
6155
6156 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
6157 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
6158 /* TEECR */
6159 if (IS_USER(s))
6160 return 1;
6161 tmp = load_reg(s, rt);
6162 gen_helper_set_teecr(cpu_env, tmp);
6163 tcg_temp_free_i32(tmp);
6164 return 0;
6165 }
6166 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
6167 /* TEEHBR */
6168 if (IS_USER(s) && (env->teecr & 1))
6169 return 1;
6170 tmp = load_reg(s, rt);
6171 store_cpu_field(tmp, teehbr);
6172 return 0;
6173 }
6174 }
6175 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
6176 op1, crn, crm, op2);
6177 return 1;
6178 }
6179
6180 static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
6181 {
6182 int cpnum;
6183
6184 cpnum = (insn >> 8) & 0xf;
6185 if (arm_feature(env, ARM_FEATURE_XSCALE)
6186 && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum)))
6187 return 1;
6188
6189 switch (cpnum) {
6190 case 0:
6191 case 1:
6192 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6193 return disas_iwmmxt_insn(env, s, insn);
6194 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
6195 return disas_dsp_insn(env, s, insn);
6196 }
6197 return 1;
6198 case 10:
6199 case 11:
6200 return disas_vfp_insn (env, s, insn);
6201 case 14:
6202 /* Coprocessors 7-15 are architecturally reserved by ARM.
6203 Unfortunately Intel decided to ignore this. */
6204 if (arm_feature(env, ARM_FEATURE_XSCALE))
6205 goto board;
6206 if (insn & (1 << 20))
6207 return disas_cp14_read(env, s, insn);
6208 else
6209 return disas_cp14_write(env, s, insn);
6210 case 15:
6211 return disas_cp15_insn (env, s, insn);
6212 default:
6213 board:
6214 /* Unknown coprocessor. See if the board has hooked it. */
6215 return disas_cp_insn (env, s, insn);
6216 }
6217 }
6218
6219
6220 /* Store a 64-bit value to a register pair. Clobbers val. */
6221 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
6222 {
6223 TCGv tmp;
6224 tmp = tcg_temp_new_i32();
6225 tcg_gen_trunc_i64_i32(tmp, val);
6226 store_reg(s, rlow, tmp);
6227 tmp = tcg_temp_new_i32();
6228 tcg_gen_shri_i64(val, val, 32);
6229 tcg_gen_trunc_i64_i32(tmp, val);
6230 store_reg(s, rhigh, tmp);
6231 }
6232
6233 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
6234 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
6235 {
6236 TCGv_i64 tmp;
6237 TCGv tmp2;
6238
6239 /* Load value and extend to 64 bits. */
6240 tmp = tcg_temp_new_i64();
6241 tmp2 = load_reg(s, rlow);
6242 tcg_gen_extu_i32_i64(tmp, tmp2);
6243 tcg_temp_free_i32(tmp2);
6244 tcg_gen_add_i64(val, val, tmp);
6245 tcg_temp_free_i64(tmp);
6246 }
6247
6248 /* load and add a 64-bit value from a register pair. */
6249 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
6250 {
6251 TCGv_i64 tmp;
6252 TCGv tmpl;
6253 TCGv tmph;
6254
6255 /* Load 64-bit value rd:rn. */
6256 tmpl = load_reg(s, rlow);
6257 tmph = load_reg(s, rhigh);
6258 tmp = tcg_temp_new_i64();
6259 tcg_gen_concat_i32_i64(tmp, tmpl, tmph);
6260 tcg_temp_free_i32(tmpl);
6261 tcg_temp_free_i32(tmph);
6262 tcg_gen_add_i64(val, val, tmp);
6263 tcg_temp_free_i64(tmp);
6264 }
6265
6266 /* Set N and Z flags from a 64-bit value. */
6267 static void gen_logicq_cc(TCGv_i64 val)
6268 {
6269 TCGv tmp = tcg_temp_new_i32();
6270 gen_helper_logicq_cc(tmp, val);
6271 gen_logic_CC(tmp);
6272 tcg_temp_free_i32(tmp);
6273 }
6274
6275 /* Load/Store exclusive instructions are implemented by remembering
6276 the value/address loaded, and seeing if these are the same
6277 when the store is performed. This should be is sufficient to implement
6278 the architecturally mandated semantics, and avoids having to monitor
6279 regular stores.
6280
6281 In system emulation mode only one CPU will be running at once, so
6282 this sequence is effectively atomic. In user emulation mode we
6283 throw an exception and handle the atomic operation elsewhere. */
6284 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
6285 TCGv addr, int size)
6286 {
6287 TCGv tmp;
6288
6289 switch (size) {
6290 case 0:
6291 tmp = gen_ld8u(addr, IS_USER(s));
6292 break;
6293 case 1:
6294 tmp = gen_ld16u(addr, IS_USER(s));
6295 break;
6296 case 2:
6297 case 3:
6298 tmp = gen_ld32(addr, IS_USER(s));
6299 break;
6300 default:
6301 abort();
6302 }
6303 tcg_gen_mov_i32(cpu_exclusive_val, tmp);
6304 store_reg(s, rt, tmp);
6305 if (size == 3) {
6306 TCGv tmp2 = tcg_temp_new_i32();
6307 tcg_gen_addi_i32(tmp2, addr, 4);
6308 tmp = gen_ld32(tmp2, IS_USER(s));
6309 tcg_temp_free_i32(tmp2);
6310 tcg_gen_mov_i32(cpu_exclusive_high, tmp);
6311 store_reg(s, rt2, tmp);
6312 }
6313 tcg_gen_mov_i32(cpu_exclusive_addr, addr);
6314 }
6315
6316 static void gen_clrex(DisasContext *s)
6317 {
6318 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6319 }
6320
6321 #ifdef CONFIG_USER_ONLY
6322 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6323 TCGv addr, int size)
6324 {
6325 tcg_gen_mov_i32(cpu_exclusive_test, addr);
6326 tcg_gen_movi_i32(cpu_exclusive_info,
6327 size | (rd << 4) | (rt << 8) | (rt2 << 12));
6328 gen_exception_insn(s, 4, EXCP_STREX);
6329 }
6330 #else
6331 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
6332 TCGv addr, int size)
6333 {
6334 TCGv tmp;
6335 int done_label;
6336 int fail_label;
6337
6338 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6339 [addr] = {Rt};
6340 {Rd} = 0;
6341 } else {
6342 {Rd} = 1;
6343 } */
6344 fail_label = gen_new_label();
6345 done_label = gen_new_label();
6346 tcg_gen_brcond_i32(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
6347 switch (size) {
6348 case 0:
6349 tmp = gen_ld8u(addr, IS_USER(s));
6350 break;
6351 case 1:
6352 tmp = gen_ld16u(addr, IS_USER(s));
6353 break;
6354 case 2:
6355 case 3:
6356 tmp = gen_ld32(addr, IS_USER(s));
6357 break;
6358 default:
6359 abort();
6360 }
6361 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
6362 tcg_temp_free_i32(tmp);
6363 if (size == 3) {
6364 TCGv tmp2 = tcg_temp_new_i32();
6365 tcg_gen_addi_i32(tmp2, addr, 4);
6366 tmp = gen_ld32(tmp2, IS_USER(s));
6367 tcg_temp_free_i32(tmp2);
6368 tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
6369 tcg_temp_free_i32(tmp);
6370 }
6371 tmp = load_reg(s, rt);
6372 switch (size) {
6373 case 0:
6374 gen_st8(tmp, addr, IS_USER(s));
6375 break;
6376 case 1:
6377 gen_st16(tmp, addr, IS_USER(s));
6378 break;
6379 case 2:
6380 case 3:
6381 gen_st32(tmp, addr, IS_USER(s));
6382 break;
6383 default:
6384 abort();
6385 }
6386 if (size == 3) {
6387 tcg_gen_addi_i32(addr, addr, 4);
6388 tmp = load_reg(s, rt2);
6389 gen_st32(tmp, addr, IS_USER(s));
6390 }
6391 tcg_gen_movi_i32(cpu_R[rd], 0);
6392 tcg_gen_br(done_label);
6393 gen_set_label(fail_label);
6394 tcg_gen_movi_i32(cpu_R[rd], 1);
6395 gen_set_label(done_label);
6396 tcg_gen_movi_i32(cpu_exclusive_addr, -1);
6397 }
6398 #endif
6399
6400 static void disas_arm_insn(CPUState * env, DisasContext *s)
6401 {
6402 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
6403 TCGv tmp;
6404 TCGv tmp2;
6405 TCGv tmp3;
6406 TCGv addr;
6407 TCGv_i64 tmp64;
6408
6409 insn = ldl_code(s->pc);
6410 s->pc += 4;
6411
6412 /* M variants do not implement ARM mode. */
6413 if (IS_M(env))
6414 goto illegal_op;
6415 cond = insn >> 28;
6416 if (cond == 0xf){
6417 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
6418 * choose to UNDEF. In ARMv5 and above the space is used
6419 * for miscellaneous unconditional instructions.
6420 */
6421 ARCH(5);
6422
6423 /* Unconditional instructions. */
6424 if (((insn >> 25) & 7) == 1) {
6425 /* NEON Data processing. */
6426 if (!arm_feature(env, ARM_FEATURE_NEON))
6427 goto illegal_op;
6428
6429 if (disas_neon_data_insn(env, s, insn))
6430 goto illegal_op;
6431 return;
6432 }
6433 if ((insn & 0x0f100000) == 0x04000000) {
6434 /* NEON load/store. */
6435 if (!arm_feature(env, ARM_FEATURE_NEON))
6436 goto illegal_op;
6437
6438 if (disas_neon_ls_insn(env, s, insn))
6439 goto illegal_op;
6440 return;
6441 }
6442 if (((insn & 0x0f30f000) == 0x0510f000) ||
6443 ((insn & 0x0f30f010) == 0x0710f000)) {
6444 if ((insn & (1 << 22)) == 0) {
6445 /* PLDW; v7MP */
6446 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6447 goto illegal_op;
6448 }
6449 }
6450 /* Otherwise PLD; v5TE+ */
6451 ARCH(5TE);
6452 return;
6453 }
6454 if (((insn & 0x0f70f000) == 0x0450f000) ||
6455 ((insn & 0x0f70f010) == 0x0650f000)) {
6456 ARCH(7);
6457 return; /* PLI; V7 */
6458 }
6459 if (((insn & 0x0f700000) == 0x04100000) ||
6460 ((insn & 0x0f700010) == 0x06100000)) {
6461 if (!arm_feature(env, ARM_FEATURE_V7MP)) {
6462 goto illegal_op;
6463 }
6464 return; /* v7MP: Unallocated memory hint: must NOP */
6465 }
6466
6467 if ((insn & 0x0ffffdff) == 0x01010000) {
6468 ARCH(6);
6469 /* setend */
6470 if (insn & (1 << 9)) {
6471 /* BE8 mode not implemented. */
6472 goto illegal_op;
6473 }
6474 return;
6475 } else if ((insn & 0x0fffff00) == 0x057ff000) {
6476 switch ((insn >> 4) & 0xf) {
6477 case 1: /* clrex */
6478 ARCH(6K);
6479 gen_clrex(s);
6480 return;
6481 case 4: /* dsb */
6482 case 5: /* dmb */
6483 case 6: /* isb */
6484 ARCH(7);
6485 /* We don't emulate caches so these are a no-op. */
6486 return;
6487 default:
6488 goto illegal_op;
6489 }
6490 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
6491 /* srs */
6492 int32_t offset;
6493 if (IS_USER(s))
6494 goto illegal_op;
6495 ARCH(6);
6496 op1 = (insn & 0x1f);
6497 addr = tcg_temp_new_i32();
6498 tmp = tcg_const_i32(op1);
6499 gen_helper_get_r13_banked(addr, cpu_env, tmp);
6500 tcg_temp_free_i32(tmp);
6501 i = (insn >> 23) & 3;
6502 switch (i) {
6503 case 0: offset = -4; break; /* DA */
6504 case 1: offset = 0; break; /* IA */
6505 case 2: offset = -8; break; /* DB */
6506 case 3: offset = 4; break; /* IB */
6507 default: abort();
6508 }
6509 if (offset)
6510 tcg_gen_addi_i32(addr, addr, offset);
6511 tmp = load_reg(s, 14);
6512 gen_st32(tmp, addr, 0);
6513 tmp = load_cpu_field(spsr);
6514 tcg_gen_addi_i32(addr, addr, 4);
6515 gen_st32(tmp, addr, 0);
6516 if (insn & (1 << 21)) {
6517 /* Base writeback. */
6518 switch (i) {
6519 case 0: offset = -8; break;
6520 case 1: offset = 4; break;
6521 case 2: offset = -4; break;
6522 case 3: offset = 0; break;
6523 default: abort();
6524 }
6525 if (offset)
6526 tcg_gen_addi_i32(addr, addr, offset);
6527 tmp = tcg_const_i32(op1);
6528 gen_helper_set_r13_banked(cpu_env, tmp, addr);
6529 tcg_temp_free_i32(tmp);
6530 tcg_temp_free_i32(addr);
6531 } else {
6532 tcg_temp_free_i32(addr);
6533 }
6534 return;
6535 } else if ((insn & 0x0e50ffe0) == 0x08100a00) {
6536 /* rfe */
6537 int32_t offset;
6538 if (IS_USER(s))
6539 goto illegal_op;
6540 ARCH(6);
6541 rn = (insn >> 16) & 0xf;
6542 addr = load_reg(s, rn);
6543 i = (insn >> 23) & 3;
6544 switch (i) {
6545 case 0: offset = -4; break; /* DA */
6546 case 1: offset = 0; break; /* IA */
6547 case 2: offset = -8; break; /* DB */
6548 case 3: offset = 4; break; /* IB */
6549 default: abort();
6550 }
6551 if (offset)
6552 tcg_gen_addi_i32(addr, addr, offset);
6553 /* Load PC into tmp and CPSR into tmp2. */
6554 tmp = gen_ld32(addr, 0);
6555 tcg_gen_addi_i32(addr, addr, 4);
6556 tmp2 = gen_ld32(addr, 0);
6557 if (insn & (1 << 21)) {
6558 /* Base writeback. */
6559 switch (i) {
6560 case 0: offset = -8; break;
6561 case 1: offset = 4; break;
6562 case 2: offset = -4; break;
6563 case 3: offset = 0; break;
6564 default: abort();
6565 }
6566 if (offset)
6567 tcg_gen_addi_i32(addr, addr, offset);
6568 store_reg(s, rn, addr);
6569 } else {
6570 tcg_temp_free_i32(addr);
6571 }
6572 gen_rfe(s, tmp, tmp2);
6573 return;
6574 } else if ((insn & 0x0e000000) == 0x0a000000) {
6575 /* branch link and change to thumb (blx <offset>) */
6576 int32_t offset;
6577
6578 val = (uint32_t)s->pc;
6579 tmp = tcg_temp_new_i32();
6580 tcg_gen_movi_i32(tmp, val);
6581 store_reg(s, 14, tmp);
6582 /* Sign-extend the 24-bit offset */
6583 offset = (((int32_t)insn) << 8) >> 8;
6584 /* offset * 4 + bit24 * 2 + (thumb bit) */
6585 val += (offset << 2) | ((insn >> 23) & 2) | 1;
6586 /* pipeline offset */
6587 val += 4;
6588 /* protected by ARCH(5); above, near the start of uncond block */
6589 gen_bx_im(s, val);
6590 return;
6591 } else if ((insn & 0x0e000f00) == 0x0c000100) {
6592 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
6593 /* iWMMXt register transfer. */
6594 if (env->cp15.c15_cpar & (1 << 1))
6595 if (!disas_iwmmxt_insn(env, s, insn))
6596 return;
6597 }
6598 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6599 /* Coprocessor double register transfer. */
6600 ARCH(5TE);
6601 } else if ((insn & 0x0f000010) == 0x0e000010) {
6602 /* Additional coprocessor register transfer. */
6603 } else if ((insn & 0x0ff10020) == 0x01000000) {
6604 uint32_t mask;
6605 uint32_t val;
6606 /* cps (privileged) */
6607 if (IS_USER(s))
6608 return;
6609 mask = val = 0;
6610 if (insn & (1 << 19)) {
6611 if (insn & (1 << 8))
6612 mask |= CPSR_A;
6613 if (insn & (1 << 7))
6614 mask |= CPSR_I;
6615 if (insn & (1 << 6))
6616 mask |= CPSR_F;
6617 if (insn & (1 << 18))
6618 val |= mask;
6619 }
6620 if (insn & (1 << 17)) {
6621 mask |= CPSR_M;
6622 val |= (insn & 0x1f);
6623 }
6624 if (mask) {
6625 gen_set_psr_im(s, mask, 0, val);
6626 }
6627 return;
6628 }
6629 goto illegal_op;
6630 }
6631 if (cond != 0xe) {
6632 /* if not always execute, we generate a conditional jump to
6633 next instruction */
6634 s->condlabel = gen_new_label();
6635 gen_test_cc(cond ^ 1, s->condlabel);
6636 s->condjmp = 1;
6637 }
6638 if ((insn & 0x0f900000) == 0x03000000) {
6639 if ((insn & (1 << 21)) == 0) {
6640 ARCH(6T2);
6641 rd = (insn >> 12) & 0xf;
6642 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6643 if ((insn & (1 << 22)) == 0) {
6644 /* MOVW */
6645 tmp = tcg_temp_new_i32();
6646 tcg_gen_movi_i32(tmp, val);
6647 } else {
6648 /* MOVT */
6649 tmp = load_reg(s, rd);
6650 tcg_gen_ext16u_i32(tmp, tmp);
6651 tcg_gen_ori_i32(tmp, tmp, val << 16);
6652 }
6653 store_reg(s, rd, tmp);
6654 } else {
6655 if (((insn >> 12) & 0xf) != 0xf)
6656 goto illegal_op;
6657 if (((insn >> 16) & 0xf) == 0) {
6658 gen_nop_hint(s, insn & 0xff);
6659 } else {
6660 /* CPSR = immediate */
6661 val = insn & 0xff;
6662 shift = ((insn >> 8) & 0xf) * 2;
6663 if (shift)
6664 val = (val >> shift) | (val << (32 - shift));
6665 i = ((insn & (1 << 22)) != 0);
6666 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
6667 goto illegal_op;
6668 }
6669 }
6670 } else if ((insn & 0x0f900000) == 0x01000000
6671 && (insn & 0x00000090) != 0x00000090) {
6672 /* miscellaneous instructions */
6673 op1 = (insn >> 21) & 3;
6674 sh = (insn >> 4) & 0xf;
6675 rm = insn & 0xf;
6676 switch (sh) {
6677 case 0x0: /* move program status register */
6678 if (op1 & 1) {
6679 /* PSR = reg */
6680 tmp = load_reg(s, rm);
6681 i = ((op1 & 2) != 0);
6682 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
6683 goto illegal_op;
6684 } else {
6685 /* reg = PSR */
6686 rd = (insn >> 12) & 0xf;
6687 if (op1 & 2) {
6688 if (IS_USER(s))
6689 goto illegal_op;
6690 tmp = load_cpu_field(spsr);
6691 } else {
6692 tmp = tcg_temp_new_i32();
6693 gen_helper_cpsr_read(tmp);
6694 }
6695 store_reg(s, rd, tmp);
6696 }
6697 break;
6698 case 0x1:
6699 if (op1 == 1) {
6700 /* branch/exchange thumb (bx). */
6701 ARCH(4T);
6702 tmp = load_reg(s, rm);
6703 gen_bx(s, tmp);
6704 } else if (op1 == 3) {
6705 /* clz */
6706 ARCH(5);
6707 rd = (insn >> 12) & 0xf;
6708 tmp = load_reg(s, rm);
6709 gen_helper_clz(tmp, tmp);
6710 store_reg(s, rd, tmp);
6711 } else {
6712 goto illegal_op;
6713 }
6714 break;
6715 case 0x2:
6716 if (op1 == 1) {
6717 ARCH(5J); /* bxj */
6718 /* Trivial implementation equivalent to bx. */
6719 tmp = load_reg(s, rm);
6720 gen_bx(s, tmp);
6721 } else {
6722 goto illegal_op;
6723 }
6724 break;
6725 case 0x3:
6726 if (op1 != 1)
6727 goto illegal_op;
6728
6729 ARCH(5);
6730 /* branch link/exchange thumb (blx) */
6731 tmp = load_reg(s, rm);
6732 tmp2 = tcg_temp_new_i32();
6733 tcg_gen_movi_i32(tmp2, s->pc);
6734 store_reg(s, 14, tmp2);
6735 gen_bx(s, tmp);
6736 break;
6737 case 0x5: /* saturating add/subtract */
6738 ARCH(5TE);
6739 rd = (insn >> 12) & 0xf;
6740 rn = (insn >> 16) & 0xf;
6741 tmp = load_reg(s, rm);
6742 tmp2 = load_reg(s, rn);
6743 if (op1 & 2)
6744 gen_helper_double_saturate(tmp2, tmp2);
6745 if (op1 & 1)
6746 gen_helper_sub_saturate(tmp, tmp, tmp2);
6747 else
6748 gen_helper_add_saturate(tmp, tmp, tmp2);
6749 tcg_temp_free_i32(tmp2);
6750 store_reg(s, rd, tmp);
6751 break;
6752 case 7:
6753 /* SMC instruction (op1 == 3)
6754 and undefined instructions (op1 == 0 || op1 == 2)
6755 will trap */
6756 if (op1 != 1) {
6757 goto illegal_op;
6758 }
6759 /* bkpt */
6760 ARCH(5);
6761 gen_exception_insn(s, 4, EXCP_BKPT);
6762 break;
6763 case 0x8: /* signed multiply */
6764 case 0xa:
6765 case 0xc:
6766 case 0xe:
6767 ARCH(5TE);
6768 rs = (insn >> 8) & 0xf;
6769 rn = (insn >> 12) & 0xf;
6770 rd = (insn >> 16) & 0xf;
6771 if (op1 == 1) {
6772 /* (32 * 16) >> 16 */
6773 tmp = load_reg(s, rm);
6774 tmp2 = load_reg(s, rs);
6775 if (sh & 4)
6776 tcg_gen_sari_i32(tmp2, tmp2, 16);
6777 else
6778 gen_sxth(tmp2);
6779 tmp64 = gen_muls_i64_i32(tmp, tmp2);
6780 tcg_gen_shri_i64(tmp64, tmp64, 16);
6781 tmp = tcg_temp_new_i32();
6782 tcg_gen_trunc_i64_i32(tmp, tmp64);
6783 tcg_temp_free_i64(tmp64);
6784 if ((sh & 2) == 0) {
6785 tmp2 = load_reg(s, rn);
6786 gen_helper_add_setq(tmp, tmp, tmp2);
6787 tcg_temp_free_i32(tmp2);
6788 }
6789 store_reg(s, rd, tmp);
6790 } else {
6791 /* 16 * 16 */
6792 tmp = load_reg(s, rm);
6793 tmp2 = load_reg(s, rs);
6794 gen_mulxy(tmp, tmp2, sh & 2, sh & 4);
6795 tcg_temp_free_i32(tmp2);
6796 if (op1 == 2) {
6797 tmp64 = tcg_temp_new_i64();
6798 tcg_gen_ext_i32_i64(tmp64, tmp);
6799 tcg_temp_free_i32(tmp);
6800 gen_addq(s, tmp64, rn, rd);
6801 gen_storeq_reg(s, rn, rd, tmp64);
6802 tcg_temp_free_i64(tmp64);
6803 } else {
6804 if (op1 == 0) {
6805 tmp2 = load_reg(s, rn);
6806 gen_helper_add_setq(tmp, tmp, tmp2);
6807 tcg_temp_free_i32(tmp2);
6808 }
6809 store_reg(s, rd, tmp);
6810 }
6811 }
6812 break;
6813 default:
6814 goto illegal_op;
6815 }
6816 } else if (((insn & 0x0e000000) == 0 &&
6817 (insn & 0x00000090) != 0x90) ||
6818 ((insn & 0x0e000000) == (1 << 25))) {
6819 int set_cc, logic_cc, shiftop;
6820
6821 op1 = (insn >> 21) & 0xf;
6822 set_cc = (insn >> 20) & 1;
6823 logic_cc = table_logic_cc[op1] & set_cc;
6824
6825 /* data processing instruction */
6826 if (insn & (1 << 25)) {
6827 /* immediate operand */
6828 val = insn & 0xff;
6829 shift = ((insn >> 8) & 0xf) * 2;
6830 if (shift) {
6831 val = (val >> shift) | (val << (32 - shift));
6832 }
6833 tmp2 = tcg_temp_new_i32();
6834 tcg_gen_movi_i32(tmp2, val);
6835 if (logic_cc && shift) {
6836 gen_set_CF_bit31(tmp2);
6837 }
6838 } else {
6839 /* register */
6840 rm = (insn) & 0xf;
6841 tmp2 = load_reg(s, rm);
6842 shiftop = (insn >> 5) & 3;
6843 if (!(insn & (1 << 4))) {
6844 shift = (insn >> 7) & 0x1f;
6845 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
6846 } else {
6847 rs = (insn >> 8) & 0xf;
6848 tmp = load_reg(s, rs);
6849 gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc);
6850 }
6851 }
6852 if (op1 != 0x0f && op1 != 0x0d) {
6853 rn = (insn >> 16) & 0xf;
6854 tmp = load_reg(s, rn);
6855 } else {
6856 TCGV_UNUSED(tmp);
6857 }
6858 rd = (insn >> 12) & 0xf;
6859 switch(op1) {
6860 case 0x00:
6861 tcg_gen_and_i32(tmp, tmp, tmp2);
6862 if (logic_cc) {
6863 gen_logic_CC(tmp);
6864 }
6865 store_reg_bx(env, s, rd, tmp);
6866 break;
6867 case 0x01:
6868 tcg_gen_xor_i32(tmp, tmp, tmp2);
6869 if (logic_cc) {
6870 gen_logic_CC(tmp);
6871 }
6872 store_reg_bx(env, s, rd, tmp);
6873 break;
6874 case 0x02:
6875 if (set_cc && rd == 15) {
6876 /* SUBS r15, ... is used for exception return. */
6877 if (IS_USER(s)) {
6878 goto illegal_op;
6879 }
6880 gen_helper_sub_cc(tmp, tmp, tmp2);
6881 gen_exception_return(s, tmp);
6882 } else {
6883 if (set_cc) {
6884 gen_helper_sub_cc(tmp, tmp, tmp2);
6885 } else {
6886 tcg_gen_sub_i32(tmp, tmp, tmp2);
6887 }
6888 store_reg_bx(env, s, rd, tmp);
6889 }
6890 break;
6891 case 0x03:
6892 if (set_cc) {
6893 gen_helper_sub_cc(tmp, tmp2, tmp);
6894 } else {
6895 tcg_gen_sub_i32(tmp, tmp2, tmp);
6896 }
6897 store_reg_bx(env, s, rd, tmp);
6898 break;
6899 case 0x04:
6900 if (set_cc) {
6901 gen_helper_add_cc(tmp, tmp, tmp2);
6902 } else {
6903 tcg_gen_add_i32(tmp, tmp, tmp2);
6904 }
6905 store_reg_bx(env, s, rd, tmp);
6906 break;
6907 case 0x05:
6908 if (set_cc) {
6909 gen_helper_adc_cc(tmp, tmp, tmp2);
6910 } else {
6911 gen_add_carry(tmp, tmp, tmp2);
6912 }
6913 store_reg_bx(env, s, rd, tmp);
6914 break;
6915 case 0x06:
6916 if (set_cc) {
6917 gen_helper_sbc_cc(tmp, tmp, tmp2);
6918 } else {
6919 gen_sub_carry(tmp, tmp, tmp2);
6920 }
6921 store_reg_bx(env, s, rd, tmp);
6922 break;
6923 case 0x07:
6924 if (set_cc) {
6925 gen_helper_sbc_cc(tmp, tmp2, tmp);
6926 } else {
6927 gen_sub_carry(tmp, tmp2, tmp);
6928 }
6929 store_reg_bx(env, s, rd, tmp);
6930 break;
6931 case 0x08:
6932 if (set_cc) {
6933 tcg_gen_and_i32(tmp, tmp, tmp2);
6934 gen_logic_CC(tmp);
6935 }
6936 tcg_temp_free_i32(tmp);
6937 break;
6938 case 0x09:
6939 if (set_cc) {
6940 tcg_gen_xor_i32(tmp, tmp, tmp2);
6941 gen_logic_CC(tmp);
6942 }
6943 tcg_temp_free_i32(tmp);
6944 break;
6945 case 0x0a:
6946 if (set_cc) {
6947 gen_helper_sub_cc(tmp, tmp, tmp2);
6948 }
6949 tcg_temp_free_i32(tmp);
6950 break;
6951 case 0x0b:
6952 if (set_cc) {
6953 gen_helper_add_cc(tmp, tmp, tmp2);
6954 }
6955 tcg_temp_free_i32(tmp);
6956 break;
6957 case 0x0c:
6958 tcg_gen_or_i32(tmp, tmp, tmp2);
6959 if (logic_cc) {
6960 gen_logic_CC(tmp);
6961 }
6962 store_reg_bx(env, s, rd, tmp);
6963 break;
6964 case 0x0d:
6965 if (logic_cc && rd == 15) {
6966 /* MOVS r15, ... is used for exception return. */
6967 if (IS_USER(s)) {
6968 goto illegal_op;
6969 }
6970 gen_exception_return(s, tmp2);
6971 } else {
6972 if (logic_cc) {
6973 gen_logic_CC(tmp2);
6974 }
6975 store_reg_bx(env, s, rd, tmp2);
6976 }
6977 break;
6978 case 0x0e:
6979 tcg_gen_andc_i32(tmp, tmp, tmp2);
6980 if (logic_cc) {
6981 gen_logic_CC(tmp);
6982 }
6983 store_reg_bx(env, s, rd, tmp);
6984 break;
6985 default:
6986 case 0x0f:
6987 tcg_gen_not_i32(tmp2, tmp2);
6988 if (logic_cc) {
6989 gen_logic_CC(tmp2);
6990 }
6991 store_reg_bx(env, s, rd, tmp2);
6992 break;
6993 }
6994 if (op1 != 0x0f && op1 != 0x0d) {
6995 tcg_temp_free_i32(tmp2);
6996 }
6997 } else {
6998 /* other instructions */
6999 op1 = (insn >> 24) & 0xf;
7000 switch(op1) {
7001 case 0x0:
7002 case 0x1:
7003 /* multiplies, extra load/stores */
7004 sh = (insn >> 5) & 3;
7005 if (sh == 0) {
7006 if (op1 == 0x0) {
7007 rd = (insn >> 16) & 0xf;
7008 rn = (insn >> 12) & 0xf;
7009 rs = (insn >> 8) & 0xf;
7010 rm = (insn) & 0xf;
7011 op1 = (insn >> 20) & 0xf;
7012 switch (op1) {
7013 case 0: case 1: case 2: case 3: case 6:
7014 /* 32 bit mul */
7015 tmp = load_reg(s, rs);
7016 tmp2 = load_reg(s, rm);
7017 tcg_gen_mul_i32(tmp, tmp, tmp2);
7018 tcg_temp_free_i32(tmp2);
7019 if (insn & (1 << 22)) {
7020 /* Subtract (mls) */
7021 ARCH(6T2);
7022 tmp2 = load_reg(s, rn);
7023 tcg_gen_sub_i32(tmp, tmp2, tmp);
7024 tcg_temp_free_i32(tmp2);
7025 } else if (insn & (1 << 21)) {
7026 /* Add */
7027 tmp2 = load_reg(s, rn);
7028 tcg_gen_add_i32(tmp, tmp, tmp2);
7029 tcg_temp_free_i32(tmp2);
7030 }
7031 if (insn & (1 << 20))
7032 gen_logic_CC(tmp);
7033 store_reg(s, rd, tmp);
7034 break;
7035 case 4:
7036 /* 64 bit mul double accumulate (UMAAL) */
7037 ARCH(6);
7038 tmp = load_reg(s, rs);
7039 tmp2 = load_reg(s, rm);
7040 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
7041 gen_addq_lo(s, tmp64, rn);
7042 gen_addq_lo(s, tmp64, rd);
7043 gen_storeq_reg(s, rn, rd, tmp64);
7044 tcg_temp_free_i64(tmp64);
7045 break;
7046 case 8: case 9: case 10: case 11:
7047 case 12: case 13: case 14: case 15:
7048 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
7049 tmp = load_reg(s, rs);
7050 tmp2 = load_reg(s, rm);
7051 if (insn & (1 << 22)) {
7052 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7053 } else {
7054 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
7055 }
7056 if (insn & (1 << 21)) { /* mult accumulate */
7057 gen_addq(s, tmp64, rn, rd);
7058 }
7059 if (insn & (1 << 20)) {
7060 gen_logicq_cc(tmp64);
7061 }
7062 gen_storeq_reg(s, rn, rd, tmp64);
7063 tcg_temp_free_i64(tmp64);
7064 break;
7065 default:
7066 goto illegal_op;
7067 }
7068 } else {
7069 rn = (insn >> 16) & 0xf;
7070 rd = (insn >> 12) & 0xf;
7071 if (insn & (1 << 23)) {
7072 /* load/store exclusive */
7073 op1 = (insn >> 21) & 0x3;
7074 if (op1)
7075 ARCH(6K);
7076 else
7077 ARCH(6);
7078 addr = tcg_temp_local_new_i32();
7079 load_reg_var(s, addr, rn);
7080 if (insn & (1 << 20)) {
7081 switch (op1) {
7082 case 0: /* ldrex */
7083 gen_load_exclusive(s, rd, 15, addr, 2);
7084 break;
7085 case 1: /* ldrexd */
7086 gen_load_exclusive(s, rd, rd + 1, addr, 3);
7087 break;
7088 case 2: /* ldrexb */
7089 gen_load_exclusive(s, rd, 15, addr, 0);
7090 break;
7091 case 3: /* ldrexh */
7092 gen_load_exclusive(s, rd, 15, addr, 1);
7093 break;
7094 default:
7095 abort();
7096 }
7097 } else {
7098 rm = insn & 0xf;
7099 switch (op1) {
7100 case 0: /* strex */
7101 gen_store_exclusive(s, rd, rm, 15, addr, 2);
7102 break;
7103 case 1: /* strexd */
7104 gen_store_exclusive(s, rd, rm, rm + 1, addr, 3);
7105 break;
7106 case 2: /* strexb */
7107 gen_store_exclusive(s, rd, rm, 15, addr, 0);
7108 break;
7109 case 3: /* strexh */
7110 gen_store_exclusive(s, rd, rm, 15, addr, 1);
7111 break;
7112 default:
7113 abort();
7114 }
7115 }
7116 tcg_temp_free(addr);
7117 } else {
7118 /* SWP instruction */
7119 rm = (insn) & 0xf;
7120
7121 /* ??? This is not really atomic. However we know
7122 we never have multiple CPUs running in parallel,
7123 so it is good enough. */
7124 addr = load_reg(s, rn);
7125 tmp = load_reg(s, rm);
7126 if (insn & (1 << 22)) {
7127 tmp2 = gen_ld8u(addr, IS_USER(s));
7128 gen_st8(tmp, addr, IS_USER(s));
7129 } else {
7130 tmp2 = gen_ld32(addr, IS_USER(s));
7131 gen_st32(tmp, addr, IS_USER(s));
7132 }
7133 tcg_temp_free_i32(addr);
7134 store_reg(s, rd, tmp2);
7135 }
7136 }
7137 } else {
7138 int address_offset;
7139 int load;
7140 /* Misc load/store */
7141 rn = (insn >> 16) & 0xf;
7142 rd = (insn >> 12) & 0xf;
7143 addr = load_reg(s, rn);
7144 if (insn & (1 << 24))
7145 gen_add_datah_offset(s, insn, 0, addr);
7146 address_offset = 0;
7147 if (insn & (1 << 20)) {
7148 /* load */
7149 switch(sh) {
7150 case 1:
7151 tmp = gen_ld16u(addr, IS_USER(s));
7152 break;
7153 case 2:
7154 tmp = gen_ld8s(addr, IS_USER(s));
7155 break;
7156 default:
7157 case 3:
7158 tmp = gen_ld16s(addr, IS_USER(s));
7159 break;
7160 }
7161 load = 1;
7162 } else if (sh & 2) {
7163 ARCH(5TE);
7164 /* doubleword */
7165 if (sh & 1) {
7166 /* store */
7167 tmp = load_reg(s, rd);
7168 gen_st32(tmp, addr, IS_USER(s));
7169 tcg_gen_addi_i32(addr, addr, 4);
7170 tmp = load_reg(s, rd + 1);
7171 gen_st32(tmp, addr, IS_USER(s));
7172 load = 0;
7173 } else {
7174 /* load */
7175 tmp = gen_ld32(addr, IS_USER(s));
7176 store_reg(s, rd, tmp);
7177 tcg_gen_addi_i32(addr, addr, 4);
7178 tmp = gen_ld32(addr, IS_USER(s));
7179 rd++;
7180 load = 1;
7181 }
7182 address_offset = -4;
7183 } else {
7184 /* store */
7185 tmp = load_reg(s, rd);
7186 gen_st16(tmp, addr, IS_USER(s));
7187 load = 0;
7188 }
7189 /* Perform base writeback before the loaded value to
7190 ensure correct behavior with overlapping index registers.
7191 ldrd with base writeback is is undefined if the
7192 destination and index registers overlap. */
7193 if (!(insn & (1 << 24))) {
7194 gen_add_datah_offset(s, insn, address_offset, addr);
7195 store_reg(s, rn, addr);
7196 } else if (insn & (1 << 21)) {
7197 if (address_offset)
7198 tcg_gen_addi_i32(addr, addr, address_offset);
7199 store_reg(s, rn, addr);
7200 } else {
7201 tcg_temp_free_i32(addr);
7202 }
7203 if (load) {
7204 /* Complete the load. */
7205 store_reg(s, rd, tmp);
7206 }
7207 }
7208 break;
7209 case 0x4:
7210 case 0x5:
7211 goto do_ldst;
7212 case 0x6:
7213 case 0x7:
7214 if (insn & (1 << 4)) {
7215 ARCH(6);
7216 /* Armv6 Media instructions. */
7217 rm = insn & 0xf;
7218 rn = (insn >> 16) & 0xf;
7219 rd = (insn >> 12) & 0xf;
7220 rs = (insn >> 8) & 0xf;
7221 switch ((insn >> 23) & 3) {
7222 case 0: /* Parallel add/subtract. */
7223 op1 = (insn >> 20) & 7;
7224 tmp = load_reg(s, rn);
7225 tmp2 = load_reg(s, rm);
7226 sh = (insn >> 5) & 7;
7227 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
7228 goto illegal_op;
7229 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
7230 tcg_temp_free_i32(tmp2);
7231 store_reg(s, rd, tmp);
7232 break;
7233 case 1:
7234 if ((insn & 0x00700020) == 0) {
7235 /* Halfword pack. */
7236 tmp = load_reg(s, rn);
7237 tmp2 = load_reg(s, rm);
7238 shift = (insn >> 7) & 0x1f;
7239 if (insn & (1 << 6)) {
7240 /* pkhtb */
7241 if (shift == 0)
7242 shift = 31;
7243 tcg_gen_sari_i32(tmp2, tmp2, shift);
7244 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
7245 tcg_gen_ext16u_i32(tmp2, tmp2);
7246 } else {
7247 /* pkhbt */
7248 if (shift)
7249 tcg_gen_shli_i32(tmp2, tmp2, shift);
7250 tcg_gen_ext16u_i32(tmp, tmp);
7251 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
7252 }
7253 tcg_gen_or_i32(tmp, tmp, tmp2);
7254 tcg_temp_free_i32(tmp2);
7255 store_reg(s, rd, tmp);
7256 } else if ((insn & 0x00200020) == 0x00200000) {
7257 /* [us]sat */
7258 tmp = load_reg(s, rm);
7259 shift = (insn >> 7) & 0x1f;
7260 if (insn & (1 << 6)) {
7261 if (shift == 0)
7262 shift = 31;
7263 tcg_gen_sari_i32(tmp, tmp, shift);
7264 } else {
7265 tcg_gen_shli_i32(tmp, tmp, shift);
7266 }
7267 sh = (insn >> 16) & 0x1f;
7268 tmp2 = tcg_const_i32(sh);
7269 if (insn & (1 << 22))
7270 gen_helper_usat(tmp, tmp, tmp2);
7271 else
7272 gen_helper_ssat(tmp, tmp, tmp2);
7273 tcg_temp_free_i32(tmp2);
7274 store_reg(s, rd, tmp);
7275 } else if ((insn & 0x00300fe0) == 0x00200f20) {
7276 /* [us]sat16 */
7277 tmp = load_reg(s, rm);
7278 sh = (insn >> 16) & 0x1f;
7279 tmp2 = tcg_const_i32(sh);
7280 if (insn & (1 << 22))
7281 gen_helper_usat16(tmp, tmp, tmp2);
7282 else
7283 gen_helper_ssat16(tmp, tmp, tmp2);
7284 tcg_temp_free_i32(tmp2);
7285 store_reg(s, rd, tmp);
7286 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
7287 /* Select bytes. */
7288 tmp = load_reg(s, rn);
7289 tmp2 = load_reg(s, rm);
7290 tmp3 = tcg_temp_new_i32();
7291 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
7292 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
7293 tcg_temp_free_i32(tmp3);
7294 tcg_temp_free_i32(tmp2);
7295 store_reg(s, rd, tmp);
7296 } else if ((insn & 0x000003e0) == 0x00000060) {
7297 tmp = load_reg(s, rm);
7298 shift = (insn >> 10) & 3;
7299 /* ??? In many cases it's not neccessary to do a
7300 rotate, a shift is sufficient. */
7301 if (shift != 0)
7302 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
7303 op1 = (insn >> 20) & 7;
7304 switch (op1) {
7305 case 0: gen_sxtb16(tmp); break;
7306 case 2: gen_sxtb(tmp); break;
7307 case 3: gen_sxth(tmp); break;
7308 case 4: gen_uxtb16(tmp); break;
7309 case 6: gen_uxtb(tmp); break;
7310 case 7: gen_uxth(tmp); break;
7311 default: goto illegal_op;
7312 }
7313 if (rn != 15) {
7314 tmp2 = load_reg(s, rn);
7315 if ((op1 & 3) == 0) {
7316 gen_add16(tmp, tmp2);
7317 } else {
7318 tcg_gen_add_i32(tmp, tmp, tmp2);
7319 tcg_temp_free_i32(tmp2);
7320 }
7321 }
7322 store_reg(s, rd, tmp);
7323 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
7324 /* rev */
7325 tmp = load_reg(s, rm);
7326 if (insn & (1 << 22)) {
7327 if (insn & (1 << 7)) {
7328 gen_revsh(tmp);
7329 } else {
7330 ARCH(6T2);
7331 gen_helper_rbit(tmp, tmp);
7332 }
7333 } else {
7334 if (insn & (1 << 7))
7335 gen_rev16(tmp);
7336 else
7337 tcg_gen_bswap32_i32(tmp, tmp);
7338 }
7339 store_reg(s, rd, tmp);
7340 } else {
7341 goto illegal_op;
7342 }
7343 break;
7344 case 2: /* Multiplies (Type 3). */
7345 tmp = load_reg(s, rm);
7346 tmp2 = load_reg(s, rs);
7347 if (insn & (1 << 20)) {
7348 /* Signed multiply most significant [accumulate].
7349 (SMMUL, SMMLA, SMMLS) */
7350 tmp64 = gen_muls_i64_i32(tmp, tmp2);
7351
7352 if (rd != 15) {
7353 tmp = load_reg(s, rd);
7354 if (insn & (1 << 6)) {
7355 tmp64 = gen_subq_msw(tmp64, tmp);
7356 } else {
7357 tmp64 = gen_addq_msw(tmp64, tmp);
7358 }
7359 }
7360 if (insn & (1 << 5)) {
7361 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
7362 }
7363 tcg_gen_shri_i64(tmp64, tmp64, 32);
7364 tmp = tcg_temp_new_i32();
7365 tcg_gen_trunc_i64_i32(tmp, tmp64);
7366 tcg_temp_free_i64(tmp64);
7367 store_reg(s, rn, tmp);
7368 } else {
7369 if (insn & (1 << 5))
7370 gen_swap_half(tmp2);
7371 gen_smul_dual(tmp, tmp2);
7372 if (insn & (1 << 6)) {
7373 /* This subtraction cannot overflow. */
7374 tcg_gen_sub_i32(tmp, tmp, tmp2);
7375 } else {
7376 /* This addition cannot overflow 32 bits;
7377 * however it may overflow considered as a signed
7378 * operation, in which case we must set the Q flag.
7379 */
7380 gen_helper_add_setq(tmp, tmp, tmp2);
7381 }
7382 tcg_temp_free_i32(tmp2);
7383 if (insn & (1 << 22)) {
7384 /* smlald, smlsld */
7385 tmp64 = tcg_temp_new_i64();
7386 tcg_gen_ext_i32_i64(tmp64, tmp);
7387 tcg_temp_free_i32(tmp);
7388 gen_addq(s, tmp64, rd, rn);
7389 gen_storeq_reg(s, rd, rn, tmp64);
7390 tcg_temp_free_i64(tmp64);
7391 } else {
7392 /* smuad, smusd, smlad, smlsd */
7393 if (rd != 15)
7394 {
7395 tmp2 = load_reg(s, rd);
7396 gen_helper_add_setq(tmp, tmp, tmp2);
7397 tcg_temp_free_i32(tmp2);
7398 }
7399 store_reg(s, rn, tmp);
7400 }
7401 }
7402 break;
7403 case 3:
7404 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
7405 switch (op1) {
7406 case 0: /* Unsigned sum of absolute differences. */
7407 ARCH(6);
7408 tmp = load_reg(s, rm);
7409 tmp2 = load_reg(s, rs);
7410 gen_helper_usad8(tmp, tmp, tmp2);
7411 tcg_temp_free_i32(tmp2);
7412 if (rd != 15) {
7413 tmp2 = load_reg(s, rd);
7414 tcg_gen_add_i32(tmp, tmp, tmp2);
7415 tcg_temp_free_i32(tmp2);
7416 }
7417 store_reg(s, rn, tmp);
7418 break;
7419 case 0x20: case 0x24: case 0x28: case 0x2c:
7420 /* Bitfield insert/clear. */
7421 ARCH(6T2);
7422 shift = (insn >> 7) & 0x1f;
7423 i = (insn >> 16) & 0x1f;
7424 i = i + 1 - shift;
7425 if (rm == 15) {
7426 tmp = tcg_temp_new_i32();
7427 tcg_gen_movi_i32(tmp, 0);
7428 } else {
7429 tmp = load_reg(s, rm);
7430 }
7431 if (i != 32) {
7432 tmp2 = load_reg(s, rd);
7433 gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1);
7434 tcg_temp_free_i32(tmp2);
7435 }
7436 store_reg(s, rd, tmp);
7437 break;
7438 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7439 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7440 ARCH(6T2);
7441 tmp = load_reg(s, rm);
7442 shift = (insn >> 7) & 0x1f;
7443 i = ((insn >> 16) & 0x1f) + 1;
7444 if (shift + i > 32)
7445 goto illegal_op;
7446 if (i < 32) {
7447 if (op1 & 0x20) {
7448 gen_ubfx(tmp, shift, (1u << i) - 1);
7449 } else {
7450 gen_sbfx(tmp, shift, i);
7451 }
7452 }
7453 store_reg(s, rd, tmp);
7454 break;
7455 default:
7456 goto illegal_op;
7457 }
7458 break;
7459 }
7460 break;
7461 }
7462 do_ldst:
7463 /* Check for undefined extension instructions
7464 * per the ARM Bible IE:
7465 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7466 */
7467 sh = (0xf << 20) | (0xf << 4);
7468 if (op1 == 0x7 && ((insn & sh) == sh))
7469 {
7470 goto illegal_op;
7471 }
7472 /* load/store byte/word */
7473 rn = (insn >> 16) & 0xf;
7474 rd = (insn >> 12) & 0xf;
7475 tmp2 = load_reg(s, rn);
7476 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
7477 if (insn & (1 << 24))
7478 gen_add_data_offset(s, insn, tmp2);
7479 if (insn & (1 << 20)) {
7480 /* load */
7481 if (insn & (1 << 22)) {
7482 tmp = gen_ld8u(tmp2, i);
7483 } else {
7484 tmp = gen_ld32(tmp2, i);
7485 }
7486 } else {
7487 /* store */
7488 tmp = load_reg(s, rd);
7489 if (insn & (1 << 22))
7490 gen_st8(tmp, tmp2, i);
7491 else
7492 gen_st32(tmp, tmp2, i);
7493 }
7494 if (!(insn & (1 << 24))) {
7495 gen_add_data_offset(s, insn, tmp2);
7496 store_reg(s, rn, tmp2);
7497 } else if (insn & (1 << 21)) {
7498 store_reg(s, rn, tmp2);
7499 } else {
7500 tcg_temp_free_i32(tmp2);
7501 }
7502 if (insn & (1 << 20)) {
7503 /* Complete the load. */
7504 store_reg_from_load(env, s, rd, tmp);
7505 }
7506 break;
7507 case 0x08:
7508 case 0x09:
7509 {
7510 int j, n, user, loaded_base;
7511 TCGv loaded_var;
7512 /* load/store multiple words */
7513 /* XXX: store correct base if write back */
7514 user = 0;
7515 if (insn & (1 << 22)) {
7516 if (IS_USER(s))
7517 goto illegal_op; /* only usable in supervisor mode */
7518
7519 if ((insn & (1 << 15)) == 0)
7520 user = 1;
7521 }
7522 rn = (insn >> 16) & 0xf;
7523 addr = load_reg(s, rn);
7524
7525 /* compute total size */
7526 loaded_base = 0;
7527 TCGV_UNUSED(loaded_var);
7528 n = 0;
7529 for(i=0;i<16;i++) {
7530 if (insn & (1 << i))
7531 n++;
7532 }
7533 /* XXX: test invalid n == 0 case ? */
7534 if (insn & (1 << 23)) {
7535 if (insn & (1 << 24)) {
7536 /* pre increment */
7537 tcg_gen_addi_i32(addr, addr, 4);
7538 } else {
7539 /* post increment */
7540 }
7541 } else {
7542 if (insn & (1 << 24)) {
7543 /* pre decrement */
7544 tcg_gen_addi_i32(addr, addr, -(n * 4));
7545 } else {
7546 /* post decrement */
7547 if (n != 1)
7548 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7549 }
7550 }
7551 j = 0;
7552 for(i=0;i<16;i++) {
7553 if (insn & (1 << i)) {
7554 if (insn & (1 << 20)) {
7555 /* load */
7556 tmp = gen_ld32(addr, IS_USER(s));
7557 if (user) {
7558 tmp2 = tcg_const_i32(i);
7559 gen_helper_set_user_reg(tmp2, tmp);
7560 tcg_temp_free_i32(tmp2);
7561 tcg_temp_free_i32(tmp);
7562 } else if (i == rn) {
7563 loaded_var = tmp;
7564 loaded_base = 1;
7565 } else {
7566 store_reg_from_load(env, s, i, tmp);
7567 }
7568 } else {
7569 /* store */
7570 if (i == 15) {
7571 /* special case: r15 = PC + 8 */
7572 val = (long)s->pc + 4;
7573 tmp = tcg_temp_new_i32();
7574 tcg_gen_movi_i32(tmp, val);
7575 } else if (user) {
7576 tmp = tcg_temp_new_i32();
7577 tmp2 = tcg_const_i32(i);
7578 gen_helper_get_user_reg(tmp, tmp2);
7579 tcg_temp_free_i32(tmp2);
7580 } else {
7581 tmp = load_reg(s, i);
7582 }
7583 gen_st32(tmp, addr, IS_USER(s));
7584 }
7585 j++;
7586 /* no need to add after the last transfer */
7587 if (j != n)
7588 tcg_gen_addi_i32(addr, addr, 4);
7589 }
7590 }
7591 if (insn & (1 << 21)) {
7592 /* write back */
7593 if (insn & (1 << 23)) {
7594 if (insn & (1 << 24)) {
7595 /* pre increment */
7596 } else {
7597 /* post increment */
7598 tcg_gen_addi_i32(addr, addr, 4);
7599 }
7600 } else {
7601 if (insn & (1 << 24)) {
7602 /* pre decrement */
7603 if (n != 1)
7604 tcg_gen_addi_i32(addr, addr, -((n - 1) * 4));
7605 } else {
7606 /* post decrement */
7607 tcg_gen_addi_i32(addr, addr, -(n * 4));
7608 }
7609 }
7610 store_reg(s, rn, addr);
7611 } else {
7612 tcg_temp_free_i32(addr);
7613 }
7614 if (loaded_base) {
7615 store_reg(s, rn, loaded_var);
7616 }
7617 if ((insn & (1 << 22)) && !user) {
7618 /* Restore CPSR from SPSR. */
7619 tmp = load_cpu_field(spsr);
7620 gen_set_cpsr(tmp, 0xffffffff);
7621 tcg_temp_free_i32(tmp);
7622 s->is_jmp = DISAS_UPDATE;
7623 }
7624 }
7625 break;
7626 case 0xa:
7627 case 0xb:
7628 {
7629 int32_t offset;
7630
7631 /* branch (and link) */
7632 val = (int32_t)s->pc;
7633 if (insn & (1 << 24)) {
7634 tmp = tcg_temp_new_i32();
7635 tcg_gen_movi_i32(tmp, val);
7636 store_reg(s, 14, tmp);
7637 }
7638 offset = (((int32_t)insn << 8) >> 8);
7639 val += (offset << 2) + 4;
7640 gen_jmp(s, val);
7641 }
7642 break;
7643 case 0xc:
7644 case 0xd:
7645 case 0xe:
7646 /* Coprocessor. */
7647 if (disas_coproc_insn(env, s, insn))
7648 goto illegal_op;
7649 break;
7650 case 0xf:
7651 /* swi */
7652 gen_set_pc_im(s->pc);
7653 s->is_jmp = DISAS_SWI;
7654 break;
7655 default:
7656 illegal_op:
7657 gen_exception_insn(s, 4, EXCP_UDEF);
7658 break;
7659 }
7660 }
7661 }
7662
7663 /* Return true if this is a Thumb-2 logical op. */
7664 static int
7665 thumb2_logic_op(int op)
7666 {
7667 return (op < 8);
7668 }
7669
7670 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7671 then set condition code flags based on the result of the operation.
7672 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7673 to the high bit of T1.
7674 Returns zero if the opcode is valid. */
7675
7676 static int
7677 gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCGv t0, TCGv t1)
7678 {
7679 int logic_cc;
7680
7681 logic_cc = 0;
7682 switch (op) {
7683 case 0: /* and */
7684 tcg_gen_and_i32(t0, t0, t1);
7685 logic_cc = conds;
7686 break;
7687 case 1: /* bic */
7688 tcg_gen_andc_i32(t0, t0, t1);
7689 logic_cc = conds;
7690 break;
7691 case 2: /* orr */
7692 tcg_gen_or_i32(t0, t0, t1);
7693 logic_cc = conds;
7694 break;
7695 case 3: /* orn */
7696 tcg_gen_orc_i32(t0, t0, t1);
7697 logic_cc = conds;
7698 break;
7699 case 4: /* eor */
7700 tcg_gen_xor_i32(t0, t0, t1);
7701 logic_cc = conds;
7702 break;
7703 case 8: /* add */
7704 if (conds)
7705 gen_helper_add_cc(t0, t0, t1);
7706 else
7707 tcg_gen_add_i32(t0, t0, t1);
7708 break;
7709 case 10: /* adc */
7710 if (conds)
7711 gen_helper_adc_cc(t0, t0, t1);
7712 else
7713 gen_adc(t0, t1);
7714 break;
7715 case 11: /* sbc */
7716 if (conds)
7717 gen_helper_sbc_cc(t0, t0, t1);
7718 else
7719 gen_sub_carry(t0, t0, t1);
7720 break;
7721 case 13: /* sub */
7722 if (conds)
7723 gen_helper_sub_cc(t0, t0, t1);
7724 else
7725 tcg_gen_sub_i32(t0, t0, t1);
7726 break;
7727 case 14: /* rsb */
7728 if (conds)
7729 gen_helper_sub_cc(t0, t1, t0);
7730 else
7731 tcg_gen_sub_i32(t0, t1, t0);
7732 break;
7733 default: /* 5, 6, 7, 9, 12, 15. */
7734 return 1;
7735 }
7736 if (logic_cc) {
7737 gen_logic_CC(t0);
7738 if (shifter_out)
7739 gen_set_CF_bit31(t1);
7740 }
7741 return 0;
7742 }
7743
7744 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7745 is not legal. */
7746 static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
7747 {
7748 uint32_t insn, imm, shift, offset;
7749 uint32_t rd, rn, rm, rs;
7750 TCGv tmp;
7751 TCGv tmp2;
7752 TCGv tmp3;
7753 TCGv addr;
7754 TCGv_i64 tmp64;
7755 int op;
7756 int shiftop;
7757 int conds;
7758 int logic_cc;
7759
7760 if (!(arm_feature(env, ARM_FEATURE_THUMB2)
7761 || arm_feature (env, ARM_FEATURE_M))) {
7762 /* Thumb-1 cores may need to treat bl and blx as a pair of
7763 16-bit instructions to get correct prefetch abort behavior. */
7764 insn = insn_hw1;
7765 if ((insn & (1 << 12)) == 0) {
7766 ARCH(5);
7767 /* Second half of blx. */
7768 offset = ((insn & 0x7ff) << 1);
7769 tmp = load_reg(s, 14);
7770 tcg_gen_addi_i32(tmp, tmp, offset);
7771 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
7772
7773 tmp2 = tcg_temp_new_i32();
7774 tcg_gen_movi_i32(tmp2, s->pc | 1);
7775 store_reg(s, 14, tmp2);
7776 gen_bx(s, tmp);
7777 return 0;
7778 }
7779 if (insn & (1 << 11)) {
7780 /* Second half of bl. */
7781 offset = ((insn & 0x7ff) << 1) | 1;
7782 tmp = load_reg(s, 14);
7783 tcg_gen_addi_i32(tmp, tmp, offset);
7784
7785 tmp2 = tcg_temp_new_i32();
7786 tcg_gen_movi_i32(tmp2, s->pc | 1);
7787 store_reg(s, 14, tmp2);
7788 gen_bx(s, tmp);
7789 return 0;
7790 }
7791 if ((s->pc & ~TARGET_PAGE_MASK) == 0) {
7792 /* Instruction spans a page boundary. Implement it as two
7793 16-bit instructions in case the second half causes an
7794 prefetch abort. */
7795 offset = ((int32_t)insn << 21) >> 9;
7796 tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + offset);
7797 return 0;
7798 }
7799 /* Fall through to 32-bit decode. */
7800 }
7801
7802 insn = lduw_code(s->pc);
7803 s->pc += 2;
7804 insn |= (uint32_t)insn_hw1 << 16;
7805
7806 if ((insn & 0xf800e800) != 0xf000e800) {
7807 ARCH(6T2);
7808 }
7809
7810 rn = (insn >> 16) & 0xf;
7811 rs = (insn >> 12) & 0xf;
7812 rd = (insn >> 8) & 0xf;
7813 rm = insn & 0xf;
7814 switch ((insn >> 25) & 0xf) {
7815 case 0: case 1: case 2: case 3:
7816 /* 16-bit instructions. Should never happen. */
7817 abort();
7818 case 4:
7819 if (insn & (1 << 22)) {
7820 /* Other load/store, table branch. */
7821 if (insn & 0x01200000) {
7822 /* Load/store doubleword. */
7823 if (rn == 15) {
7824 addr = tcg_temp_new_i32();
7825 tcg_gen_movi_i32(addr, s->pc & ~3);
7826 } else {
7827 addr = load_reg(s, rn);
7828 }
7829 offset = (insn & 0xff) * 4;
7830 if ((insn & (1 << 23)) == 0)
7831 offset = -offset;
7832 if (insn & (1 << 24)) {
7833 tcg_gen_addi_i32(addr, addr, offset);
7834 offset = 0;
7835 }
7836 if (insn & (1 << 20)) {
7837 /* ldrd */
7838 tmp = gen_ld32(addr, IS_USER(s));
7839 store_reg(s, rs, tmp);
7840 tcg_gen_addi_i32(addr, addr, 4);
7841 tmp = gen_ld32(addr, IS_USER(s));
7842 store_reg(s, rd, tmp);
7843 } else {
7844 /* strd */
7845 tmp = load_reg(s, rs);
7846 gen_st32(tmp, addr, IS_USER(s));
7847 tcg_gen_addi_i32(addr, addr, 4);
7848 tmp = load_reg(s, rd);
7849 gen_st32(tmp, addr, IS_USER(s));
7850 }
7851 if (insn & (1 << 21)) {
7852 /* Base writeback. */
7853 if (rn == 15)
7854 goto illegal_op;
7855 tcg_gen_addi_i32(addr, addr, offset - 4);
7856 store_reg(s, rn, addr);
7857 } else {
7858 tcg_temp_free_i32(addr);
7859 }
7860 } else if ((insn & (1 << 23)) == 0) {
7861 /* Load/store exclusive word. */
7862 addr = tcg_temp_local_new();
7863 load_reg_var(s, addr, rn);
7864 tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2);
7865 if (insn & (1 << 20)) {
7866 gen_load_exclusive(s, rs, 15, addr, 2);
7867 } else {
7868 gen_store_exclusive(s, rd, rs, 15, addr, 2);
7869 }
7870 tcg_temp_free(addr);
7871 } else if ((insn & (1 << 6)) == 0) {
7872 /* Table Branch. */
7873 if (rn == 15) {
7874 addr = tcg_temp_new_i32();
7875 tcg_gen_movi_i32(addr, s->pc);
7876 } else {
7877 addr = load_reg(s, rn);
7878 }
7879 tmp = load_reg(s, rm);
7880 tcg_gen_add_i32(addr, addr, tmp);
7881 if (insn & (1 << 4)) {
7882 /* tbh */
7883 tcg_gen_add_i32(addr, addr, tmp);
7884 tcg_temp_free_i32(tmp);
7885 tmp = gen_ld16u(addr, IS_USER(s));
7886 } else { /* tbb */
7887 tcg_temp_free_i32(tmp);
7888 tmp = gen_ld8u(addr, IS_USER(s));
7889 }
7890 tcg_temp_free_i32(addr);
7891 tcg_gen_shli_i32(tmp, tmp, 1);
7892 tcg_gen_addi_i32(tmp, tmp, s->pc);
7893 store_reg(s, 15, tmp);
7894 } else {
7895 /* Load/store exclusive byte/halfword/doubleword. */
7896 ARCH(7);
7897 op = (insn >> 4) & 0x3;
7898 if (op == 2) {
7899 goto illegal_op;
7900 }
7901 addr = tcg_temp_local_new();
7902 load_reg_var(s, addr, rn);
7903 if (insn & (1 << 20)) {
7904 gen_load_exclusive(s, rs, rd, addr, op);
7905 } else {
7906 gen_store_exclusive(s, rm, rs, rd, addr, op);
7907 }
7908 tcg_temp_free(addr);
7909 }
7910 } else {
7911 /* Load/store multiple, RFE, SRS. */
7912 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7913 /* Not available in user mode. */
7914 if (IS_USER(s))
7915 goto illegal_op;
7916 if (insn & (1 << 20)) {
7917 /* rfe */
7918 addr = load_reg(s, rn);
7919 if ((insn & (1 << 24)) == 0)
7920 tcg_gen_addi_i32(addr, addr, -8);
7921 /* Load PC into tmp and CPSR into tmp2. */
7922 tmp = gen_ld32(addr, 0);
7923 tcg_gen_addi_i32(addr, addr, 4);
7924 tmp2 = gen_ld32(addr, 0);
7925 if (insn & (1 << 21)) {
7926 /* Base writeback. */
7927 if (insn & (1 << 24)) {
7928 tcg_gen_addi_i32(addr, addr, 4);
7929 } else {
7930 tcg_gen_addi_i32(addr, addr, -4);
7931 }
7932 store_reg(s, rn, addr);
7933 } else {
7934 tcg_temp_free_i32(addr);
7935 }
7936 gen_rfe(s, tmp, tmp2);
7937 } else {
7938 /* srs */
7939 op = (insn & 0x1f);
7940 addr = tcg_temp_new_i32();
7941 tmp = tcg_const_i32(op);
7942 gen_helper_get_r13_banked(addr, cpu_env, tmp);
7943 tcg_temp_free_i32(tmp);
7944 if ((insn & (1 << 24)) == 0) {
7945 tcg_gen_addi_i32(addr, addr, -8);
7946 }
7947 tmp = load_reg(s, 14);
7948 gen_st32(tmp, addr, 0);
7949 tcg_gen_addi_i32(addr, addr, 4);
7950 tmp = tcg_temp_new_i32();
7951 gen_helper_cpsr_read(tmp);
7952 gen_st32(tmp, addr, 0);
7953 if (insn & (1 << 21)) {
7954 if ((insn & (1 << 24)) == 0) {
7955 tcg_gen_addi_i32(addr, addr, -4);
7956 } else {
7957 tcg_gen_addi_i32(addr, addr, 4);
7958 }
7959 tmp = tcg_const_i32(op);
7960 gen_helper_set_r13_banked(cpu_env, tmp, addr);
7961 tcg_temp_free_i32(tmp);
7962 } else {
7963 tcg_temp_free_i32(addr);
7964 }
7965 }
7966 } else {
7967 int i;
7968 /* Load/store multiple. */
7969 addr = load_reg(s, rn);
7970 offset = 0;
7971 for (i = 0; i < 16; i++) {
7972 if (insn & (1 << i))
7973 offset += 4;
7974 }
7975 if (insn & (1 << 24)) {
7976 tcg_gen_addi_i32(addr, addr, -offset);
7977 }
7978
7979 for (i = 0; i < 16; i++) {
7980 if ((insn & (1 << i)) == 0)
7981 continue;
7982 if (insn & (1 << 20)) {
7983 /* Load. */
7984 tmp = gen_ld32(addr, IS_USER(s));
7985 if (i == 15) {
7986 gen_bx(s, tmp);
7987 } else {
7988 store_reg(s, i, tmp);
7989 }
7990 } else {
7991 /* Store. */
7992 tmp = load_reg(s, i);
7993 gen_st32(tmp, addr, IS_USER(s));
7994 }
7995 tcg_gen_addi_i32(addr, addr, 4);
7996 }
7997 if (insn & (1 << 21)) {
7998 /* Base register writeback. */
7999 if (insn & (1 << 24)) {
8000 tcg_gen_addi_i32(addr, addr, -offset);
8001 }
8002 /* Fault if writeback register is in register list. */
8003 if (insn & (1 << rn))
8004 goto illegal_op;
8005 store_reg(s, rn, addr);
8006 } else {
8007 tcg_temp_free_i32(addr);
8008 }
8009 }
8010 }
8011 break;
8012 case 5:
8013
8014 op = (insn >> 21) & 0xf;
8015 if (op == 6) {
8016 /* Halfword pack. */
8017 tmp = load_reg(s, rn);
8018 tmp2 = load_reg(s, rm);
8019 shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
8020 if (insn & (1 << 5)) {
8021 /* pkhtb */
8022 if (shift == 0)
8023 shift = 31;
8024 tcg_gen_sari_i32(tmp2, tmp2, shift);
8025 tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
8026 tcg_gen_ext16u_i32(tmp2, tmp2);
8027 } else {
8028 /* pkhbt */
8029 if (shift)
8030 tcg_gen_shli_i32(tmp2, tmp2, shift);
8031 tcg_gen_ext16u_i32(tmp, tmp);
8032 tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
8033 }
8034 tcg_gen_or_i32(tmp, tmp, tmp2);
8035 tcg_temp_free_i32(tmp2);
8036 store_reg(s, rd, tmp);
8037 } else {
8038 /* Data processing register constant shift. */
8039 if (rn == 15) {
8040 tmp = tcg_temp_new_i32();
8041 tcg_gen_movi_i32(tmp, 0);
8042 } else {
8043 tmp = load_reg(s, rn);
8044 }
8045 tmp2 = load_reg(s, rm);
8046
8047 shiftop = (insn >> 4) & 3;
8048 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8049 conds = (insn & (1 << 20)) != 0;
8050 logic_cc = (conds && thumb2_logic_op(op));
8051 gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
8052 if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
8053 goto illegal_op;
8054 tcg_temp_free_i32(tmp2);
8055 if (rd != 15) {
8056 store_reg(s, rd, tmp);
8057 } else {
8058 tcg_temp_free_i32(tmp);
8059 }
8060 }
8061 break;
8062 case 13: /* Misc data processing. */
8063 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
8064 if (op < 4 && (insn & 0xf000) != 0xf000)
8065 goto illegal_op;
8066 switch (op) {
8067 case 0: /* Register controlled shift. */
8068 tmp = load_reg(s, rn);
8069 tmp2 = load_reg(s, rm);
8070 if ((insn & 0x70) != 0)
8071 goto illegal_op;
8072 op = (insn >> 21) & 3;
8073 logic_cc = (insn & (1 << 20)) != 0;
8074 gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
8075 if (logic_cc)
8076 gen_logic_CC(tmp);
8077 store_reg_bx(env, s, rd, tmp);
8078 break;
8079 case 1: /* Sign/zero extend. */
8080 tmp = load_reg(s, rm);
8081 shift = (insn >> 4) & 3;
8082 /* ??? In many cases it's not neccessary to do a
8083 rotate, a shift is sufficient. */
8084 if (shift != 0)
8085 tcg_gen_rotri_i32(tmp, tmp, shift * 8);
8086 op = (insn >> 20) & 7;
8087 switch (op) {
8088 case 0: gen_sxth(tmp); break;
8089 case 1: gen_uxth(tmp); break;
8090 case 2: gen_sxtb16(tmp); break;
8091 case 3: gen_uxtb16(tmp); break;
8092 case 4: gen_sxtb(tmp); break;
8093 case 5: gen_uxtb(tmp); break;
8094 default: goto illegal_op;
8095 }
8096 if (rn != 15) {
8097 tmp2 = load_reg(s, rn);
8098 if ((op >> 1) == 1) {
8099 gen_add16(tmp, tmp2);
8100 } else {
8101 tcg_gen_add_i32(tmp, tmp, tmp2);
8102 tcg_temp_free_i32(tmp2);
8103 }
8104 }
8105 store_reg(s, rd, tmp);
8106 break;
8107 case 2: /* SIMD add/subtract. */
8108 op = (insn >> 20) & 7;
8109 shift = (insn >> 4) & 7;
8110 if ((op & 3) == 3 || (shift & 3) == 3)
8111 goto illegal_op;
8112 tmp = load_reg(s, rn);
8113 tmp2 = load_reg(s, rm);
8114 gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
8115 tcg_temp_free_i32(tmp2);
8116 store_reg(s, rd, tmp);
8117 break;
8118 case 3: /* Other data processing. */
8119 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
8120 if (op < 4) {
8121 /* Saturating add/subtract. */
8122 tmp = load_reg(s, rn);
8123 tmp2 = load_reg(s, rm);
8124 if (op & 1)
8125 gen_helper_double_saturate(tmp, tmp);
8126 if (op & 2)
8127 gen_helper_sub_saturate(tmp, tmp2, tmp);
8128 else
8129 gen_helper_add_saturate(tmp, tmp, tmp2);
8130 tcg_temp_free_i32(tmp2);
8131 } else {
8132 tmp = load_reg(s, rn);
8133 switch (op) {
8134 case 0x0a: /* rbit */
8135 gen_helper_rbit(tmp, tmp);
8136 break;
8137 case 0x08: /* rev */
8138 tcg_gen_bswap32_i32(tmp, tmp);
8139 break;
8140 case 0x09: /* rev16 */
8141 gen_rev16(tmp);
8142 break;
8143 case 0x0b: /* revsh */
8144 gen_revsh(tmp);
8145 break;
8146 case 0x10: /* sel */
8147 tmp2 = load_reg(s, rm);
8148 tmp3 = tcg_temp_new_i32();
8149 tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
8150 gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
8151 tcg_temp_free_i32(tmp3);
8152 tcg_temp_free_i32(tmp2);
8153 break;
8154 case 0x18: /* clz */
8155 gen_helper_clz(tmp, tmp);
8156 break;
8157 default:
8158 goto illegal_op;
8159 }
8160 }
8161 store_reg(s, rd, tmp);
8162 break;
8163 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
8164 op = (insn >> 4) & 0xf;
8165 tmp = load_reg(s, rn);
8166 tmp2 = load_reg(s, rm);
8167 switch ((insn >> 20) & 7) {
8168 case 0: /* 32 x 32 -> 32 */
8169 tcg_gen_mul_i32(tmp, tmp, tmp2);
8170 tcg_temp_free_i32(tmp2);
8171 if (rs != 15) {
8172 tmp2 = load_reg(s, rs);
8173 if (op)
8174 tcg_gen_sub_i32(tmp, tmp2, tmp);
8175 else
8176 tcg_gen_add_i32(tmp, tmp, tmp2);
8177 tcg_temp_free_i32(tmp2);
8178 }
8179 break;
8180 case 1: /* 16 x 16 -> 32 */
8181 gen_mulxy(tmp, tmp2, op & 2, op & 1);
8182 tcg_temp_free_i32(tmp2);
8183 if (rs != 15) {
8184 tmp2 = load_reg(s, rs);
8185 gen_helper_add_setq(tmp, tmp, tmp2);
8186 tcg_temp_free_i32(tmp2);
8187 }
8188 break;
8189 case 2: /* Dual multiply add. */
8190 case 4: /* Dual multiply subtract. */
8191 if (op)
8192 gen_swap_half(tmp2);
8193 gen_smul_dual(tmp, tmp2);
8194 if (insn & (1 << 22)) {
8195 /* This subtraction cannot overflow. */
8196 tcg_gen_sub_i32(tmp, tmp, tmp2);
8197 } else {
8198 /* This addition cannot overflow 32 bits;
8199 * however it may overflow considered as a signed
8200 * operation, in which case we must set the Q flag.
8201 */
8202 gen_helper_add_setq(tmp, tmp, tmp2);
8203 }
8204 tcg_temp_free_i32(tmp2);
8205 if (rs != 15)
8206 {
8207 tmp2 = load_reg(s, rs);
8208 gen_helper_add_setq(tmp, tmp, tmp2);
8209 tcg_temp_free_i32(tmp2);
8210 }
8211 break;
8212 case 3: /* 32 * 16 -> 32msb */
8213 if (op)
8214 tcg_gen_sari_i32(tmp2, tmp2, 16);
8215 else
8216 gen_sxth(tmp2);
8217 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8218 tcg_gen_shri_i64(tmp64, tmp64, 16);
8219 tmp = tcg_temp_new_i32();
8220 tcg_gen_trunc_i64_i32(tmp, tmp64);
8221 tcg_temp_free_i64(tmp64);
8222 if (rs != 15)
8223 {
8224 tmp2 = load_reg(s, rs);
8225 gen_helper_add_setq(tmp, tmp, tmp2);
8226 tcg_temp_free_i32(tmp2);
8227 }
8228 break;
8229 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
8230 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8231 if (rs != 15) {
8232 tmp = load_reg(s, rs);
8233 if (insn & (1 << 20)) {
8234 tmp64 = gen_addq_msw(tmp64, tmp);
8235 } else {
8236 tmp64 = gen_subq_msw(tmp64, tmp);
8237 }
8238 }
8239 if (insn & (1 << 4)) {
8240 tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
8241 }
8242 tcg_gen_shri_i64(tmp64, tmp64, 32);
8243 tmp = tcg_temp_new_i32();
8244 tcg_gen_trunc_i64_i32(tmp, tmp64);
8245 tcg_temp_free_i64(tmp64);
8246 break;
8247 case 7: /* Unsigned sum of absolute differences. */
8248 gen_helper_usad8(tmp, tmp, tmp2);
8249 tcg_temp_free_i32(tmp2);
8250 if (rs != 15) {
8251 tmp2 = load_reg(s, rs);
8252 tcg_gen_add_i32(tmp, tmp, tmp2);
8253 tcg_temp_free_i32(tmp2);
8254 }
8255 break;
8256 }
8257 store_reg(s, rd, tmp);
8258 break;
8259 case 6: case 7: /* 64-bit multiply, Divide. */
8260 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
8261 tmp = load_reg(s, rn);
8262 tmp2 = load_reg(s, rm);
8263 if ((op & 0x50) == 0x10) {
8264 /* sdiv, udiv */
8265 if (!arm_feature(env, ARM_FEATURE_DIV))
8266 goto illegal_op;
8267 if (op & 0x20)
8268 gen_helper_udiv(tmp, tmp, tmp2);
8269 else
8270 gen_helper_sdiv(tmp, tmp, tmp2);
8271 tcg_temp_free_i32(tmp2);
8272 store_reg(s, rd, tmp);
8273 } else if ((op & 0xe) == 0xc) {
8274 /* Dual multiply accumulate long. */
8275 if (op & 1)
8276 gen_swap_half(tmp2);
8277 gen_smul_dual(tmp, tmp2);
8278 if (op & 0x10) {
8279 tcg_gen_sub_i32(tmp, tmp, tmp2);
8280 } else {
8281 tcg_gen_add_i32(tmp, tmp, tmp2);
8282 }
8283 tcg_temp_free_i32(tmp2);
8284 /* BUGFIX */
8285 tmp64 = tcg_temp_new_i64();
8286 tcg_gen_ext_i32_i64(tmp64, tmp);
8287 tcg_temp_free_i32(tmp);
8288 gen_addq(s, tmp64, rs, rd);
8289 gen_storeq_reg(s, rs, rd, tmp64);
8290 tcg_temp_free_i64(tmp64);
8291 } else {
8292 if (op & 0x20) {
8293 /* Unsigned 64-bit multiply */
8294 tmp64 = gen_mulu_i64_i32(tmp, tmp2);
8295 } else {
8296 if (op & 8) {
8297 /* smlalxy */
8298 gen_mulxy(tmp, tmp2, op & 2, op & 1);
8299 tcg_temp_free_i32(tmp2);
8300 tmp64 = tcg_temp_new_i64();
8301 tcg_gen_ext_i32_i64(tmp64, tmp);
8302 tcg_temp_free_i32(tmp);
8303 } else {
8304 /* Signed 64-bit multiply */
8305 tmp64 = gen_muls_i64_i32(tmp, tmp2);
8306 }
8307 }
8308 if (op & 4) {
8309 /* umaal */
8310 gen_addq_lo(s, tmp64, rs);
8311 gen_addq_lo(s, tmp64, rd);
8312 } else if (op & 0x40) {
8313 /* 64-bit accumulate. */
8314 gen_addq(s, tmp64, rs, rd);
8315 }
8316 gen_storeq_reg(s, rs, rd, tmp64);
8317 tcg_temp_free_i64(tmp64);
8318 }
8319 break;
8320 }
8321 break;
8322 case 6: case 7: case 14: case 15:
8323 /* Coprocessor. */
8324 if (((insn >> 24) & 3) == 3) {
8325 /* Translate into the equivalent ARM encoding. */
8326 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
8327 if (disas_neon_data_insn(env, s, insn))
8328 goto illegal_op;
8329 } else {
8330 if (insn & (1 << 28))
8331 goto illegal_op;
8332 if (disas_coproc_insn (env, s, insn))
8333 goto illegal_op;
8334 }
8335 break;
8336 case 8: case 9: case 10: case 11:
8337 if (insn & (1 << 15)) {
8338 /* Branches, misc control. */
8339 if (insn & 0x5000) {
8340 /* Unconditional branch. */
8341 /* signextend(hw1[10:0]) -> offset[:12]. */
8342 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
8343 /* hw1[10:0] -> offset[11:1]. */
8344 offset |= (insn & 0x7ff) << 1;
8345 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8346 offset[24:22] already have the same value because of the
8347 sign extension above. */
8348 offset ^= ((~insn) & (1 << 13)) << 10;
8349 offset ^= ((~insn) & (1 << 11)) << 11;
8350
8351 if (insn & (1 << 14)) {
8352 /* Branch and link. */
8353 tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
8354 }
8355
8356 offset += s->pc;
8357 if (insn & (1 << 12)) {
8358 /* b/bl */
8359 gen_jmp(s, offset);
8360 } else {
8361 /* blx */
8362 offset &= ~(uint32_t)2;
8363 /* thumb2 bx, no need to check */
8364 gen_bx_im(s, offset);
8365 }
8366 } else if (((insn >> 23) & 7) == 7) {
8367 /* Misc control */
8368 if (insn & (1 << 13))
8369 goto illegal_op;
8370
8371 if (insn & (1 << 26)) {
8372 /* Secure monitor call (v6Z) */
8373 goto illegal_op; /* not implemented. */
8374 } else {
8375 op = (insn >> 20) & 7;
8376 switch (op) {
8377 case 0: /* msr cpsr. */
8378 if (IS_M(env)) {
8379 tmp = load_reg(s, rn);
8380 addr = tcg_const_i32(insn & 0xff);
8381 gen_helper_v7m_msr(cpu_env, addr, tmp);
8382 tcg_temp_free_i32(addr);
8383 tcg_temp_free_i32(tmp);
8384 gen_lookup_tb(s);
8385 break;
8386 }
8387 /* fall through */
8388 case 1: /* msr spsr. */
8389 if (IS_M(env))
8390 goto illegal_op;
8391 tmp = load_reg(s, rn);
8392 if (gen_set_psr(s,
8393 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
8394 op == 1, tmp))
8395 goto illegal_op;
8396 break;
8397 case 2: /* cps, nop-hint. */
8398 if (((insn >> 8) & 7) == 0) {
8399 gen_nop_hint(s, insn & 0xff);
8400 }
8401 /* Implemented as NOP in user mode. */
8402 if (IS_USER(s))
8403 break;
8404 offset = 0;
8405 imm = 0;
8406 if (insn & (1 << 10)) {
8407 if (insn & (1 << 7))
8408 offset |= CPSR_A;
8409 if (insn & (1 << 6))
8410 offset |= CPSR_I;
8411 if (insn & (1 << 5))
8412 offset |= CPSR_F;
8413 if (insn & (1 << 9))
8414 imm = CPSR_A | CPSR_I | CPSR_F;
8415 }
8416 if (insn & (1 << 8)) {
8417 offset |= 0x1f;
8418 imm |= (insn & 0x1f);
8419 }
8420 if (offset) {
8421 gen_set_psr_im(s, offset, 0, imm);
8422 }
8423 break;
8424 case 3: /* Special control operations. */
8425 ARCH(7);
8426 op = (insn >> 4) & 0xf;
8427 switch (op) {
8428 case 2: /* clrex */
8429 gen_clrex(s);
8430 break;
8431 case 4: /* dsb */
8432 case 5: /* dmb */
8433 case 6: /* isb */
8434 /* These execute as NOPs. */
8435 break;
8436 default:
8437 goto illegal_op;
8438 }
8439 break;
8440 case 4: /* bxj */
8441 /* Trivial implementation equivalent to bx. */
8442 tmp = load_reg(s, rn);
8443 gen_bx(s, tmp);
8444 break;
8445 case 5: /* Exception return. */
8446 if (IS_USER(s)) {
8447 goto illegal_op;
8448 }
8449 if (rn != 14 || rd != 15) {
8450 goto illegal_op;
8451 }
8452 tmp = load_reg(s, rn);
8453 tcg_gen_subi_i32(tmp, tmp, insn & 0xff);
8454 gen_exception_return(s, tmp);
8455 break;
8456 case 6: /* mrs cpsr. */
8457 tmp = tcg_temp_new_i32();
8458 if (IS_M(env)) {
8459 addr = tcg_const_i32(insn & 0xff);
8460 gen_helper_v7m_mrs(tmp, cpu_env, addr);
8461 tcg_temp_free_i32(addr);
8462 } else {
8463 gen_helper_cpsr_read(tmp);
8464 }
8465 store_reg(s, rd, tmp);
8466 break;
8467 case 7: /* mrs spsr. */
8468 /* Not accessible in user mode. */
8469 if (IS_USER(s) || IS_M(env))
8470 goto illegal_op;
8471 tmp = load_cpu_field(spsr);
8472 store_reg(s, rd, tmp);
8473 break;
8474 }
8475 }
8476 } else {
8477 /* Conditional branch. */
8478 op = (insn >> 22) & 0xf;
8479 /* Generate a conditional jump to next instruction. */
8480 s->condlabel = gen_new_label();
8481 gen_test_cc(op ^ 1, s->condlabel);
8482 s->condjmp = 1;
8483
8484 /* offset[11:1] = insn[10:0] */
8485 offset = (insn & 0x7ff) << 1;
8486 /* offset[17:12] = insn[21:16]. */
8487 offset |= (insn & 0x003f0000) >> 4;
8488 /* offset[31:20] = insn[26]. */
8489 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
8490 /* offset[18] = insn[13]. */
8491 offset |= (insn & (1 << 13)) << 5;
8492 /* offset[19] = insn[11]. */
8493 offset |= (insn & (1 << 11)) << 8;
8494
8495 /* jump to the offset */
8496 gen_jmp(s, s->pc + offset);
8497 }
8498 } else {
8499 /* Data processing immediate. */
8500 if (insn & (1 << 25)) {
8501 if (insn & (1 << 24)) {
8502 if (insn & (1 << 20))
8503 goto illegal_op;
8504 /* Bitfield/Saturate. */
8505 op = (insn >> 21) & 7;
8506 imm = insn & 0x1f;
8507 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
8508 if (rn == 15) {
8509 tmp = tcg_temp_new_i32();
8510 tcg_gen_movi_i32(tmp, 0);
8511 } else {
8512 tmp = load_reg(s, rn);
8513 }
8514 switch (op) {
8515 case 2: /* Signed bitfield extract. */
8516 imm++;
8517 if (shift + imm > 32)
8518 goto illegal_op;
8519 if (imm < 32)
8520 gen_sbfx(tmp, shift, imm);
8521 break;
8522 case 6: /* Unsigned bitfield extract. */
8523 imm++;
8524 if (shift + imm > 32)
8525 goto illegal_op;
8526 if (imm < 32)
8527 gen_ubfx(tmp, shift, (1u << imm) - 1);
8528 break;
8529 case 3: /* Bitfield insert/clear. */
8530 if (imm < shift)
8531 goto illegal_op;
8532 imm = imm + 1 - shift;
8533 if (imm != 32) {
8534 tmp2 = load_reg(s, rd);
8535 gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1);
8536 tcg_temp_free_i32(tmp2);
8537 }
8538 break;
8539 case 7:
8540 goto illegal_op;
8541 default: /* Saturate. */
8542 if (shift) {
8543 if (op & 1)
8544 tcg_gen_sari_i32(tmp, tmp, shift);
8545 else
8546 tcg_gen_shli_i32(tmp, tmp, shift);
8547 }
8548 tmp2 = tcg_const_i32(imm);
8549 if (op & 4) {
8550 /* Unsigned. */
8551 if ((op & 1) && shift == 0)
8552 gen_helper_usat16(tmp, tmp, tmp2);
8553 else
8554 gen_helper_usat(tmp, tmp, tmp2);
8555 } else {
8556 /* Signed. */
8557 if ((op & 1) && shift == 0)
8558 gen_helper_ssat16(tmp, tmp, tmp2);
8559 else
8560 gen_helper_ssat(tmp, tmp, tmp2);
8561 }
8562 tcg_temp_free_i32(tmp2);
8563 break;
8564 }
8565 store_reg(s, rd, tmp);
8566 } else {
8567 imm = ((insn & 0x04000000) >> 15)
8568 | ((insn & 0x7000) >> 4) | (insn & 0xff);
8569 if (insn & (1 << 22)) {
8570 /* 16-bit immediate. */
8571 imm |= (insn >> 4) & 0xf000;
8572 if (insn & (1 << 23)) {
8573 /* movt */
8574 tmp = load_reg(s, rd);
8575 tcg_gen_ext16u_i32(tmp, tmp);
8576 tcg_gen_ori_i32(tmp, tmp, imm << 16);
8577 } else {
8578 /* movw */
8579 tmp = tcg_temp_new_i32();
8580 tcg_gen_movi_i32(tmp, imm);
8581 }
8582 } else {
8583 /* Add/sub 12-bit immediate. */
8584 if (rn == 15) {
8585 offset = s->pc & ~(uint32_t)3;
8586 if (insn & (1 << 23))
8587 offset -= imm;
8588 else
8589 offset += imm;
8590 tmp = tcg_temp_new_i32();
8591 tcg_gen_movi_i32(tmp, offset);
8592 } else {
8593 tmp = load_reg(s, rn);
8594 if (insn & (1 << 23))
8595 tcg_gen_subi_i32(tmp, tmp, imm);
8596 else
8597 tcg_gen_addi_i32(tmp, tmp, imm);
8598 }
8599 }
8600 store_reg(s, rd, tmp);
8601 }
8602 } else {
8603 int shifter_out = 0;
8604 /* modified 12-bit immediate. */
8605 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8606 imm = (insn & 0xff);
8607 switch (shift) {
8608 case 0: /* XY */
8609 /* Nothing to do. */
8610 break;
8611 case 1: /* 00XY00XY */
8612 imm |= imm << 16;
8613 break;
8614 case 2: /* XY00XY00 */
8615 imm |= imm << 16;
8616 imm <<= 8;
8617 break;
8618 case 3: /* XYXYXYXY */
8619 imm |= imm << 16;
8620 imm |= imm << 8;
8621 break;
8622 default: /* Rotated constant. */
8623 shift = (shift << 1) | (imm >> 7);
8624 imm |= 0x80;
8625 imm = imm << (32 - shift);
8626 shifter_out = 1;
8627 break;
8628 }
8629 tmp2 = tcg_temp_new_i32();
8630 tcg_gen_movi_i32(tmp2, imm);
8631 rn = (insn >> 16) & 0xf;
8632 if (rn == 15) {
8633 tmp = tcg_temp_new_i32();
8634 tcg_gen_movi_i32(tmp, 0);
8635 } else {
8636 tmp = load_reg(s, rn);
8637 }
8638 op = (insn >> 21) & 0xf;
8639 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8640 shifter_out, tmp, tmp2))
8641 goto illegal_op;
8642 tcg_temp_free_i32(tmp2);
8643 rd = (insn >> 8) & 0xf;
8644 if (rd != 15) {
8645 store_reg(s, rd, tmp);
8646 } else {
8647 tcg_temp_free_i32(tmp);
8648 }
8649 }
8650 }
8651 break;
8652 case 12: /* Load/store single data item. */
8653 {
8654 int postinc = 0;
8655 int writeback = 0;
8656 int user;
8657 if ((insn & 0x01100000) == 0x01000000) {
8658 if (disas_neon_ls_insn(env, s, insn))
8659 goto illegal_op;
8660 break;
8661 }
8662 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8663 if (rs == 15) {
8664 if (!(insn & (1 << 20))) {
8665 goto illegal_op;
8666 }
8667 if (op != 2) {
8668 /* Byte or halfword load space with dest == r15 : memory hints.
8669 * Catch them early so we don't emit pointless addressing code.
8670 * This space is a mix of:
8671 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8672 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8673 * cores)
8674 * unallocated hints, which must be treated as NOPs
8675 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8676 * which is easiest for the decoding logic
8677 * Some space which must UNDEF
8678 */
8679 int op1 = (insn >> 23) & 3;
8680 int op2 = (insn >> 6) & 0x3f;
8681 if (op & 2) {
8682 goto illegal_op;
8683 }
8684 if (rn == 15) {
8685 /* UNPREDICTABLE or unallocated hint */
8686 return 0;
8687 }
8688 if (op1 & 1) {
8689 return 0; /* PLD* or unallocated hint */
8690 }
8691 if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) {
8692 return 0; /* PLD* or unallocated hint */
8693 }
8694 /* UNDEF space, or an UNPREDICTABLE */
8695 return 1;
8696 }
8697 }
8698 user = IS_USER(s);
8699 if (rn == 15) {
8700 addr = tcg_temp_new_i32();
8701 /* PC relative. */
8702 /* s->pc has already been incremented by 4. */
8703 imm = s->pc & 0xfffffffc;
8704 if (insn & (1 << 23))
8705 imm += insn & 0xfff;
8706 else
8707 imm -= insn & 0xfff;
8708 tcg_gen_movi_i32(addr, imm);
8709 } else {
8710 addr = load_reg(s, rn);
8711 if (insn & (1 << 23)) {
8712 /* Positive offset. */
8713 imm = insn & 0xfff;
8714 tcg_gen_addi_i32(addr, addr, imm);
8715 } else {
8716 imm = insn & 0xff;
8717 switch ((insn >> 8) & 0xf) {
8718 case 0x0: /* Shifted Register. */
8719 shift = (insn >> 4) & 0xf;
8720 if (shift > 3) {
8721 tcg_temp_free_i32(addr);
8722 goto illegal_op;
8723 }
8724 tmp = load_reg(s, rm);
8725 if (shift)
8726 tcg_gen_shli_i32(tmp, tmp, shift);
8727 tcg_gen_add_i32(addr, addr, tmp);
8728 tcg_temp_free_i32(tmp);
8729 break;
8730 case 0xc: /* Negative offset. */
8731 tcg_gen_addi_i32(addr, addr, -imm);
8732 break;
8733 case 0xe: /* User privilege. */
8734 tcg_gen_addi_i32(addr, addr, imm);
8735 user = 1;
8736 break;
8737 case 0x9: /* Post-decrement. */
8738 imm = -imm;
8739 /* Fall through. */
8740 case 0xb: /* Post-increment. */
8741 postinc = 1;
8742 writeback = 1;
8743 break;
8744 case 0xd: /* Pre-decrement. */
8745 imm = -imm;
8746 /* Fall through. */
8747 case 0xf: /* Pre-increment. */
8748 tcg_gen_addi_i32(addr, addr, imm);
8749 writeback = 1;
8750 break;
8751 default:
8752 tcg_temp_free_i32(addr);
8753 goto illegal_op;
8754 }
8755 }
8756 }
8757 if (insn & (1 << 20)) {
8758 /* Load. */
8759 switch (op) {
8760 case 0: tmp = gen_ld8u(addr, user); break;
8761 case 4: tmp = gen_ld8s(addr, user); break;
8762 case 1: tmp = gen_ld16u(addr, user); break;
8763 case 5: tmp = gen_ld16s(addr, user); break;
8764 case 2: tmp = gen_ld32(addr, user); break;
8765 default:
8766 tcg_temp_free_i32(addr);
8767 goto illegal_op;
8768 }
8769 if (rs == 15) {
8770 gen_bx(s, tmp);
8771 } else {
8772 store_reg(s, rs, tmp);
8773 }
8774 } else {
8775 /* Store. */
8776 tmp = load_reg(s, rs);
8777 switch (op) {
8778 case 0: gen_st8(tmp, addr, user); break;
8779 case 1: gen_st16(tmp, addr, user); break;
8780 case 2: gen_st32(tmp, addr, user); break;
8781 default:
8782 tcg_temp_free_i32(addr);
8783 goto illegal_op;
8784 }
8785 }
8786 if (postinc)
8787 tcg_gen_addi_i32(addr, addr, imm);
8788 if (writeback) {
8789 store_reg(s, rn, addr);
8790 } else {
8791 tcg_temp_free_i32(addr);
8792 }
8793 }
8794 break;
8795 default:
8796 goto illegal_op;
8797 }
8798 return 0;
8799 illegal_op:
8800 return 1;
8801 }
8802
8803 static void disas_thumb_insn(CPUState *env, DisasContext *s)
8804 {
8805 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8806 int32_t offset;
8807 int i;
8808 TCGv tmp;
8809 TCGv tmp2;
8810 TCGv addr;
8811
8812 if (s->condexec_mask) {
8813 cond = s->condexec_cond;
8814 if (cond != 0x0e) { /* Skip conditional when condition is AL. */
8815 s->condlabel = gen_new_label();
8816 gen_test_cc(cond ^ 1, s->condlabel);
8817 s->condjmp = 1;
8818 }
8819 }
8820
8821 insn = lduw_code(s->pc);
8822 s->pc += 2;
8823
8824 switch (insn >> 12) {
8825 case 0: case 1:
8826
8827 rd = insn & 7;
8828 op = (insn >> 11) & 3;
8829 if (op == 3) {
8830 /* add/subtract */
8831 rn = (insn >> 3) & 7;
8832 tmp = load_reg(s, rn);
8833 if (insn & (1 << 10)) {
8834 /* immediate */
8835 tmp2 = tcg_temp_new_i32();
8836 tcg_gen_movi_i32(tmp2, (insn >> 6) & 7);
8837 } else {
8838 /* reg */
8839 rm = (insn >> 6) & 7;
8840 tmp2 = load_reg(s, rm);
8841 }
8842 if (insn & (1 << 9)) {
8843 if (s->condexec_mask)
8844 tcg_gen_sub_i32(tmp, tmp, tmp2);
8845 else
8846 gen_helper_sub_cc(tmp, tmp, tmp2);
8847 } else {
8848 if (s->condexec_mask)
8849 tcg_gen_add_i32(tmp, tmp, tmp2);
8850 else
8851 gen_helper_add_cc(tmp, tmp, tmp2);
8852 }
8853 tcg_temp_free_i32(tmp2);
8854 store_reg(s, rd, tmp);
8855 } else {
8856 /* shift immediate */
8857 rm = (insn >> 3) & 7;
8858 shift = (insn >> 6) & 0x1f;
8859 tmp = load_reg(s, rm);
8860 gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);
8861 if (!s->condexec_mask)
8862 gen_logic_CC(tmp);
8863 store_reg(s, rd, tmp);
8864 }
8865 break;
8866 case 2: case 3:
8867 /* arithmetic large immediate */
8868 op = (insn >> 11) & 3;
8869 rd = (insn >> 8) & 0x7;
8870 if (op == 0) { /* mov */
8871 tmp = tcg_temp_new_i32();
8872 tcg_gen_movi_i32(tmp, insn & 0xff);
8873 if (!s->condexec_mask)
8874 gen_logic_CC(tmp);
8875 store_reg(s, rd, tmp);
8876 } else {
8877 tmp = load_reg(s, rd);
8878 tmp2 = tcg_temp_new_i32();
8879 tcg_gen_movi_i32(tmp2, insn & 0xff);
8880 switch (op) {
8881 case 1: /* cmp */
8882 gen_helper_sub_cc(tmp, tmp, tmp2);
8883 tcg_temp_free_i32(tmp);
8884 tcg_temp_free_i32(tmp2);
8885 break;
8886 case 2: /* add */
8887 if (s->condexec_mask)
8888 tcg_gen_add_i32(tmp, tmp, tmp2);
8889 else
8890 gen_helper_add_cc(tmp, tmp, tmp2);
8891 tcg_temp_free_i32(tmp2);
8892 store_reg(s, rd, tmp);
8893 break;
8894 case 3: /* sub */
8895 if (s->condexec_mask)
8896 tcg_gen_sub_i32(tmp, tmp, tmp2);
8897 else
8898 gen_helper_sub_cc(tmp, tmp, tmp2);
8899 tcg_temp_free_i32(tmp2);
8900 store_reg(s, rd, tmp);
8901 break;
8902 }
8903 }
8904 break;
8905 case 4:
8906 if (insn & (1 << 11)) {
8907 rd = (insn >> 8) & 7;
8908 /* load pc-relative. Bit 1 of PC is ignored. */
8909 val = s->pc + 2 + ((insn & 0xff) * 4);
8910 val &= ~(uint32_t)2;
8911 addr = tcg_temp_new_i32();
8912 tcg_gen_movi_i32(addr, val);
8913 tmp = gen_ld32(addr, IS_USER(s));
8914 tcg_temp_free_i32(addr);
8915 store_reg(s, rd, tmp);
8916 break;
8917 }
8918 if (insn & (1 << 10)) {
8919 /* data processing extended or blx */
8920 rd = (insn & 7) | ((insn >> 4) & 8);
8921 rm = (insn >> 3) & 0xf;
8922 op = (insn >> 8) & 3;
8923 switch (op) {
8924 case 0: /* add */
8925 tmp = load_reg(s, rd);
8926 tmp2 = load_reg(s, rm);
8927 tcg_gen_add_i32(tmp, tmp, tmp2);
8928 tcg_temp_free_i32(tmp2);
8929 store_reg(s, rd, tmp);
8930 break;
8931 case 1: /* cmp */
8932 tmp = load_reg(s, rd);
8933 tmp2 = load_reg(s, rm);
8934 gen_helper_sub_cc(tmp, tmp, tmp2);
8935 tcg_temp_free_i32(tmp2);
8936 tcg_temp_free_i32(tmp);
8937 break;
8938 case 2: /* mov/cpy */
8939 tmp = load_reg(s, rm);
8940 store_reg(s, rd, tmp);
8941 break;
8942 case 3:/* branch [and link] exchange thumb register */
8943 tmp = load_reg(s, rm);
8944 if (insn & (1 << 7)) {
8945 ARCH(5);
8946 val = (uint32_t)s->pc | 1;
8947 tmp2 = tcg_temp_new_i32();
8948 tcg_gen_movi_i32(tmp2, val);
8949 store_reg(s, 14, tmp2);
8950 }
8951 /* already thumb, no need to check */
8952 gen_bx(s, tmp);
8953 break;
8954 }
8955 break;
8956 }
8957
8958 /* data processing register */
8959 rd = insn & 7;
8960 rm = (insn >> 3) & 7;
8961 op = (insn >> 6) & 0xf;
8962 if (op == 2 || op == 3 || op == 4 || op == 7) {
8963 /* the shift/rotate ops want the operands backwards */
8964 val = rm;
8965 rm = rd;
8966 rd = val;
8967 val = 1;
8968 } else {
8969 val = 0;
8970 }
8971
8972 if (op == 9) { /* neg */
8973 tmp = tcg_temp_new_i32();
8974 tcg_gen_movi_i32(tmp, 0);
8975 } else if (op != 0xf) { /* mvn doesn't read its first operand */
8976 tmp = load_reg(s, rd);
8977 } else {
8978 TCGV_UNUSED(tmp);
8979 }
8980
8981 tmp2 = load_reg(s, rm);
8982 switch (op) {
8983 case 0x0: /* and */
8984 tcg_gen_and_i32(tmp, tmp, tmp2);
8985 if (!s->condexec_mask)
8986 gen_logic_CC(tmp);
8987 break;
8988 case 0x1: /* eor */
8989 tcg_gen_xor_i32(tmp, tmp, tmp2);
8990 if (!s->condexec_mask)
8991 gen_logic_CC(tmp);
8992 break;
8993 case 0x2: /* lsl */
8994 if (s->condexec_mask) {
8995 gen_helper_shl(tmp2, tmp2, tmp);
8996 } else {
8997 gen_helper_shl_cc(tmp2, tmp2, tmp);
8998 gen_logic_CC(tmp2);
8999 }
9000 break;
9001 case 0x3: /* lsr */
9002 if (s->condexec_mask) {
9003 gen_helper_shr(tmp2, tmp2, tmp);
9004 } else {
9005 gen_helper_shr_cc(tmp2, tmp2, tmp);
9006 gen_logic_CC(tmp2);
9007 }
9008 break;
9009 case 0x4: /* asr */
9010 if (s->condexec_mask) {
9011 gen_helper_sar(tmp2, tmp2, tmp);
9012 } else {
9013 gen_helper_sar_cc(tmp2, tmp2, tmp);
9014 gen_logic_CC(tmp2);
9015 }
9016 break;
9017 case 0x5: /* adc */
9018 if (s->condexec_mask)
9019 gen_adc(tmp, tmp2);
9020 else
9021 gen_helper_adc_cc(tmp, tmp, tmp2);
9022 break;
9023 case 0x6: /* sbc */
9024 if (s->condexec_mask)
9025 gen_sub_carry(tmp, tmp, tmp2);
9026 else
9027 gen_helper_sbc_cc(tmp, tmp, tmp2);
9028 break;
9029 case 0x7: /* ror */
9030 if (s->condexec_mask) {
9031 tcg_gen_andi_i32(tmp, tmp, 0x1f);
9032 tcg_gen_rotr_i32(tmp2, tmp2, tmp);
9033 } else {
9034 gen_helper_ror_cc(tmp2, tmp2, tmp);
9035 gen_logic_CC(tmp2);
9036 }
9037 break;
9038 case 0x8: /* tst */
9039 tcg_gen_and_i32(tmp, tmp, tmp2);
9040 gen_logic_CC(tmp);
9041 rd = 16;
9042 break;
9043 case 0x9: /* neg */
9044 if (s->condexec_mask)
9045 tcg_gen_neg_i32(tmp, tmp2);
9046 else
9047 gen_helper_sub_cc(tmp, tmp, tmp2);
9048 break;
9049 case 0xa: /* cmp */
9050 gen_helper_sub_cc(tmp, tmp, tmp2);
9051 rd = 16;
9052 break;
9053 case 0xb: /* cmn */
9054 gen_helper_add_cc(tmp, tmp, tmp2);
9055 rd = 16;
9056 break;
9057 case 0xc: /* orr */
9058 tcg_gen_or_i32(tmp, tmp, tmp2);
9059 if (!s->condexec_mask)
9060 gen_logic_CC(tmp);
9061 break;
9062 case 0xd: /* mul */
9063 tcg_gen_mul_i32(tmp, tmp, tmp2);
9064 if (!s->condexec_mask)
9065 gen_logic_CC(tmp);
9066 break;
9067 case 0xe: /* bic */
9068 tcg_gen_andc_i32(tmp, tmp, tmp2);
9069 if (!s->condexec_mask)
9070 gen_logic_CC(tmp);
9071 break;
9072 case 0xf: /* mvn */
9073 tcg_gen_not_i32(tmp2, tmp2);
9074 if (!s->condexec_mask)
9075 gen_logic_CC(tmp2);
9076 val = 1;
9077 rm = rd;
9078 break;
9079 }
9080 if (rd != 16) {
9081 if (val) {
9082 store_reg(s, rm, tmp2);
9083 if (op != 0xf)
9084 tcg_temp_free_i32(tmp);
9085 } else {
9086 store_reg(s, rd, tmp);
9087 tcg_temp_free_i32(tmp2);
9088 }
9089 } else {
9090 tcg_temp_free_i32(tmp);
9091 tcg_temp_free_i32(tmp2);
9092 }
9093 break;
9094
9095 case 5:
9096 /* load/store register offset. */
9097 rd = insn & 7;
9098 rn = (insn >> 3) & 7;
9099 rm = (insn >> 6) & 7;
9100 op = (insn >> 9) & 7;
9101 addr = load_reg(s, rn);
9102 tmp = load_reg(s, rm);
9103 tcg_gen_add_i32(addr, addr, tmp);
9104 tcg_temp_free_i32(tmp);
9105
9106 if (op < 3) /* store */
9107 tmp = load_reg(s, rd);
9108
9109 switch (op) {
9110 case 0: /* str */
9111 gen_st32(tmp, addr, IS_USER(s));
9112 break;
9113 case 1: /* strh */
9114 gen_st16(tmp, addr, IS_USER(s));
9115 break;
9116 case 2: /* strb */
9117 gen_st8(tmp, addr, IS_USER(s));
9118 break;
9119 case 3: /* ldrsb */
9120 tmp = gen_ld8s(addr, IS_USER(s));
9121 break;
9122 case 4: /* ldr */
9123 tmp = gen_ld32(addr, IS_USER(s));
9124 break;
9125 case 5: /* ldrh */
9126 tmp = gen_ld16u(addr, IS_USER(s));
9127 break;
9128 case 6: /* ldrb */
9129 tmp = gen_ld8u(addr, IS_USER(s));
9130 break;
9131 case 7: /* ldrsh */
9132 tmp = gen_ld16s(addr, IS_USER(s));
9133 break;
9134 }
9135 if (op >= 3) /* load */
9136 store_reg(s, rd, tmp);
9137 tcg_temp_free_i32(addr);
9138 break;
9139
9140 case 6:
9141 /* load/store word immediate offset */
9142 rd = insn & 7;
9143 rn = (insn >> 3) & 7;
9144 addr = load_reg(s, rn);
9145 val = (insn >> 4) & 0x7c;
9146 tcg_gen_addi_i32(addr, addr, val);
9147
9148 if (insn & (1 << 11)) {
9149 /* load */
9150 tmp = gen_ld32(addr, IS_USER(s));
9151 store_reg(s, rd, tmp);
9152 } else {
9153 /* store */
9154 tmp = load_reg(s, rd);
9155 gen_st32(tmp, addr, IS_USER(s));
9156 }
9157 tcg_temp_free_i32(addr);
9158 break;
9159
9160 case 7:
9161 /* load/store byte immediate offset */
9162 rd = insn & 7;
9163 rn = (insn >> 3) & 7;
9164 addr = load_reg(s, rn);
9165 val = (insn >> 6) & 0x1f;
9166 tcg_gen_addi_i32(addr, addr, val);
9167
9168 if (insn & (1 << 11)) {
9169 /* load */
9170 tmp = gen_ld8u(addr, IS_USER(s));
9171 store_reg(s, rd, tmp);
9172 } else {
9173 /* store */
9174 tmp = load_reg(s, rd);
9175 gen_st8(tmp, addr, IS_USER(s));
9176 }
9177 tcg_temp_free_i32(addr);
9178 break;
9179
9180 case 8:
9181 /* load/store halfword immediate offset */
9182 rd = insn & 7;
9183 rn = (insn >> 3) & 7;
9184 addr = load_reg(s, rn);
9185 val = (insn >> 5) & 0x3e;
9186 tcg_gen_addi_i32(addr, addr, val);
9187
9188 if (insn & (1 << 11)) {
9189 /* load */
9190 tmp = gen_ld16u(addr, IS_USER(s));
9191 store_reg(s, rd, tmp);
9192 } else {
9193 /* store */
9194 tmp = load_reg(s, rd);
9195 gen_st16(tmp, addr, IS_USER(s));
9196 }
9197 tcg_temp_free_i32(addr);
9198 break;
9199
9200 case 9:
9201 /* load/store from stack */
9202 rd = (insn >> 8) & 7;
9203 addr = load_reg(s, 13);
9204 val = (insn & 0xff) * 4;
9205 tcg_gen_addi_i32(addr, addr, val);
9206
9207 if (insn & (1 << 11)) {
9208 /* load */
9209 tmp = gen_ld32(addr, IS_USER(s));
9210 store_reg(s, rd, tmp);
9211 } else {
9212 /* store */
9213 tmp = load_reg(s, rd);
9214 gen_st32(tmp, addr, IS_USER(s));
9215 }
9216 tcg_temp_free_i32(addr);
9217 break;
9218
9219 case 10:
9220 /* add to high reg */
9221 rd = (insn >> 8) & 7;
9222 if (insn & (1 << 11)) {
9223 /* SP */
9224 tmp = load_reg(s, 13);
9225 } else {
9226 /* PC. bit 1 is ignored. */
9227 tmp = tcg_temp_new_i32();
9228 tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
9229 }
9230 val = (insn & 0xff) * 4;
9231 tcg_gen_addi_i32(tmp, tmp, val);
9232 store_reg(s, rd, tmp);
9233 break;
9234
9235 case 11:
9236 /* misc */
9237 op = (insn >> 8) & 0xf;
9238 switch (op) {
9239 case 0:
9240 /* adjust stack pointer */
9241 tmp = load_reg(s, 13);
9242 val = (insn & 0x7f) * 4;
9243 if (insn & (1 << 7))
9244 val = -(int32_t)val;
9245 tcg_gen_addi_i32(tmp, tmp, val);
9246 store_reg(s, 13, tmp);
9247 break;
9248
9249 case 2: /* sign/zero extend. */
9250 ARCH(6);
9251 rd = insn & 7;
9252 rm = (insn >> 3) & 7;
9253 tmp = load_reg(s, rm);
9254 switch ((insn >> 6) & 3) {
9255 case 0: gen_sxth(tmp); break;
9256 case 1: gen_sxtb(tmp); break;
9257 case 2: gen_uxth(tmp); break;
9258 case 3: gen_uxtb(tmp); break;
9259 }
9260 store_reg(s, rd, tmp);
9261 break;
9262 case 4: case 5: case 0xc: case 0xd:
9263 /* push/pop */
9264 addr = load_reg(s, 13);
9265 if (insn & (1 << 8))
9266 offset = 4;
9267 else
9268 offset = 0;
9269 for (i = 0; i < 8; i++) {
9270 if (insn & (1 << i))
9271 offset += 4;
9272 }
9273 if ((insn & (1 << 11)) == 0) {
9274 tcg_gen_addi_i32(addr, addr, -offset);
9275 }
9276 for (i = 0; i < 8; i++) {
9277 if (insn & (1 << i)) {
9278 if (insn & (1 << 11)) {
9279 /* pop */
9280 tmp = gen_ld32(addr, IS_USER(s));
9281 store_reg(s, i, tmp);
9282 } else {
9283 /* push */
9284 tmp = load_reg(s, i);
9285 gen_st32(tmp, addr, IS_USER(s));
9286 }
9287 /* advance to the next address. */
9288 tcg_gen_addi_i32(addr, addr, 4);
9289 }
9290 }
9291 TCGV_UNUSED(tmp);
9292 if (insn & (1 << 8)) {
9293 if (insn & (1 << 11)) {
9294 /* pop pc */
9295 tmp = gen_ld32(addr, IS_USER(s));
9296 /* don't set the pc until the rest of the instruction
9297 has completed */
9298 } else {
9299 /* push lr */
9300 tmp = load_reg(s, 14);
9301 gen_st32(tmp, addr, IS_USER(s));
9302 }
9303 tcg_gen_addi_i32(addr, addr, 4);
9304 }
9305 if ((insn & (1 << 11)) == 0) {
9306 tcg_gen_addi_i32(addr, addr, -offset);
9307 }
9308 /* write back the new stack pointer */
9309 store_reg(s, 13, addr);
9310 /* set the new PC value */
9311 if ((insn & 0x0900) == 0x0900) {
9312 store_reg_from_load(env, s, 15, tmp);
9313 }
9314 break;
9315
9316 case 1: case 3: case 9: case 11: /* czb */
9317 rm = insn & 7;
9318 tmp = load_reg(s, rm);
9319 s->condlabel = gen_new_label();
9320 s->condjmp = 1;
9321 if (insn & (1 << 11))
9322 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel);
9323 else
9324 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
9325 tcg_temp_free_i32(tmp);
9326 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
9327 val = (uint32_t)s->pc + 2;
9328 val += offset;
9329 gen_jmp(s, val);
9330 break;
9331
9332 case 15: /* IT, nop-hint. */
9333 if ((insn & 0xf) == 0) {
9334 gen_nop_hint(s, (insn >> 4) & 0xf);
9335 break;
9336 }
9337 /* If Then. */
9338 s->condexec_cond = (insn >> 4) & 0xe;
9339 s->condexec_mask = insn & 0x1f;
9340 /* No actual code generated for this insn, just setup state. */
9341 break;
9342
9343 case 0xe: /* bkpt */
9344 ARCH(5);
9345 gen_exception_insn(s, 2, EXCP_BKPT);
9346 break;
9347
9348 case 0xa: /* rev */
9349 ARCH(6);
9350 rn = (insn >> 3) & 0x7;
9351 rd = insn & 0x7;
9352 tmp = load_reg(s, rn);
9353 switch ((insn >> 6) & 3) {
9354 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
9355 case 1: gen_rev16(tmp); break;
9356 case 3: gen_revsh(tmp); break;
9357 default: goto illegal_op;
9358 }
9359 store_reg(s, rd, tmp);
9360 break;
9361
9362 case 6: /* cps */
9363 ARCH(6);
9364 if (IS_USER(s))
9365 break;
9366 if (IS_M(env)) {
9367 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
9368 /* PRIMASK */
9369 if (insn & 1) {
9370 addr = tcg_const_i32(16);
9371 gen_helper_v7m_msr(cpu_env, addr, tmp);
9372 tcg_temp_free_i32(addr);
9373 }
9374 /* FAULTMASK */
9375 if (insn & 2) {
9376 addr = tcg_const_i32(17);
9377 gen_helper_v7m_msr(cpu_env, addr, tmp);
9378 tcg_temp_free_i32(addr);
9379 }
9380 tcg_temp_free_i32(tmp);
9381 gen_lookup_tb(s);
9382 } else {
9383 if (insn & (1 << 4))
9384 shift = CPSR_A | CPSR_I | CPSR_F;
9385 else
9386 shift = 0;
9387 gen_set_psr_im(s, ((insn & 7) << 6), 0, shift);
9388 }
9389 break;
9390
9391 default:
9392 goto undef;
9393 }
9394 break;
9395
9396 case 12:
9397 /* load/store multiple */
9398 rn = (insn >> 8) & 0x7;
9399 addr = load_reg(s, rn);
9400 for (i = 0; i < 8; i++) {
9401 if (insn & (1 << i)) {
9402 if (insn & (1 << 11)) {
9403 /* load */
9404 tmp = gen_ld32(addr, IS_USER(s));
9405 store_reg(s, i, tmp);
9406 } else {
9407 /* store */
9408 tmp = load_reg(s, i);
9409 gen_st32(tmp, addr, IS_USER(s));
9410 }
9411 /* advance to the next address */
9412 tcg_gen_addi_i32(addr, addr, 4);
9413 }
9414 }
9415 /* Base register writeback. */
9416 if ((insn & (1 << rn)) == 0) {
9417 store_reg(s, rn, addr);
9418 } else {
9419 tcg_temp_free_i32(addr);
9420 }
9421 break;
9422
9423 case 13:
9424 /* conditional branch or swi */
9425 cond = (insn >> 8) & 0xf;
9426 if (cond == 0xe)
9427 goto undef;
9428
9429 if (cond == 0xf) {
9430 /* swi */
9431 gen_set_pc_im(s->pc);
9432 s->is_jmp = DISAS_SWI;
9433 break;
9434 }
9435 /* generate a conditional jump to next instruction */
9436 s->condlabel = gen_new_label();
9437 gen_test_cc(cond ^ 1, s->condlabel);
9438 s->condjmp = 1;
9439
9440 /* jump to the offset */
9441 val = (uint32_t)s->pc + 2;
9442 offset = ((int32_t)insn << 24) >> 24;
9443 val += offset << 1;
9444 gen_jmp(s, val);
9445 break;
9446
9447 case 14:
9448 if (insn & (1 << 11)) {
9449 if (disas_thumb2_insn(env, s, insn))
9450 goto undef32;
9451 break;
9452 }
9453 /* unconditional branch */
9454 val = (uint32_t)s->pc;
9455 offset = ((int32_t)insn << 21) >> 21;
9456 val += (offset << 1) + 2;
9457 gen_jmp(s, val);
9458 break;
9459
9460 case 15:
9461 if (disas_thumb2_insn(env, s, insn))
9462 goto undef32;
9463 break;
9464 }
9465 return;
9466 undef32:
9467 gen_exception_insn(s, 4, EXCP_UDEF);
9468 return;
9469 illegal_op:
9470 undef:
9471 gen_exception_insn(s, 2, EXCP_UDEF);
9472 }
9473
9474 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9475 basic block 'tb'. If search_pc is TRUE, also generate PC
9476 information for each intermediate instruction. */
9477 static inline void gen_intermediate_code_internal(CPUState *env,
9478 TranslationBlock *tb,
9479 int search_pc)
9480 {
9481 DisasContext dc1, *dc = &dc1;
9482 CPUBreakpoint *bp;
9483 uint16_t *gen_opc_end;
9484 int j, lj;
9485 target_ulong pc_start;
9486 uint32_t next_page_start;
9487 int num_insns;
9488 int max_insns;
9489
9490 /* generate intermediate code */
9491 pc_start = tb->pc;
9492
9493 dc->tb = tb;
9494
9495 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
9496
9497 dc->is_jmp = DISAS_NEXT;
9498 dc->pc = pc_start;
9499 dc->singlestep_enabled = env->singlestep_enabled;
9500 dc->condjmp = 0;
9501 dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
9502 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9503 dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
9504 #if !defined(CONFIG_USER_ONLY)
9505 dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
9506 #endif
9507 dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
9508 dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
9509 dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
9510 cpu_F0s = tcg_temp_new_i32();
9511 cpu_F1s = tcg_temp_new_i32();
9512 cpu_F0d = tcg_temp_new_i64();
9513 cpu_F1d = tcg_temp_new_i64();
9514 cpu_V0 = cpu_F0d;
9515 cpu_V1 = cpu_F1d;
9516 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9517 cpu_M0 = tcg_temp_new_i64();
9518 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
9519 lj = -1;
9520 num_insns = 0;
9521 max_insns = tb->cflags & CF_COUNT_MASK;
9522 if (max_insns == 0)
9523 max_insns = CF_COUNT_MASK;
9524
9525 gen_icount_start();
9526
9527 tcg_clear_temp_count();
9528
9529 /* A note on handling of the condexec (IT) bits:
9530 *
9531 * We want to avoid the overhead of having to write the updated condexec
9532 * bits back to the CPUState for every instruction in an IT block. So:
9533 * (1) if the condexec bits are not already zero then we write
9534 * zero back into the CPUState now. This avoids complications trying
9535 * to do it at the end of the block. (For example if we don't do this
9536 * it's hard to identify whether we can safely skip writing condexec
9537 * at the end of the TB, which we definitely want to do for the case
9538 * where a TB doesn't do anything with the IT state at all.)
9539 * (2) if we are going to leave the TB then we call gen_set_condexec()
9540 * which will write the correct value into CPUState if zero is wrong.
9541 * This is done both for leaving the TB at the end, and for leaving
9542 * it because of an exception we know will happen, which is done in
9543 * gen_exception_insn(). The latter is necessary because we need to
9544 * leave the TB with the PC/IT state just prior to execution of the
9545 * instruction which caused the exception.
9546 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9547 * then the CPUState will be wrong and we need to reset it.
9548 * This is handled in the same way as restoration of the
9549 * PC in these situations: we will be called again with search_pc=1
9550 * and generate a mapping of the condexec bits for each PC in
9551 * gen_opc_condexec_bits[]. gen_pc_load[] then uses this to restore
9552 * the condexec bits.
9553 *
9554 * Note that there are no instructions which can read the condexec
9555 * bits, and none which can write non-static values to them, so
9556 * we don't need to care about whether CPUState is correct in the
9557 * middle of a TB.
9558 */
9559
9560 /* Reset the conditional execution bits immediately. This avoids
9561 complications trying to do it at the end of the block. */
9562 if (dc->condexec_mask || dc->condexec_cond)
9563 {
9564 TCGv tmp = tcg_temp_new_i32();
9565 tcg_gen_movi_i32(tmp, 0);
9566 store_cpu_field(tmp, condexec_bits);
9567 }
9568 do {
9569 #ifdef CONFIG_USER_ONLY
9570 /* Intercept jump to the magic kernel page. */
9571 if (dc->pc >= 0xffff0000) {
9572 /* We always get here via a jump, so know we are not in a
9573 conditional execution block. */
9574 gen_exception(EXCP_KERNEL_TRAP);
9575 dc->is_jmp = DISAS_UPDATE;
9576 break;
9577 }
9578 #else
9579 if (dc->pc >= 0xfffffff0 && IS_M(env)) {
9580 /* We always get here via a jump, so know we are not in a
9581 conditional execution block. */
9582 gen_exception(EXCP_EXCEPTION_EXIT);
9583 dc->is_jmp = DISAS_UPDATE;
9584 break;
9585 }
9586 #endif
9587
9588 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9589 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9590 if (bp->pc == dc->pc) {
9591 gen_exception_insn(dc, 0, EXCP_DEBUG);
9592 /* Advance PC so that clearing the breakpoint will
9593 invalidate this TB. */
9594 dc->pc += 2;
9595 goto done_generating;
9596 break;
9597 }
9598 }
9599 }
9600 if (search_pc) {
9601 j = gen_opc_ptr - gen_opc_buf;
9602 if (lj < j) {
9603 lj++;
9604 while (lj < j)
9605 gen_opc_instr_start[lj++] = 0;
9606 }
9607 gen_opc_pc[lj] = dc->pc;
9608 gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1);
9609 gen_opc_instr_start[lj] = 1;
9610 gen_opc_icount[lj] = num_insns;
9611 }
9612
9613 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9614 gen_io_start();
9615
9616 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
9617 tcg_gen_debug_insn_start(dc->pc);
9618 }
9619
9620 if (dc->thumb) {
9621 disas_thumb_insn(env, dc);
9622 if (dc->condexec_mask) {
9623 dc->condexec_cond = (dc->condexec_cond & 0xe)
9624 | ((dc->condexec_mask >> 4) & 1);
9625 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f;
9626 if (dc->condexec_mask == 0) {
9627 dc->condexec_cond = 0;
9628 }
9629 }
9630 } else {
9631 disas_arm_insn(env, dc);
9632 }
9633
9634 if (dc->condjmp && !dc->is_jmp) {
9635 gen_set_label(dc->condlabel);
9636 dc->condjmp = 0;
9637 }
9638
9639 if (tcg_check_temp_count()) {
9640 fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc);
9641 }
9642
9643 /* Translation stops when a conditional branch is encountered.
9644 * Otherwise the subsequent code could get translated several times.
9645 * Also stop translation when a page boundary is reached. This
9646 * ensures prefetch aborts occur at the right place. */
9647 num_insns ++;
9648 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
9649 !env->singlestep_enabled &&
9650 !singlestep &&
9651 dc->pc < next_page_start &&
9652 num_insns < max_insns);
9653
9654 if (tb->cflags & CF_LAST_IO) {
9655 if (dc->condjmp) {
9656 /* FIXME: This can theoretically happen with self-modifying
9657 code. */
9658 cpu_abort(env, "IO on conditional branch instruction");
9659 }
9660 gen_io_end();
9661 }
9662
9663 /* At this stage dc->condjmp will only be set when the skipped
9664 instruction was a conditional branch or trap, and the PC has
9665 already been written. */
9666 if (unlikely(env->singlestep_enabled)) {
9667 /* Make sure the pc is updated, and raise a debug exception. */
9668 if (dc->condjmp) {
9669 gen_set_condexec(dc);
9670 if (dc->is_jmp == DISAS_SWI) {
9671 gen_exception(EXCP_SWI);
9672 } else {
9673 gen_exception(EXCP_DEBUG);
9674 }
9675 gen_set_label(dc->condlabel);
9676 }
9677 if (dc->condjmp || !dc->is_jmp) {
9678 gen_set_pc_im(dc->pc);
9679 dc->condjmp = 0;
9680 }
9681 gen_set_condexec(dc);
9682 if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
9683 gen_exception(EXCP_SWI);
9684 } else {
9685 /* FIXME: Single stepping a WFI insn will not halt
9686 the CPU. */
9687 gen_exception(EXCP_DEBUG);
9688 }
9689 } else {
9690 /* While branches must always occur at the end of an IT block,
9691 there are a few other things that can cause us to terminate
9692 the TB in the middel of an IT block:
9693 - Exception generating instructions (bkpt, swi, undefined).
9694 - Page boundaries.
9695 - Hardware watchpoints.
9696 Hardware breakpoints have already been handled and skip this code.
9697 */
9698 gen_set_condexec(dc);
9699 switch(dc->is_jmp) {
9700 case DISAS_NEXT:
9701 gen_goto_tb(dc, 1, dc->pc);
9702 break;
9703 default:
9704 case DISAS_JUMP:
9705 case DISAS_UPDATE:
9706 /* indicate that the hash table must be used to find the next TB */
9707 tcg_gen_exit_tb(0);
9708 break;
9709 case DISAS_TB_JUMP:
9710 /* nothing more to generate */
9711 break;
9712 case DISAS_WFI:
9713 gen_helper_wfi();
9714 break;
9715 case DISAS_SWI:
9716 gen_exception(EXCP_SWI);
9717 break;
9718 }
9719 if (dc->condjmp) {
9720 gen_set_label(dc->condlabel);
9721 gen_set_condexec(dc);
9722 gen_goto_tb(dc, 1, dc->pc);
9723 dc->condjmp = 0;
9724 }
9725 }
9726
9727 done_generating:
9728 gen_icount_end(tb, num_insns);
9729 *gen_opc_ptr = INDEX_op_end;
9730
9731 #ifdef DEBUG_DISAS
9732 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9733 qemu_log("----------------\n");
9734 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9735 log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
9736 qemu_log("\n");
9737 }
9738 #endif
9739 if (search_pc) {
9740 j = gen_opc_ptr - gen_opc_buf;
9741 lj++;
9742 while (lj <= j)
9743 gen_opc_instr_start[lj++] = 0;
9744 } else {
9745 tb->size = dc->pc - pc_start;
9746 tb->icount = num_insns;
9747 }
9748 }
9749
9750 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
9751 {
9752 gen_intermediate_code_internal(env, tb, 0);
9753 }
9754
9755 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
9756 {
9757 gen_intermediate_code_internal(env, tb, 1);
9758 }
9759
9760 static const char *cpu_mode_names[16] = {
9761 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9762 "???", "???", "???", "und", "???", "???", "???", "sys"
9763 };
9764
9765 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
9766 int flags)
9767 {
9768 int i;
9769 #if 0
9770 union {
9771 uint32_t i;
9772 float s;
9773 } s0, s1;
9774 CPU_DoubleU d;
9775 /* ??? This assumes float64 and double have the same layout.
9776 Oh well, it's only debug dumps. */
9777 union {
9778 float64 f64;
9779 double d;
9780 } d0;
9781 #endif
9782 uint32_t psr;
9783
9784 for(i=0;i<16;i++) {
9785 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
9786 if ((i % 4) == 3)
9787 cpu_fprintf(f, "\n");
9788 else
9789 cpu_fprintf(f, " ");
9790 }
9791 psr = cpsr_read(env);
9792 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
9793 psr,
9794 psr & (1 << 31) ? 'N' : '-',
9795 psr & (1 << 30) ? 'Z' : '-',
9796 psr & (1 << 29) ? 'C' : '-',
9797 psr & (1 << 28) ? 'V' : '-',
9798 psr & CPSR_T ? 'T' : 'A',
9799 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
9800
9801 #if 0
9802 for (i = 0; i < 16; i++) {
9803 d.d = env->vfp.regs[i];
9804 s0.i = d.l.lower;
9805 s1.i = d.l.upper;
9806 d0.f64 = d.d;
9807 cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9808 i * 2, (int)s0.i, s0.s,
9809 i * 2 + 1, (int)s1.i, s1.s,
9810 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
9811 d0.d);
9812 }
9813 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
9814 #endif
9815 }
9816
9817 void gen_pc_load(CPUState *env, TranslationBlock *tb,
9818 unsigned long searched_pc, int pc_pos, void *puc)
9819 {
9820 env->regs[15] = gen_opc_pc[pc_pos];
9821 env->condexec_bits = gen_opc_condexec_bits[pc_pos];
9822 }
QEmu