2 * ARM translation: AArch32 VFP instructions
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 * Copyright (c) 2019 Linaro, Ltd.
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "tcg/tcg-op.h"
25 #include "tcg/tcg-op-gvec.h"
26 #include "exec/exec-all.h"
27 #include "exec/gen-icount.h"
28 #include "translate.h"
29 #include "translate-a32.h"
31 /* Include the generated VFP decoder */
32 #include "decode-vfp.c.inc"
33 #include "decode-vfp-uncond.c.inc"
35 static inline void vfp_load_reg64(TCGv_i64 var
, int reg
)
37 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(true, reg
));
40 static inline void vfp_store_reg64(TCGv_i64 var
, int reg
)
42 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(true, reg
));
45 static inline void vfp_load_reg32(TCGv_i32 var
, int reg
)
47 tcg_gen_ld_i32(var
, cpu_env
, vfp_reg_offset(false, reg
));
50 static inline void vfp_store_reg32(TCGv_i32 var
, int reg
)
52 tcg_gen_st_i32(var
, cpu_env
, vfp_reg_offset(false, reg
));
56 * The imm8 encodes the sign bit, enough bits to represent an exponent in
57 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
58 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
60 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
66 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
67 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
68 extract32(imm8
, 0, 6);
72 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
73 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
74 (extract32(imm8
, 0, 6) << 3);
78 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
79 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
80 (extract32(imm8
, 0, 6) << 6);
83 g_assert_not_reached();
89 * Return the offset of a 16-bit half of the specified VFP single-precision
90 * register. If top is true, returns the top 16 bits; otherwise the bottom
93 static inline long vfp_f16_offset(unsigned reg
, bool top
)
95 long offs
= vfp_reg_offset(false, reg
);
96 #ifdef HOST_WORDS_BIGENDIAN
109 * Generate code for M-profile lazy FP state preservation if needed;
110 * this corresponds to the pseudocode PreserveFPState() function.
112 static void gen_preserve_fp_state(DisasContext
*s
, bool skip_context_update
)
116 * Lazy state saving affects external memory and also the NVIC,
117 * so we must mark it as an IO operation for icount (and cause
118 * this to be the last insn in the TB).
120 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
121 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
124 gen_helper_v7m_preserve_fp_state(cpu_env
);
126 * If the preserve_fp_state helper doesn't throw an exception
127 * then it will clear LSPACT; we don't need to repeat this for
128 * any further FP insns in this TB.
130 s
->v7m_lspact
= false;
132 * The helper might have zeroed VPR, so we do not know the
133 * correct value for the MVE_NO_PRED TB flag any more.
134 * If we're about to create a new fp context then that
135 * will precisely determine the MVE_NO_PRED value (see
136 * gen_update_fp_context()). Otherwise, we must:
137 * - set s->mve_no_pred to false, so this instruction
138 * is generated to use helper functions
139 * - end the TB now, without chaining to the next TB
141 if (skip_context_update
|| !s
->v7m_new_fp_ctxt_needed
) {
142 s
->mve_no_pred
= false;
143 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
149 * Generate code for M-profile FP context handling: update the
150 * ownership of the FP context, and create a new context if
151 * necessary. This corresponds to the parts of the pseudocode
152 * ExecuteFPCheck() after the inital PreserveFPState() call.
154 static void gen_update_fp_context(DisasContext
*s
)
156 /* Update ownership of FP context: set FPCCR.S to match current state */
157 if (s
->v8m_fpccr_s_wrong
) {
160 tmp
= load_cpu_field(v7m
.fpccr
[M_REG_S
]);
162 tcg_gen_ori_i32(tmp
, tmp
, R_V7M_FPCCR_S_MASK
);
164 tcg_gen_andi_i32(tmp
, tmp
, ~R_V7M_FPCCR_S_MASK
);
166 store_cpu_field(tmp
, v7m
.fpccr
[M_REG_S
]);
167 /* Don't need to do this for any further FP insns in this TB */
168 s
->v8m_fpccr_s_wrong
= false;
171 if (s
->v7m_new_fp_ctxt_needed
) {
173 * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA,
174 * the FPSCR, and VPR.
176 TCGv_i32 control
, fpscr
;
177 uint32_t bits
= R_V7M_CONTROL_FPCA_MASK
;
179 fpscr
= load_cpu_field(v7m
.fpdscr
[s
->v8m_secure
]);
180 gen_helper_vfp_set_fpscr(cpu_env
, fpscr
);
181 tcg_temp_free_i32(fpscr
);
182 if (dc_isar_feature(aa32_mve
, s
)) {
183 TCGv_i32 z32
= tcg_const_i32(0);
184 store_cpu_field(z32
, v7m
.vpr
);
187 * We just updated the FPSCR and VPR. Some of this state is cached
188 * in the MVE_NO_PRED TB flag. We want to avoid having to end the
189 * TB here, which means we need the new value of the MVE_NO_PRED
190 * flag to be exactly known here and the same for all executions.
191 * Luckily FPDSCR.LTPSIZE is always constant 4 and the VPR is
192 * always set to 0, so the new MVE_NO_PRED flag is always 1
193 * if and only if we have MVE.
195 * (The other FPSCR state cached in TB flags is VECLEN and VECSTRIDE,
196 * but those do not exist for M-profile, so are not relevant here.)
198 s
->mve_no_pred
= dc_isar_feature(aa32_mve
, s
);
201 bits
|= R_V7M_CONTROL_SFPA_MASK
;
203 control
= load_cpu_field(v7m
.control
[M_REG_S
]);
204 tcg_gen_ori_i32(control
, control
, bits
);
205 store_cpu_field(control
, v7m
.control
[M_REG_S
]);
206 /* Don't need to do this for any further FP insns in this TB */
207 s
->v7m_new_fp_ctxt_needed
= false;
212 * Check that VFP access is enabled, A-profile specific version.
214 * If VFP is enabled, return true. If not, emit code to generate an
215 * appropriate exception and return false.
216 * The ignore_vfp_enabled argument specifies that we should ignore
217 * whether VFP is enabled via FPEXC.EN: this should be true for FMXR/FMRX
218 * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns.
220 static bool vfp_access_check_a(DisasContext
*s
, bool ignore_vfp_enabled
)
223 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
224 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
228 if (!s
->vfp_enabled
&& !ignore_vfp_enabled
) {
229 assert(!arm_dc_feature(s
, ARM_FEATURE_M
));
230 unallocated_encoding(s
);
237 * Check that VFP access is enabled, M-profile specific version.
239 * If VFP is enabled, do the necessary M-profile lazy-FP handling and then
240 * return true. If not, emit code to generate an appropriate exception and
242 * skip_context_update is true to skip the "update FP context" part of this.
244 bool vfp_access_check_m(DisasContext
*s
, bool skip_context_update
)
248 * M-profile mostly catches the "FPU disabled" case early, in
249 * disas_m_nocp(), but a few insns (eg LCTP, WLSTP, DLSTP)
250 * which do coprocessor-checks are outside the large ranges of
251 * the encoding space handled by the patterns in m-nocp.decode,
252 * and for them we may need to raise NOCP here.
254 gen_exception_insn(s
, s
->pc_curr
, EXCP_NOCP
,
255 syn_uncategorized(), s
->fp_excp_el
);
259 /* Handle M-profile lazy FP state mechanics */
261 /* Trigger lazy-state preservation if necessary */
262 gen_preserve_fp_state(s
, skip_context_update
);
264 if (!skip_context_update
) {
265 /* Update ownership of FP context and create new FP context if needed */
266 gen_update_fp_context(s
);
273 * The most usual kind of VFP access check, for everything except
274 * FMXR/FMRX to the always-available special registers.
276 bool vfp_access_check(DisasContext
*s
)
278 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
279 return vfp_access_check_m(s
, false);
281 return vfp_access_check_a(s
, false);
285 static bool trans_VSEL(DisasContext
*s
, arg_VSEL
*a
)
290 if (!dc_isar_feature(aa32_vsel
, s
)) {
294 if (sz
== 3 && !dc_isar_feature(aa32_fpdp_v2
, s
)) {
298 if (sz
== 1 && !dc_isar_feature(aa32_fp16_arith
, s
)) {
302 /* UNDEF accesses to D16-D31 if they don't exist */
303 if (sz
== 3 && !dc_isar_feature(aa32_simd_r32
, s
) &&
304 ((a
->vm
| a
->vn
| a
->vd
) & 0x10)) {
312 if (!vfp_access_check(s
)) {
317 TCGv_i64 frn
, frm
, dest
;
318 TCGv_i64 tmp
, zero
, zf
, nf
, vf
;
320 zero
= tcg_const_i64(0);
322 frn
= tcg_temp_new_i64();
323 frm
= tcg_temp_new_i64();
324 dest
= tcg_temp_new_i64();
326 zf
= tcg_temp_new_i64();
327 nf
= tcg_temp_new_i64();
328 vf
= tcg_temp_new_i64();
330 tcg_gen_extu_i32_i64(zf
, cpu_ZF
);
331 tcg_gen_ext_i32_i64(nf
, cpu_NF
);
332 tcg_gen_ext_i32_i64(vf
, cpu_VF
);
334 vfp_load_reg64(frn
, rn
);
335 vfp_load_reg64(frm
, rm
);
338 tcg_gen_movcond_i64(TCG_COND_EQ
, dest
, zf
, zero
,
342 tcg_gen_movcond_i64(TCG_COND_LT
, dest
, vf
, zero
,
345 case 2: /* ge: N == V -> N ^ V == 0 */
346 tmp
= tcg_temp_new_i64();
347 tcg_gen_xor_i64(tmp
, vf
, nf
);
348 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
350 tcg_temp_free_i64(tmp
);
352 case 3: /* gt: !Z && N == V */
353 tcg_gen_movcond_i64(TCG_COND_NE
, dest
, zf
, zero
,
355 tmp
= tcg_temp_new_i64();
356 tcg_gen_xor_i64(tmp
, vf
, nf
);
357 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
359 tcg_temp_free_i64(tmp
);
362 vfp_store_reg64(dest
, rd
);
363 tcg_temp_free_i64(frn
);
364 tcg_temp_free_i64(frm
);
365 tcg_temp_free_i64(dest
);
367 tcg_temp_free_i64(zf
);
368 tcg_temp_free_i64(nf
);
369 tcg_temp_free_i64(vf
);
371 tcg_temp_free_i64(zero
);
373 TCGv_i32 frn
, frm
, dest
;
376 zero
= tcg_const_i32(0);
378 frn
= tcg_temp_new_i32();
379 frm
= tcg_temp_new_i32();
380 dest
= tcg_temp_new_i32();
381 vfp_load_reg32(frn
, rn
);
382 vfp_load_reg32(frm
, rm
);
385 tcg_gen_movcond_i32(TCG_COND_EQ
, dest
, cpu_ZF
, zero
,
389 tcg_gen_movcond_i32(TCG_COND_LT
, dest
, cpu_VF
, zero
,
392 case 2: /* ge: N == V -> N ^ V == 0 */
393 tmp
= tcg_temp_new_i32();
394 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
395 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
397 tcg_temp_free_i32(tmp
);
399 case 3: /* gt: !Z && N == V */
400 tcg_gen_movcond_i32(TCG_COND_NE
, dest
, cpu_ZF
, zero
,
402 tmp
= tcg_temp_new_i32();
403 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
404 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
406 tcg_temp_free_i32(tmp
);
409 /* For fp16 the top half is always zeroes */
411 tcg_gen_andi_i32(dest
, dest
, 0xffff);
413 vfp_store_reg32(dest
, rd
);
414 tcg_temp_free_i32(frn
);
415 tcg_temp_free_i32(frm
);
416 tcg_temp_free_i32(dest
);
418 tcg_temp_free_i32(zero
);
425 * Table for converting the most common AArch32 encoding of
426 * rounding mode to arm_fprounding order (which matches the
427 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
429 static const uint8_t fp_decode_rm
[] = {
436 static bool trans_VRINT(DisasContext
*s
, arg_VRINT
*a
)
442 int rounding
= fp_decode_rm
[a
->rm
];
444 if (!dc_isar_feature(aa32_vrint
, s
)) {
448 if (sz
== 3 && !dc_isar_feature(aa32_fpdp_v2
, s
)) {
452 if (sz
== 1 && !dc_isar_feature(aa32_fp16_arith
, s
)) {
456 /* UNDEF accesses to D16-D31 if they don't exist */
457 if (sz
== 3 && !dc_isar_feature(aa32_simd_r32
, s
) &&
458 ((a
->vm
| a
->vd
) & 0x10)) {
465 if (!vfp_access_check(s
)) {
470 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
472 fpst
= fpstatus_ptr(FPST_FPCR
);
475 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
476 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
481 tcg_op
= tcg_temp_new_i64();
482 tcg_res
= tcg_temp_new_i64();
483 vfp_load_reg64(tcg_op
, rm
);
484 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
485 vfp_store_reg64(tcg_res
, rd
);
486 tcg_temp_free_i64(tcg_op
);
487 tcg_temp_free_i64(tcg_res
);
491 tcg_op
= tcg_temp_new_i32();
492 tcg_res
= tcg_temp_new_i32();
493 vfp_load_reg32(tcg_op
, rm
);
495 gen_helper_rinth(tcg_res
, tcg_op
, fpst
);
497 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
499 vfp_store_reg32(tcg_res
, rd
);
500 tcg_temp_free_i32(tcg_op
);
501 tcg_temp_free_i32(tcg_res
);
504 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
505 tcg_temp_free_i32(tcg_rmode
);
507 tcg_temp_free_ptr(fpst
);
511 static bool trans_VCVT(DisasContext
*s
, arg_VCVT
*a
)
516 TCGv_i32 tcg_rmode
, tcg_shift
;
517 int rounding
= fp_decode_rm
[a
->rm
];
518 bool is_signed
= a
->op
;
520 if (!dc_isar_feature(aa32_vcvt_dr
, s
)) {
524 if (sz
== 3 && !dc_isar_feature(aa32_fpdp_v2
, s
)) {
528 if (sz
== 1 && !dc_isar_feature(aa32_fp16_arith
, s
)) {
532 /* UNDEF accesses to D16-D31 if they don't exist */
533 if (sz
== 3 && !dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
540 if (!vfp_access_check(s
)) {
545 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
547 fpst
= fpstatus_ptr(FPST_FPCR
);
550 tcg_shift
= tcg_const_i32(0);
552 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
553 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
556 TCGv_i64 tcg_double
, tcg_res
;
558 tcg_double
= tcg_temp_new_i64();
559 tcg_res
= tcg_temp_new_i64();
560 tcg_tmp
= tcg_temp_new_i32();
561 vfp_load_reg64(tcg_double
, rm
);
563 gen_helper_vfp_tosld(tcg_res
, tcg_double
, tcg_shift
, fpst
);
565 gen_helper_vfp_tould(tcg_res
, tcg_double
, tcg_shift
, fpst
);
567 tcg_gen_extrl_i64_i32(tcg_tmp
, tcg_res
);
568 vfp_store_reg32(tcg_tmp
, rd
);
569 tcg_temp_free_i32(tcg_tmp
);
570 tcg_temp_free_i64(tcg_res
);
571 tcg_temp_free_i64(tcg_double
);
573 TCGv_i32 tcg_single
, tcg_res
;
574 tcg_single
= tcg_temp_new_i32();
575 tcg_res
= tcg_temp_new_i32();
576 vfp_load_reg32(tcg_single
, rm
);
579 gen_helper_vfp_toslh(tcg_res
, tcg_single
, tcg_shift
, fpst
);
581 gen_helper_vfp_toulh(tcg_res
, tcg_single
, tcg_shift
, fpst
);
585 gen_helper_vfp_tosls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
587 gen_helper_vfp_touls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
590 vfp_store_reg32(tcg_res
, rd
);
591 tcg_temp_free_i32(tcg_res
);
592 tcg_temp_free_i32(tcg_single
);
595 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
596 tcg_temp_free_i32(tcg_rmode
);
598 tcg_temp_free_i32(tcg_shift
);
600 tcg_temp_free_ptr(fpst
);
605 bool mve_skip_vmov(DisasContext
*s
, int vn
, int index
, int size
)
608 * In a CPU with MVE, the VMOV (vector lane to general-purpose register)
609 * and VMOV (general-purpose register to vector lane) insns are not
610 * predicated, but they are subject to beatwise execution if they are
611 * not in an IT block.
613 * Since our implementation always executes all 4 beats in one tick,
614 * this means only that if PSR.ECI says we should not be executing
615 * the beat corresponding to the lane of the vector register being
616 * accessed then we should skip performing the move, and that we need
617 * to do the usual check for bad ECI state and advance of ECI state.
619 * Note that if PSR.ECI is non-zero then we cannot be in an IT block.
621 * Return true if this VMOV scalar <-> gpreg should be skipped because
622 * the MVE PSR.ECI state says we skip the beat where the store happens.
625 /* Calculate the byte offset into Qn which we're going to access */
626 int ofs
= (index
<< size
) + ((vn
& 1) * 8);
628 if (!dc_isar_feature(aa32_mve
, s
)) {
643 g_assert_not_reached();
647 static bool trans_VMOV_to_gp(DisasContext
*s
, arg_VMOV_to_gp
*a
)
649 /* VMOV scalar to general purpose register */
653 * SIZE == MO_32 is a VFP instruction; otherwise NEON. MVE has
654 * all sizes, whether the CPU has fp or not.
656 if (!dc_isar_feature(aa32_mve
, s
)) {
658 ? !dc_isar_feature(aa32_fpsp_v2
, s
)
659 : !arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
664 /* UNDEF accesses to D16-D31 if they don't exist */
665 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vn
& 0x10)) {
669 if (dc_isar_feature(aa32_mve
, s
)) {
670 if (!mve_eci_check(s
)) {
675 if (!vfp_access_check(s
)) {
679 if (!mve_skip_vmov(s
, a
->vn
, a
->index
, a
->size
)) {
680 tmp
= tcg_temp_new_i32();
681 read_neon_element32(tmp
, a
->vn
, a
->index
,
682 a
->size
| (a
->u
? 0 : MO_SIGN
));
683 store_reg(s
, a
->rt
, tmp
);
686 if (dc_isar_feature(aa32_mve
, s
)) {
687 mve_update_and_store_eci(s
);
692 static bool trans_VMOV_from_gp(DisasContext
*s
, arg_VMOV_from_gp
*a
)
694 /* VMOV general purpose register to scalar */
698 * SIZE == MO_32 is a VFP instruction; otherwise NEON. MVE has
699 * all sizes, whether the CPU has fp or not.
701 if (!dc_isar_feature(aa32_mve
, s
)) {
703 ? !dc_isar_feature(aa32_fpsp_v2
, s
)
704 : !arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
709 /* UNDEF accesses to D16-D31 if they don't exist */
710 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vn
& 0x10)) {
714 if (dc_isar_feature(aa32_mve
, s
)) {
715 if (!mve_eci_check(s
)) {
720 if (!vfp_access_check(s
)) {
724 if (!mve_skip_vmov(s
, a
->vn
, a
->index
, a
->size
)) {
725 tmp
= load_reg(s
, a
->rt
);
726 write_neon_element32(tmp
, a
->vn
, a
->index
, a
->size
);
727 tcg_temp_free_i32(tmp
);
730 if (dc_isar_feature(aa32_mve
, s
)) {
731 mve_update_and_store_eci(s
);
736 static bool trans_VDUP(DisasContext
*s
, arg_VDUP
*a
)
738 /* VDUP (general purpose register) */
742 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
746 /* UNDEF accesses to D16-D31 if they don't exist */
747 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vn
& 0x10)) {
755 if (a
->q
&& (a
->vn
& 1)) {
759 vec_size
= a
->q
? 16 : 8;
768 if (!vfp_access_check(s
)) {
772 tmp
= load_reg(s
, a
->rt
);
773 tcg_gen_gvec_dup_i32(size
, neon_full_reg_offset(a
->vn
),
774 vec_size
, vec_size
, tmp
);
775 tcg_temp_free_i32(tmp
);
780 static bool trans_VMSR_VMRS(DisasContext
*s
, arg_VMSR_VMRS
*a
)
783 bool ignore_vfp_enabled
= false;
785 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
786 /* M profile version was already handled in m-nocp.decode */
790 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
797 * VFPv2 allows access to FPSID from userspace; VFPv3 restricts
798 * all ID registers to privileged access only.
800 if (IS_USER(s
) && dc_isar_feature(aa32_fpsp_v3
, s
)) {
803 ignore_vfp_enabled
= true;
807 if (IS_USER(s
) || !arm_dc_feature(s
, ARM_FEATURE_MVFR
)) {
810 ignore_vfp_enabled
= true;
813 if (IS_USER(s
) || !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
816 ignore_vfp_enabled
= true;
824 ignore_vfp_enabled
= true;
827 case ARM_VFP_FPINST2
:
828 /* Not present in VFPv3 */
829 if (IS_USER(s
) || dc_isar_feature(aa32_fpsp_v3
, s
)) {
838 * Call vfp_access_check_a() directly, because we need to tell
839 * it to ignore FPEXC.EN for some register accesses.
841 if (!vfp_access_check_a(s
, ignore_vfp_enabled
)) {
846 /* VMRS, move VFP special register to gp register */
852 if (s
->current_el
== 1) {
853 TCGv_i32 tcg_reg
, tcg_rt
;
856 gen_set_pc_im(s
, s
->pc_curr
);
857 tcg_reg
= tcg_const_i32(a
->reg
);
858 tcg_rt
= tcg_const_i32(a
->rt
);
859 gen_helper_check_hcr_el2_trap(cpu_env
, tcg_rt
, tcg_reg
);
860 tcg_temp_free_i32(tcg_reg
);
861 tcg_temp_free_i32(tcg_rt
);
866 case ARM_VFP_FPINST2
:
867 tmp
= load_cpu_field(vfp
.xregs
[a
->reg
]);
871 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
872 tcg_gen_andi_i32(tmp
, tmp
, FPCR_NZCV_MASK
);
874 tmp
= tcg_temp_new_i32();
875 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
879 g_assert_not_reached();
883 /* Set the 4 flag bits in the CPSR. */
885 tcg_temp_free_i32(tmp
);
887 store_reg(s
, a
->rt
, tmp
);
890 /* VMSR, move gp register to VFP special register */
896 /* Writes are ignored. */
899 tmp
= load_reg(s
, a
->rt
);
900 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
901 tcg_temp_free_i32(tmp
);
906 * TODO: VFP subarchitecture support.
907 * For now, keep the EN bit only
909 tmp
= load_reg(s
, a
->rt
);
910 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
911 store_cpu_field(tmp
, vfp
.xregs
[a
->reg
]);
915 case ARM_VFP_FPINST2
:
916 tmp
= load_reg(s
, a
->rt
);
917 store_cpu_field(tmp
, vfp
.xregs
[a
->reg
]);
920 g_assert_not_reached();
928 static bool trans_VMOV_half(DisasContext
*s
, arg_VMOV_single
*a
)
932 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
937 /* UNPREDICTABLE; we choose to UNDEF */
941 if (!vfp_access_check(s
)) {
946 /* VFP to general purpose register */
947 tmp
= tcg_temp_new_i32();
948 vfp_load_reg32(tmp
, a
->vn
);
949 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
950 store_reg(s
, a
->rt
, tmp
);
952 /* general purpose register to VFP */
953 tmp
= load_reg(s
, a
->rt
);
954 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
955 vfp_store_reg32(tmp
, a
->vn
);
956 tcg_temp_free_i32(tmp
);
962 static bool trans_VMOV_single(DisasContext
*s
, arg_VMOV_single
*a
)
966 if (!dc_isar_feature(aa32_fpsp_v2
, s
) && !dc_isar_feature(aa32_mve
, s
)) {
970 if (!vfp_access_check(s
)) {
975 /* VFP to general purpose register */
976 tmp
= tcg_temp_new_i32();
977 vfp_load_reg32(tmp
, a
->vn
);
979 /* Set the 4 flag bits in the CPSR. */
981 tcg_temp_free_i32(tmp
);
983 store_reg(s
, a
->rt
, tmp
);
986 /* general purpose register to VFP */
987 tmp
= load_reg(s
, a
->rt
);
988 vfp_store_reg32(tmp
, a
->vn
);
989 tcg_temp_free_i32(tmp
);
995 static bool trans_VMOV_64_sp(DisasContext
*s
, arg_VMOV_64_sp
*a
)
999 if (!dc_isar_feature(aa32_fpsp_v2
, s
) && !dc_isar_feature(aa32_mve
, s
)) {
1004 * VMOV between two general-purpose registers and two single precision
1005 * floating point registers
1007 if (!vfp_access_check(s
)) {
1012 /* fpreg to gpreg */
1013 tmp
= tcg_temp_new_i32();
1014 vfp_load_reg32(tmp
, a
->vm
);
1015 store_reg(s
, a
->rt
, tmp
);
1016 tmp
= tcg_temp_new_i32();
1017 vfp_load_reg32(tmp
, a
->vm
+ 1);
1018 store_reg(s
, a
->rt2
, tmp
);
1020 /* gpreg to fpreg */
1021 tmp
= load_reg(s
, a
->rt
);
1022 vfp_store_reg32(tmp
, a
->vm
);
1023 tcg_temp_free_i32(tmp
);
1024 tmp
= load_reg(s
, a
->rt2
);
1025 vfp_store_reg32(tmp
, a
->vm
+ 1);
1026 tcg_temp_free_i32(tmp
);
1032 static bool trans_VMOV_64_dp(DisasContext
*s
, arg_VMOV_64_dp
*a
)
1037 * VMOV between two general-purpose registers and one double precision
1038 * floating point register. Note that this does not require support
1039 * for double precision arithmetic.
1041 if (!dc_isar_feature(aa32_fpsp_v2
, s
) && !dc_isar_feature(aa32_mve
, s
)) {
1045 /* UNDEF accesses to D16-D31 if they don't exist */
1046 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
1050 if (!vfp_access_check(s
)) {
1055 /* fpreg to gpreg */
1056 tmp
= tcg_temp_new_i32();
1057 vfp_load_reg32(tmp
, a
->vm
* 2);
1058 store_reg(s
, a
->rt
, tmp
);
1059 tmp
= tcg_temp_new_i32();
1060 vfp_load_reg32(tmp
, a
->vm
* 2 + 1);
1061 store_reg(s
, a
->rt2
, tmp
);
1063 /* gpreg to fpreg */
1064 tmp
= load_reg(s
, a
->rt
);
1065 vfp_store_reg32(tmp
, a
->vm
* 2);
1066 tcg_temp_free_i32(tmp
);
1067 tmp
= load_reg(s
, a
->rt2
);
1068 vfp_store_reg32(tmp
, a
->vm
* 2 + 1);
1069 tcg_temp_free_i32(tmp
);
1075 static bool trans_VLDR_VSTR_hp(DisasContext
*s
, arg_VLDR_VSTR_sp
*a
)
1080 if (!dc_isar_feature(aa32_fpsp_v2
, s
) && !dc_isar_feature(aa32_mve
, s
)) {
1084 if (!vfp_access_check(s
)) {
1088 /* imm8 field is offset/2 for fp16, unlike fp32 and fp64 */
1089 offset
= a
->imm
<< 1;
1094 /* For thumb, use of PC is UNPREDICTABLE. */
1095 addr
= add_reg_for_lit(s
, a
->rn
, offset
);
1096 tmp
= tcg_temp_new_i32();
1098 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), MO_UW
| MO_ALIGN
);
1099 vfp_store_reg32(tmp
, a
->vd
);
1101 vfp_load_reg32(tmp
, a
->vd
);
1102 gen_aa32_st_i32(s
, tmp
, addr
, get_mem_index(s
), MO_UW
| MO_ALIGN
);
1104 tcg_temp_free_i32(tmp
);
1105 tcg_temp_free_i32(addr
);
1110 static bool trans_VLDR_VSTR_sp(DisasContext
*s
, arg_VLDR_VSTR_sp
*a
)
1115 if (!dc_isar_feature(aa32_fpsp_v2
, s
) && !dc_isar_feature(aa32_mve
, s
)) {
1119 if (!vfp_access_check(s
)) {
1123 offset
= a
->imm
<< 2;
1128 /* For thumb, use of PC is UNPREDICTABLE. */
1129 addr
= add_reg_for_lit(s
, a
->rn
, offset
);
1130 tmp
= tcg_temp_new_i32();
1132 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), MO_UL
| MO_ALIGN
);
1133 vfp_store_reg32(tmp
, a
->vd
);
1135 vfp_load_reg32(tmp
, a
->vd
);
1136 gen_aa32_st_i32(s
, tmp
, addr
, get_mem_index(s
), MO_UL
| MO_ALIGN
);
1138 tcg_temp_free_i32(tmp
);
1139 tcg_temp_free_i32(addr
);
1144 static bool trans_VLDR_VSTR_dp(DisasContext
*s
, arg_VLDR_VSTR_dp
*a
)
1150 /* Note that this does not require support for double arithmetic. */
1151 if (!dc_isar_feature(aa32_fpsp_v2
, s
) && !dc_isar_feature(aa32_mve
, s
)) {
1155 /* UNDEF accesses to D16-D31 if they don't exist */
1156 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
1160 if (!vfp_access_check(s
)) {
1164 offset
= a
->imm
<< 2;
1169 /* For thumb, use of PC is UNPREDICTABLE. */
1170 addr
= add_reg_for_lit(s
, a
->rn
, offset
);
1171 tmp
= tcg_temp_new_i64();
1173 gen_aa32_ld_i64(s
, tmp
, addr
, get_mem_index(s
), MO_UQ
| MO_ALIGN_4
);
1174 vfp_store_reg64(tmp
, a
->vd
);
1176 vfp_load_reg64(tmp
, a
->vd
);
1177 gen_aa32_st_i64(s
, tmp
, addr
, get_mem_index(s
), MO_UQ
| MO_ALIGN_4
);
1179 tcg_temp_free_i64(tmp
);
1180 tcg_temp_free_i32(addr
);
1185 static bool trans_VLDM_VSTM_sp(DisasContext
*s
, arg_VLDM_VSTM_sp
*a
)
1191 if (!dc_isar_feature(aa32_fpsp_v2
, s
) && !dc_isar_feature(aa32_mve
, s
)) {
1197 if (n
== 0 || (a
->vd
+ n
) > 32) {
1199 * UNPREDICTABLE cases for bad immediates: we choose to
1200 * UNDEF to avoid generating huge numbers of TCG ops
1204 if (a
->rn
== 15 && a
->w
) {
1205 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
1209 s
->eci_handled
= true;
1211 if (!vfp_access_check(s
)) {
1215 /* For thumb, use of PC is UNPREDICTABLE. */
1216 addr
= add_reg_for_lit(s
, a
->rn
, 0);
1219 tcg_gen_addi_i32(addr
, addr
, -(a
->imm
<< 2));
1222 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
1224 * Here 'addr' is the lowest address we will store to,
1225 * and is either the old SP (if post-increment) or
1226 * the new SP (if pre-decrement). For post-increment
1227 * where the old value is below the limit and the new
1228 * value is above, it is UNKNOWN whether the limit check
1229 * triggers; we choose to trigger.
1231 gen_helper_v8m_stackcheck(cpu_env
, addr
);
1235 tmp
= tcg_temp_new_i32();
1236 for (i
= 0; i
< n
; i
++) {
1239 gen_aa32_ld_i32(s
, tmp
, addr
, get_mem_index(s
), MO_UL
| MO_ALIGN
);
1240 vfp_store_reg32(tmp
, a
->vd
+ i
);
1243 vfp_load_reg32(tmp
, a
->vd
+ i
);
1244 gen_aa32_st_i32(s
, tmp
, addr
, get_mem_index(s
), MO_UL
| MO_ALIGN
);
1246 tcg_gen_addi_i32(addr
, addr
, offset
);
1248 tcg_temp_free_i32(tmp
);
1252 offset
= -offset
* n
;
1253 tcg_gen_addi_i32(addr
, addr
, offset
);
1255 store_reg(s
, a
->rn
, addr
);
1257 tcg_temp_free_i32(addr
);
1264 static bool trans_VLDM_VSTM_dp(DisasContext
*s
, arg_VLDM_VSTM_dp
*a
)
1271 /* Note that this does not require support for double arithmetic. */
1272 if (!dc_isar_feature(aa32_fpsp_v2
, s
) && !dc_isar_feature(aa32_mve
, s
)) {
1278 if (n
== 0 || (a
->vd
+ n
) > 32 || n
> 16) {
1280 * UNPREDICTABLE cases for bad immediates: we choose to
1281 * UNDEF to avoid generating huge numbers of TCG ops
1285 if (a
->rn
== 15 && a
->w
) {
1286 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
1290 /* UNDEF accesses to D16-D31 if they don't exist */
1291 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
+ n
) > 16) {
1295 s
->eci_handled
= true;
1297 if (!vfp_access_check(s
)) {
1301 /* For thumb, use of PC is UNPREDICTABLE. */
1302 addr
= add_reg_for_lit(s
, a
->rn
, 0);
1305 tcg_gen_addi_i32(addr
, addr
, -(a
->imm
<< 2));
1308 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
1310 * Here 'addr' is the lowest address we will store to,
1311 * and is either the old SP (if post-increment) or
1312 * the new SP (if pre-decrement). For post-increment
1313 * where the old value is below the limit and the new
1314 * value is above, it is UNKNOWN whether the limit check
1315 * triggers; we choose to trigger.
1317 gen_helper_v8m_stackcheck(cpu_env
, addr
);
1321 tmp
= tcg_temp_new_i64();
1322 for (i
= 0; i
< n
; i
++) {
1325 gen_aa32_ld_i64(s
, tmp
, addr
, get_mem_index(s
), MO_UQ
| MO_ALIGN_4
);
1326 vfp_store_reg64(tmp
, a
->vd
+ i
);
1329 vfp_load_reg64(tmp
, a
->vd
+ i
);
1330 gen_aa32_st_i64(s
, tmp
, addr
, get_mem_index(s
), MO_UQ
| MO_ALIGN_4
);
1332 tcg_gen_addi_i32(addr
, addr
, offset
);
1334 tcg_temp_free_i64(tmp
);
1338 offset
= -offset
* n
;
1339 } else if (a
->imm
& 1) {
1346 tcg_gen_addi_i32(addr
, addr
, offset
);
1348 store_reg(s
, a
->rn
, addr
);
1350 tcg_temp_free_i32(addr
);
1358 * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp().
1359 * The callback should emit code to write a value to vd. If
1360 * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd
1361 * will contain the old value of the relevant VFP register;
1362 * otherwise it must be written to only.
1364 typedef void VFPGen3OpSPFn(TCGv_i32 vd
,
1365 TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
);
1366 typedef void VFPGen3OpDPFn(TCGv_i64 vd
,
1367 TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
);
1370 * Types for callbacks for do_vfp_2op_sp() and do_vfp_2op_dp().
1371 * The callback should emit code to write a value to vd (which
1372 * should be written to only).
1374 typedef void VFPGen2OpSPFn(TCGv_i32 vd
, TCGv_i32 vm
);
1375 typedef void VFPGen2OpDPFn(TCGv_i64 vd
, TCGv_i64 vm
);
1378 * Return true if the specified S reg is in a scalar bank
1379 * (ie if it is s0..s7)
1381 static inline bool vfp_sreg_is_scalar(int reg
)
1383 return (reg
& 0x18) == 0;
1387 * Return true if the specified D reg is in a scalar bank
1388 * (ie if it is d0..d3 or d16..d19)
1390 static inline bool vfp_dreg_is_scalar(int reg
)
1392 return (reg
& 0xc) == 0;
1396 * Advance the S reg number forwards by delta within its bank
1397 * (ie increment the low 3 bits but leave the rest the same)
1399 static inline int vfp_advance_sreg(int reg
, int delta
)
1401 return ((reg
+ delta
) & 0x7) | (reg
& ~0x7);
1405 * Advance the D reg number forwards by delta within its bank
1406 * (ie increment the low 2 bits but leave the rest the same)
1408 static inline int vfp_advance_dreg(int reg
, int delta
)
1410 return ((reg
+ delta
) & 0x3) | (reg
& ~0x3);
1414 * Perform a 3-operand VFP data processing instruction. fn is the
1415 * callback to do the actual operation; this function deals with the
1416 * code to handle looping around for VFP vector processing.
1418 static bool do_vfp_3op_sp(DisasContext
*s
, VFPGen3OpSPFn
*fn
,
1419 int vd
, int vn
, int vm
, bool reads_vd
)
1421 uint32_t delta_m
= 0;
1422 uint32_t delta_d
= 0;
1423 int veclen
= s
->vec_len
;
1424 TCGv_i32 f0
, f1
, fd
;
1427 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
1431 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1432 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1436 if (!vfp_access_check(s
)) {
1441 /* Figure out what type of vector operation this is. */
1442 if (vfp_sreg_is_scalar(vd
)) {
1446 delta_d
= s
->vec_stride
+ 1;
1448 if (vfp_sreg_is_scalar(vm
)) {
1449 /* mixed scalar/vector */
1458 f0
= tcg_temp_new_i32();
1459 f1
= tcg_temp_new_i32();
1460 fd
= tcg_temp_new_i32();
1461 fpst
= fpstatus_ptr(FPST_FPCR
);
1463 vfp_load_reg32(f0
, vn
);
1464 vfp_load_reg32(f1
, vm
);
1468 vfp_load_reg32(fd
, vd
);
1470 fn(fd
, f0
, f1
, fpst
);
1471 vfp_store_reg32(fd
, vd
);
1477 /* Set up the operands for the next iteration */
1479 vd
= vfp_advance_sreg(vd
, delta_d
);
1480 vn
= vfp_advance_sreg(vn
, delta_d
);
1481 vfp_load_reg32(f0
, vn
);
1483 vm
= vfp_advance_sreg(vm
, delta_m
);
1484 vfp_load_reg32(f1
, vm
);
1488 tcg_temp_free_i32(f0
);
1489 tcg_temp_free_i32(f1
);
1490 tcg_temp_free_i32(fd
);
1491 tcg_temp_free_ptr(fpst
);
1496 static bool do_vfp_3op_hp(DisasContext
*s
, VFPGen3OpSPFn
*fn
,
1497 int vd
, int vn
, int vm
, bool reads_vd
)
1500 * Do a half-precision operation. Functionally this is
1501 * the same as do_vfp_3op_sp(), except:
1502 * - it uses the FPST_FPCR_F16
1503 * - it doesn't need the VFP vector handling (fp16 is a
1504 * v8 feature, and in v8 VFP vectors don't exist)
1505 * - it does the aa32_fp16_arith feature test
1507 TCGv_i32 f0
, f1
, fd
;
1510 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
1514 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
1518 if (!vfp_access_check(s
)) {
1522 f0
= tcg_temp_new_i32();
1523 f1
= tcg_temp_new_i32();
1524 fd
= tcg_temp_new_i32();
1525 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
1527 vfp_load_reg32(f0
, vn
);
1528 vfp_load_reg32(f1
, vm
);
1531 vfp_load_reg32(fd
, vd
);
1533 fn(fd
, f0
, f1
, fpst
);
1534 vfp_store_reg32(fd
, vd
);
1536 tcg_temp_free_i32(f0
);
1537 tcg_temp_free_i32(f1
);
1538 tcg_temp_free_i32(fd
);
1539 tcg_temp_free_ptr(fpst
);
1544 static bool do_vfp_3op_dp(DisasContext
*s
, VFPGen3OpDPFn
*fn
,
1545 int vd
, int vn
, int vm
, bool reads_vd
)
1547 uint32_t delta_m
= 0;
1548 uint32_t delta_d
= 0;
1549 int veclen
= s
->vec_len
;
1550 TCGv_i64 f0
, f1
, fd
;
1553 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
1557 /* UNDEF accesses to D16-D31 if they don't exist */
1558 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((vd
| vn
| vm
) & 0x10)) {
1562 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1563 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1567 if (!vfp_access_check(s
)) {
1572 /* Figure out what type of vector operation this is. */
1573 if (vfp_dreg_is_scalar(vd
)) {
1577 delta_d
= (s
->vec_stride
>> 1) + 1;
1579 if (vfp_dreg_is_scalar(vm
)) {
1580 /* mixed scalar/vector */
1589 f0
= tcg_temp_new_i64();
1590 f1
= tcg_temp_new_i64();
1591 fd
= tcg_temp_new_i64();
1592 fpst
= fpstatus_ptr(FPST_FPCR
);
1594 vfp_load_reg64(f0
, vn
);
1595 vfp_load_reg64(f1
, vm
);
1599 vfp_load_reg64(fd
, vd
);
1601 fn(fd
, f0
, f1
, fpst
);
1602 vfp_store_reg64(fd
, vd
);
1607 /* Set up the operands for the next iteration */
1609 vd
= vfp_advance_dreg(vd
, delta_d
);
1610 vn
= vfp_advance_dreg(vn
, delta_d
);
1611 vfp_load_reg64(f0
, vn
);
1613 vm
= vfp_advance_dreg(vm
, delta_m
);
1614 vfp_load_reg64(f1
, vm
);
1618 tcg_temp_free_i64(f0
);
1619 tcg_temp_free_i64(f1
);
1620 tcg_temp_free_i64(fd
);
1621 tcg_temp_free_ptr(fpst
);
1626 static bool do_vfp_2op_sp(DisasContext
*s
, VFPGen2OpSPFn
*fn
, int vd
, int vm
)
1628 uint32_t delta_m
= 0;
1629 uint32_t delta_d
= 0;
1630 int veclen
= s
->vec_len
;
1633 /* Note that the caller must check the aa32_fpsp_v2 feature. */
1635 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1636 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1640 if (!vfp_access_check(s
)) {
1645 /* Figure out what type of vector operation this is. */
1646 if (vfp_sreg_is_scalar(vd
)) {
1650 delta_d
= s
->vec_stride
+ 1;
1652 if (vfp_sreg_is_scalar(vm
)) {
1653 /* mixed scalar/vector */
1662 f0
= tcg_temp_new_i32();
1663 fd
= tcg_temp_new_i32();
1665 vfp_load_reg32(f0
, vm
);
1669 vfp_store_reg32(fd
, vd
);
1676 /* single source one-many */
1678 vd
= vfp_advance_sreg(vd
, delta_d
);
1679 vfp_store_reg32(fd
, vd
);
1684 /* Set up the operands for the next iteration */
1686 vd
= vfp_advance_sreg(vd
, delta_d
);
1687 vm
= vfp_advance_sreg(vm
, delta_m
);
1688 vfp_load_reg32(f0
, vm
);
1691 tcg_temp_free_i32(f0
);
1692 tcg_temp_free_i32(fd
);
1697 static bool do_vfp_2op_hp(DisasContext
*s
, VFPGen2OpSPFn
*fn
, int vd
, int vm
)
1700 * Do a half-precision operation. Functionally this is
1701 * the same as do_vfp_2op_sp(), except:
1702 * - it doesn't need the VFP vector handling (fp16 is a
1703 * v8 feature, and in v8 VFP vectors don't exist)
1704 * - it does the aa32_fp16_arith feature test
1708 /* Note that the caller must check the aa32_fp16_arith feature */
1710 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
1714 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
1718 if (!vfp_access_check(s
)) {
1722 f0
= tcg_temp_new_i32();
1723 vfp_load_reg32(f0
, vm
);
1725 vfp_store_reg32(f0
, vd
);
1726 tcg_temp_free_i32(f0
);
1731 static bool do_vfp_2op_dp(DisasContext
*s
, VFPGen2OpDPFn
*fn
, int vd
, int vm
)
1733 uint32_t delta_m
= 0;
1734 uint32_t delta_d
= 0;
1735 int veclen
= s
->vec_len
;
1738 /* Note that the caller must check the aa32_fpdp_v2 feature. */
1740 /* UNDEF accesses to D16-D31 if they don't exist */
1741 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((vd
| vm
) & 0x10)) {
1745 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1746 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1750 if (!vfp_access_check(s
)) {
1755 /* Figure out what type of vector operation this is. */
1756 if (vfp_dreg_is_scalar(vd
)) {
1760 delta_d
= (s
->vec_stride
>> 1) + 1;
1762 if (vfp_dreg_is_scalar(vm
)) {
1763 /* mixed scalar/vector */
1772 f0
= tcg_temp_new_i64();
1773 fd
= tcg_temp_new_i64();
1775 vfp_load_reg64(f0
, vm
);
1779 vfp_store_reg64(fd
, vd
);
1786 /* single source one-many */
1788 vd
= vfp_advance_dreg(vd
, delta_d
);
1789 vfp_store_reg64(fd
, vd
);
1794 /* Set up the operands for the next iteration */
1796 vd
= vfp_advance_dreg(vd
, delta_d
);
1797 vd
= vfp_advance_dreg(vm
, delta_m
);
1798 vfp_load_reg64(f0
, vm
);
1801 tcg_temp_free_i64(f0
);
1802 tcg_temp_free_i64(fd
);
1807 static void gen_VMLA_hp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1809 /* Note that order of inputs to the add matters for NaNs */
1810 TCGv_i32 tmp
= tcg_temp_new_i32();
1812 gen_helper_vfp_mulh(tmp
, vn
, vm
, fpst
);
1813 gen_helper_vfp_addh(vd
, vd
, tmp
, fpst
);
1814 tcg_temp_free_i32(tmp
);
1817 static bool trans_VMLA_hp(DisasContext
*s
, arg_VMLA_sp
*a
)
1819 return do_vfp_3op_hp(s
, gen_VMLA_hp
, a
->vd
, a
->vn
, a
->vm
, true);
1822 static void gen_VMLA_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1824 /* Note that order of inputs to the add matters for NaNs */
1825 TCGv_i32 tmp
= tcg_temp_new_i32();
1827 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1828 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1829 tcg_temp_free_i32(tmp
);
1832 static bool trans_VMLA_sp(DisasContext
*s
, arg_VMLA_sp
*a
)
1834 return do_vfp_3op_sp(s
, gen_VMLA_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1837 static void gen_VMLA_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1839 /* Note that order of inputs to the add matters for NaNs */
1840 TCGv_i64 tmp
= tcg_temp_new_i64();
1842 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1843 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1844 tcg_temp_free_i64(tmp
);
1847 static bool trans_VMLA_dp(DisasContext
*s
, arg_VMLA_dp
*a
)
1849 return do_vfp_3op_dp(s
, gen_VMLA_dp
, a
->vd
, a
->vn
, a
->vm
, true);
1852 static void gen_VMLS_hp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1855 * VMLS: vd = vd + -(vn * vm)
1856 * Note that order of inputs to the add matters for NaNs.
1858 TCGv_i32 tmp
= tcg_temp_new_i32();
1860 gen_helper_vfp_mulh(tmp
, vn
, vm
, fpst
);
1861 gen_helper_vfp_negh(tmp
, tmp
);
1862 gen_helper_vfp_addh(vd
, vd
, tmp
, fpst
);
1863 tcg_temp_free_i32(tmp
);
1866 static bool trans_VMLS_hp(DisasContext
*s
, arg_VMLS_sp
*a
)
1868 return do_vfp_3op_hp(s
, gen_VMLS_hp
, a
->vd
, a
->vn
, a
->vm
, true);
1871 static void gen_VMLS_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1874 * VMLS: vd = vd + -(vn * vm)
1875 * Note that order of inputs to the add matters for NaNs.
1877 TCGv_i32 tmp
= tcg_temp_new_i32();
1879 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1880 gen_helper_vfp_negs(tmp
, tmp
);
1881 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1882 tcg_temp_free_i32(tmp
);
1885 static bool trans_VMLS_sp(DisasContext
*s
, arg_VMLS_sp
*a
)
1887 return do_vfp_3op_sp(s
, gen_VMLS_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1890 static void gen_VMLS_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1893 * VMLS: vd = vd + -(vn * vm)
1894 * Note that order of inputs to the add matters for NaNs.
1896 TCGv_i64 tmp
= tcg_temp_new_i64();
1898 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1899 gen_helper_vfp_negd(tmp
, tmp
);
1900 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1901 tcg_temp_free_i64(tmp
);
1904 static bool trans_VMLS_dp(DisasContext
*s
, arg_VMLS_dp
*a
)
1906 return do_vfp_3op_dp(s
, gen_VMLS_dp
, a
->vd
, a
->vn
, a
->vm
, true);
1909 static void gen_VNMLS_hp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1912 * VNMLS: -fd + (fn * fm)
1913 * Note that it isn't valid to replace (-A + B) with (B - A) or similar
1914 * plausible looking simplifications because this will give wrong results
1917 TCGv_i32 tmp
= tcg_temp_new_i32();
1919 gen_helper_vfp_mulh(tmp
, vn
, vm
, fpst
);
1920 gen_helper_vfp_negh(vd
, vd
);
1921 gen_helper_vfp_addh(vd
, vd
, tmp
, fpst
);
1922 tcg_temp_free_i32(tmp
);
1925 static bool trans_VNMLS_hp(DisasContext
*s
, arg_VNMLS_sp
*a
)
1927 return do_vfp_3op_hp(s
, gen_VNMLS_hp
, a
->vd
, a
->vn
, a
->vm
, true);
1930 static void gen_VNMLS_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1933 * VNMLS: -fd + (fn * fm)
1934 * Note that it isn't valid to replace (-A + B) with (B - A) or similar
1935 * plausible looking simplifications because this will give wrong results
1938 TCGv_i32 tmp
= tcg_temp_new_i32();
1940 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1941 gen_helper_vfp_negs(vd
, vd
);
1942 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1943 tcg_temp_free_i32(tmp
);
1946 static bool trans_VNMLS_sp(DisasContext
*s
, arg_VNMLS_sp
*a
)
1948 return do_vfp_3op_sp(s
, gen_VNMLS_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1951 static void gen_VNMLS_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1954 * VNMLS: -fd + (fn * fm)
1955 * Note that it isn't valid to replace (-A + B) with (B - A) or similar
1956 * plausible looking simplifications because this will give wrong results
1959 TCGv_i64 tmp
= tcg_temp_new_i64();
1961 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1962 gen_helper_vfp_negd(vd
, vd
);
1963 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1964 tcg_temp_free_i64(tmp
);
1967 static bool trans_VNMLS_dp(DisasContext
*s
, arg_VNMLS_dp
*a
)
1969 return do_vfp_3op_dp(s
, gen_VNMLS_dp
, a
->vd
, a
->vn
, a
->vm
, true);
1972 static void gen_VNMLA_hp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1974 /* VNMLA: -fd + -(fn * fm) */
1975 TCGv_i32 tmp
= tcg_temp_new_i32();
1977 gen_helper_vfp_mulh(tmp
, vn
, vm
, fpst
);
1978 gen_helper_vfp_negh(tmp
, tmp
);
1979 gen_helper_vfp_negh(vd
, vd
);
1980 gen_helper_vfp_addh(vd
, vd
, tmp
, fpst
);
1981 tcg_temp_free_i32(tmp
);
1984 static bool trans_VNMLA_hp(DisasContext
*s
, arg_VNMLA_sp
*a
)
1986 return do_vfp_3op_hp(s
, gen_VNMLA_hp
, a
->vd
, a
->vn
, a
->vm
, true);
1989 static void gen_VNMLA_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1991 /* VNMLA: -fd + -(fn * fm) */
1992 TCGv_i32 tmp
= tcg_temp_new_i32();
1994 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1995 gen_helper_vfp_negs(tmp
, tmp
);
1996 gen_helper_vfp_negs(vd
, vd
);
1997 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1998 tcg_temp_free_i32(tmp
);
2001 static bool trans_VNMLA_sp(DisasContext
*s
, arg_VNMLA_sp
*a
)
2003 return do_vfp_3op_sp(s
, gen_VNMLA_sp
, a
->vd
, a
->vn
, a
->vm
, true);
2006 static void gen_VNMLA_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
2008 /* VNMLA: -fd + (fn * fm) */
2009 TCGv_i64 tmp
= tcg_temp_new_i64();
2011 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
2012 gen_helper_vfp_negd(tmp
, tmp
);
2013 gen_helper_vfp_negd(vd
, vd
);
2014 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
2015 tcg_temp_free_i64(tmp
);
2018 static bool trans_VNMLA_dp(DisasContext
*s
, arg_VNMLA_dp
*a
)
2020 return do_vfp_3op_dp(s
, gen_VNMLA_dp
, a
->vd
, a
->vn
, a
->vm
, true);
2023 static bool trans_VMUL_hp(DisasContext
*s
, arg_VMUL_sp
*a
)
2025 return do_vfp_3op_hp(s
, gen_helper_vfp_mulh
, a
->vd
, a
->vn
, a
->vm
, false);
2028 static bool trans_VMUL_sp(DisasContext
*s
, arg_VMUL_sp
*a
)
2030 return do_vfp_3op_sp(s
, gen_helper_vfp_muls
, a
->vd
, a
->vn
, a
->vm
, false);
2033 static bool trans_VMUL_dp(DisasContext
*s
, arg_VMUL_dp
*a
)
2035 return do_vfp_3op_dp(s
, gen_helper_vfp_muld
, a
->vd
, a
->vn
, a
->vm
, false);
2038 static void gen_VNMUL_hp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
2040 /* VNMUL: -(fn * fm) */
2041 gen_helper_vfp_mulh(vd
, vn
, vm
, fpst
);
2042 gen_helper_vfp_negh(vd
, vd
);
2045 static bool trans_VNMUL_hp(DisasContext
*s
, arg_VNMUL_sp
*a
)
2047 return do_vfp_3op_hp(s
, gen_VNMUL_hp
, a
->vd
, a
->vn
, a
->vm
, false);
2050 static void gen_VNMUL_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
2052 /* VNMUL: -(fn * fm) */
2053 gen_helper_vfp_muls(vd
, vn
, vm
, fpst
);
2054 gen_helper_vfp_negs(vd
, vd
);
2057 static bool trans_VNMUL_sp(DisasContext
*s
, arg_VNMUL_sp
*a
)
2059 return do_vfp_3op_sp(s
, gen_VNMUL_sp
, a
->vd
, a
->vn
, a
->vm
, false);
2062 static void gen_VNMUL_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
2064 /* VNMUL: -(fn * fm) */
2065 gen_helper_vfp_muld(vd
, vn
, vm
, fpst
);
2066 gen_helper_vfp_negd(vd
, vd
);
2069 static bool trans_VNMUL_dp(DisasContext
*s
, arg_VNMUL_dp
*a
)
2071 return do_vfp_3op_dp(s
, gen_VNMUL_dp
, a
->vd
, a
->vn
, a
->vm
, false);
2074 static bool trans_VADD_hp(DisasContext
*s
, arg_VADD_sp
*a
)
2076 return do_vfp_3op_hp(s
, gen_helper_vfp_addh
, a
->vd
, a
->vn
, a
->vm
, false);
2079 static bool trans_VADD_sp(DisasContext
*s
, arg_VADD_sp
*a
)
2081 return do_vfp_3op_sp(s
, gen_helper_vfp_adds
, a
->vd
, a
->vn
, a
->vm
, false);
2084 static bool trans_VADD_dp(DisasContext
*s
, arg_VADD_dp
*a
)
2086 return do_vfp_3op_dp(s
, gen_helper_vfp_addd
, a
->vd
, a
->vn
, a
->vm
, false);
2089 static bool trans_VSUB_hp(DisasContext
*s
, arg_VSUB_sp
*a
)
2091 return do_vfp_3op_hp(s
, gen_helper_vfp_subh
, a
->vd
, a
->vn
, a
->vm
, false);
2094 static bool trans_VSUB_sp(DisasContext
*s
, arg_VSUB_sp
*a
)
2096 return do_vfp_3op_sp(s
, gen_helper_vfp_subs
, a
->vd
, a
->vn
, a
->vm
, false);
2099 static bool trans_VSUB_dp(DisasContext
*s
, arg_VSUB_dp
*a
)
2101 return do_vfp_3op_dp(s
, gen_helper_vfp_subd
, a
->vd
, a
->vn
, a
->vm
, false);
2104 static bool trans_VDIV_hp(DisasContext
*s
, arg_VDIV_sp
*a
)
2106 return do_vfp_3op_hp(s
, gen_helper_vfp_divh
, a
->vd
, a
->vn
, a
->vm
, false);
2109 static bool trans_VDIV_sp(DisasContext
*s
, arg_VDIV_sp
*a
)
2111 return do_vfp_3op_sp(s
, gen_helper_vfp_divs
, a
->vd
, a
->vn
, a
->vm
, false);
2114 static bool trans_VDIV_dp(DisasContext
*s
, arg_VDIV_dp
*a
)
2116 return do_vfp_3op_dp(s
, gen_helper_vfp_divd
, a
->vd
, a
->vn
, a
->vm
, false);
2119 static bool trans_VMINNM_hp(DisasContext
*s
, arg_VMINNM_sp
*a
)
2121 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
2124 return do_vfp_3op_hp(s
, gen_helper_vfp_minnumh
,
2125 a
->vd
, a
->vn
, a
->vm
, false);
2128 static bool trans_VMAXNM_hp(DisasContext
*s
, arg_VMAXNM_sp
*a
)
2130 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
2133 return do_vfp_3op_hp(s
, gen_helper_vfp_maxnumh
,
2134 a
->vd
, a
->vn
, a
->vm
, false);
2137 static bool trans_VMINNM_sp(DisasContext
*s
, arg_VMINNM_sp
*a
)
2139 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
2142 return do_vfp_3op_sp(s
, gen_helper_vfp_minnums
,
2143 a
->vd
, a
->vn
, a
->vm
, false);
2146 static bool trans_VMAXNM_sp(DisasContext
*s
, arg_VMAXNM_sp
*a
)
2148 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
2151 return do_vfp_3op_sp(s
, gen_helper_vfp_maxnums
,
2152 a
->vd
, a
->vn
, a
->vm
, false);
2155 static bool trans_VMINNM_dp(DisasContext
*s
, arg_VMINNM_dp
*a
)
2157 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
2160 return do_vfp_3op_dp(s
, gen_helper_vfp_minnumd
,
2161 a
->vd
, a
->vn
, a
->vm
, false);
2164 static bool trans_VMAXNM_dp(DisasContext
*s
, arg_VMAXNM_dp
*a
)
2166 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
2169 return do_vfp_3op_dp(s
, gen_helper_vfp_maxnumd
,
2170 a
->vd
, a
->vn
, a
->vm
, false);
2173 static bool do_vfm_hp(DisasContext
*s
, arg_VFMA_sp
*a
, bool neg_n
, bool neg_d
)
2176 * VFNMA : fd = muladd(-fd, fn, fm)
2177 * VFNMS : fd = muladd(-fd, -fn, fm)
2178 * VFMA : fd = muladd( fd, fn, fm)
2179 * VFMS : fd = muladd( fd, -fn, fm)
2181 * These are fused multiply-add, and must be done as one floating
2182 * point operation with no rounding between the multiplication and
2183 * addition steps. NB that doing the negations here as separate
2184 * steps is correct : an input NaN should come out with its sign
2185 * bit flipped if it is a negated-input.
2188 TCGv_i32 vn
, vm
, vd
;
2191 * Present in VFPv4 only, and only with the FP16 extension.
2192 * Note that we can't rely on the SIMDFMAC check alone, because
2193 * in a Neon-no-VFP core that ID register field will be non-zero.
2195 if (!dc_isar_feature(aa32_fp16_arith
, s
) ||
2196 !dc_isar_feature(aa32_simdfmac
, s
) ||
2197 !dc_isar_feature(aa32_fpsp_v2
, s
)) {
2201 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
2205 if (!vfp_access_check(s
)) {
2209 vn
= tcg_temp_new_i32();
2210 vm
= tcg_temp_new_i32();
2211 vd
= tcg_temp_new_i32();
2213 vfp_load_reg32(vn
, a
->vn
);
2214 vfp_load_reg32(vm
, a
->vm
);
2217 gen_helper_vfp_negh(vn
, vn
);
2219 vfp_load_reg32(vd
, a
->vd
);
2222 gen_helper_vfp_negh(vd
, vd
);
2224 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
2225 gen_helper_vfp_muladdh(vd
, vn
, vm
, vd
, fpst
);
2226 vfp_store_reg32(vd
, a
->vd
);
2228 tcg_temp_free_ptr(fpst
);
2229 tcg_temp_free_i32(vn
);
2230 tcg_temp_free_i32(vm
);
2231 tcg_temp_free_i32(vd
);
2236 static bool do_vfm_sp(DisasContext
*s
, arg_VFMA_sp
*a
, bool neg_n
, bool neg_d
)
2239 * VFNMA : fd = muladd(-fd, fn, fm)
2240 * VFNMS : fd = muladd(-fd, -fn, fm)
2241 * VFMA : fd = muladd( fd, fn, fm)
2242 * VFMS : fd = muladd( fd, -fn, fm)
2244 * These are fused multiply-add, and must be done as one floating
2245 * point operation with no rounding between the multiplication and
2246 * addition steps. NB that doing the negations here as separate
2247 * steps is correct : an input NaN should come out with its sign
2248 * bit flipped if it is a negated-input.
2251 TCGv_i32 vn
, vm
, vd
;
2254 * Present in VFPv4 only.
2255 * Note that we can't rely on the SIMDFMAC check alone, because
2256 * in a Neon-no-VFP core that ID register field will be non-zero.
2258 if (!dc_isar_feature(aa32_simdfmac
, s
) ||
2259 !dc_isar_feature(aa32_fpsp_v2
, s
)) {
2263 * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
2264 * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
2266 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
2270 if (!vfp_access_check(s
)) {
2274 vn
= tcg_temp_new_i32();
2275 vm
= tcg_temp_new_i32();
2276 vd
= tcg_temp_new_i32();
2278 vfp_load_reg32(vn
, a
->vn
);
2279 vfp_load_reg32(vm
, a
->vm
);
2282 gen_helper_vfp_negs(vn
, vn
);
2284 vfp_load_reg32(vd
, a
->vd
);
2287 gen_helper_vfp_negs(vd
, vd
);
2289 fpst
= fpstatus_ptr(FPST_FPCR
);
2290 gen_helper_vfp_muladds(vd
, vn
, vm
, vd
, fpst
);
2291 vfp_store_reg32(vd
, a
->vd
);
2293 tcg_temp_free_ptr(fpst
);
2294 tcg_temp_free_i32(vn
);
2295 tcg_temp_free_i32(vm
);
2296 tcg_temp_free_i32(vd
);
2301 static bool do_vfm_dp(DisasContext
*s
, arg_VFMA_dp
*a
, bool neg_n
, bool neg_d
)
2304 * VFNMA : fd = muladd(-fd, fn, fm)
2305 * VFNMS : fd = muladd(-fd, -fn, fm)
2306 * VFMA : fd = muladd( fd, fn, fm)
2307 * VFMS : fd = muladd( fd, -fn, fm)
2309 * These are fused multiply-add, and must be done as one floating
2310 * point operation with no rounding between the multiplication and
2311 * addition steps. NB that doing the negations here as separate
2312 * steps is correct : an input NaN should come out with its sign
2313 * bit flipped if it is a negated-input.
2316 TCGv_i64 vn
, vm
, vd
;
2319 * Present in VFPv4 only.
2320 * Note that we can't rely on the SIMDFMAC check alone, because
2321 * in a Neon-no-VFP core that ID register field will be non-zero.
2323 if (!dc_isar_feature(aa32_simdfmac
, s
) ||
2324 !dc_isar_feature(aa32_fpdp_v2
, s
)) {
2328 * In v7A, UNPREDICTABLE with non-zero vector length/stride; from
2329 * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
2331 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
2335 /* UNDEF accesses to D16-D31 if they don't exist. */
2336 if (!dc_isar_feature(aa32_simd_r32
, s
) &&
2337 ((a
->vd
| a
->vn
| a
->vm
) & 0x10)) {
2341 if (!vfp_access_check(s
)) {
2345 vn
= tcg_temp_new_i64();
2346 vm
= tcg_temp_new_i64();
2347 vd
= tcg_temp_new_i64();
2349 vfp_load_reg64(vn
, a
->vn
);
2350 vfp_load_reg64(vm
, a
->vm
);
2353 gen_helper_vfp_negd(vn
, vn
);
2355 vfp_load_reg64(vd
, a
->vd
);
2358 gen_helper_vfp_negd(vd
, vd
);
2360 fpst
= fpstatus_ptr(FPST_FPCR
);
2361 gen_helper_vfp_muladdd(vd
, vn
, vm
, vd
, fpst
);
2362 vfp_store_reg64(vd
, a
->vd
);
2364 tcg_temp_free_ptr(fpst
);
2365 tcg_temp_free_i64(vn
);
2366 tcg_temp_free_i64(vm
);
2367 tcg_temp_free_i64(vd
);
2372 #define MAKE_ONE_VFM_TRANS_FN(INSN, PREC, NEGN, NEGD) \
2373 static bool trans_##INSN##_##PREC(DisasContext *s, \
2374 arg_##INSN##_##PREC *a) \
2376 return do_vfm_##PREC(s, a, NEGN, NEGD); \
2379 #define MAKE_VFM_TRANS_FNS(PREC) \
2380 MAKE_ONE_VFM_TRANS_FN(VFMA, PREC, false, false) \
2381 MAKE_ONE_VFM_TRANS_FN(VFMS, PREC, true, false) \
2382 MAKE_ONE_VFM_TRANS_FN(VFNMA, PREC, false, true) \
2383 MAKE_ONE_VFM_TRANS_FN(VFNMS, PREC, true, true)
2385 MAKE_VFM_TRANS_FNS(hp
)
2386 MAKE_VFM_TRANS_FNS(sp
)
2387 MAKE_VFM_TRANS_FNS(dp
)
2389 static bool trans_VMOV_imm_hp(DisasContext
*s
, arg_VMOV_imm_sp
*a
)
2393 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
2397 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
2401 if (!vfp_access_check(s
)) {
2405 fd
= tcg_const_i32(vfp_expand_imm(MO_16
, a
->imm
));
2406 vfp_store_reg32(fd
, a
->vd
);
2407 tcg_temp_free_i32(fd
);
2411 static bool trans_VMOV_imm_sp(DisasContext
*s
, arg_VMOV_imm_sp
*a
)
2413 uint32_t delta_d
= 0;
2414 int veclen
= s
->vec_len
;
2420 if (!dc_isar_feature(aa32_fpsp_v3
, s
)) {
2424 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
2425 (veclen
!= 0 || s
->vec_stride
!= 0)) {
2429 if (!vfp_access_check(s
)) {
2434 /* Figure out what type of vector operation this is. */
2435 if (vfp_sreg_is_scalar(vd
)) {
2439 delta_d
= s
->vec_stride
+ 1;
2443 fd
= tcg_const_i32(vfp_expand_imm(MO_32
, a
->imm
));
2446 vfp_store_reg32(fd
, vd
);
2452 /* Set up the operands for the next iteration */
2454 vd
= vfp_advance_sreg(vd
, delta_d
);
2457 tcg_temp_free_i32(fd
);
2461 static bool trans_VMOV_imm_dp(DisasContext
*s
, arg_VMOV_imm_dp
*a
)
2463 uint32_t delta_d
= 0;
2464 int veclen
= s
->vec_len
;
2470 if (!dc_isar_feature(aa32_fpdp_v3
, s
)) {
2474 /* UNDEF accesses to D16-D31 if they don't exist. */
2475 if (!dc_isar_feature(aa32_simd_r32
, s
) && (vd
& 0x10)) {
2479 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
2480 (veclen
!= 0 || s
->vec_stride
!= 0)) {
2484 if (!vfp_access_check(s
)) {
2489 /* Figure out what type of vector operation this is. */
2490 if (vfp_dreg_is_scalar(vd
)) {
2494 delta_d
= (s
->vec_stride
>> 1) + 1;
2498 fd
= tcg_const_i64(vfp_expand_imm(MO_64
, a
->imm
));
2501 vfp_store_reg64(fd
, vd
);
2507 /* Set up the operands for the next iteration */
2509 vd
= vfp_advance_dreg(vd
, delta_d
);
2512 tcg_temp_free_i64(fd
);
2516 #define DO_VFP_2OP(INSN, PREC, FN, CHECK) \
2517 static bool trans_##INSN##_##PREC(DisasContext *s, \
2518 arg_##INSN##_##PREC *a) \
2520 if (!dc_isar_feature(CHECK, s)) { \
2523 return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \
2526 #define DO_VFP_VMOV(INSN, PREC, FN) \
2527 static bool trans_##INSN##_##PREC(DisasContext *s, \
2528 arg_##INSN##_##PREC *a) \
2530 if (!dc_isar_feature(aa32_fp##PREC##_v2, s) && \
2531 !dc_isar_feature(aa32_mve, s)) { \
2534 return do_vfp_2op_##PREC(s, FN, a->vd, a->vm); \
2537 DO_VFP_VMOV(VMOV_reg
, sp
, tcg_gen_mov_i32
)
2538 DO_VFP_VMOV(VMOV_reg
, dp
, tcg_gen_mov_i64
)
2540 DO_VFP_2OP(VABS
, hp
, gen_helper_vfp_absh
, aa32_fp16_arith
)
2541 DO_VFP_2OP(VABS
, sp
, gen_helper_vfp_abss
, aa32_fpsp_v2
)
2542 DO_VFP_2OP(VABS
, dp
, gen_helper_vfp_absd
, aa32_fpdp_v2
)
2544 DO_VFP_2OP(VNEG
, hp
, gen_helper_vfp_negh
, aa32_fp16_arith
)
2545 DO_VFP_2OP(VNEG
, sp
, gen_helper_vfp_negs
, aa32_fpsp_v2
)
2546 DO_VFP_2OP(VNEG
, dp
, gen_helper_vfp_negd
, aa32_fpdp_v2
)
2548 static void gen_VSQRT_hp(TCGv_i32 vd
, TCGv_i32 vm
)
2550 gen_helper_vfp_sqrth(vd
, vm
, cpu_env
);
2553 static void gen_VSQRT_sp(TCGv_i32 vd
, TCGv_i32 vm
)
2555 gen_helper_vfp_sqrts(vd
, vm
, cpu_env
);
2558 static void gen_VSQRT_dp(TCGv_i64 vd
, TCGv_i64 vm
)
2560 gen_helper_vfp_sqrtd(vd
, vm
, cpu_env
);
2563 DO_VFP_2OP(VSQRT
, hp
, gen_VSQRT_hp
, aa32_fp16_arith
)
2564 DO_VFP_2OP(VSQRT
, sp
, gen_VSQRT_sp
, aa32_fpsp_v2
)
2565 DO_VFP_2OP(VSQRT
, dp
, gen_VSQRT_dp
, aa32_fpdp_v2
)
2567 static bool trans_VCMP_hp(DisasContext
*s
, arg_VCMP_sp
*a
)
2571 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
2575 /* Vm/M bits must be zero for the Z variant */
2576 if (a
->z
&& a
->vm
!= 0) {
2580 if (!vfp_access_check(s
)) {
2584 vd
= tcg_temp_new_i32();
2585 vm
= tcg_temp_new_i32();
2587 vfp_load_reg32(vd
, a
->vd
);
2589 tcg_gen_movi_i32(vm
, 0);
2591 vfp_load_reg32(vm
, a
->vm
);
2595 gen_helper_vfp_cmpeh(vd
, vm
, cpu_env
);
2597 gen_helper_vfp_cmph(vd
, vm
, cpu_env
);
2600 tcg_temp_free_i32(vd
);
2601 tcg_temp_free_i32(vm
);
2606 static bool trans_VCMP_sp(DisasContext
*s
, arg_VCMP_sp
*a
)
2610 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
2614 /* Vm/M bits must be zero for the Z variant */
2615 if (a
->z
&& a
->vm
!= 0) {
2619 if (!vfp_access_check(s
)) {
2623 vd
= tcg_temp_new_i32();
2624 vm
= tcg_temp_new_i32();
2626 vfp_load_reg32(vd
, a
->vd
);
2628 tcg_gen_movi_i32(vm
, 0);
2630 vfp_load_reg32(vm
, a
->vm
);
2634 gen_helper_vfp_cmpes(vd
, vm
, cpu_env
);
2636 gen_helper_vfp_cmps(vd
, vm
, cpu_env
);
2639 tcg_temp_free_i32(vd
);
2640 tcg_temp_free_i32(vm
);
2645 static bool trans_VCMP_dp(DisasContext
*s
, arg_VCMP_dp
*a
)
2649 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2653 /* Vm/M bits must be zero for the Z variant */
2654 if (a
->z
&& a
->vm
!= 0) {
2658 /* UNDEF accesses to D16-D31 if they don't exist. */
2659 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((a
->vd
| a
->vm
) & 0x10)) {
2663 if (!vfp_access_check(s
)) {
2667 vd
= tcg_temp_new_i64();
2668 vm
= tcg_temp_new_i64();
2670 vfp_load_reg64(vd
, a
->vd
);
2672 tcg_gen_movi_i64(vm
, 0);
2674 vfp_load_reg64(vm
, a
->vm
);
2678 gen_helper_vfp_cmped(vd
, vm
, cpu_env
);
2680 gen_helper_vfp_cmpd(vd
, vm
, cpu_env
);
2683 tcg_temp_free_i64(vd
);
2684 tcg_temp_free_i64(vm
);
2689 static bool trans_VCVT_f32_f16(DisasContext
*s
, arg_VCVT_f32_f16
*a
)
2695 if (!dc_isar_feature(aa32_fp16_spconv
, s
)) {
2699 if (!vfp_access_check(s
)) {
2703 fpst
= fpstatus_ptr(FPST_FPCR
);
2704 ahp_mode
= get_ahp_flag();
2705 tmp
= tcg_temp_new_i32();
2706 /* The T bit tells us if we want the low or high 16 bits of Vm */
2707 tcg_gen_ld16u_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vm
, a
->t
));
2708 gen_helper_vfp_fcvt_f16_to_f32(tmp
, tmp
, fpst
, ahp_mode
);
2709 vfp_store_reg32(tmp
, a
->vd
);
2710 tcg_temp_free_i32(ahp_mode
);
2711 tcg_temp_free_ptr(fpst
);
2712 tcg_temp_free_i32(tmp
);
2716 static bool trans_VCVT_f64_f16(DisasContext
*s
, arg_VCVT_f64_f16
*a
)
2723 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2727 if (!dc_isar_feature(aa32_fp16_dpconv
, s
)) {
2731 /* UNDEF accesses to D16-D31 if they don't exist. */
2732 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
2736 if (!vfp_access_check(s
)) {
2740 fpst
= fpstatus_ptr(FPST_FPCR
);
2741 ahp_mode
= get_ahp_flag();
2742 tmp
= tcg_temp_new_i32();
2743 /* The T bit tells us if we want the low or high 16 bits of Vm */
2744 tcg_gen_ld16u_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vm
, a
->t
));
2745 vd
= tcg_temp_new_i64();
2746 gen_helper_vfp_fcvt_f16_to_f64(vd
, tmp
, fpst
, ahp_mode
);
2747 vfp_store_reg64(vd
, a
->vd
);
2748 tcg_temp_free_i32(ahp_mode
);
2749 tcg_temp_free_ptr(fpst
);
2750 tcg_temp_free_i32(tmp
);
2751 tcg_temp_free_i64(vd
);
2755 static bool trans_VCVT_b16_f32(DisasContext
*s
, arg_VCVT_b16_f32
*a
)
2760 if (!dc_isar_feature(aa32_bf16
, s
)) {
2764 if (!vfp_access_check(s
)) {
2768 fpst
= fpstatus_ptr(FPST_FPCR
);
2769 tmp
= tcg_temp_new_i32();
2771 vfp_load_reg32(tmp
, a
->vm
);
2772 gen_helper_bfcvt(tmp
, tmp
, fpst
);
2773 tcg_gen_st16_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vd
, a
->t
));
2774 tcg_temp_free_ptr(fpst
);
2775 tcg_temp_free_i32(tmp
);
2779 static bool trans_VCVT_f16_f32(DisasContext
*s
, arg_VCVT_f16_f32
*a
)
2785 if (!dc_isar_feature(aa32_fp16_spconv
, s
)) {
2789 if (!vfp_access_check(s
)) {
2793 fpst
= fpstatus_ptr(FPST_FPCR
);
2794 ahp_mode
= get_ahp_flag();
2795 tmp
= tcg_temp_new_i32();
2797 vfp_load_reg32(tmp
, a
->vm
);
2798 gen_helper_vfp_fcvt_f32_to_f16(tmp
, tmp
, fpst
, ahp_mode
);
2799 tcg_gen_st16_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vd
, a
->t
));
2800 tcg_temp_free_i32(ahp_mode
);
2801 tcg_temp_free_ptr(fpst
);
2802 tcg_temp_free_i32(tmp
);
2806 static bool trans_VCVT_f16_f64(DisasContext
*s
, arg_VCVT_f16_f64
*a
)
2813 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2817 if (!dc_isar_feature(aa32_fp16_dpconv
, s
)) {
2821 /* UNDEF accesses to D16-D31 if they don't exist. */
2822 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
2826 if (!vfp_access_check(s
)) {
2830 fpst
= fpstatus_ptr(FPST_FPCR
);
2831 ahp_mode
= get_ahp_flag();
2832 tmp
= tcg_temp_new_i32();
2833 vm
= tcg_temp_new_i64();
2835 vfp_load_reg64(vm
, a
->vm
);
2836 gen_helper_vfp_fcvt_f64_to_f16(tmp
, vm
, fpst
, ahp_mode
);
2837 tcg_temp_free_i64(vm
);
2838 tcg_gen_st16_i32(tmp
, cpu_env
, vfp_f16_offset(a
->vd
, a
->t
));
2839 tcg_temp_free_i32(ahp_mode
);
2840 tcg_temp_free_ptr(fpst
);
2841 tcg_temp_free_i32(tmp
);
2845 static bool trans_VRINTR_hp(DisasContext
*s
, arg_VRINTR_sp
*a
)
2850 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
2854 if (!vfp_access_check(s
)) {
2858 tmp
= tcg_temp_new_i32();
2859 vfp_load_reg32(tmp
, a
->vm
);
2860 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
2861 gen_helper_rinth(tmp
, tmp
, fpst
);
2862 vfp_store_reg32(tmp
, a
->vd
);
2863 tcg_temp_free_ptr(fpst
);
2864 tcg_temp_free_i32(tmp
);
2868 static bool trans_VRINTR_sp(DisasContext
*s
, arg_VRINTR_sp
*a
)
2873 if (!dc_isar_feature(aa32_vrint
, s
)) {
2877 if (!vfp_access_check(s
)) {
2881 tmp
= tcg_temp_new_i32();
2882 vfp_load_reg32(tmp
, a
->vm
);
2883 fpst
= fpstatus_ptr(FPST_FPCR
);
2884 gen_helper_rints(tmp
, tmp
, fpst
);
2885 vfp_store_reg32(tmp
, a
->vd
);
2886 tcg_temp_free_ptr(fpst
);
2887 tcg_temp_free_i32(tmp
);
2891 static bool trans_VRINTR_dp(DisasContext
*s
, arg_VRINTR_dp
*a
)
2896 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2900 if (!dc_isar_feature(aa32_vrint
, s
)) {
2904 /* UNDEF accesses to D16-D31 if they don't exist. */
2905 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((a
->vd
| a
->vm
) & 0x10)) {
2909 if (!vfp_access_check(s
)) {
2913 tmp
= tcg_temp_new_i64();
2914 vfp_load_reg64(tmp
, a
->vm
);
2915 fpst
= fpstatus_ptr(FPST_FPCR
);
2916 gen_helper_rintd(tmp
, tmp
, fpst
);
2917 vfp_store_reg64(tmp
, a
->vd
);
2918 tcg_temp_free_ptr(fpst
);
2919 tcg_temp_free_i64(tmp
);
2923 static bool trans_VRINTZ_hp(DisasContext
*s
, arg_VRINTZ_sp
*a
)
2929 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
2933 if (!vfp_access_check(s
)) {
2937 tmp
= tcg_temp_new_i32();
2938 vfp_load_reg32(tmp
, a
->vm
);
2939 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
2940 tcg_rmode
= tcg_const_i32(float_round_to_zero
);
2941 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
2942 gen_helper_rinth(tmp
, tmp
, fpst
);
2943 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
2944 vfp_store_reg32(tmp
, a
->vd
);
2945 tcg_temp_free_ptr(fpst
);
2946 tcg_temp_free_i32(tcg_rmode
);
2947 tcg_temp_free_i32(tmp
);
2951 static bool trans_VRINTZ_sp(DisasContext
*s
, arg_VRINTZ_sp
*a
)
2957 if (!dc_isar_feature(aa32_vrint
, s
)) {
2961 if (!vfp_access_check(s
)) {
2965 tmp
= tcg_temp_new_i32();
2966 vfp_load_reg32(tmp
, a
->vm
);
2967 fpst
= fpstatus_ptr(FPST_FPCR
);
2968 tcg_rmode
= tcg_const_i32(float_round_to_zero
);
2969 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
2970 gen_helper_rints(tmp
, tmp
, fpst
);
2971 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
2972 vfp_store_reg32(tmp
, a
->vd
);
2973 tcg_temp_free_ptr(fpst
);
2974 tcg_temp_free_i32(tcg_rmode
);
2975 tcg_temp_free_i32(tmp
);
2979 static bool trans_VRINTZ_dp(DisasContext
*s
, arg_VRINTZ_dp
*a
)
2985 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
2989 if (!dc_isar_feature(aa32_vrint
, s
)) {
2993 /* UNDEF accesses to D16-D31 if they don't exist. */
2994 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((a
->vd
| a
->vm
) & 0x10)) {
2998 if (!vfp_access_check(s
)) {
3002 tmp
= tcg_temp_new_i64();
3003 vfp_load_reg64(tmp
, a
->vm
);
3004 fpst
= fpstatus_ptr(FPST_FPCR
);
3005 tcg_rmode
= tcg_const_i32(float_round_to_zero
);
3006 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
3007 gen_helper_rintd(tmp
, tmp
, fpst
);
3008 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
3009 vfp_store_reg64(tmp
, a
->vd
);
3010 tcg_temp_free_ptr(fpst
);
3011 tcg_temp_free_i64(tmp
);
3012 tcg_temp_free_i32(tcg_rmode
);
3016 static bool trans_VRINTX_hp(DisasContext
*s
, arg_VRINTX_sp
*a
)
3021 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
3025 if (!vfp_access_check(s
)) {
3029 tmp
= tcg_temp_new_i32();
3030 vfp_load_reg32(tmp
, a
->vm
);
3031 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
3032 gen_helper_rinth_exact(tmp
, tmp
, fpst
);
3033 vfp_store_reg32(tmp
, a
->vd
);
3034 tcg_temp_free_ptr(fpst
);
3035 tcg_temp_free_i32(tmp
);
3039 static bool trans_VRINTX_sp(DisasContext
*s
, arg_VRINTX_sp
*a
)
3044 if (!dc_isar_feature(aa32_vrint
, s
)) {
3048 if (!vfp_access_check(s
)) {
3052 tmp
= tcg_temp_new_i32();
3053 vfp_load_reg32(tmp
, a
->vm
);
3054 fpst
= fpstatus_ptr(FPST_FPCR
);
3055 gen_helper_rints_exact(tmp
, tmp
, fpst
);
3056 vfp_store_reg32(tmp
, a
->vd
);
3057 tcg_temp_free_ptr(fpst
);
3058 tcg_temp_free_i32(tmp
);
3062 static bool trans_VRINTX_dp(DisasContext
*s
, arg_VRINTX_dp
*a
)
3067 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
3071 if (!dc_isar_feature(aa32_vrint
, s
)) {
3075 /* UNDEF accesses to D16-D31 if they don't exist. */
3076 if (!dc_isar_feature(aa32_simd_r32
, s
) && ((a
->vd
| a
->vm
) & 0x10)) {
3080 if (!vfp_access_check(s
)) {
3084 tmp
= tcg_temp_new_i64();
3085 vfp_load_reg64(tmp
, a
->vm
);
3086 fpst
= fpstatus_ptr(FPST_FPCR
);
3087 gen_helper_rintd_exact(tmp
, tmp
, fpst
);
3088 vfp_store_reg64(tmp
, a
->vd
);
3089 tcg_temp_free_ptr(fpst
);
3090 tcg_temp_free_i64(tmp
);
3094 static bool trans_VCVT_sp(DisasContext
*s
, arg_VCVT_sp
*a
)
3099 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
3103 /* UNDEF accesses to D16-D31 if they don't exist. */
3104 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
3108 if (!vfp_access_check(s
)) {
3112 vm
= tcg_temp_new_i32();
3113 vd
= tcg_temp_new_i64();
3114 vfp_load_reg32(vm
, a
->vm
);
3115 gen_helper_vfp_fcvtds(vd
, vm
, cpu_env
);
3116 vfp_store_reg64(vd
, a
->vd
);
3117 tcg_temp_free_i32(vm
);
3118 tcg_temp_free_i64(vd
);
3122 static bool trans_VCVT_dp(DisasContext
*s
, arg_VCVT_dp
*a
)
3127 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
3131 /* UNDEF accesses to D16-D31 if they don't exist. */
3132 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
3136 if (!vfp_access_check(s
)) {
3140 vd
= tcg_temp_new_i32();
3141 vm
= tcg_temp_new_i64();
3142 vfp_load_reg64(vm
, a
->vm
);
3143 gen_helper_vfp_fcvtsd(vd
, vm
, cpu_env
);
3144 vfp_store_reg32(vd
, a
->vd
);
3145 tcg_temp_free_i32(vd
);
3146 tcg_temp_free_i64(vm
);
3150 static bool trans_VCVT_int_hp(DisasContext
*s
, arg_VCVT_int_sp
*a
)
3155 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
3159 if (!vfp_access_check(s
)) {
3163 vm
= tcg_temp_new_i32();
3164 vfp_load_reg32(vm
, a
->vm
);
3165 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
3168 gen_helper_vfp_sitoh(vm
, vm
, fpst
);
3171 gen_helper_vfp_uitoh(vm
, vm
, fpst
);
3173 vfp_store_reg32(vm
, a
->vd
);
3174 tcg_temp_free_i32(vm
);
3175 tcg_temp_free_ptr(fpst
);
3179 static bool trans_VCVT_int_sp(DisasContext
*s
, arg_VCVT_int_sp
*a
)
3184 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
3188 if (!vfp_access_check(s
)) {
3192 vm
= tcg_temp_new_i32();
3193 vfp_load_reg32(vm
, a
->vm
);
3194 fpst
= fpstatus_ptr(FPST_FPCR
);
3197 gen_helper_vfp_sitos(vm
, vm
, fpst
);
3200 gen_helper_vfp_uitos(vm
, vm
, fpst
);
3202 vfp_store_reg32(vm
, a
->vd
);
3203 tcg_temp_free_i32(vm
);
3204 tcg_temp_free_ptr(fpst
);
3208 static bool trans_VCVT_int_dp(DisasContext
*s
, arg_VCVT_int_dp
*a
)
3214 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
3218 /* UNDEF accesses to D16-D31 if they don't exist. */
3219 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
3223 if (!vfp_access_check(s
)) {
3227 vm
= tcg_temp_new_i32();
3228 vd
= tcg_temp_new_i64();
3229 vfp_load_reg32(vm
, a
->vm
);
3230 fpst
= fpstatus_ptr(FPST_FPCR
);
3233 gen_helper_vfp_sitod(vd
, vm
, fpst
);
3236 gen_helper_vfp_uitod(vd
, vm
, fpst
);
3238 vfp_store_reg64(vd
, a
->vd
);
3239 tcg_temp_free_i32(vm
);
3240 tcg_temp_free_i64(vd
);
3241 tcg_temp_free_ptr(fpst
);
3245 static bool trans_VJCVT(DisasContext
*s
, arg_VJCVT
*a
)
3250 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
3254 if (!dc_isar_feature(aa32_jscvt
, s
)) {
3258 /* UNDEF accesses to D16-D31 if they don't exist. */
3259 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
3263 if (!vfp_access_check(s
)) {
3267 vm
= tcg_temp_new_i64();
3268 vd
= tcg_temp_new_i32();
3269 vfp_load_reg64(vm
, a
->vm
);
3270 gen_helper_vjcvt(vd
, vm
, cpu_env
);
3271 vfp_store_reg32(vd
, a
->vd
);
3272 tcg_temp_free_i64(vm
);
3273 tcg_temp_free_i32(vd
);
3277 static bool trans_VCVT_fix_hp(DisasContext
*s
, arg_VCVT_fix_sp
*a
)
3283 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
3287 if (!vfp_access_check(s
)) {
3291 frac_bits
= (a
->opc
& 1) ? (32 - a
->imm
) : (16 - a
->imm
);
3293 vd
= tcg_temp_new_i32();
3294 vfp_load_reg32(vd
, a
->vd
);
3296 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
3297 shift
= tcg_const_i32(frac_bits
);
3299 /* Switch on op:U:sx bits */
3302 gen_helper_vfp_shtoh_round_to_nearest(vd
, vd
, shift
, fpst
);
3305 gen_helper_vfp_sltoh_round_to_nearest(vd
, vd
, shift
, fpst
);
3308 gen_helper_vfp_uhtoh_round_to_nearest(vd
, vd
, shift
, fpst
);
3311 gen_helper_vfp_ultoh_round_to_nearest(vd
, vd
, shift
, fpst
);
3314 gen_helper_vfp_toshh_round_to_zero(vd
, vd
, shift
, fpst
);
3317 gen_helper_vfp_toslh_round_to_zero(vd
, vd
, shift
, fpst
);
3320 gen_helper_vfp_touhh_round_to_zero(vd
, vd
, shift
, fpst
);
3323 gen_helper_vfp_toulh_round_to_zero(vd
, vd
, shift
, fpst
);
3326 g_assert_not_reached();
3329 vfp_store_reg32(vd
, a
->vd
);
3330 tcg_temp_free_i32(vd
);
3331 tcg_temp_free_i32(shift
);
3332 tcg_temp_free_ptr(fpst
);
3336 static bool trans_VCVT_fix_sp(DisasContext
*s
, arg_VCVT_fix_sp
*a
)
3342 if (!dc_isar_feature(aa32_fpsp_v3
, s
)) {
3346 if (!vfp_access_check(s
)) {
3350 frac_bits
= (a
->opc
& 1) ? (32 - a
->imm
) : (16 - a
->imm
);
3352 vd
= tcg_temp_new_i32();
3353 vfp_load_reg32(vd
, a
->vd
);
3355 fpst
= fpstatus_ptr(FPST_FPCR
);
3356 shift
= tcg_const_i32(frac_bits
);
3358 /* Switch on op:U:sx bits */
3361 gen_helper_vfp_shtos_round_to_nearest(vd
, vd
, shift
, fpst
);
3364 gen_helper_vfp_sltos_round_to_nearest(vd
, vd
, shift
, fpst
);
3367 gen_helper_vfp_uhtos_round_to_nearest(vd
, vd
, shift
, fpst
);
3370 gen_helper_vfp_ultos_round_to_nearest(vd
, vd
, shift
, fpst
);
3373 gen_helper_vfp_toshs_round_to_zero(vd
, vd
, shift
, fpst
);
3376 gen_helper_vfp_tosls_round_to_zero(vd
, vd
, shift
, fpst
);
3379 gen_helper_vfp_touhs_round_to_zero(vd
, vd
, shift
, fpst
);
3382 gen_helper_vfp_touls_round_to_zero(vd
, vd
, shift
, fpst
);
3385 g_assert_not_reached();
3388 vfp_store_reg32(vd
, a
->vd
);
3389 tcg_temp_free_i32(vd
);
3390 tcg_temp_free_i32(shift
);
3391 tcg_temp_free_ptr(fpst
);
3395 static bool trans_VCVT_fix_dp(DisasContext
*s
, arg_VCVT_fix_dp
*a
)
3402 if (!dc_isar_feature(aa32_fpdp_v3
, s
)) {
3406 /* UNDEF accesses to D16-D31 if they don't exist. */
3407 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vd
& 0x10)) {
3411 if (!vfp_access_check(s
)) {
3415 frac_bits
= (a
->opc
& 1) ? (32 - a
->imm
) : (16 - a
->imm
);
3417 vd
= tcg_temp_new_i64();
3418 vfp_load_reg64(vd
, a
->vd
);
3420 fpst
= fpstatus_ptr(FPST_FPCR
);
3421 shift
= tcg_const_i32(frac_bits
);
3423 /* Switch on op:U:sx bits */
3426 gen_helper_vfp_shtod_round_to_nearest(vd
, vd
, shift
, fpst
);
3429 gen_helper_vfp_sltod_round_to_nearest(vd
, vd
, shift
, fpst
);
3432 gen_helper_vfp_uhtod_round_to_nearest(vd
, vd
, shift
, fpst
);
3435 gen_helper_vfp_ultod_round_to_nearest(vd
, vd
, shift
, fpst
);
3438 gen_helper_vfp_toshd_round_to_zero(vd
, vd
, shift
, fpst
);
3441 gen_helper_vfp_tosld_round_to_zero(vd
, vd
, shift
, fpst
);
3444 gen_helper_vfp_touhd_round_to_zero(vd
, vd
, shift
, fpst
);
3447 gen_helper_vfp_tould_round_to_zero(vd
, vd
, shift
, fpst
);
3450 g_assert_not_reached();
3453 vfp_store_reg64(vd
, a
->vd
);
3454 tcg_temp_free_i64(vd
);
3455 tcg_temp_free_i32(shift
);
3456 tcg_temp_free_ptr(fpst
);
3460 static bool trans_VCVT_hp_int(DisasContext
*s
, arg_VCVT_sp_int
*a
)
3465 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
3469 if (!vfp_access_check(s
)) {
3473 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
3474 vm
= tcg_temp_new_i32();
3475 vfp_load_reg32(vm
, a
->vm
);
3479 gen_helper_vfp_tosizh(vm
, vm
, fpst
);
3481 gen_helper_vfp_tosih(vm
, vm
, fpst
);
3485 gen_helper_vfp_touizh(vm
, vm
, fpst
);
3487 gen_helper_vfp_touih(vm
, vm
, fpst
);
3490 vfp_store_reg32(vm
, a
->vd
);
3491 tcg_temp_free_i32(vm
);
3492 tcg_temp_free_ptr(fpst
);
3496 static bool trans_VCVT_sp_int(DisasContext
*s
, arg_VCVT_sp_int
*a
)
3501 if (!dc_isar_feature(aa32_fpsp_v2
, s
)) {
3505 if (!vfp_access_check(s
)) {
3509 fpst
= fpstatus_ptr(FPST_FPCR
);
3510 vm
= tcg_temp_new_i32();
3511 vfp_load_reg32(vm
, a
->vm
);
3515 gen_helper_vfp_tosizs(vm
, vm
, fpst
);
3517 gen_helper_vfp_tosis(vm
, vm
, fpst
);
3521 gen_helper_vfp_touizs(vm
, vm
, fpst
);
3523 gen_helper_vfp_touis(vm
, vm
, fpst
);
3526 vfp_store_reg32(vm
, a
->vd
);
3527 tcg_temp_free_i32(vm
);
3528 tcg_temp_free_ptr(fpst
);
3532 static bool trans_VCVT_dp_int(DisasContext
*s
, arg_VCVT_dp_int
*a
)
3538 if (!dc_isar_feature(aa32_fpdp_v2
, s
)) {
3542 /* UNDEF accesses to D16-D31 if they don't exist. */
3543 if (!dc_isar_feature(aa32_simd_r32
, s
) && (a
->vm
& 0x10)) {
3547 if (!vfp_access_check(s
)) {
3551 fpst
= fpstatus_ptr(FPST_FPCR
);
3552 vm
= tcg_temp_new_i64();
3553 vd
= tcg_temp_new_i32();
3554 vfp_load_reg64(vm
, a
->vm
);
3558 gen_helper_vfp_tosizd(vd
, vm
, fpst
);
3560 gen_helper_vfp_tosid(vd
, vm
, fpst
);
3564 gen_helper_vfp_touizd(vd
, vm
, fpst
);
3566 gen_helper_vfp_touid(vd
, vm
, fpst
);
3569 vfp_store_reg32(vd
, a
->vd
);
3570 tcg_temp_free_i32(vd
);
3571 tcg_temp_free_i64(vm
);
3572 tcg_temp_free_ptr(fpst
);
3576 static bool trans_VINS(DisasContext
*s
, arg_VINS
*a
)
3580 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
3584 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
3588 if (!vfp_access_check(s
)) {
3592 /* Insert low half of Vm into high half of Vd */
3593 rm
= tcg_temp_new_i32();
3594 rd
= tcg_temp_new_i32();
3595 vfp_load_reg32(rm
, a
->vm
);
3596 vfp_load_reg32(rd
, a
->vd
);
3597 tcg_gen_deposit_i32(rd
, rd
, rm
, 16, 16);
3598 vfp_store_reg32(rd
, a
->vd
);
3599 tcg_temp_free_i32(rm
);
3600 tcg_temp_free_i32(rd
);
3604 static bool trans_VMOVX(DisasContext
*s
, arg_VINS
*a
)
3608 if (!dc_isar_feature(aa32_fp16_arith
, s
)) {
3612 if (s
->vec_len
!= 0 || s
->vec_stride
!= 0) {
3616 if (!vfp_access_check(s
)) {
3620 /* Set Vd to high half of Vm */
3621 rm
= tcg_temp_new_i32();
3622 vfp_load_reg32(rm
, a
->vm
);
3623 tcg_gen_shri_i32(rm
, rm
, 16);
3624 vfp_store_reg32(rm
, a
->vd
);
3625 tcg_temp_free_i32(rm
);