hw/display/virtio-vga.c

   1 #include "qemu/osdep.h"
   2 #include "hw/pci/pci.h"
   3 #include "hw/qdev-properties.h"
   4 #include "hw/virtio/virtio-gpu.h"
   5 #include "qapi/error.h"
   6 #include "qemu/module.h"
   7 #include "virtio-vga.h"
   8 #include "qom/object.h"
   9
  10 static void virtio_vga_base_invalidate_display(void *opaque)
  11 {
  12     VirtIOVGABase *vvga = opaque;
  13     VirtIOGPUBase *g = vvga->vgpu;
  14
  15     if (g->enable) {
  16         g->hw_ops->invalidate(g);
  17     } else {
  18         vvga->vga.hw_ops->invalidate(&vvga->vga);
  19     }
  20 }
  21
  22 static void virtio_vga_base_update_display(void *opaque)
  23 {
  24     VirtIOVGABase *vvga = opaque;
  25     VirtIOGPUBase *g = vvga->vgpu;
  26
  27     if (g->enable) {
  28         g->hw_ops->gfx_update(g);
  29     } else {
  30         vvga->vga.hw_ops->gfx_update(&vvga->vga);
  31     }
  32 }
  33
  34 static void virtio_vga_base_text_update(void *opaque, console_ch_t *chardata)
  35 {
  36     VirtIOVGABase *vvga = opaque;
  37     VirtIOGPUBase *g = vvga->vgpu;
  38
  39     if (g->enable) {
  40         if (g->hw_ops->text_update) {
  41             g->hw_ops->text_update(g, chardata);
  42         }
  43     } else {
  44         if (vvga->vga.hw_ops->text_update) {
  45             vvga->vga.hw_ops->text_update(&vvga->vga, chardata);
  46         }
  47     }
  48 }
  49
  50 static int virtio_vga_base_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
  51 {
  52     VirtIOVGABase *vvga = opaque;
  53     VirtIOGPUBase *g = vvga->vgpu;
  54
  55     if (g->hw_ops->ui_info) {
  56         return g->hw_ops->ui_info(g, idx, info);
  57     }
  58     return -1;
  59 }
  60
  61 static void virtio_vga_base_gl_block(void *opaque, bool block)
  62 {
  63     VirtIOVGABase *vvga = opaque;
  64     VirtIOGPUBase *g = vvga->vgpu;
  65
  66     if (g->hw_ops->gl_block) {
  67         g->hw_ops->gl_block(g, block);
  68     }
  69 }
  70
  71 static int virtio_vga_base_get_flags(void *opaque)
  72 {
  73     VirtIOVGABase *vvga = opaque;
  74     VirtIOGPUBase *g = vvga->vgpu;
  75
  76     return g->hw_ops->get_flags(g);
  77 }
  78
  79 static const GraphicHwOps virtio_vga_base_ops = {
  80     .get_flags = virtio_vga_base_get_flags,
  81     .invalidate = virtio_vga_base_invalidate_display,
  82     .gfx_update = virtio_vga_base_update_display,
  83     .text_update = virtio_vga_base_text_update,
  84     .ui_info = virtio_vga_base_ui_info,
  85     .gl_block = virtio_vga_base_gl_block,
  86 };
  87
  88 static const VMStateDescription vmstate_virtio_vga_base = {
  89     .name = "virtio-vga",
  90     .version_id = 2,
  91     .minimum_version_id = 2,
  92     .fields = (VMStateField[]) {
  93         /* no pci stuff here, saving the virtio device will handle that */
  94         VMSTATE_STRUCT(vga, VirtIOVGABase, 0,
  95                        vmstate_vga_common, VGACommonState),
  96         VMSTATE_END_OF_LIST()
  97     }
  98 };
  99
 100 /* VGA device wrapper around PCI device around virtio GPU */
 101 static void virtio_vga_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
 102 {
 103     VirtIOVGABase *vvga = VIRTIO_VGA_BASE(vpci_dev);
 104     VirtIOGPUBase *g = vvga->vgpu;
 105     VGACommonState *vga = &vvga->vga;
 106     uint32_t offset;
 107     int i;
 108
 109     /* init vga compat bits */
 110     vga->vram_size_mb = 8;
 111     vga_common_init(vga, OBJECT(vpci_dev));
 112     vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev),
 113              pci_address_space_io(&vpci_dev->pci_dev), true);
 114     pci_register_bar(&vpci_dev->pci_dev, 0,
 115                      PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram);
 116
 117     /*
 118      * Configure virtio bar and regions
 119      *
 120      * We use bar #2 for the mmio regions, to be compatible with stdvga.
 121      * virtio regions are moved to the end of bar #2, to make room for
 122      * the stdvga mmio registers at the start of bar #2.
 123      */
 124     vpci_dev->modern_mem_bar_idx = 2;
 125     vpci_dev->msix_bar_idx = 4;
 126     vpci_dev->modern_io_bar_idx = 5;
 127
 128     if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) {
 129         /*
 130          * with page-per-vq=off there is no padding space we can use
 131          * for the stdvga registers.  Make the common and isr regions
 132          * smaller then.
 133          */
 134         vpci_dev->common.size /= 2;
 135         vpci_dev->isr.size /= 2;
 136     }
 137
 138     offset = memory_region_size(&vpci_dev->modern_bar);
 139     offset -= vpci_dev->notify.size;
 140     vpci_dev->notify.offset = offset;
 141     offset -= vpci_dev->device.size;
 142     vpci_dev->device.offset = offset;
 143     offset -= vpci_dev->isr.size;
 144     vpci_dev->isr.offset = offset;
 145     offset -= vpci_dev->common.size;
 146     vpci_dev->common.offset = offset;
 147
 148     /* init virtio bits */
 149     virtio_pci_force_virtio_1(vpci_dev);
 150     if (!qdev_realize(DEVICE(g), BUS(&vpci_dev->bus), errp)) {
 151         return;
 152     }
 153
 154     /* add stdvga mmio regions */
 155     pci_std_vga_mmio_region_init(vga, OBJECT(vvga), &vpci_dev->modern_bar,
 156                                  vvga->vga_mrs, true, false);
 157
 158     vga->con = g->scanout[0].con;
 159     graphic_console_set_hwops(vga->con, &virtio_vga_base_ops, vvga);
 160
 161     for (i = 0; i < g->conf.max_outputs; i++) {
 162         object_property_set_link(OBJECT(g->scanout[i].con), "device",
 163                                  OBJECT(vpci_dev), &error_abort);
 164     }
 165 }
 166
 167 static void virtio_vga_base_reset(DeviceState *dev)
 168 {
 169     VirtIOVGABaseClass *klass = VIRTIO_VGA_BASE_GET_CLASS(dev);
 170     VirtIOVGABase *vvga = VIRTIO_VGA_BASE(dev);
 171
 172     /* reset virtio-gpu */
 173     klass->parent_reset(dev);
 174
 175     /* reset vga */
 176     vga_common_reset(&vvga->vga);
 177     vga_dirty_log_start(&vvga->vga);
 178 }
 179
 180 static bool virtio_vga_get_big_endian_fb(Object *obj, Error **errp)
 181 {
 182     VirtIOVGABase *d = VIRTIO_VGA_BASE(obj);
 183
 184     return d->vga.big_endian_fb;
 185 }
 186
 187 static void virtio_vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
 188 {
 189     VirtIOVGABase *d = VIRTIO_VGA_BASE(obj);
 190
 191     d->vga.big_endian_fb = value;
 192 }
 193
 194 static Property virtio_vga_base_properties[] = {
 195     DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy),
 196     DEFINE_PROP_END_OF_LIST(),
 197 };
 198
 199 static void virtio_vga_base_class_init(ObjectClass *klass, void *data)
 200 {
 201     DeviceClass *dc = DEVICE_CLASS(klass);
 202     VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass);
 203     VirtIOVGABaseClass *v = VIRTIO_VGA_BASE_CLASS(klass);
 204     PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass);
 205
 206     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 207     device_class_set_props(dc, virtio_vga_base_properties);
 208     dc->vmsd = &vmstate_virtio_vga_base;
 209     dc->hotpluggable = false;
 210     device_class_set_parent_reset(dc, virtio_vga_base_reset,
 211                                   &v->parent_reset);
 212
 213     k->realize = virtio_vga_base_realize;
 214     pcidev_k->romfile = "vgabios-virtio.bin";
 215     pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA;
 216
 217     /* Expose framebuffer byteorder via QOM */
 218     object_class_property_add_bool(klass, "big-endian-framebuffer",
 219                                    virtio_vga_get_big_endian_fb,
 220                                    virtio_vga_set_big_endian_fb);
 221 }
 222
 223 static TypeInfo virtio_vga_base_info = {
 224     .name          = TYPE_VIRTIO_VGA_BASE,
 225     .parent        = TYPE_VIRTIO_PCI,
 226     .instance_size = sizeof(VirtIOVGABase),
 227     .class_size    = sizeof(VirtIOVGABaseClass),
 228     .class_init    = virtio_vga_base_class_init,
 229     .abstract      = true,
 230 };
 231 module_obj(TYPE_VIRTIO_VGA_BASE);
 232
 233 #define TYPE_VIRTIO_VGA "virtio-vga"
 234
 235 typedef struct VirtIOVGA VirtIOVGA;
 236 DECLARE_INSTANCE_CHECKER(VirtIOVGA, VIRTIO_VGA,
 237                          TYPE_VIRTIO_VGA)
 238
 239 struct VirtIOVGA {
 240     VirtIOVGABase parent_obj;
 241
 242     VirtIOGPU     vdev;
 243 };
 244
 245 static void virtio_vga_inst_initfn(Object *obj)
 246 {
 247     VirtIOVGA *dev = VIRTIO_VGA(obj);
 248
 249     virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev),
 250                                 TYPE_VIRTIO_GPU);
 251     VIRTIO_VGA_BASE(dev)->vgpu = VIRTIO_GPU_BASE(&dev->vdev);
 252 }
 253
 254
 255 static VirtioPCIDeviceTypeInfo virtio_vga_info = {
 256     .generic_name  = TYPE_VIRTIO_VGA,
 257     .parent        = TYPE_VIRTIO_VGA_BASE,
 258     .instance_size = sizeof(VirtIOVGA),
 259     .instance_init = virtio_vga_inst_initfn,
 260 };
 261 module_obj(TYPE_VIRTIO_VGA);
 262
 263 static void virtio_vga_register_types(void)
 264 {
 265     type_register_static(&virtio_vga_base_info);
 266     virtio_pci_types_register(&virtio_vga_info);
 267 }
 268
 269 type_init(virtio_vga_register_types)