hw/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sun4m.h"
  26 #include "qemu-timer.h"
  27 #include "sysbus.h"
  28
  29 //#define DEBUG_TIMER
  30
  31 #ifdef DEBUG_TIMER
  32 #define DPRINTF(fmt, ...)                                       \
  33     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define DPRINTF(fmt, ...) do {} while (0)
  36 #endif
  37
  38 /*
  39  * Registers of hardware timer in sun4m.
  40  *
  41  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  42  * produced as NCR89C105. See
  43  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  44  *
  45  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  46  * are zero. Bit 31 is 1 when count has been reached.
  47  *
  48  * Per-CPU timers interrupt local CPU, system timer uses normal
  49  * interrupt routing.
  50  *
  51  */
  52
  53 #define MAX_CPUS 16
  54
  55 typedef struct CPUTimerState {
  56     qemu_irq irq;
  57     ptimer_state *timer;
  58     uint32_t count, counthigh, reached;
  59     uint64_t limit;
  60     // processor only
  61     uint32_t running;
  62 } CPUTimerState;
  63
  64 typedef struct SLAVIO_TIMERState {
  65     SysBusDevice busdev;
  66     uint32_t num_cpus;
  67     CPUTimerState cputimer[MAX_CPUS + 1];
  68     uint32_t cputimer_mode;
  69 } SLAVIO_TIMERState;
  70
  71 typedef struct TimerContext {
  72     SLAVIO_TIMERState *s;
  73     unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
  74 } TimerContext;
  75
  76 #define SYS_TIMER_SIZE 0x14
  77 #define CPU_TIMER_SIZE 0x10
  78
  79 #define TIMER_LIMIT         0
  80 #define TIMER_COUNTER       1
  81 #define TIMER_COUNTER_NORST 2
  82 #define TIMER_STATUS        3
  83 #define TIMER_MODE          4
  84
  85 #define TIMER_COUNT_MASK32 0xfffffe00
  86 #define TIMER_LIMIT_MASK32 0x7fffffff
  87 #define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
  88 #define TIMER_MAX_COUNT32  0x7ffffe00ULL
  89 #define TIMER_REACHED      0x80000000
  90 #define TIMER_PERIOD       500ULL // 500ns
  91 #define LIMIT_TO_PERIODS(l) ((l) >> 9)
  92 #define PERIODS_TO_LIMIT(l) ((l) << 9)
  93
  94 static int slavio_timer_is_user(TimerContext *tc)
  95 {
  96     SLAVIO_TIMERState *s = tc->s;
  97     unsigned int timer_index = tc->timer_index;
  98
  99     return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
 100 }
 101
 102 // Update count, set irq, update expire_time
 103 // Convert from ptimer countdown units
 104 static void slavio_timer_get_out(CPUTimerState *t)
 105 {
 106     uint64_t count, limit;
 107
 108     if (t->limit == 0) { /* free-run system or processor counter */
 109         limit = TIMER_MAX_COUNT32;
 110     } else {
 111         limit = t->limit;
 112     }
 113     if (t->timer) {
 114         count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
 115     } else {
 116         count = 0;
 117     }
 118     DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh,
 119             t->count);
 120     t->count = count & TIMER_COUNT_MASK32;
 121     t->counthigh = count >> 32;
 122 }
 123
 124 // timer callback
 125 static void slavio_timer_irq(void *opaque)
 126 {
 127     TimerContext *tc = opaque;
 128     SLAVIO_TIMERState *s = tc->s;
 129     CPUTimerState *t = &s->cputimer[tc->timer_index];
 130
 131     slavio_timer_get_out(t);
 132     DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
 133     t->reached = TIMER_REACHED;
 134     if (!slavio_timer_is_user(tc)) {
 135         qemu_irq_raise(t->irq);
 136     }
 137 }
 138
 139 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
 140 {
 141     TimerContext *tc = opaque;
 142     SLAVIO_TIMERState *s = tc->s;
 143     uint32_t saddr, ret;
 144     unsigned int timer_index = tc->timer_index;
 145     CPUTimerState *t = &s->cputimer[timer_index];
 146
 147     saddr = addr >> 2;
 148     switch (saddr) {
 149     case TIMER_LIMIT:
 150         // read limit (system counter mode) or read most signifying
 151         // part of counter (user mode)
 152         if (slavio_timer_is_user(tc)) {
 153             // read user timer MSW
 154             slavio_timer_get_out(t);
 155             ret = t->counthigh | t->reached;
 156         } else {
 157             // read limit
 158             // clear irq
 159             qemu_irq_lower(t->irq);
 160             t->reached = 0;
 161             ret = t->limit & TIMER_LIMIT_MASK32;
 162         }
 163         break;
 164     case TIMER_COUNTER:
 165         // read counter and reached bit (system mode) or read lsbits
 166         // of counter (user mode)
 167         slavio_timer_get_out(t);
 168         if (slavio_timer_is_user(tc)) { // read user timer LSW
 169             ret = t->count & TIMER_MAX_COUNT64;
 170         } else { // read limit
 171             ret = (t->count & TIMER_MAX_COUNT32) |
 172                 t->reached;
 173         }
 174         break;
 175     case TIMER_STATUS:
 176         // only available in processor counter/timer
 177         // read start/stop status
 178         if (timer_index > 0) {
 179             ret = t->running;
 180         } else {
 181             ret = 0;
 182         }
 183         break;
 184     case TIMER_MODE:
 185         // only available in system counter
 186         // read user/system mode
 187         ret = s->cputimer_mode;
 188         break;
 189     default:
 190         DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
 191         ret = 0;
 192         break;
 193     }
 194     DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
 195
 196     return ret;
 197 }
 198
 199 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
 200                                     uint32_t val)
 201 {
 202     TimerContext *tc = opaque;
 203     SLAVIO_TIMERState *s = tc->s;
 204     uint32_t saddr;
 205     unsigned int timer_index = tc->timer_index;
 206     CPUTimerState *t = &s->cputimer[timer_index];
 207
 208     DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
 209     saddr = addr >> 2;
 210     switch (saddr) {
 211     case TIMER_LIMIT:
 212         if (slavio_timer_is_user(tc)) {
 213             uint64_t count;
 214
 215             // set user counter MSW, reset counter
 216             t->limit = TIMER_MAX_COUNT64;
 217             t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
 218             t->reached = 0;
 219             count = ((uint64_t)t->counthigh << 32) | t->count;
 220             DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
 221                     timer_index, count);
 222             if (t->timer) {
 223                 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 224             }
 225         } else {
 226             // set limit, reset counter
 227             qemu_irq_lower(t->irq);
 228             t->limit = val & TIMER_MAX_COUNT32;
 229             if (t->timer) {
 230                 if (t->limit == 0) { /* free-run */
 231                     ptimer_set_limit(t->timer,
 232                                      LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 233                 } else {
 234                     ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
 235                 }
 236             }
 237         }
 238         break;
 239     case TIMER_COUNTER:
 240         if (slavio_timer_is_user(tc)) {
 241             uint64_t count;
 242
 243             // set user counter LSW, reset counter
 244             t->limit = TIMER_MAX_COUNT64;
 245             t->count = val & TIMER_MAX_COUNT64;
 246             t->reached = 0;
 247             count = ((uint64_t)t->counthigh) << 32 | t->count;
 248             DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
 249                     timer_index, count);
 250             if (t->timer) {
 251                 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 252             }
 253         } else
 254             DPRINTF("not user timer\n");
 255         break;
 256     case TIMER_COUNTER_NORST:
 257         // set limit without resetting counter
 258         t->limit = val & TIMER_MAX_COUNT32;
 259         if (t->timer) {
 260             if (t->limit == 0) { /* free-run */
 261                 ptimer_set_limit(t->timer,
 262                                  LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
 263             } else {
 264                 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
 265             }
 266         }
 267         break;
 268     case TIMER_STATUS:
 269         if (slavio_timer_is_user(tc)) {
 270             // start/stop user counter
 271             if ((val & 1) && !t->running) {
 272                 DPRINTF("processor %d user timer started\n",
 273                         timer_index);
 274                 if (t->timer) {
 275                     ptimer_run(t->timer, 0);
 276                 }
 277                 t->running = 1;
 278             } else if (!(val & 1) && t->running) {
 279                 DPRINTF("processor %d user timer stopped\n",
 280                         timer_index);
 281                 if (t->timer) {
 282                     ptimer_stop(t->timer);
 283                 }
 284                 t->running = 0;
 285             }
 286         }
 287         break;
 288     case TIMER_MODE:
 289         if (timer_index == 0) {
 290             unsigned int i;
 291
 292             for (i = 0; i < s->num_cpus; i++) {
 293                 unsigned int processor = 1 << i;
 294                 CPUTimerState *curr_timer = &s->cputimer[i + 1];
 295
 296                 // check for a change in timer mode for this processor
 297                 if ((val & processor) != (s->cputimer_mode & processor)) {
 298                     if (val & processor) { // counter -> user timer
 299                         qemu_irq_lower(curr_timer->irq);
 300                         // counters are always running
 301                         ptimer_stop(curr_timer->timer);
 302                         curr_timer->running = 0;
 303                         // user timer limit is always the same
 304                         curr_timer->limit = TIMER_MAX_COUNT64;
 305                         ptimer_set_limit(curr_timer->timer,
 306                                          LIMIT_TO_PERIODS(curr_timer->limit),
 307                                          1);
 308                         // set this processors user timer bit in config
 309                         // register
 310                         s->cputimer_mode |= processor;
 311                         DPRINTF("processor %d changed from counter to user "
 312                                 "timer\n", timer_index);
 313                     } else { // user timer -> counter
 314                         // stop the user timer if it is running
 315                         if (curr_timer->running) {
 316                             ptimer_stop(curr_timer->timer);
 317                         }
 318                         // start the counter
 319                         ptimer_run(curr_timer->timer, 0);
 320                         curr_timer->running = 1;
 321                         // clear this processors user timer bit in config
 322                         // register
 323                         s->cputimer_mode &= ~processor;
 324                         DPRINTF("processor %d changed from user timer to "
 325                                 "counter\n", timer_index);
 326                     }
 327                 }
 328             }
 329         } else {
 330             DPRINTF("not system timer\n");
 331         }
 332         break;
 333     default:
 334         DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
 335         break;
 336     }
 337 }
 338
 339 static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = {
 340     NULL,
 341     NULL,
 342     slavio_timer_mem_readl,
 343 };
 344
 345 static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = {
 346     NULL,
 347     NULL,
 348     slavio_timer_mem_writel,
 349 };
 350
 351 static void slavio_timer_save(QEMUFile *f, void *opaque)
 352 {
 353     SLAVIO_TIMERState *s = opaque;
 354     unsigned int i;
 355     CPUTimerState *curr_timer;
 356
 357     for (i = 0; i <= MAX_CPUS; i++) {
 358         curr_timer = &s->cputimer[i];
 359         qemu_put_be64s(f, &curr_timer->limit);
 360         qemu_put_be32s(f, &curr_timer->count);
 361         qemu_put_be32s(f, &curr_timer->counthigh);
 362         qemu_put_be32s(f, &curr_timer->reached);
 363         qemu_put_be32s(f, &curr_timer->running);
 364         if (curr_timer->timer) {
 365             qemu_put_ptimer(f, curr_timer->timer);
 366         }
 367     }
 368 }
 369
 370 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
 371 {
 372     SLAVIO_TIMERState *s = opaque;
 373     unsigned int i;
 374     CPUTimerState *curr_timer;
 375
 376     if (version_id != 3)
 377         return -EINVAL;
 378
 379     for (i = 0; i <= MAX_CPUS; i++) {
 380         curr_timer = &s->cputimer[i];
 381         qemu_get_be64s(f, &curr_timer->limit);
 382         qemu_get_be32s(f, &curr_timer->count);
 383         qemu_get_be32s(f, &curr_timer->counthigh);
 384         qemu_get_be32s(f, &curr_timer->reached);
 385         qemu_get_be32s(f, &curr_timer->running);
 386         if (curr_timer->timer) {
 387             qemu_get_ptimer(f, curr_timer->timer);
 388         }
 389     }
 390
 391     return 0;
 392 }
 393
 394 static void slavio_timer_reset(void *opaque)
 395 {
 396     SLAVIO_TIMERState *s = opaque;
 397     unsigned int i;
 398     CPUTimerState *curr_timer;
 399
 400     for (i = 0; i <= MAX_CPUS; i++) {
 401         curr_timer = &s->cputimer[i];
 402         curr_timer->limit = 0;
 403         curr_timer->count = 0;
 404         curr_timer->reached = 0;
 405         if (i < s->num_cpus) {
 406             ptimer_set_limit(curr_timer->timer,
 407                              LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 408             ptimer_run(curr_timer->timer, 0);
 409         }
 410         curr_timer->running = 1;
 411     }
 412     s->cputimer_mode = 0;
 413 }
 414
 415 static int slavio_timer_init1(SysBusDevice *dev)
 416 {
 417     int io;
 418     SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
 419     QEMUBH *bh;
 420     unsigned int i;
 421     TimerContext *tc;
 422
 423     for (i = 0; i <= MAX_CPUS; i++) {
 424         tc = qemu_mallocz(sizeof(TimerContext));
 425         tc->s = s;
 426         tc->timer_index = i;
 427
 428         bh = qemu_bh_new(slavio_timer_irq, tc);
 429         s->cputimer[i].timer = ptimer_init(bh);
 430         ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
 431
 432         io = cpu_register_io_memory(slavio_timer_mem_read,
 433                                     slavio_timer_mem_write, tc);
 434         if (i == 0) {
 435             sysbus_init_mmio(dev, SYS_TIMER_SIZE, io);
 436         } else {
 437             sysbus_init_mmio(dev, CPU_TIMER_SIZE, io);
 438         }
 439
 440         sysbus_init_irq(dev, &s->cputimer[i].irq);
 441     }
 442
 443     register_savevm("slavio_timer", -1, 3, slavio_timer_save,
 444                     slavio_timer_load, s);
 445     qemu_register_reset(slavio_timer_reset, s);
 446     slavio_timer_reset(s);
 447     return 0;
 448 }
 449
 450 static SysBusDeviceInfo slavio_timer_info = {
 451     .init = slavio_timer_init1,
 452     .qdev.name  = "slavio_timer",
 453     .qdev.size  = sizeof(SLAVIO_TIMERState),
 454     .qdev.props = (Property[]) {
 455         DEFINE_PROP_UINT32("num_cpus",  SLAVIO_TIMERState, num_cpus,  0),
 456         DEFINE_PROP_END_OF_LIST(),
 457     }
 458 };
 459
 460 static void slavio_timer_register_devices(void)
 461 {
 462     sysbus_register_withprop(&slavio_timer_info);
 463 }
 464
 465 device_init(slavio_timer_register_devices)