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hw/pcie: better hotplug/hotunplug support
[qemu.git] / target-ppc / cpu.h
blob74407ee209d3a290cc96023e8b4884a37346c024
1 /*
2 * PowerPC emulation cpu definitions for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined (__CPU_PPC_H__)
20 #define __CPU_PPC_H__
21
22 #include "config.h"
23 #include "qemu-common.h"
24
25 //#define PPC_EMULATE_32BITS_HYPV
26
27 #if defined (TARGET_PPC64)
28 /* PowerPC 64 definitions */
29 #define TARGET_LONG_BITS 64
30 #define TARGET_PAGE_BITS 12
31
32 /* Note that the official physical address space bits is 62-M where M
33 is implementation dependent. I've not looked up M for the set of
34 cpus we emulate at the system level. */
35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
36
37 /* Note that the PPC environment architecture talks about 80 bit virtual
38 addresses, with segmentation. Obviously that's not all visible to a
39 single process, which is all we're concerned with here. */
40 #ifdef TARGET_ABI32
41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
42 #else
43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
44 #endif
45
46 #define TARGET_PAGE_BITS_16M 24
47
48 #else /* defined (TARGET_PPC64) */
49 /* PowerPC 32 definitions */
50 #define TARGET_LONG_BITS 32
51
52 #if defined(TARGET_PPCEMB)
53 /* Specific definitions for PowerPC embedded */
54 /* BookE have 36 bits physical address space */
55 #if defined(CONFIG_USER_ONLY)
56 /* It looks like a lot of Linux programs assume page size
57 * is 4kB long. This is evil, but we have to deal with it...
58 */
59 #define TARGET_PAGE_BITS 12
60 #else /* defined(CONFIG_USER_ONLY) */
61 /* Pages can be 1 kB small */
62 #define TARGET_PAGE_BITS 10
63 #endif /* defined(CONFIG_USER_ONLY) */
64 #else /* defined(TARGET_PPCEMB) */
65 /* "standard" PowerPC 32 definitions */
66 #define TARGET_PAGE_BITS 12
67 #endif /* defined(TARGET_PPCEMB) */
68
69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
71
72 #endif /* defined (TARGET_PPC64) */
73
74 #define CPUArchState struct CPUPPCState
75
76 #include "exec/cpu-defs.h"
77
78 #include "fpu/softfloat.h"
79
80 #define TARGET_HAS_ICE 1
81
82 #if defined (TARGET_PPC64)
83 #define ELF_MACHINE EM_PPC64
84 #else
85 #define ELF_MACHINE EM_PPC
86 #endif
87
88 /*****************************************************************************/
89 /* MMU model */
90 typedef enum powerpc_mmu_t powerpc_mmu_t;
91 enum powerpc_mmu_t {
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93 /* Standard 32 bits PowerPC MMU */
94 POWERPC_MMU_32B = 0x00000001,
95 /* PowerPC 6xx MMU with software TLB */
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97 /* PowerPC 74xx MMU with software TLB */
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99 /* PowerPC 4xx MMU with software TLB */
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101 /* PowerPC 4xx MMU with software TLB and zones protections */
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103 /* PowerPC MMU in real mode only */
104 POWERPC_MMU_REAL = 0x00000006,
105 /* Freescale MPC8xx MMU model */
106 POWERPC_MMU_MPC8xx = 0x00000007,
107 /* BookE MMU model */
108 POWERPC_MMU_BOOKE = 0x00000008,
109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
111 /* PowerPC 601 MMU model (specific BATs format) */
112 POWERPC_MMU_601 = 0x0000000A,
113 #if defined(TARGET_PPC64)
114 #define POWERPC_MMU_64 0x00010000
115 #define POWERPC_MMU_1TSEG 0x00020000
116 #define POWERPC_MMU_AMR 0x00040000
117 /* 64 bits PowerPC MMU */
118 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
119 /* Architecture 2.06 variant */
120 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
121 | POWERPC_MMU_AMR | 0x00000003,
122 /* Architecture 2.06 "degraded" (no 1T segments) */
123 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
124 | 0x00000003,
125 /* Architecture 2.06 "degraded" (no 1T segments or AMR) */
126 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
127 #endif /* defined(TARGET_PPC64) */
128 };
129
130 /*****************************************************************************/
131 /* Exception model */
132 typedef enum powerpc_excp_t powerpc_excp_t;
133 enum powerpc_excp_t {
134 POWERPC_EXCP_UNKNOWN = 0,
135 /* Standard PowerPC exception model */
136 POWERPC_EXCP_STD,
137 /* PowerPC 40x exception model */
138 POWERPC_EXCP_40x,
139 /* PowerPC 601 exception model */
140 POWERPC_EXCP_601,
141 /* PowerPC 602 exception model */
142 POWERPC_EXCP_602,
143 /* PowerPC 603 exception model */
144 POWERPC_EXCP_603,
145 /* PowerPC 603e exception model */
146 POWERPC_EXCP_603E,
147 /* PowerPC G2 exception model */
148 POWERPC_EXCP_G2,
149 /* PowerPC 604 exception model */
150 POWERPC_EXCP_604,
151 /* PowerPC 7x0 exception model */
152 POWERPC_EXCP_7x0,
153 /* PowerPC 7x5 exception model */
154 POWERPC_EXCP_7x5,
155 /* PowerPC 74xx exception model */
156 POWERPC_EXCP_74xx,
157 /* BookE exception model */
158 POWERPC_EXCP_BOOKE,
159 #if defined(TARGET_PPC64)
160 /* PowerPC 970 exception model */
161 POWERPC_EXCP_970,
162 /* POWER7 exception model */
163 POWERPC_EXCP_POWER7,
164 #endif /* defined(TARGET_PPC64) */
165 };
166
167 /*****************************************************************************/
168 /* Exception vectors definitions */
169 enum {
170 POWERPC_EXCP_NONE = -1,
171 /* The 64 first entries are used by the PowerPC embedded specification */
172 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
173 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
174 POWERPC_EXCP_DSI = 2, /* Data storage exception */
175 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
176 POWERPC_EXCP_EXTERNAL = 4, /* External input */
177 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
178 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
179 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
180 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
181 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
182 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
183 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
184 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
185 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
186 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
187 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
188 /* Vectors 16 to 31 are reserved */
189 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
190 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
191 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
192 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
193 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
194 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
195 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
196 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
197 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
198 /* Vectors 42 to 63 are reserved */
199 /* Exceptions defined in the PowerPC server specification */
200 POWERPC_EXCP_RESET = 64, /* System reset exception */
201 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
202 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
203 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
204 POWERPC_EXCP_TRACE = 68, /* Trace exception */
205 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
206 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
207 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
208 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
209 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
210 /* 40x specific exceptions */
211 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
212 /* 601 specific exceptions */
213 POWERPC_EXCP_IO = 75, /* IO error exception */
214 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
215 /* 602 specific exceptions */
216 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
217 /* 602/603 specific exceptions */
218 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
219 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
220 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
221 /* Exceptions available on most PowerPC */
222 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
223 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
224 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
225 POWERPC_EXCP_SMI = 84, /* System management interrupt */
226 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
227 /* 7xx/74xx specific exceptions */
228 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
229 /* 74xx specific exceptions */
230 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
231 /* 970FX specific exceptions */
232 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
233 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
234 /* Freescale embedded cores specific exceptions */
235 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
236 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
237 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
238 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
239 /* VSX Unavailable (Power ISA 2.06 and later) */
240 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
241 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
242 /* EOL */
243 POWERPC_EXCP_NB = 96,
244 /* QEMU exceptions: used internally during code translation */
245 POWERPC_EXCP_STOP = 0x200, /* stop translation */
246 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
247 /* QEMU exceptions: special cases we want to stop translation */
248 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
249 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
250 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
251 };
252
253 /* Exceptions error codes */
254 enum {
255 /* Exception subtypes for POWERPC_EXCP_ALIGN */
256 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
257 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
258 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
259 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
260 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
261 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
262 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
263 /* FP exceptions */
264 POWERPC_EXCP_FP = 0x10,
265 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
266 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
267 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
268 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
269 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
270 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
271 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
272 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
273 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
274 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
275 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
276 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
277 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
278 /* Invalid instruction */
279 POWERPC_EXCP_INVAL = 0x20,
280 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
281 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
282 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
283 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
284 /* Privileged instruction */
285 POWERPC_EXCP_PRIV = 0x30,
286 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
287 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
288 /* Trap */
289 POWERPC_EXCP_TRAP = 0x40,
290 };
291
292 /*****************************************************************************/
293 /* Input pins model */
294 typedef enum powerpc_input_t powerpc_input_t;
295 enum powerpc_input_t {
296 PPC_FLAGS_INPUT_UNKNOWN = 0,
297 /* PowerPC 6xx bus */
298 PPC_FLAGS_INPUT_6xx,
299 /* BookE bus */
300 PPC_FLAGS_INPUT_BookE,
301 /* PowerPC 405 bus */
302 PPC_FLAGS_INPUT_405,
303 /* PowerPC 970 bus */
304 PPC_FLAGS_INPUT_970,
305 /* PowerPC POWER7 bus */
306 PPC_FLAGS_INPUT_POWER7,
307 /* PowerPC 401 bus */
308 PPC_FLAGS_INPUT_401,
309 /* Freescale RCPU bus */
310 PPC_FLAGS_INPUT_RCPU,
311 };
312
313 #define PPC_INPUT(env) (env->bus_model)
314
315 /*****************************************************************************/
316 typedef struct opc_handler_t opc_handler_t;
317
318 /*****************************************************************************/
319 /* Types used to describe some PowerPC registers */
320 typedef struct CPUPPCState CPUPPCState;
321 typedef struct ppc_tb_t ppc_tb_t;
322 typedef struct ppc_spr_t ppc_spr_t;
323 typedef struct ppc_dcr_t ppc_dcr_t;
324 typedef union ppc_avr_t ppc_avr_t;
325 typedef union ppc_tlb_t ppc_tlb_t;
326
327 /* SPR access micro-ops generations callbacks */
328 struct ppc_spr_t {
329 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
330 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
331 #if !defined(CONFIG_USER_ONLY)
332 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
333 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
334 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
335 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
336 #endif
337 const char *name;
338 target_ulong default_value;
339 #ifdef CONFIG_KVM
340 /* We (ab)use the fact that all the SPRs will have ids for the
341 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
342 * don't sync this */
343 uint64_t one_reg_id;
344 #endif
345 };
346
347 /* Altivec registers (128 bits) */
348 union ppc_avr_t {
349 float32 f[4];
350 uint8_t u8[16];
351 uint16_t u16[8];
352 uint32_t u32[4];
353 int8_t s8[16];
354 int16_t s16[8];
355 int32_t s32[4];
356 uint64_t u64[2];
357 int64_t s64[2];
358 #ifdef CONFIG_INT128
359 __uint128_t u128;
360 #endif
361 };
362
363 #if !defined(CONFIG_USER_ONLY)
364 /* Software TLB cache */
365 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
366 struct ppc6xx_tlb_t {
367 target_ulong pte0;
368 target_ulong pte1;
369 target_ulong EPN;
370 };
371
372 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
373 struct ppcemb_tlb_t {
374 uint64_t RPN;
375 target_ulong EPN;
376 target_ulong PID;
377 target_ulong size;
378 uint32_t prot;
379 uint32_t attr; /* Storage attributes */
380 };
381
382 typedef struct ppcmas_tlb_t {
383 uint32_t mas8;
384 uint32_t mas1;
385 uint64_t mas2;
386 uint64_t mas7_3;
387 } ppcmas_tlb_t;
388
389 union ppc_tlb_t {
390 ppc6xx_tlb_t *tlb6;
391 ppcemb_tlb_t *tlbe;
392 ppcmas_tlb_t *tlbm;
393 };
394
395 /* possible TLB variants */
396 #define TLB_NONE 0
397 #define TLB_6XX 1
398 #define TLB_EMB 2
399 #define TLB_MAS 3
400 #endif
401
402 #define SDR_32_HTABORG 0xFFFF0000UL
403 #define SDR_32_HTABMASK 0x000001FFUL
404
405 #if defined(TARGET_PPC64)
406 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
407 #define SDR_64_HTABSIZE 0x000000000000001FULL
408 #endif /* defined(TARGET_PPC64 */
409
410 typedef struct ppc_slb_t ppc_slb_t;
411 struct ppc_slb_t {
412 uint64_t esid;
413 uint64_t vsid;
414 };
415
416 #define MAX_SLB_ENTRIES 64
417 #define SEGMENT_SHIFT_256M 28
418 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
419
420 #define SEGMENT_SHIFT_1T 40
421 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
422
423
424 /*****************************************************************************/
425 /* Machine state register bits definition */
426 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
427 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
428 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
429 #define MSR_SHV 60 /* hypervisor state hflags */
430 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
431 #define MSR_TS1 33
432 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
433 #define MSR_CM 31 /* Computation mode for BookE hflags */
434 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
435 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
436 #define MSR_GS 28 /* guest state for BookE */
437 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
438 #define MSR_VR 25 /* altivec available x hflags */
439 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
440 #define MSR_AP 23 /* Access privilege state on 602 hflags */
441 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
442 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
443 #define MSR_KEY 19 /* key bit on 603e */
444 #define MSR_POW 18 /* Power management */
445 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
446 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
447 #define MSR_ILE 16 /* Interrupt little-endian mode */
448 #define MSR_EE 15 /* External interrupt enable */
449 #define MSR_PR 14 /* Problem state hflags */
450 #define MSR_FP 13 /* Floating point available hflags */
451 #define MSR_ME 12 /* Machine check interrupt enable */
452 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
453 #define MSR_SE 10 /* Single-step trace enable x hflags */
454 #define MSR_DWE 10 /* Debug wait enable on 405 x */
455 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
456 #define MSR_BE 9 /* Branch trace enable x hflags */
457 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
458 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
459 #define MSR_AL 7 /* AL bit on POWER */
460 #define MSR_EP 6 /* Exception prefix on 601 */
461 #define MSR_IR 5 /* Instruction relocate */
462 #define MSR_DR 4 /* Data relocate */
463 #define MSR_PE 3 /* Protection enable on 403 */
464 #define MSR_PX 2 /* Protection exclusive on 403 x */
465 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
466 #define MSR_RI 1 /* Recoverable interrupt 1 */
467 #define MSR_LE 0 /* Little-endian mode 1 hflags */
468
469 #define LPCR_ILE (1 << (63-38))
470 #define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
471 #define LPCR_AIL (3 << LPCR_AIL_SHIFT)
472
473 #define msr_sf ((env->msr >> MSR_SF) & 1)
474 #define msr_isf ((env->msr >> MSR_ISF) & 1)
475 #define msr_shv ((env->msr >> MSR_SHV) & 1)
476 #define msr_cm ((env->msr >> MSR_CM) & 1)
477 #define msr_icm ((env->msr >> MSR_ICM) & 1)
478 #define msr_thv ((env->msr >> MSR_THV) & 1)
479 #define msr_gs ((env->msr >> MSR_GS) & 1)
480 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
481 #define msr_vr ((env->msr >> MSR_VR) & 1)
482 #define msr_spe ((env->msr >> MSR_SPE) & 1)
483 #define msr_ap ((env->msr >> MSR_AP) & 1)
484 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
485 #define msr_sa ((env->msr >> MSR_SA) & 1)
486 #define msr_key ((env->msr >> MSR_KEY) & 1)
487 #define msr_pow ((env->msr >> MSR_POW) & 1)
488 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
489 #define msr_ce ((env->msr >> MSR_CE) & 1)
490 #define msr_ile ((env->msr >> MSR_ILE) & 1)
491 #define msr_ee ((env->msr >> MSR_EE) & 1)
492 #define msr_pr ((env->msr >> MSR_PR) & 1)
493 #define msr_fp ((env->msr >> MSR_FP) & 1)
494 #define msr_me ((env->msr >> MSR_ME) & 1)
495 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
496 #define msr_se ((env->msr >> MSR_SE) & 1)
497 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
498 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
499 #define msr_be ((env->msr >> MSR_BE) & 1)
500 #define msr_de ((env->msr >> MSR_DE) & 1)
501 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
502 #define msr_al ((env->msr >> MSR_AL) & 1)
503 #define msr_ep ((env->msr >> MSR_EP) & 1)
504 #define msr_ir ((env->msr >> MSR_IR) & 1)
505 #define msr_dr ((env->msr >> MSR_DR) & 1)
506 #define msr_pe ((env->msr >> MSR_PE) & 1)
507 #define msr_px ((env->msr >> MSR_PX) & 1)
508 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
509 #define msr_ri ((env->msr >> MSR_RI) & 1)
510 #define msr_le ((env->msr >> MSR_LE) & 1)
511 #define msr_ts ((env->msr >> MSR_TS1) & 3)
512 #define msr_tm ((env->msr >> MSR_TM) & 1)
513
514 /* Hypervisor bit is more specific */
515 #if defined(TARGET_PPC64)
516 #define MSR_HVB (1ULL << MSR_SHV)
517 #define msr_hv msr_shv
518 #else
519 #if defined(PPC_EMULATE_32BITS_HYPV)
520 #define MSR_HVB (1ULL << MSR_THV)
521 #define msr_hv msr_thv
522 #else
523 #define MSR_HVB (0ULL)
524 #define msr_hv (0)
525 #endif
526 #endif
527
528 /* Facility Status and Control (FSCR) bits */
529 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
530 #define FSCR_TAR (63 - 55) /* Target Address Register */
531 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
532 #define FSCR_IC_MASK (0xFFULL)
533 #define FSCR_IC_POS (63 - 7)
534 #define FSCR_IC_DSCR_SPR3 2
535 #define FSCR_IC_PMU 3
536 #define FSCR_IC_BHRB 4
537 #define FSCR_IC_TM 5
538 #define FSCR_IC_EBB 7
539 #define FSCR_IC_TAR 8
540
541 /* Exception state register bits definition */
542 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
543 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
544 #define ESR_PTR (1 << (63 - 38)) /* Trap */
545 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
546 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
547 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
548 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
549 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
550 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
551 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
552 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
553 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
554 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
555 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
556 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
557 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
558
559 enum {
560 POWERPC_FLAG_NONE = 0x00000000,
561 /* Flag for MSR bit 25 signification (VRE/SPE) */
562 POWERPC_FLAG_SPE = 0x00000001,
563 POWERPC_FLAG_VRE = 0x00000002,
564 /* Flag for MSR bit 17 signification (TGPR/CE) */
565 POWERPC_FLAG_TGPR = 0x00000004,
566 POWERPC_FLAG_CE = 0x00000008,
567 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
568 POWERPC_FLAG_SE = 0x00000010,
569 POWERPC_FLAG_DWE = 0x00000020,
570 POWERPC_FLAG_UBLE = 0x00000040,
571 /* Flag for MSR bit 9 signification (BE/DE) */
572 POWERPC_FLAG_BE = 0x00000080,
573 POWERPC_FLAG_DE = 0x00000100,
574 /* Flag for MSR bit 2 signification (PX/PMM) */
575 POWERPC_FLAG_PX = 0x00000200,
576 POWERPC_FLAG_PMM = 0x00000400,
577 /* Flag for special features */
578 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
579 POWERPC_FLAG_RTC_CLK = 0x00010000,
580 POWERPC_FLAG_BUS_CLK = 0x00020000,
581 /* Has CFAR */
582 POWERPC_FLAG_CFAR = 0x00040000,
583 /* Has VSX */
584 POWERPC_FLAG_VSX = 0x00080000,
585 };
586
587 /*****************************************************************************/
588 /* Floating point status and control register */
589 #define FPSCR_FX 31 /* Floating-point exception summary */
590 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
591 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
592 #define FPSCR_OX 28 /* Floating-point overflow exception */
593 #define FPSCR_UX 27 /* Floating-point underflow exception */
594 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
595 #define FPSCR_XX 25 /* Floating-point inexact exception */
596 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
597 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
598 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
599 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
600 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
601 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
602 #define FPSCR_FR 18 /* Floating-point fraction rounded */
603 #define FPSCR_FI 17 /* Floating-point fraction inexact */
604 #define FPSCR_C 16 /* Floating-point result class descriptor */
605 #define FPSCR_FL 15 /* Floating-point less than or negative */
606 #define FPSCR_FG 14 /* Floating-point greater than or negative */
607 #define FPSCR_FE 13 /* Floating-point equal or zero */
608 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
609 #define FPSCR_FPCC 12 /* Floating-point condition code */
610 #define FPSCR_FPRF 12 /* Floating-point result flags */
611 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
612 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
613 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
614 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
615 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
616 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
617 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
618 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
619 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
620 #define FPSCR_RN1 1
621 #define FPSCR_RN 0 /* Floating-point rounding control */
622 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
623 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
624 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
625 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
626 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
627 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
628 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
629 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
630 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
631 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
632 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
633 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
634 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
635 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
636 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
637 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
638 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
639 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
640 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
641 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
642 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
643 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
644 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
645 /* Invalid operation exception summary */
646 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
647 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
648 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
649 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
650 (1 << FPSCR_VXCVI)))
651 /* exception summary */
652 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
653 /* enabled exception summary */
654 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
655 0x1F)
656
657 /*****************************************************************************/
658 /* Vector status and control register */
659 #define VSCR_NJ 16 /* Vector non-java */
660 #define VSCR_SAT 0 /* Vector saturation */
661 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
662 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
663
664 /*****************************************************************************/
665 /* BookE e500 MMU registers */
666
667 #define MAS0_NV_SHIFT 0
668 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
669
670 #define MAS0_WQ_SHIFT 12
671 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
672 /* Write TLB entry regardless of reservation */
673 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
674 /* Write TLB entry only already in use */
675 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
676 /* Clear TLB entry */
677 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
678
679 #define MAS0_HES_SHIFT 14
680 #define MAS0_HES (1 << MAS0_HES_SHIFT)
681
682 #define MAS0_ESEL_SHIFT 16
683 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
684
685 #define MAS0_TLBSEL_SHIFT 28
686 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
687 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
688 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
689 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
690 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
691
692 #define MAS0_ATSEL_SHIFT 31
693 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
694 #define MAS0_ATSEL_TLB 0
695 #define MAS0_ATSEL_LRAT MAS0_ATSEL
696
697 #define MAS1_TSIZE_SHIFT 7
698 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
699
700 #define MAS1_TS_SHIFT 12
701 #define MAS1_TS (1 << MAS1_TS_SHIFT)
702
703 #define MAS1_IND_SHIFT 13
704 #define MAS1_IND (1 << MAS1_IND_SHIFT)
705
706 #define MAS1_TID_SHIFT 16
707 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
708
709 #define MAS1_IPROT_SHIFT 30
710 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
711
712 #define MAS1_VALID_SHIFT 31
713 #define MAS1_VALID 0x80000000
714
715 #define MAS2_EPN_SHIFT 12
716 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
717
718 #define MAS2_ACM_SHIFT 6
719 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
720
721 #define MAS2_VLE_SHIFT 5
722 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
723
724 #define MAS2_W_SHIFT 4
725 #define MAS2_W (1 << MAS2_W_SHIFT)
726
727 #define MAS2_I_SHIFT 3
728 #define MAS2_I (1 << MAS2_I_SHIFT)
729
730 #define MAS2_M_SHIFT 2
731 #define MAS2_M (1 << MAS2_M_SHIFT)
732
733 #define MAS2_G_SHIFT 1
734 #define MAS2_G (1 << MAS2_G_SHIFT)
735
736 #define MAS2_E_SHIFT 0
737 #define MAS2_E (1 << MAS2_E_SHIFT)
738
739 #define MAS3_RPN_SHIFT 12
740 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
741
742 #define MAS3_U0 0x00000200
743 #define MAS3_U1 0x00000100
744 #define MAS3_U2 0x00000080
745 #define MAS3_U3 0x00000040
746 #define MAS3_UX 0x00000020
747 #define MAS3_SX 0x00000010
748 #define MAS3_UW 0x00000008
749 #define MAS3_SW 0x00000004
750 #define MAS3_UR 0x00000002
751 #define MAS3_SR 0x00000001
752 #define MAS3_SPSIZE_SHIFT 1
753 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
754
755 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
756 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
757 #define MAS4_TIDSELD_MASK 0x00030000
758 #define MAS4_TIDSELD_PID0 0x00000000
759 #define MAS4_TIDSELD_PID1 0x00010000
760 #define MAS4_TIDSELD_PID2 0x00020000
761 #define MAS4_TIDSELD_PIDZ 0x00030000
762 #define MAS4_INDD 0x00008000 /* Default IND */
763 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
764 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
765 #define MAS4_ACMD 0x00000040
766 #define MAS4_VLED 0x00000020
767 #define MAS4_WD 0x00000010
768 #define MAS4_ID 0x00000008
769 #define MAS4_MD 0x00000004
770 #define MAS4_GD 0x00000002
771 #define MAS4_ED 0x00000001
772 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
773 #define MAS4_WIMGED_SHIFT 0
774
775 #define MAS5_SGS 0x80000000
776 #define MAS5_SLPID_MASK 0x00000fff
777
778 #define MAS6_SPID0 0x3fff0000
779 #define MAS6_SPID1 0x00007ffe
780 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
781 #define MAS6_SAS 0x00000001
782 #define MAS6_SPID MAS6_SPID0
783 #define MAS6_SIND 0x00000002 /* Indirect page */
784 #define MAS6_SIND_SHIFT 1
785 #define MAS6_SPID_MASK 0x3fff0000
786 #define MAS6_SPID_SHIFT 16
787 #define MAS6_ISIZE_MASK 0x00000f80
788 #define MAS6_ISIZE_SHIFT 7
789
790 #define MAS7_RPN 0xffffffff
791
792 #define MAS8_TGS 0x80000000
793 #define MAS8_VF 0x40000000
794 #define MAS8_TLBPID 0x00000fff
795
796 /* Bit definitions for MMUCFG */
797 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
798 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
799 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
800 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
801 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
802 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
803 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
804 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
805 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
806
807 /* Bit definitions for MMUCSR0 */
808 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
809 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
810 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
811 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
812 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
813 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
814 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
815 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
816 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
817 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
818
819 /* TLBnCFG encoding */
820 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
821 #define TLBnCFG_HES 0x00002000 /* HW select supported */
822 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
823 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
824 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
825 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
826 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
827 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
828 #define TLBnCFG_MINSIZE_SHIFT 20
829 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
830 #define TLBnCFG_MAXSIZE_SHIFT 16
831 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
832 #define TLBnCFG_ASSOC_SHIFT 24
833
834 /* TLBnPS encoding */
835 #define TLBnPS_4K 0x00000004
836 #define TLBnPS_8K 0x00000008
837 #define TLBnPS_16K 0x00000010
838 #define TLBnPS_32K 0x00000020
839 #define TLBnPS_64K 0x00000040
840 #define TLBnPS_128K 0x00000080
841 #define TLBnPS_256K 0x00000100
842 #define TLBnPS_512K 0x00000200
843 #define TLBnPS_1M 0x00000400
844 #define TLBnPS_2M 0x00000800
845 #define TLBnPS_4M 0x00001000
846 #define TLBnPS_8M 0x00002000
847 #define TLBnPS_16M 0x00004000
848 #define TLBnPS_32M 0x00008000
849 #define TLBnPS_64M 0x00010000
850 #define TLBnPS_128M 0x00020000
851 #define TLBnPS_256M 0x00040000
852 #define TLBnPS_512M 0x00080000
853 #define TLBnPS_1G 0x00100000
854 #define TLBnPS_2G 0x00200000
855 #define TLBnPS_4G 0x00400000
856 #define TLBnPS_8G 0x00800000
857 #define TLBnPS_16G 0x01000000
858 #define TLBnPS_32G 0x02000000
859 #define TLBnPS_64G 0x04000000
860 #define TLBnPS_128G 0x08000000
861 #define TLBnPS_256G 0x10000000
862
863 /* tlbilx action encoding */
864 #define TLBILX_T_ALL 0
865 #define TLBILX_T_TID 1
866 #define TLBILX_T_FULLMATCH 3
867 #define TLBILX_T_CLASS0 4
868 #define TLBILX_T_CLASS1 5
869 #define TLBILX_T_CLASS2 6
870 #define TLBILX_T_CLASS3 7
871
872 /* BookE 2.06 helper defines */
873
874 #define BOOKE206_FLUSH_TLB0 (1 << 0)
875 #define BOOKE206_FLUSH_TLB1 (1 << 1)
876 #define BOOKE206_FLUSH_TLB2 (1 << 2)
877 #define BOOKE206_FLUSH_TLB3 (1 << 3)
878
879 /* number of possible TLBs */
880 #define BOOKE206_MAX_TLBN 4
881
882 /*****************************************************************************/
883 /* Embedded.Processor Control */
884
885 #define DBELL_TYPE_SHIFT 27
886 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
887 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
888 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
889 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
890 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
891 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
892
893 #define DBELL_BRDCAST (1 << 26)
894 #define DBELL_LPIDTAG_SHIFT 14
895 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
896 #define DBELL_PIRTAG_MASK 0x3fff
897
898 /*****************************************************************************/
899 /* Segment page size information, used by recent hash MMUs
900 * The format of this structure mirrors kvm_ppc_smmu_info
901 */
902
903 #define PPC_PAGE_SIZES_MAX_SZ 8
904
905 struct ppc_one_page_size {
906 uint32_t page_shift; /* Page shift (or 0) */
907 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
908 };
909
910 struct ppc_one_seg_page_size {
911 uint32_t page_shift; /* Base page shift of segment (or 0) */
912 uint32_t slb_enc; /* SLB encoding for BookS */
913 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
914 };
915
916 struct ppc_segment_page_sizes {
917 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
918 };
919
920
921 /*****************************************************************************/
922 /* The whole PowerPC CPU context */
923 #define NB_MMU_MODES 3
924
925 #define PPC_CPU_OPCODES_LEN 0x40
926
927 struct CPUPPCState {
928 /* First are the most commonly used resources
929 * during translated code execution
930 */
931 /* general purpose registers */
932 target_ulong gpr[32];
933 /* Storage for GPR MSB, used by the SPE extension */
934 target_ulong gprh[32];
935 /* LR */
936 target_ulong lr;
937 /* CTR */
938 target_ulong ctr;
939 /* condition register */
940 uint32_t crf[8];
941 #if defined(TARGET_PPC64)
942 /* CFAR */
943 target_ulong cfar;
944 #endif
945 /* XER (with SO, OV, CA split out) */
946 target_ulong xer;
947 target_ulong so;
948 target_ulong ov;
949 target_ulong ca;
950 /* Reservation address */
951 target_ulong reserve_addr;
952 /* Reservation value */
953 target_ulong reserve_val;
954 target_ulong reserve_val2;
955 /* Reservation store address */
956 target_ulong reserve_ea;
957 /* Reserved store source register and size */
958 target_ulong reserve_info;
959
960 /* Those ones are used in supervisor mode only */
961 /* machine state register */
962 target_ulong msr;
963 /* temporary general purpose registers */
964 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
965
966 /* Floating point execution context */
967 float_status fp_status;
968 /* floating point registers */
969 float64 fpr[32];
970 /* floating point status and control register */
971 target_ulong fpscr;
972
973 /* Next instruction pointer */
974 target_ulong nip;
975
976 int access_type; /* when a memory exception occurs, the access
977 type is stored here */
978
979 CPU_COMMON
980
981 /* MMU context - only relevant for full system emulation */
982 #if !defined(CONFIG_USER_ONLY)
983 #if defined(TARGET_PPC64)
984 /* PowerPC 64 SLB area */
985 ppc_slb_t slb[MAX_SLB_ENTRIES];
986 int32_t slb_nr;
987 #endif
988 /* segment registers */
989 hwaddr htab_base;
990 /* mask used to normalize hash value to PTEG index */
991 hwaddr htab_mask;
992 target_ulong sr[32];
993 /* externally stored hash table */
994 uint8_t *external_htab;
995 /* BATs */
996 uint32_t nb_BATs;
997 target_ulong DBAT[2][8];
998 target_ulong IBAT[2][8];
999 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1000 int32_t nb_tlb; /* Total number of TLB */
1001 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1002 int nb_ways; /* Number of ways in the TLB set */
1003 int last_way; /* Last used way used to allocate TLB in a LRU way */
1004 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1005 int nb_pids; /* Number of available PID registers */
1006 int tlb_type; /* Type of TLB we're dealing with */
1007 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1008 /* 403 dedicated access protection registers */
1009 target_ulong pb[4];
1010 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1011 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1012 #endif
1013
1014 /* Other registers */
1015 /* Special purpose registers */
1016 target_ulong spr[1024];
1017 ppc_spr_t spr_cb[1024];
1018 /* Altivec registers */
1019 ppc_avr_t avr[32];
1020 uint32_t vscr;
1021 /* VSX registers */
1022 uint64_t vsr[32];
1023 /* SPE registers */
1024 uint64_t spe_acc;
1025 uint32_t spe_fscr;
1026 /* SPE and Altivec can share a status since they will never be used
1027 * simultaneously */
1028 float_status vec_status;
1029
1030 /* Internal devices resources */
1031 /* Time base and decrementer */
1032 ppc_tb_t *tb_env;
1033 /* Device control registers */
1034 ppc_dcr_t *dcr_env;
1035
1036 int dcache_line_size;
1037 int icache_line_size;
1038
1039 /* Those resources are used during exception processing */
1040 /* CPU model definition */
1041 target_ulong msr_mask;
1042 powerpc_mmu_t mmu_model;
1043 powerpc_excp_t excp_model;
1044 powerpc_input_t bus_model;
1045 int bfd_mach;
1046 uint32_t flags;
1047 uint64_t insns_flags;
1048 uint64_t insns_flags2;
1049 #if defined(TARGET_PPC64)
1050 struct ppc_segment_page_sizes sps;
1051 #endif
1052
1053 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1054 uint64_t vpa_addr;
1055 uint64_t slb_shadow_addr, slb_shadow_size;
1056 uint64_t dtl_addr, dtl_size;
1057 #endif /* TARGET_PPC64 */
1058
1059 int error_code;
1060 uint32_t pending_interrupts;
1061 #if !defined(CONFIG_USER_ONLY)
1062 /* This is the IRQ controller, which is implementation dependent
1063 * and only relevant when emulating a complete machine.
1064 */
1065 uint32_t irq_input_state;
1066 void **irq_inputs;
1067 /* Exception vectors */
1068 target_ulong excp_vectors[POWERPC_EXCP_NB];
1069 target_ulong excp_prefix;
1070 target_ulong ivor_mask;
1071 target_ulong ivpr_mask;
1072 target_ulong hreset_vector;
1073 hwaddr mpic_iack;
1074 /* true when the external proxy facility mode is enabled */
1075 bool mpic_proxy;
1076 #endif
1077
1078 /* Those resources are used only during code translation */
1079 /* opcode handlers */
1080 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1081
1082 /* Those resources are used only in QEMU core */
1083 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1084 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1085 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1086
1087 /* Power management */
1088 int (*check_pow)(CPUPPCState *env);
1089
1090 #if !defined(CONFIG_USER_ONLY)
1091 void *load_info; /* Holds boot loading state. */
1092 #endif
1093
1094 /* booke timers */
1095
1096 /* Specifies bit locations of the Time Base used to signal a fixed timer
1097 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1098 *
1099 * 0 selects the least significant bit.
1100 * 63 selects the most significant bit.
1101 */
1102 uint8_t fit_period[4];
1103 uint8_t wdt_period[4];
1104
1105 /* Transactional memory state */
1106 target_ulong tm_gpr[32];
1107 ppc_avr_t tm_vsr[64];
1108 uint64_t tm_cr;
1109 uint64_t tm_lr;
1110 uint64_t tm_ctr;
1111 uint64_t tm_fpscr;
1112 uint64_t tm_amr;
1113 uint64_t tm_ppr;
1114 uint64_t tm_vrsave;
1115 uint32_t tm_vscr;
1116 uint64_t tm_dscr;
1117 uint64_t tm_tar;
1118 };
1119
1120 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1121 do { \
1122 env->fit_period[0] = (a_); \
1123 env->fit_period[1] = (b_); \
1124 env->fit_period[2] = (c_); \
1125 env->fit_period[3] = (d_); \
1126 } while (0)
1127
1128 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1129 do { \
1130 env->wdt_period[0] = (a_); \
1131 env->wdt_period[1] = (b_); \
1132 env->wdt_period[2] = (c_); \
1133 env->wdt_period[3] = (d_); \
1134 } while (0)
1135
1136 #include "cpu-qom.h"
1137
1138 /*****************************************************************************/
1139 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1140 void ppc_translate_init(void);
1141 void gen_update_current_nip(void *opaque);
1142 int cpu_ppc_exec (CPUPPCState *s);
1143 /* you can call this signal handler from your SIGBUS and SIGSEGV
1144 signal handlers to inform the virtual CPU of exceptions. non zero
1145 is returned if the signal was handled by the virtual CPU. */
1146 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1147 void *puc);
1148 void ppc_hw_interrupt (CPUPPCState *env);
1149 #if defined(CONFIG_USER_ONLY)
1150 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1151 int mmu_idx);
1152 #endif
1153
1154 #if !defined(CONFIG_USER_ONLY)
1155 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1156 #endif /* !defined(CONFIG_USER_ONLY) */
1157 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1158
1159 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1160 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1161 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
1162
1163 /* Time-base and decrementer management */
1164 #ifndef NO_CPU_IO_DEFS
1165 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1166 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1167 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1168 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1169 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1170 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1171 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1172 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1173 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1174 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1175 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1176 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1177 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1178 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1179 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1180 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1181 #if !defined(CONFIG_USER_ONLY)
1182 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1183 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1184 target_ulong load_40x_pit (CPUPPCState *env);
1185 void store_40x_pit (CPUPPCState *env, target_ulong val);
1186 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1187 void store_40x_sler (CPUPPCState *env, uint32_t val);
1188 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1189 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1190 void ppc_tlb_invalidate_all (CPUPPCState *env);
1191 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1192 #endif
1193 #endif
1194
1195 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1196
1197 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1198 {
1199 uint64_t gprv;
1200
1201 gprv = env->gpr[gprn];
1202 if (env->flags & POWERPC_FLAG_SPE) {
1203 /* If the CPU implements the SPE extension, we have to get the
1204 * high bits of the GPR from the gprh storage area
1205 */
1206 gprv &= 0xFFFFFFFFULL;
1207 gprv |= (uint64_t)env->gprh[gprn] << 32;
1208 }
1209
1210 return gprv;
1211 }
1212
1213 /* Device control registers */
1214 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1215 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1216
1217 static inline CPUPPCState *cpu_init(const char *cpu_model)
1218 {
1219 PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1220 if (cpu == NULL) {
1221 return NULL;
1222 }
1223 return &cpu->env;
1224 }
1225
1226 #define cpu_exec cpu_ppc_exec
1227 #define cpu_gen_code cpu_ppc_gen_code
1228 #define cpu_signal_handler cpu_ppc_signal_handler
1229 #define cpu_list ppc_cpu_list
1230
1231 /* MMU modes definitions */
1232 #define MMU_MODE0_SUFFIX _user
1233 #define MMU_MODE1_SUFFIX _kernel
1234 #define MMU_MODE2_SUFFIX _hypv
1235 #define MMU_USER_IDX 0
1236 static inline int cpu_mmu_index (CPUPPCState *env)
1237 {
1238 return env->mmu_idx;
1239 }
1240
1241 #include "exec/cpu-all.h"
1242
1243 /*****************************************************************************/
1244 /* CRF definitions */
1245 #define CRF_LT 3
1246 #define CRF_GT 2
1247 #define CRF_EQ 1
1248 #define CRF_SO 0
1249 #define CRF_CH (1 << CRF_LT)
1250 #define CRF_CL (1 << CRF_GT)
1251 #define CRF_CH_OR_CL (1 << CRF_EQ)
1252 #define CRF_CH_AND_CL (1 << CRF_SO)
1253
1254 /* XER definitions */
1255 #define XER_SO 31
1256 #define XER_OV 30
1257 #define XER_CA 29
1258 #define XER_CMP 8
1259 #define XER_BC 0
1260 #define xer_so (env->so)
1261 #define xer_ov (env->ov)
1262 #define xer_ca (env->ca)
1263 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1264 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1265
1266 /* SPR definitions */
1267 #define SPR_MQ (0x000)
1268 #define SPR_XER (0x001)
1269 #define SPR_601_VRTCU (0x004)
1270 #define SPR_601_VRTCL (0x005)
1271 #define SPR_601_UDECR (0x006)
1272 #define SPR_LR (0x008)
1273 #define SPR_CTR (0x009)
1274 #define SPR_UAMR (0x00C)
1275 #define SPR_DSCR (0x011)
1276 #define SPR_DSISR (0x012)
1277 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1278 #define SPR_601_RTCU (0x014)
1279 #define SPR_601_RTCL (0x015)
1280 #define SPR_DECR (0x016)
1281 #define SPR_SDR1 (0x019)
1282 #define SPR_SRR0 (0x01A)
1283 #define SPR_SRR1 (0x01B)
1284 #define SPR_CFAR (0x01C)
1285 #define SPR_AMR (0x01D)
1286 #define SPR_BOOKE_PID (0x030)
1287 #define SPR_BOOKE_DECAR (0x036)
1288 #define SPR_BOOKE_CSRR0 (0x03A)
1289 #define SPR_BOOKE_CSRR1 (0x03B)
1290 #define SPR_BOOKE_DEAR (0x03D)
1291 #define SPR_BOOKE_ESR (0x03E)
1292 #define SPR_BOOKE_IVPR (0x03F)
1293 #define SPR_MPC_EIE (0x050)
1294 #define SPR_MPC_EID (0x051)
1295 #define SPR_MPC_NRI (0x052)
1296 #define SPR_TFHAR (0x080)
1297 #define SPR_TFIAR (0x081)
1298 #define SPR_TEXASR (0x082)
1299 #define SPR_TEXASRU (0x083)
1300 #define SPR_UCTRL (0x088)
1301 #define SPR_MPC_CMPA (0x090)
1302 #define SPR_MPC_CMPB (0x091)
1303 #define SPR_MPC_CMPC (0x092)
1304 #define SPR_MPC_CMPD (0x093)
1305 #define SPR_MPC_ECR (0x094)
1306 #define SPR_MPC_DER (0x095)
1307 #define SPR_MPC_COUNTA (0x096)
1308 #define SPR_MPC_COUNTB (0x097)
1309 #define SPR_CTRL (0x098)
1310 #define SPR_MPC_CMPE (0x098)
1311 #define SPR_MPC_CMPF (0x099)
1312 #define SPR_FSCR (0x099)
1313 #define SPR_MPC_CMPG (0x09A)
1314 #define SPR_MPC_CMPH (0x09B)
1315 #define SPR_MPC_LCTRL1 (0x09C)
1316 #define SPR_MPC_LCTRL2 (0x09D)
1317 #define SPR_UAMOR (0x09D)
1318 #define SPR_MPC_ICTRL (0x09E)
1319 #define SPR_MPC_BAR (0x09F)
1320 #define SPR_VRSAVE (0x100)
1321 #define SPR_USPRG0 (0x100)
1322 #define SPR_USPRG1 (0x101)
1323 #define SPR_USPRG2 (0x102)
1324 #define SPR_USPRG3 (0x103)
1325 #define SPR_USPRG4 (0x104)
1326 #define SPR_USPRG5 (0x105)
1327 #define SPR_USPRG6 (0x106)
1328 #define SPR_USPRG7 (0x107)
1329 #define SPR_VTBL (0x10C)
1330 #define SPR_VTBU (0x10D)
1331 #define SPR_SPRG0 (0x110)
1332 #define SPR_SPRG1 (0x111)
1333 #define SPR_SPRG2 (0x112)
1334 #define SPR_SPRG3 (0x113)
1335 #define SPR_SPRG4 (0x114)
1336 #define SPR_SCOMC (0x114)
1337 #define SPR_SPRG5 (0x115)
1338 #define SPR_SCOMD (0x115)
1339 #define SPR_SPRG6 (0x116)
1340 #define SPR_SPRG7 (0x117)
1341 #define SPR_ASR (0x118)
1342 #define SPR_EAR (0x11A)
1343 #define SPR_TBL (0x11C)
1344 #define SPR_TBU (0x11D)
1345 #define SPR_TBU40 (0x11E)
1346 #define SPR_SVR (0x11E)
1347 #define SPR_BOOKE_PIR (0x11E)
1348 #define SPR_PVR (0x11F)
1349 #define SPR_HSPRG0 (0x130)
1350 #define SPR_BOOKE_DBSR (0x130)
1351 #define SPR_HSPRG1 (0x131)
1352 #define SPR_HDSISR (0x132)
1353 #define SPR_HDAR (0x133)
1354 #define SPR_BOOKE_EPCR (0x133)
1355 #define SPR_SPURR (0x134)
1356 #define SPR_BOOKE_DBCR0 (0x134)
1357 #define SPR_IBCR (0x135)
1358 #define SPR_PURR (0x135)
1359 #define SPR_BOOKE_DBCR1 (0x135)
1360 #define SPR_DBCR (0x136)
1361 #define SPR_HDEC (0x136)
1362 #define SPR_BOOKE_DBCR2 (0x136)
1363 #define SPR_HIOR (0x137)
1364 #define SPR_MBAR (0x137)
1365 #define SPR_RMOR (0x138)
1366 #define SPR_BOOKE_IAC1 (0x138)
1367 #define SPR_HRMOR (0x139)
1368 #define SPR_BOOKE_IAC2 (0x139)
1369 #define SPR_HSRR0 (0x13A)
1370 #define SPR_BOOKE_IAC3 (0x13A)
1371 #define SPR_HSRR1 (0x13B)
1372 #define SPR_BOOKE_IAC4 (0x13B)
1373 #define SPR_BOOKE_DAC1 (0x13C)
1374 #define SPR_LPIDR (0x13D)
1375 #define SPR_DABR2 (0x13D)
1376 #define SPR_BOOKE_DAC2 (0x13D)
1377 #define SPR_BOOKE_DVC1 (0x13E)
1378 #define SPR_LPCR (0x13E)
1379 #define SPR_BOOKE_DVC2 (0x13F)
1380 #define SPR_BOOKE_TSR (0x150)
1381 #define SPR_PCR (0x152)
1382 #define SPR_BOOKE_TCR (0x154)
1383 #define SPR_BOOKE_TLB0PS (0x158)
1384 #define SPR_BOOKE_TLB1PS (0x159)
1385 #define SPR_BOOKE_TLB2PS (0x15A)
1386 #define SPR_BOOKE_TLB3PS (0x15B)
1387 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1388 #define SPR_BOOKE_IVOR0 (0x190)
1389 #define SPR_BOOKE_IVOR1 (0x191)
1390 #define SPR_BOOKE_IVOR2 (0x192)
1391 #define SPR_BOOKE_IVOR3 (0x193)
1392 #define SPR_BOOKE_IVOR4 (0x194)
1393 #define SPR_BOOKE_IVOR5 (0x195)
1394 #define SPR_BOOKE_IVOR6 (0x196)
1395 #define SPR_BOOKE_IVOR7 (0x197)
1396 #define SPR_BOOKE_IVOR8 (0x198)
1397 #define SPR_BOOKE_IVOR9 (0x199)
1398 #define SPR_BOOKE_IVOR10 (0x19A)
1399 #define SPR_BOOKE_IVOR11 (0x19B)
1400 #define SPR_BOOKE_IVOR12 (0x19C)
1401 #define SPR_BOOKE_IVOR13 (0x19D)
1402 #define SPR_BOOKE_IVOR14 (0x19E)
1403 #define SPR_BOOKE_IVOR15 (0x19F)
1404 #define SPR_BOOKE_IVOR38 (0x1B0)
1405 #define SPR_BOOKE_IVOR39 (0x1B1)
1406 #define SPR_BOOKE_IVOR40 (0x1B2)
1407 #define SPR_BOOKE_IVOR41 (0x1B3)
1408 #define SPR_BOOKE_IVOR42 (0x1B4)
1409 #define SPR_BOOKE_GIVOR2 (0x1B8)
1410 #define SPR_BOOKE_GIVOR3 (0x1B9)
1411 #define SPR_BOOKE_GIVOR4 (0x1BA)
1412 #define SPR_BOOKE_GIVOR8 (0x1BB)
1413 #define SPR_BOOKE_GIVOR13 (0x1BC)
1414 #define SPR_BOOKE_GIVOR14 (0x1BD)
1415 #define SPR_TIR (0x1BE)
1416 #define SPR_BOOKE_SPEFSCR (0x200)
1417 #define SPR_Exxx_BBEAR (0x201)
1418 #define SPR_Exxx_BBTAR (0x202)
1419 #define SPR_Exxx_L1CFG0 (0x203)
1420 #define SPR_Exxx_L1CFG1 (0x204)
1421 #define SPR_Exxx_NPIDR (0x205)
1422 #define SPR_ATBL (0x20E)
1423 #define SPR_ATBU (0x20F)
1424 #define SPR_IBAT0U (0x210)
1425 #define SPR_BOOKE_IVOR32 (0x210)
1426 #define SPR_RCPU_MI_GRA (0x210)
1427 #define SPR_IBAT0L (0x211)
1428 #define SPR_BOOKE_IVOR33 (0x211)
1429 #define SPR_IBAT1U (0x212)
1430 #define SPR_BOOKE_IVOR34 (0x212)
1431 #define SPR_IBAT1L (0x213)
1432 #define SPR_BOOKE_IVOR35 (0x213)
1433 #define SPR_IBAT2U (0x214)
1434 #define SPR_BOOKE_IVOR36 (0x214)
1435 #define SPR_IBAT2L (0x215)
1436 #define SPR_BOOKE_IVOR37 (0x215)
1437 #define SPR_IBAT3U (0x216)
1438 #define SPR_IBAT3L (0x217)
1439 #define SPR_DBAT0U (0x218)
1440 #define SPR_RCPU_L2U_GRA (0x218)
1441 #define SPR_DBAT0L (0x219)
1442 #define SPR_DBAT1U (0x21A)
1443 #define SPR_DBAT1L (0x21B)
1444 #define SPR_DBAT2U (0x21C)
1445 #define SPR_DBAT2L (0x21D)
1446 #define SPR_DBAT3U (0x21E)
1447 #define SPR_DBAT3L (0x21F)
1448 #define SPR_IBAT4U (0x230)
1449 #define SPR_RPCU_BBCMCR (0x230)
1450 #define SPR_MPC_IC_CST (0x230)
1451 #define SPR_Exxx_CTXCR (0x230)
1452 #define SPR_IBAT4L (0x231)
1453 #define SPR_MPC_IC_ADR (0x231)
1454 #define SPR_Exxx_DBCR3 (0x231)
1455 #define SPR_IBAT5U (0x232)
1456 #define SPR_MPC_IC_DAT (0x232)
1457 #define SPR_Exxx_DBCNT (0x232)
1458 #define SPR_IBAT5L (0x233)
1459 #define SPR_IBAT6U (0x234)
1460 #define SPR_IBAT6L (0x235)
1461 #define SPR_IBAT7U (0x236)
1462 #define SPR_IBAT7L (0x237)
1463 #define SPR_DBAT4U (0x238)
1464 #define SPR_RCPU_L2U_MCR (0x238)
1465 #define SPR_MPC_DC_CST (0x238)
1466 #define SPR_Exxx_ALTCTXCR (0x238)
1467 #define SPR_DBAT4L (0x239)
1468 #define SPR_MPC_DC_ADR (0x239)
1469 #define SPR_DBAT5U (0x23A)
1470 #define SPR_BOOKE_MCSRR0 (0x23A)
1471 #define SPR_MPC_DC_DAT (0x23A)
1472 #define SPR_DBAT5L (0x23B)
1473 #define SPR_BOOKE_MCSRR1 (0x23B)
1474 #define SPR_DBAT6U (0x23C)
1475 #define SPR_BOOKE_MCSR (0x23C)
1476 #define SPR_DBAT6L (0x23D)
1477 #define SPR_Exxx_MCAR (0x23D)
1478 #define SPR_DBAT7U (0x23E)
1479 #define SPR_BOOKE_DSRR0 (0x23E)
1480 #define SPR_DBAT7L (0x23F)
1481 #define SPR_BOOKE_DSRR1 (0x23F)
1482 #define SPR_BOOKE_SPRG8 (0x25C)
1483 #define SPR_BOOKE_SPRG9 (0x25D)
1484 #define SPR_BOOKE_MAS0 (0x270)
1485 #define SPR_BOOKE_MAS1 (0x271)
1486 #define SPR_BOOKE_MAS2 (0x272)
1487 #define SPR_BOOKE_MAS3 (0x273)
1488 #define SPR_BOOKE_MAS4 (0x274)
1489 #define SPR_BOOKE_MAS5 (0x275)
1490 #define SPR_BOOKE_MAS6 (0x276)
1491 #define SPR_BOOKE_PID1 (0x279)
1492 #define SPR_BOOKE_PID2 (0x27A)
1493 #define SPR_MPC_DPDR (0x280)
1494 #define SPR_MPC_IMMR (0x288)
1495 #define SPR_BOOKE_TLB0CFG (0x2B0)
1496 #define SPR_BOOKE_TLB1CFG (0x2B1)
1497 #define SPR_BOOKE_TLB2CFG (0x2B2)
1498 #define SPR_BOOKE_TLB3CFG (0x2B3)
1499 #define SPR_BOOKE_EPR (0x2BE)
1500 #define SPR_PERF0 (0x300)
1501 #define SPR_RCPU_MI_RBA0 (0x300)
1502 #define SPR_MPC_MI_CTR (0x300)
1503 #define SPR_PERF1 (0x301)
1504 #define SPR_RCPU_MI_RBA1 (0x301)
1505 #define SPR_POWER_UMMCR2 (0x301)
1506 #define SPR_PERF2 (0x302)
1507 #define SPR_RCPU_MI_RBA2 (0x302)
1508 #define SPR_MPC_MI_AP (0x302)
1509 #define SPR_POWER_UMMCRA (0x302)
1510 #define SPR_PERF3 (0x303)
1511 #define SPR_RCPU_MI_RBA3 (0x303)
1512 #define SPR_MPC_MI_EPN (0x303)
1513 #define SPR_POWER_UPMC1 (0x303)
1514 #define SPR_PERF4 (0x304)
1515 #define SPR_POWER_UPMC2 (0x304)
1516 #define SPR_PERF5 (0x305)
1517 #define SPR_MPC_MI_TWC (0x305)
1518 #define SPR_POWER_UPMC3 (0x305)
1519 #define SPR_PERF6 (0x306)
1520 #define SPR_MPC_MI_RPN (0x306)
1521 #define SPR_POWER_UPMC4 (0x306)
1522 #define SPR_PERF7 (0x307)
1523 #define SPR_POWER_UPMC5 (0x307)
1524 #define SPR_PERF8 (0x308)
1525 #define SPR_RCPU_L2U_RBA0 (0x308)
1526 #define SPR_MPC_MD_CTR (0x308)
1527 #define SPR_POWER_UPMC6 (0x308)
1528 #define SPR_PERF9 (0x309)
1529 #define SPR_RCPU_L2U_RBA1 (0x309)
1530 #define SPR_MPC_MD_CASID (0x309)
1531 #define SPR_970_UPMC7 (0X309)
1532 #define SPR_PERFA (0x30A)
1533 #define SPR_RCPU_L2U_RBA2 (0x30A)
1534 #define SPR_MPC_MD_AP (0x30A)
1535 #define SPR_970_UPMC8 (0X30A)
1536 #define SPR_PERFB (0x30B)
1537 #define SPR_RCPU_L2U_RBA3 (0x30B)
1538 #define SPR_MPC_MD_EPN (0x30B)
1539 #define SPR_POWER_UMMCR0 (0X30B)
1540 #define SPR_PERFC (0x30C)
1541 #define SPR_MPC_MD_TWB (0x30C)
1542 #define SPR_POWER_USIAR (0X30C)
1543 #define SPR_PERFD (0x30D)
1544 #define SPR_MPC_MD_TWC (0x30D)
1545 #define SPR_POWER_USDAR (0X30D)
1546 #define SPR_PERFE (0x30E)
1547 #define SPR_MPC_MD_RPN (0x30E)
1548 #define SPR_POWER_UMMCR1 (0X30E)
1549 #define SPR_PERFF (0x30F)
1550 #define SPR_MPC_MD_TW (0x30F)
1551 #define SPR_UPERF0 (0x310)
1552 #define SPR_UPERF1 (0x311)
1553 #define SPR_POWER_MMCR2 (0x311)
1554 #define SPR_UPERF2 (0x312)
1555 #define SPR_POWER_MMCRA (0X312)
1556 #define SPR_UPERF3 (0x313)
1557 #define SPR_POWER_PMC1 (0X313)
1558 #define SPR_UPERF4 (0x314)
1559 #define SPR_POWER_PMC2 (0X314)
1560 #define SPR_UPERF5 (0x315)
1561 #define SPR_POWER_PMC3 (0X315)
1562 #define SPR_UPERF6 (0x316)
1563 #define SPR_POWER_PMC4 (0X316)
1564 #define SPR_UPERF7 (0x317)
1565 #define SPR_POWER_PMC5 (0X317)
1566 #define SPR_UPERF8 (0x318)
1567 #define SPR_POWER_PMC6 (0X318)
1568 #define SPR_UPERF9 (0x319)
1569 #define SPR_970_PMC7 (0X319)
1570 #define SPR_UPERFA (0x31A)
1571 #define SPR_970_PMC8 (0X31A)
1572 #define SPR_UPERFB (0x31B)
1573 #define SPR_POWER_MMCR0 (0X31B)
1574 #define SPR_UPERFC (0x31C)
1575 #define SPR_POWER_SIAR (0X31C)
1576 #define SPR_UPERFD (0x31D)
1577 #define SPR_POWER_SDAR (0X31D)
1578 #define SPR_UPERFE (0x31E)
1579 #define SPR_POWER_MMCR1 (0X31E)
1580 #define SPR_UPERFF (0x31F)
1581 #define SPR_RCPU_MI_RA0 (0x320)
1582 #define SPR_MPC_MI_DBCAM (0x320)
1583 #define SPR_BESCRS (0x320)
1584 #define SPR_RCPU_MI_RA1 (0x321)
1585 #define SPR_MPC_MI_DBRAM0 (0x321)
1586 #define SPR_BESCRSU (0x321)
1587 #define SPR_RCPU_MI_RA2 (0x322)
1588 #define SPR_MPC_MI_DBRAM1 (0x322)
1589 #define SPR_BESCRR (0x322)
1590 #define SPR_RCPU_MI_RA3 (0x323)
1591 #define SPR_BESCRRU (0x323)
1592 #define SPR_EBBHR (0x324)
1593 #define SPR_EBBRR (0x325)
1594 #define SPR_BESCR (0x326)
1595 #define SPR_RCPU_L2U_RA0 (0x328)
1596 #define SPR_MPC_MD_DBCAM (0x328)
1597 #define SPR_RCPU_L2U_RA1 (0x329)
1598 #define SPR_MPC_MD_DBRAM0 (0x329)
1599 #define SPR_RCPU_L2U_RA2 (0x32A)
1600 #define SPR_MPC_MD_DBRAM1 (0x32A)
1601 #define SPR_RCPU_L2U_RA3 (0x32B)
1602 #define SPR_TAR (0x32F)
1603 #define SPR_440_INV0 (0x370)
1604 #define SPR_440_INV1 (0x371)
1605 #define SPR_440_INV2 (0x372)
1606 #define SPR_440_INV3 (0x373)
1607 #define SPR_440_ITV0 (0x374)
1608 #define SPR_440_ITV1 (0x375)
1609 #define SPR_440_ITV2 (0x376)
1610 #define SPR_440_ITV3 (0x377)
1611 #define SPR_440_CCR1 (0x378)
1612 #define SPR_DCRIPR (0x37B)
1613 #define SPR_POWER_MMCRS (0x37E)
1614 #define SPR_PPR (0x380)
1615 #define SPR_750_GQR0 (0x390)
1616 #define SPR_440_DNV0 (0x390)
1617 #define SPR_750_GQR1 (0x391)
1618 #define SPR_440_DNV1 (0x391)
1619 #define SPR_750_GQR2 (0x392)
1620 #define SPR_440_DNV2 (0x392)
1621 #define SPR_750_GQR3 (0x393)
1622 #define SPR_440_DNV3 (0x393)
1623 #define SPR_750_GQR4 (0x394)
1624 #define SPR_440_DTV0 (0x394)
1625 #define SPR_750_GQR5 (0x395)
1626 #define SPR_440_DTV1 (0x395)
1627 #define SPR_750_GQR6 (0x396)
1628 #define SPR_440_DTV2 (0x396)
1629 #define SPR_750_GQR7 (0x397)
1630 #define SPR_440_DTV3 (0x397)
1631 #define SPR_750_THRM4 (0x398)
1632 #define SPR_750CL_HID2 (0x398)
1633 #define SPR_440_DVLIM (0x398)
1634 #define SPR_750_WPAR (0x399)
1635 #define SPR_440_IVLIM (0x399)
1636 #define SPR_750_DMAU (0x39A)
1637 #define SPR_750_DMAL (0x39B)
1638 #define SPR_440_RSTCFG (0x39B)
1639 #define SPR_BOOKE_DCDBTRL (0x39C)
1640 #define SPR_BOOKE_DCDBTRH (0x39D)
1641 #define SPR_BOOKE_ICDBTRL (0x39E)
1642 #define SPR_BOOKE_ICDBTRH (0x39F)
1643 #define SPR_74XX_UMMCR2 (0x3A0)
1644 #define SPR_7XX_UPMC5 (0x3A1)
1645 #define SPR_7XX_UPMC6 (0x3A2)
1646 #define SPR_UBAMR (0x3A7)
1647 #define SPR_7XX_UMMCR0 (0x3A8)
1648 #define SPR_7XX_UPMC1 (0x3A9)
1649 #define SPR_7XX_UPMC2 (0x3AA)
1650 #define SPR_7XX_USIAR (0x3AB)
1651 #define SPR_7XX_UMMCR1 (0x3AC)
1652 #define SPR_7XX_UPMC3 (0x3AD)
1653 #define SPR_7XX_UPMC4 (0x3AE)
1654 #define SPR_USDA (0x3AF)
1655 #define SPR_40x_ZPR (0x3B0)
1656 #define SPR_BOOKE_MAS7 (0x3B0)
1657 #define SPR_74XX_MMCR2 (0x3B0)
1658 #define SPR_7XX_PMC5 (0x3B1)
1659 #define SPR_40x_PID (0x3B1)
1660 #define SPR_7XX_PMC6 (0x3B2)
1661 #define SPR_440_MMUCR (0x3B2)
1662 #define SPR_4xx_CCR0 (0x3B3)
1663 #define SPR_BOOKE_EPLC (0x3B3)
1664 #define SPR_405_IAC3 (0x3B4)
1665 #define SPR_BOOKE_EPSC (0x3B4)
1666 #define SPR_405_IAC4 (0x3B5)
1667 #define SPR_405_DVC1 (0x3B6)
1668 #define SPR_405_DVC2 (0x3B7)
1669 #define SPR_BAMR (0x3B7)
1670 #define SPR_7XX_MMCR0 (0x3B8)
1671 #define SPR_7XX_PMC1 (0x3B9)
1672 #define SPR_40x_SGR (0x3B9)
1673 #define SPR_7XX_PMC2 (0x3BA)
1674 #define SPR_40x_DCWR (0x3BA)
1675 #define SPR_7XX_SIAR (0x3BB)
1676 #define SPR_405_SLER (0x3BB)
1677 #define SPR_7XX_MMCR1 (0x3BC)
1678 #define SPR_405_SU0R (0x3BC)
1679 #define SPR_401_SKR (0x3BC)
1680 #define SPR_7XX_PMC3 (0x3BD)
1681 #define SPR_405_DBCR1 (0x3BD)
1682 #define SPR_7XX_PMC4 (0x3BE)
1683 #define SPR_SDA (0x3BF)
1684 #define SPR_403_VTBL (0x3CC)
1685 #define SPR_403_VTBU (0x3CD)
1686 #define SPR_DMISS (0x3D0)
1687 #define SPR_DCMP (0x3D1)
1688 #define SPR_HASH1 (0x3D2)
1689 #define SPR_HASH2 (0x3D3)
1690 #define SPR_BOOKE_ICDBDR (0x3D3)
1691 #define SPR_TLBMISS (0x3D4)
1692 #define SPR_IMISS (0x3D4)
1693 #define SPR_40x_ESR (0x3D4)
1694 #define SPR_PTEHI (0x3D5)
1695 #define SPR_ICMP (0x3D5)
1696 #define SPR_40x_DEAR (0x3D5)
1697 #define SPR_PTELO (0x3D6)
1698 #define SPR_RPA (0x3D6)
1699 #define SPR_40x_EVPR (0x3D6)
1700 #define SPR_L3PM (0x3D7)
1701 #define SPR_403_CDBCR (0x3D7)
1702 #define SPR_L3ITCR0 (0x3D8)
1703 #define SPR_TCR (0x3D8)
1704 #define SPR_40x_TSR (0x3D8)
1705 #define SPR_IBR (0x3DA)
1706 #define SPR_40x_TCR (0x3DA)
1707 #define SPR_ESASRR (0x3DB)
1708 #define SPR_40x_PIT (0x3DB)
1709 #define SPR_403_TBL (0x3DC)
1710 #define SPR_403_TBU (0x3DD)
1711 #define SPR_SEBR (0x3DE)
1712 #define SPR_40x_SRR2 (0x3DE)
1713 #define SPR_SER (0x3DF)
1714 #define SPR_40x_SRR3 (0x3DF)
1715 #define SPR_L3OHCR (0x3E8)
1716 #define SPR_L3ITCR1 (0x3E9)
1717 #define SPR_L3ITCR2 (0x3EA)
1718 #define SPR_L3ITCR3 (0x3EB)
1719 #define SPR_HID0 (0x3F0)
1720 #define SPR_40x_DBSR (0x3F0)
1721 #define SPR_HID1 (0x3F1)
1722 #define SPR_IABR (0x3F2)
1723 #define SPR_40x_DBCR0 (0x3F2)
1724 #define SPR_601_HID2 (0x3F2)
1725 #define SPR_Exxx_L1CSR0 (0x3F2)
1726 #define SPR_ICTRL (0x3F3)
1727 #define SPR_HID2 (0x3F3)
1728 #define SPR_750CL_HID4 (0x3F3)
1729 #define SPR_Exxx_L1CSR1 (0x3F3)
1730 #define SPR_440_DBDR (0x3F3)
1731 #define SPR_LDSTDB (0x3F4)
1732 #define SPR_750_TDCL (0x3F4)
1733 #define SPR_40x_IAC1 (0x3F4)
1734 #define SPR_MMUCSR0 (0x3F4)
1735 #define SPR_970_HID4 (0x3F4)
1736 #define SPR_DABR (0x3F5)
1737 #define DABR_MASK (~(target_ulong)0x7)
1738 #define SPR_Exxx_BUCSR (0x3F5)
1739 #define SPR_40x_IAC2 (0x3F5)
1740 #define SPR_601_HID5 (0x3F5)
1741 #define SPR_40x_DAC1 (0x3F6)
1742 #define SPR_MSSCR0 (0x3F6)
1743 #define SPR_970_HID5 (0x3F6)
1744 #define SPR_MSSSR0 (0x3F7)
1745 #define SPR_MSSCR1 (0x3F7)
1746 #define SPR_DABRX (0x3F7)
1747 #define SPR_40x_DAC2 (0x3F7)
1748 #define SPR_MMUCFG (0x3F7)
1749 #define SPR_LDSTCR (0x3F8)
1750 #define SPR_L2PMCR (0x3F8)
1751 #define SPR_750FX_HID2 (0x3F8)
1752 #define SPR_Exxx_L1FINV0 (0x3F8)
1753 #define SPR_L2CR (0x3F9)
1754 #define SPR_L3CR (0x3FA)
1755 #define SPR_750_TDCH (0x3FA)
1756 #define SPR_IABR2 (0x3FA)
1757 #define SPR_40x_DCCR (0x3FA)
1758 #define SPR_ICTC (0x3FB)
1759 #define SPR_40x_ICCR (0x3FB)
1760 #define SPR_THRM1 (0x3FC)
1761 #define SPR_403_PBL1 (0x3FC)
1762 #define SPR_SP (0x3FD)
1763 #define SPR_THRM2 (0x3FD)
1764 #define SPR_403_PBU1 (0x3FD)
1765 #define SPR_604_HID13 (0x3FD)
1766 #define SPR_LT (0x3FE)
1767 #define SPR_THRM3 (0x3FE)
1768 #define SPR_RCPU_FPECR (0x3FE)
1769 #define SPR_403_PBL2 (0x3FE)
1770 #define SPR_PIR (0x3FF)
1771 #define SPR_403_PBU2 (0x3FF)
1772 #define SPR_601_HID15 (0x3FF)
1773 #define SPR_604_HID15 (0x3FF)
1774 #define SPR_E500_SVR (0x3FF)
1775
1776 /* Disable MAS Interrupt Updates for Hypervisor */
1777 #define EPCR_DMIUH (1 << 22)
1778 /* Disable Guest TLB Management Instructions */
1779 #define EPCR_DGTMI (1 << 23)
1780 /* Guest Interrupt Computation Mode */
1781 #define EPCR_GICM (1 << 24)
1782 /* Interrupt Computation Mode */
1783 #define EPCR_ICM (1 << 25)
1784 /* Disable Embedded Hypervisor Debug */
1785 #define EPCR_DUVD (1 << 26)
1786 /* Instruction Storage Interrupt Directed to Guest State */
1787 #define EPCR_ISIGS (1 << 27)
1788 /* Data Storage Interrupt Directed to Guest State */
1789 #define EPCR_DSIGS (1 << 28)
1790 /* Instruction TLB Error Interrupt Directed to Guest State */
1791 #define EPCR_ITLBGS (1 << 29)
1792 /* Data TLB Error Interrupt Directed to Guest State */
1793 #define EPCR_DTLBGS (1 << 30)
1794 /* External Input Interrupt Directed to Guest State */
1795 #define EPCR_EXTGS (1 << 31)
1796
1797 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1798 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1799 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1800 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1801 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1802
1803 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1804 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1805 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1806 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1807 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1808
1809 /* HID0 bits */
1810 #define HID0_DEEPNAP (1 << 24)
1811 #define HID0_DOZE (1 << 23)
1812 #define HID0_NAP (1 << 22)
1813
1814 /*****************************************************************************/
1815 /* PowerPC Instructions types definitions */
1816 enum {
1817 PPC_NONE = 0x0000000000000000ULL,
1818 /* PowerPC base instructions set */
1819 PPC_INSNS_BASE = 0x0000000000000001ULL,
1820 /* integer operations instructions */
1821 #define PPC_INTEGER PPC_INSNS_BASE
1822 /* flow control instructions */
1823 #define PPC_FLOW PPC_INSNS_BASE
1824 /* virtual memory instructions */
1825 #define PPC_MEM PPC_INSNS_BASE
1826 /* ld/st with reservation instructions */
1827 #define PPC_RES PPC_INSNS_BASE
1828 /* spr/msr access instructions */
1829 #define PPC_MISC PPC_INSNS_BASE
1830 /* Deprecated instruction sets */
1831 /* Original POWER instruction set */
1832 PPC_POWER = 0x0000000000000002ULL,
1833 /* POWER2 instruction set extension */
1834 PPC_POWER2 = 0x0000000000000004ULL,
1835 /* Power RTC support */
1836 PPC_POWER_RTC = 0x0000000000000008ULL,
1837 /* Power-to-PowerPC bridge (601) */
1838 PPC_POWER_BR = 0x0000000000000010ULL,
1839 /* 64 bits PowerPC instruction set */
1840 PPC_64B = 0x0000000000000020ULL,
1841 /* New 64 bits extensions (PowerPC 2.0x) */
1842 PPC_64BX = 0x0000000000000040ULL,
1843 /* 64 bits hypervisor extensions */
1844 PPC_64H = 0x0000000000000080ULL,
1845 /* New wait instruction (PowerPC 2.0x) */
1846 PPC_WAIT = 0x0000000000000100ULL,
1847 /* Time base mftb instruction */
1848 PPC_MFTB = 0x0000000000000200ULL,
1849
1850 /* Fixed-point unit extensions */
1851 /* PowerPC 602 specific */
1852 PPC_602_SPEC = 0x0000000000000400ULL,
1853 /* isel instruction */
1854 PPC_ISEL = 0x0000000000000800ULL,
1855 /* popcntb instruction */
1856 PPC_POPCNTB = 0x0000000000001000ULL,
1857 /* string load / store */
1858 PPC_STRING = 0x0000000000002000ULL,
1859
1860 /* Floating-point unit extensions */
1861 /* Optional floating point instructions */
1862 PPC_FLOAT = 0x0000000000010000ULL,
1863 /* New floating-point extensions (PowerPC 2.0x) */
1864 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1865 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1866 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1867 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1868 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1869 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1870 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1871
1872 /* Vector/SIMD extensions */
1873 /* Altivec support */
1874 PPC_ALTIVEC = 0x0000000001000000ULL,
1875 /* PowerPC 2.03 SPE extension */
1876 PPC_SPE = 0x0000000002000000ULL,
1877 /* PowerPC 2.03 SPE single-precision floating-point extension */
1878 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1879 /* PowerPC 2.03 SPE double-precision floating-point extension */
1880 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1881
1882 /* Optional memory control instructions */
1883 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1884 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1885 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1886 /* sync instruction */
1887 PPC_MEM_SYNC = 0x0000000080000000ULL,
1888 /* eieio instruction */
1889 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1890
1891 /* Cache control instructions */
1892 PPC_CACHE = 0x0000000200000000ULL,
1893 /* icbi instruction */
1894 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1895 /* dcbz instruction */
1896 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1897 /* dcba instruction */
1898 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1899 /* Freescale cache locking instructions */
1900 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1901
1902 /* MMU related extensions */
1903 /* external control instructions */
1904 PPC_EXTERN = 0x0000010000000000ULL,
1905 /* segment register access instructions */
1906 PPC_SEGMENT = 0x0000020000000000ULL,
1907 /* PowerPC 6xx TLB management instructions */
1908 PPC_6xx_TLB = 0x0000040000000000ULL,
1909 /* PowerPC 74xx TLB management instructions */
1910 PPC_74xx_TLB = 0x0000080000000000ULL,
1911 /* PowerPC 40x TLB management instructions */
1912 PPC_40x_TLB = 0x0000100000000000ULL,
1913 /* segment register access instructions for PowerPC 64 "bridge" */
1914 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1915 /* SLB management */
1916 PPC_SLBI = 0x0000400000000000ULL,
1917
1918 /* Embedded PowerPC dedicated instructions */
1919 PPC_WRTEE = 0x0001000000000000ULL,
1920 /* PowerPC 40x exception model */
1921 PPC_40x_EXCP = 0x0002000000000000ULL,
1922 /* PowerPC 405 Mac instructions */
1923 PPC_405_MAC = 0x0004000000000000ULL,
1924 /* PowerPC 440 specific instructions */
1925 PPC_440_SPEC = 0x0008000000000000ULL,
1926 /* BookE (embedded) PowerPC specification */
1927 PPC_BOOKE = 0x0010000000000000ULL,
1928 /* mfapidi instruction */
1929 PPC_MFAPIDI = 0x0020000000000000ULL,
1930 /* tlbiva instruction */
1931 PPC_TLBIVA = 0x0040000000000000ULL,
1932 /* tlbivax instruction */
1933 PPC_TLBIVAX = 0x0080000000000000ULL,
1934 /* PowerPC 4xx dedicated instructions */
1935 PPC_4xx_COMMON = 0x0100000000000000ULL,
1936 /* PowerPC 40x ibct instructions */
1937 PPC_40x_ICBT = 0x0200000000000000ULL,
1938 /* rfmci is not implemented in all BookE PowerPC */
1939 PPC_RFMCI = 0x0400000000000000ULL,
1940 /* rfdi instruction */
1941 PPC_RFDI = 0x0800000000000000ULL,
1942 /* DCR accesses */
1943 PPC_DCR = 0x1000000000000000ULL,
1944 /* DCR extended accesse */
1945 PPC_DCRX = 0x2000000000000000ULL,
1946 /* user-mode DCR access, implemented in PowerPC 460 */
1947 PPC_DCRUX = 0x4000000000000000ULL,
1948 /* popcntw and popcntd instructions */
1949 PPC_POPCNTWD = 0x8000000000000000ULL,
1950
1951 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1952 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1953 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1954 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1955 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1956 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1957 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1958 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1959 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1960 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1961 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1962 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1963 | PPC_CACHE | PPC_CACHE_ICBI \
1964 | PPC_CACHE_DCBZ \
1965 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1966 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1967 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1968 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1969 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1970 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1971 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1972 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1973 | PPC_POPCNTWD)
1974
1975 /* extended type values */
1976
1977 /* BookE 2.06 PowerPC specification */
1978 PPC2_BOOKE206 = 0x0000000000000001ULL,
1979 /* VSX (extensions to Altivec / VMX) */
1980 PPC2_VSX = 0x0000000000000002ULL,
1981 /* Decimal Floating Point (DFP) */
1982 PPC2_DFP = 0x0000000000000004ULL,
1983 /* Embedded.Processor Control */
1984 PPC2_PRCNTL = 0x0000000000000008ULL,
1985 /* Byte-reversed, indexed, double-word load and store */
1986 PPC2_DBRX = 0x0000000000000010ULL,
1987 /* Book I 2.05 PowerPC specification */
1988 PPC2_ISA205 = 0x0000000000000020ULL,
1989 /* VSX additions in ISA 2.07 */
1990 PPC2_VSX207 = 0x0000000000000040ULL,
1991 /* ISA 2.06B bpermd */
1992 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
1993 /* ISA 2.06B divide extended variants */
1994 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1995 /* ISA 2.06B larx/stcx. instructions */
1996 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1997 /* ISA 2.06B floating point integer conversion */
1998 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
1999 /* ISA 2.06B floating point test instructions */
2000 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2001 /* ISA 2.07 bctar instruction */
2002 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2003 /* ISA 2.07 load/store quadword */
2004 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2005 /* ISA 2.07 Altivec */
2006 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2007 /* PowerISA 2.07 Book3s specification */
2008 PPC2_ISA207S = 0x0000000000008000ULL,
2009
2010 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2011 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2012 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2013 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2014 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2015 PPC2_ALTIVEC_207 | PPC2_ISA207S)
2016 };
2017
2018 /*****************************************************************************/
2019 /* Memory access type :
2020 * may be needed for precise access rights control and precise exceptions.
2021 */
2022 enum {
2023 /* 1 bit to define user level / supervisor access */
2024 ACCESS_USER = 0x00,
2025 ACCESS_SUPER = 0x01,
2026 /* Type of instruction that generated the access */
2027 ACCESS_CODE = 0x10, /* Code fetch access */
2028 ACCESS_INT = 0x20, /* Integer load/store access */
2029 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2030 ACCESS_RES = 0x40, /* load/store with reservation */
2031 ACCESS_EXT = 0x50, /* external access */
2032 ACCESS_CACHE = 0x60, /* Cache manipulation */
2033 };
2034
2035 /* Hardware interruption sources:
2036 * all those exception can be raised simulteaneously
2037 */
2038 /* Input pins definitions */
2039 enum {
2040 /* 6xx bus input pins */
2041 PPC6xx_INPUT_HRESET = 0,
2042 PPC6xx_INPUT_SRESET = 1,
2043 PPC6xx_INPUT_CKSTP_IN = 2,
2044 PPC6xx_INPUT_MCP = 3,
2045 PPC6xx_INPUT_SMI = 4,
2046 PPC6xx_INPUT_INT = 5,
2047 PPC6xx_INPUT_TBEN = 6,
2048 PPC6xx_INPUT_WAKEUP = 7,
2049 PPC6xx_INPUT_NB,
2050 };
2051
2052 enum {
2053 /* Embedded PowerPC input pins */
2054 PPCBookE_INPUT_HRESET = 0,
2055 PPCBookE_INPUT_SRESET = 1,
2056 PPCBookE_INPUT_CKSTP_IN = 2,
2057 PPCBookE_INPUT_MCP = 3,
2058 PPCBookE_INPUT_SMI = 4,
2059 PPCBookE_INPUT_INT = 5,
2060 PPCBookE_INPUT_CINT = 6,
2061 PPCBookE_INPUT_NB,
2062 };
2063
2064 enum {
2065 /* PowerPC E500 input pins */
2066 PPCE500_INPUT_RESET_CORE = 0,
2067 PPCE500_INPUT_MCK = 1,
2068 PPCE500_INPUT_CINT = 3,
2069 PPCE500_INPUT_INT = 4,
2070 PPCE500_INPUT_DEBUG = 6,
2071 PPCE500_INPUT_NB,
2072 };
2073
2074 enum {
2075 /* PowerPC 40x input pins */
2076 PPC40x_INPUT_RESET_CORE = 0,
2077 PPC40x_INPUT_RESET_CHIP = 1,
2078 PPC40x_INPUT_RESET_SYS = 2,
2079 PPC40x_INPUT_CINT = 3,
2080 PPC40x_INPUT_INT = 4,
2081 PPC40x_INPUT_HALT = 5,
2082 PPC40x_INPUT_DEBUG = 6,
2083 PPC40x_INPUT_NB,
2084 };
2085
2086 enum {
2087 /* RCPU input pins */
2088 PPCRCPU_INPUT_PORESET = 0,
2089 PPCRCPU_INPUT_HRESET = 1,
2090 PPCRCPU_INPUT_SRESET = 2,
2091 PPCRCPU_INPUT_IRQ0 = 3,
2092 PPCRCPU_INPUT_IRQ1 = 4,
2093 PPCRCPU_INPUT_IRQ2 = 5,
2094 PPCRCPU_INPUT_IRQ3 = 6,
2095 PPCRCPU_INPUT_IRQ4 = 7,
2096 PPCRCPU_INPUT_IRQ5 = 8,
2097 PPCRCPU_INPUT_IRQ6 = 9,
2098 PPCRCPU_INPUT_IRQ7 = 10,
2099 PPCRCPU_INPUT_NB,
2100 };
2101
2102 #if defined(TARGET_PPC64)
2103 enum {
2104 /* PowerPC 970 input pins */
2105 PPC970_INPUT_HRESET = 0,
2106 PPC970_INPUT_SRESET = 1,
2107 PPC970_INPUT_CKSTP = 2,
2108 PPC970_INPUT_TBEN = 3,
2109 PPC970_INPUT_MCP = 4,
2110 PPC970_INPUT_INT = 5,
2111 PPC970_INPUT_THINT = 6,
2112 PPC970_INPUT_NB,
2113 };
2114
2115 enum {
2116 /* POWER7 input pins */
2117 POWER7_INPUT_INT = 0,
2118 /* POWER7 probably has other inputs, but we don't care about them
2119 * for any existing machine. We can wire these up when we need
2120 * them */
2121 POWER7_INPUT_NB,
2122 };
2123 #endif
2124
2125 /* Hardware exceptions definitions */
2126 enum {
2127 /* External hardware exception sources */
2128 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2129 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2130 PPC_INTERRUPT_MCK, /* Machine check exception */
2131 PPC_INTERRUPT_EXT, /* External interrupt */
2132 PPC_INTERRUPT_SMI, /* System management interrupt */
2133 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2134 PPC_INTERRUPT_DEBUG, /* External debug exception */
2135 PPC_INTERRUPT_THERM, /* Thermal exception */
2136 /* Internal hardware exception sources */
2137 PPC_INTERRUPT_DECR, /* Decrementer exception */
2138 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2139 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2140 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2141 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2142 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2143 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2144 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2145 };
2146
2147 /* Processor Compatibility mask (PCR) */
2148 enum {
2149 PCR_COMPAT_2_05 = 1ull << (63-62),
2150 PCR_COMPAT_2_06 = 1ull << (63-61),
2151 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2152 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2153 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2154 };
2155
2156 /*****************************************************************************/
2157
2158 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2159 {
2160 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2161 }
2162
2163 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2164 {
2165 env->so = (xer >> XER_SO) & 1;
2166 env->ov = (xer >> XER_OV) & 1;
2167 env->ca = (xer >> XER_CA) & 1;
2168 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2169 }
2170
2171 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2172 target_ulong *cs_base, int *flags)
2173 {
2174 *pc = env->nip;
2175 *cs_base = 0;
2176 *flags = env->hflags;
2177 }
2178
2179 #if !defined(CONFIG_USER_ONLY)
2180 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2181 {
2182 uintptr_t tlbml = (uintptr_t)tlbm;
2183 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2184
2185 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2186 }
2187
2188 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2189 {
2190 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2191 int r = tlbncfg & TLBnCFG_N_ENTRY;
2192 return r;
2193 }
2194
2195 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2196 {
2197 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2198 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2199 return r;
2200 }
2201
2202 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2203 {
2204 int id = booke206_tlbm_id(env, tlbm);
2205 int end = 0;
2206 int i;
2207
2208 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2209 end += booke206_tlb_size(env, i);
2210 if (id < end) {
2211 return i;
2212 }
2213 }
2214
2215 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2216 return 0;
2217 }
2218
2219 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2220 {
2221 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2222 int tlbid = booke206_tlbm_id(env, tlb);
2223 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2224 }
2225
2226 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2227 target_ulong ea, int way)
2228 {
2229 int r;
2230 uint32_t ways = booke206_tlb_ways(env, tlbn);
2231 int ways_bits = ffs(ways) - 1;
2232 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2233 int i;
2234
2235 way &= ways - 1;
2236 ea >>= MAS2_EPN_SHIFT;
2237 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2238 r = (ea << ways_bits) | way;
2239
2240 if (r >= booke206_tlb_size(env, tlbn)) {
2241 return NULL;
2242 }
2243
2244 /* bump up to tlbn index */
2245 for (i = 0; i < tlbn; i++) {
2246 r += booke206_tlb_size(env, i);
2247 }
2248
2249 return &env->tlb.tlbm[r];
2250 }
2251
2252 /* returns bitmap of supported page sizes for a given TLB */
2253 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2254 {
2255 bool mav2 = false;
2256 uint32_t ret = 0;
2257
2258 if (mav2) {
2259 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2260 } else {
2261 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2262 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2263 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2264 int i;
2265 for (i = min; i <= max; i++) {
2266 ret |= (1 << (i << 1));
2267 }
2268 }
2269
2270 return ret;
2271 }
2272
2273 #endif
2274
2275 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2276 {
2277 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2278 return msr & (1ULL << MSR_CM);
2279 }
2280
2281 return msr & (1ULL << MSR_SF);
2282 }
2283
2284 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2285
2286 #include "exec/exec-all.h"
2287
2288 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2289
2290 /**
2291 * ppc_get_vcpu_dt_id:
2292 * @cs: a PowerPCCPU struct.
2293 *
2294 * Returns a device-tree ID for a CPU.
2295 */
2296 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2297
2298 /**
2299 * ppc_get_vcpu_by_dt_id:
2300 * @cpu_dt_id: a device tree id
2301 *
2302 * Searches for a CPU by @cpu_dt_id.
2303 *
2304 * Returns: a PowerPCCPU struct
2305 */
2306 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2307
2308 #endif /* !defined (__CPU_PPC_H__) */
QEmu