target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & ARM_CP_SPECIAL) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 112         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 115 #else
 116         /* Reset into the highest available EL */
 117         if (arm_feature(env, ARM_FEATURE_EL3)) {
 118             env->pstate = PSTATE_MODE_EL3h;
 119         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 120             env->pstate = PSTATE_MODE_EL2h;
 121         } else {
 122             env->pstate = PSTATE_MODE_EL1h;
 123         }
 124         env->pc = cpu->rvbar;
 125 #endif
 126     } else {
 127 #if defined(CONFIG_USER_ONLY)
 128         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 129         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 130 #endif
 131     }
 132
 133 #if defined(CONFIG_USER_ONLY)
 134     env->uncached_cpsr = ARM_CPU_MODE_USR;
 135     /* For user mode we must enable access to coprocessors */
 136     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 137     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 138         env->cp15.c15_cpar = 3;
 139     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 140         env->cp15.c15_cpar = 1;
 141     }
 142 #else
 143     /* SVC mode with interrupts disabled.  */
 144     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 145     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 146     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 147      * clear at reset. Initial SP and PC are loaded from ROM.
 148      */
 149     if (IS_M(env)) {
 150         uint32_t initial_msp; /* Loaded from 0x0 */
 151         uint32_t initial_pc; /* Loaded from 0x4 */
 152         uint8_t *rom;
 153
 154         env->daif &= ~PSTATE_I;
 155         rom = rom_ptr(0);
 156         if (rom) {
 157             /* Address zero is covered by ROM which hasn't yet been
 158              * copied into physical memory.
 159              */
 160             initial_msp = ldl_p(rom);
 161             initial_pc = ldl_p(rom + 4);
 162         } else {
 163             /* Address zero not covered by a ROM blob, or the ROM blob
 164              * is in non-modifiable memory and this is a second reset after
 165              * it got copied into memory. In the latter case, rom_ptr
 166              * will return a NULL pointer and we should use ldl_phys instead.
 167              */
 168             initial_msp = ldl_phys(s->as, 0);
 169             initial_pc = ldl_phys(s->as, 4);
 170         }
 171
 172         env->regs[13] = initial_msp & 0xFFFFFFFC;
 173         env->regs[15] = initial_pc & ~1;
 174         env->thumb = initial_pc & 1;
 175     }
 176
 177     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 178      * executing as AArch32 then check if highvecs are enabled and
 179      * adjust the PC accordingly.
 180      */
 181     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 182         env->regs[15] = 0xFFFF0000;
 183     }
 184
 185     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 186 #endif
 187     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 188     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 189     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 190     set_float_detect_tininess(float_tininess_before_rounding,
 191                               &env->vfp.fp_status);
 192     set_float_detect_tininess(float_tininess_before_rounding,
 193                               &env->vfp.standard_fp_status);
 194     tlb_flush(s, 1);
 195
 196 #ifndef CONFIG_USER_ONLY
 197     if (kvm_enabled()) {
 198         kvm_arm_reset_vcpu(cpu);
 199     }
 200 #endif
 201
 202     hw_breakpoint_update_all(cpu);
 203     hw_watchpoint_update_all(cpu);
 204 }
 205
 206 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 207 {
 208     CPUClass *cc = CPU_GET_CLASS(cs);
 209     bool ret = false;
 210
 211     if (interrupt_request & CPU_INTERRUPT_FIQ
 212         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 213         cs->exception_index = EXCP_FIQ;
 214         cc->do_interrupt(cs);
 215         ret = true;
 216     }
 217     if (interrupt_request & CPU_INTERRUPT_HARD
 218         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 219         cs->exception_index = EXCP_IRQ;
 220         cc->do_interrupt(cs);
 221         ret = true;
 222     }
 223     if (interrupt_request & CPU_INTERRUPT_VIRQ
 224         && arm_excp_unmasked(cs, EXCP_VIRQ)) {
 225         cs->exception_index = EXCP_VIRQ;
 226         cc->do_interrupt(cs);
 227         ret = true;
 228     }
 229     if (interrupt_request & CPU_INTERRUPT_VFIQ
 230         && arm_excp_unmasked(cs, EXCP_VFIQ)) {
 231         cs->exception_index = EXCP_VFIQ;
 232         cc->do_interrupt(cs);
 233         ret = true;
 234     }
 235
 236     return ret;
 237 }
 238
 239 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 240 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 241 {
 242     CPUClass *cc = CPU_GET_CLASS(cs);
 243     ARMCPU *cpu = ARM_CPU(cs);
 244     CPUARMState *env = &cpu->env;
 245     bool ret = false;
 246
 247
 248     if (interrupt_request & CPU_INTERRUPT_FIQ
 249         && !(env->daif & PSTATE_F)) {
 250         cs->exception_index = EXCP_FIQ;
 251         cc->do_interrupt(cs);
 252         ret = true;
 253     }
 254     /* ARMv7-M interrupt return works by loading a magic value
 255      * into the PC.  On real hardware the load causes the
 256      * return to occur.  The qemu implementation performs the
 257      * jump normally, then does the exception return when the
 258      * CPU tries to execute code at the magic address.
 259      * This will cause the magic PC value to be pushed to
 260      * the stack if an interrupt occurred at the wrong time.
 261      * We avoid this by disabling interrupts when
 262      * pc contains a magic address.
 263      */
 264     if (interrupt_request & CPU_INTERRUPT_HARD
 265         && !(env->daif & PSTATE_I)
 266         && (env->regs[15] < 0xfffffff0)) {
 267         cs->exception_index = EXCP_IRQ;
 268         cc->do_interrupt(cs);
 269         ret = true;
 270     }
 271     return ret;
 272 }
 273 #endif
 274
 275 #ifndef CONFIG_USER_ONLY
 276 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 277 {
 278     ARMCPU *cpu = opaque;
 279     CPUARMState *env = &cpu->env;
 280     CPUState *cs = CPU(cpu);
 281     static const int mask[] = {
 282         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 283         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 284         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 285         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 286     };
 287
 288     switch (irq) {
 289     case ARM_CPU_VIRQ:
 290     case ARM_CPU_VFIQ:
 291         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 292             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 293                      __func__, irq);
 294         }
 295         /* fall through */
 296     case ARM_CPU_IRQ:
 297     case ARM_CPU_FIQ:
 298         if (level) {
 299             cpu_interrupt(cs, mask[irq]);
 300         } else {
 301             cpu_reset_interrupt(cs, mask[irq]);
 302         }
 303         break;
 304     default:
 305         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 306     }
 307 }
 308
 309 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 310 {
 311 #ifdef CONFIG_KVM
 312     ARMCPU *cpu = opaque;
 313     CPUState *cs = CPU(cpu);
 314     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 315
 316     switch (irq) {
 317     case ARM_CPU_IRQ:
 318         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 319         break;
 320     case ARM_CPU_FIQ:
 321         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 322         break;
 323     default:
 324         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 325     }
 326     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 327     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 328 #endif
 329 }
 330 #endif
 331
 332 static inline void set_feature(CPUARMState *env, int feature)
 333 {
 334     env->features |= 1ULL << feature;
 335 }
 336
 337 static inline void unset_feature(CPUARMState *env, int feature)
 338 {
 339     env->features &= ~(1ULL << feature);
 340 }
 341
 342 static void arm_cpu_initfn(Object *obj)
 343 {
 344     CPUState *cs = CPU(obj);
 345     ARMCPU *cpu = ARM_CPU(obj);
 346     static bool inited;
 347
 348     cs->env_ptr = &cpu->env;
 349     cpu_exec_init(&cpu->env);
 350     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 351                                          g_free, g_free);
 352
 353 #ifndef CONFIG_USER_ONLY
 354     /* Our inbound IRQ and FIQ lines */
 355     if (kvm_enabled()) {
 356         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 357          * the same interface as non-KVM CPUs.
 358          */
 359         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 360     } else {
 361         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 362     }
 363
 364     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 365                                                 arm_gt_ptimer_cb, cpu);
 366     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 367                                                 arm_gt_vtimer_cb, cpu);
 368     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 369                        ARRAY_SIZE(cpu->gt_timer_outputs));
 370 #endif
 371
 372     /* DTB consumers generally don't in fact care what the 'compatible'
 373      * string is, so always provide some string and trust that a hypothetical
 374      * picky DTB consumer will also provide a helpful error message.
 375      */
 376     cpu->dtb_compatible = "qemu,unknown";
 377     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 378     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 379
 380     if (tcg_enabled()) {
 381         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 382         if (!inited) {
 383             inited = true;
 384             arm_translate_init();
 385         }
 386     }
 387 }
 388
 389 static Property arm_cpu_reset_cbar_property =
 390             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 391
 392 static Property arm_cpu_reset_hivecs_property =
 393             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 394
 395 static Property arm_cpu_rvbar_property =
 396             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 397
 398 static Property arm_cpu_has_el3_property =
 399             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 400
 401 static void arm_cpu_post_init(Object *obj)
 402 {
 403     ARMCPU *cpu = ARM_CPU(obj);
 404
 405     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 406         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 407         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 408                                  &error_abort);
 409     }
 410
 411     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 412         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 413                                  &error_abort);
 414     }
 415
 416     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 417         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 418                                  &error_abort);
 419     }
 420
 421     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 422         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 423          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 424          */
 425         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 426                                  &error_abort);
 427     }
 428 }
 429
 430 static void arm_cpu_finalizefn(Object *obj)
 431 {
 432     ARMCPU *cpu = ARM_CPU(obj);
 433     g_hash_table_destroy(cpu->cp_regs);
 434 }
 435
 436 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 437 {
 438     CPUState *cs = CPU(dev);
 439     ARMCPU *cpu = ARM_CPU(dev);
 440     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 441     CPUARMState *env = &cpu->env;
 442
 443     /* Some features automatically imply others: */
 444     if (arm_feature(env, ARM_FEATURE_V8)) {
 445         set_feature(env, ARM_FEATURE_V7);
 446         set_feature(env, ARM_FEATURE_ARM_DIV);
 447         set_feature(env, ARM_FEATURE_LPAE);
 448     }
 449     if (arm_feature(env, ARM_FEATURE_V7)) {
 450         set_feature(env, ARM_FEATURE_VAPA);
 451         set_feature(env, ARM_FEATURE_THUMB2);
 452         set_feature(env, ARM_FEATURE_MPIDR);
 453         if (!arm_feature(env, ARM_FEATURE_M)) {
 454             set_feature(env, ARM_FEATURE_V6K);
 455         } else {
 456             set_feature(env, ARM_FEATURE_V6);
 457         }
 458     }
 459     if (arm_feature(env, ARM_FEATURE_V6K)) {
 460         set_feature(env, ARM_FEATURE_V6);
 461         set_feature(env, ARM_FEATURE_MVFR);
 462     }
 463     if (arm_feature(env, ARM_FEATURE_V6)) {
 464         set_feature(env, ARM_FEATURE_V5);
 465         if (!arm_feature(env, ARM_FEATURE_M)) {
 466             set_feature(env, ARM_FEATURE_AUXCR);
 467         }
 468     }
 469     if (arm_feature(env, ARM_FEATURE_V5)) {
 470         set_feature(env, ARM_FEATURE_V4T);
 471     }
 472     if (arm_feature(env, ARM_FEATURE_M)) {
 473         set_feature(env, ARM_FEATURE_THUMB_DIV);
 474     }
 475     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 476         set_feature(env, ARM_FEATURE_THUMB_DIV);
 477     }
 478     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 479         set_feature(env, ARM_FEATURE_VFP3);
 480         set_feature(env, ARM_FEATURE_VFP_FP16);
 481     }
 482     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 483         set_feature(env, ARM_FEATURE_VFP);
 484     }
 485     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 486         set_feature(env, ARM_FEATURE_V7MP);
 487         set_feature(env, ARM_FEATURE_PXN);
 488     }
 489     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 490         set_feature(env, ARM_FEATURE_CBAR);
 491     }
 492
 493     if (cpu->reset_hivecs) {
 494             cpu->reset_sctlr |= (1 << 13);
 495     }
 496
 497     if (!cpu->has_el3) {
 498         /* If the has_el3 CPU property is disabled then we need to disable the
 499          * feature.
 500          */
 501         unset_feature(env, ARM_FEATURE_EL3);
 502
 503         /* Disable the security extension feature bits in the processor feature
 504          * register as well.  This is id_pfr1[7:4].
 505          */
 506         cpu->id_pfr1 &= ~0xf0;
 507     }
 508
 509     register_cp_regs_for_features(cpu);
 510     arm_cpu_register_gdb_regs_for_features(cpu);
 511
 512     init_cpreg_list(cpu);
 513
 514     qemu_init_vcpu(cs);
 515     cpu_reset(cs);
 516
 517     acc->parent_realize(dev, errp);
 518 }
 519
 520 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 521 {
 522     ObjectClass *oc;
 523     char *typename;
 524
 525     if (!cpu_model) {
 526         return NULL;
 527     }
 528
 529     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 530     oc = object_class_by_name(typename);
 531     g_free(typename);
 532     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 533         object_class_is_abstract(oc)) {
 534         return NULL;
 535     }
 536     return oc;
 537 }
 538
 539 /* CPU models. These are not needed for the AArch64 linux-user build. */
 540 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 541
 542 static void arm926_initfn(Object *obj)
 543 {
 544     ARMCPU *cpu = ARM_CPU(obj);
 545
 546     cpu->dtb_compatible = "arm,arm926";
 547     set_feature(&cpu->env, ARM_FEATURE_V5);
 548     set_feature(&cpu->env, ARM_FEATURE_VFP);
 549     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 550     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 551     cpu->midr = 0x41069265;
 552     cpu->reset_fpsid = 0x41011090;
 553     cpu->ctr = 0x1dd20d2;
 554     cpu->reset_sctlr = 0x00090078;
 555 }
 556
 557 static void arm946_initfn(Object *obj)
 558 {
 559     ARMCPU *cpu = ARM_CPU(obj);
 560
 561     cpu->dtb_compatible = "arm,arm946";
 562     set_feature(&cpu->env, ARM_FEATURE_V5);
 563     set_feature(&cpu->env, ARM_FEATURE_MPU);
 564     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 565     cpu->midr = 0x41059461;
 566     cpu->ctr = 0x0f004006;
 567     cpu->reset_sctlr = 0x00000078;
 568 }
 569
 570 static void arm1026_initfn(Object *obj)
 571 {
 572     ARMCPU *cpu = ARM_CPU(obj);
 573
 574     cpu->dtb_compatible = "arm,arm1026";
 575     set_feature(&cpu->env, ARM_FEATURE_V5);
 576     set_feature(&cpu->env, ARM_FEATURE_VFP);
 577     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 578     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 579     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 580     cpu->midr = 0x4106a262;
 581     cpu->reset_fpsid = 0x410110a0;
 582     cpu->ctr = 0x1dd20d2;
 583     cpu->reset_sctlr = 0x00090078;
 584     cpu->reset_auxcr = 1;
 585     {
 586         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 587         ARMCPRegInfo ifar = {
 588             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 589             .access = PL1_RW,
 590             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 591             .resetvalue = 0
 592         };
 593         define_one_arm_cp_reg(cpu, &ifar);
 594     }
 595 }
 596
 597 static void arm1136_r2_initfn(Object *obj)
 598 {
 599     ARMCPU *cpu = ARM_CPU(obj);
 600     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 601      * older core than plain "arm1136". In particular this does not
 602      * have the v6K features.
 603      * These ID register values are correct for 1136 but may be wrong
 604      * for 1136_r2 (in particular r0p2 does not actually implement most
 605      * of the ID registers).
 606      */
 607
 608     cpu->dtb_compatible = "arm,arm1136";
 609     set_feature(&cpu->env, ARM_FEATURE_V6);
 610     set_feature(&cpu->env, ARM_FEATURE_VFP);
 611     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 612     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 613     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 614     cpu->midr = 0x4107b362;
 615     cpu->reset_fpsid = 0x410120b4;
 616     cpu->mvfr0 = 0x11111111;
 617     cpu->mvfr1 = 0x00000000;
 618     cpu->ctr = 0x1dd20d2;
 619     cpu->reset_sctlr = 0x00050078;
 620     cpu->id_pfr0 = 0x111;
 621     cpu->id_pfr1 = 0x1;
 622     cpu->id_dfr0 = 0x2;
 623     cpu->id_afr0 = 0x3;
 624     cpu->id_mmfr0 = 0x01130003;
 625     cpu->id_mmfr1 = 0x10030302;
 626     cpu->id_mmfr2 = 0x01222110;
 627     cpu->id_isar0 = 0x00140011;
 628     cpu->id_isar1 = 0x12002111;
 629     cpu->id_isar2 = 0x11231111;
 630     cpu->id_isar3 = 0x01102131;
 631     cpu->id_isar4 = 0x141;
 632     cpu->reset_auxcr = 7;
 633 }
 634
 635 static void arm1136_initfn(Object *obj)
 636 {
 637     ARMCPU *cpu = ARM_CPU(obj);
 638
 639     cpu->dtb_compatible = "arm,arm1136";
 640     set_feature(&cpu->env, ARM_FEATURE_V6K);
 641     set_feature(&cpu->env, ARM_FEATURE_V6);
 642     set_feature(&cpu->env, ARM_FEATURE_VFP);
 643     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 644     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 645     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 646     cpu->midr = 0x4117b363;
 647     cpu->reset_fpsid = 0x410120b4;
 648     cpu->mvfr0 = 0x11111111;
 649     cpu->mvfr1 = 0x00000000;
 650     cpu->ctr = 0x1dd20d2;
 651     cpu->reset_sctlr = 0x00050078;
 652     cpu->id_pfr0 = 0x111;
 653     cpu->id_pfr1 = 0x1;
 654     cpu->id_dfr0 = 0x2;
 655     cpu->id_afr0 = 0x3;
 656     cpu->id_mmfr0 = 0x01130003;
 657     cpu->id_mmfr1 = 0x10030302;
 658     cpu->id_mmfr2 = 0x01222110;
 659     cpu->id_isar0 = 0x00140011;
 660     cpu->id_isar1 = 0x12002111;
 661     cpu->id_isar2 = 0x11231111;
 662     cpu->id_isar3 = 0x01102131;
 663     cpu->id_isar4 = 0x141;
 664     cpu->reset_auxcr = 7;
 665 }
 666
 667 static void arm1176_initfn(Object *obj)
 668 {
 669     ARMCPU *cpu = ARM_CPU(obj);
 670
 671     cpu->dtb_compatible = "arm,arm1176";
 672     set_feature(&cpu->env, ARM_FEATURE_V6K);
 673     set_feature(&cpu->env, ARM_FEATURE_VFP);
 674     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 675     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 676     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 677     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 678     set_feature(&cpu->env, ARM_FEATURE_EL3);
 679     cpu->midr = 0x410fb767;
 680     cpu->reset_fpsid = 0x410120b5;
 681     cpu->mvfr0 = 0x11111111;
 682     cpu->mvfr1 = 0x00000000;
 683     cpu->ctr = 0x1dd20d2;
 684     cpu->reset_sctlr = 0x00050078;
 685     cpu->id_pfr0 = 0x111;
 686     cpu->id_pfr1 = 0x11;
 687     cpu->id_dfr0 = 0x33;
 688     cpu->id_afr0 = 0;
 689     cpu->id_mmfr0 = 0x01130003;
 690     cpu->id_mmfr1 = 0x10030302;
 691     cpu->id_mmfr2 = 0x01222100;
 692     cpu->id_isar0 = 0x0140011;
 693     cpu->id_isar1 = 0x12002111;
 694     cpu->id_isar2 = 0x11231121;
 695     cpu->id_isar3 = 0x01102131;
 696     cpu->id_isar4 = 0x01141;
 697     cpu->reset_auxcr = 7;
 698 }
 699
 700 static void arm11mpcore_initfn(Object *obj)
 701 {
 702     ARMCPU *cpu = ARM_CPU(obj);
 703
 704     cpu->dtb_compatible = "arm,arm11mpcore";
 705     set_feature(&cpu->env, ARM_FEATURE_V6K);
 706     set_feature(&cpu->env, ARM_FEATURE_VFP);
 707     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 708     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 709     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 710     cpu->midr = 0x410fb022;
 711     cpu->reset_fpsid = 0x410120b4;
 712     cpu->mvfr0 = 0x11111111;
 713     cpu->mvfr1 = 0x00000000;
 714     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 715     cpu->id_pfr0 = 0x111;
 716     cpu->id_pfr1 = 0x1;
 717     cpu->id_dfr0 = 0;
 718     cpu->id_afr0 = 0x2;
 719     cpu->id_mmfr0 = 0x01100103;
 720     cpu->id_mmfr1 = 0x10020302;
 721     cpu->id_mmfr2 = 0x01222000;
 722     cpu->id_isar0 = 0x00100011;
 723     cpu->id_isar1 = 0x12002111;
 724     cpu->id_isar2 = 0x11221011;
 725     cpu->id_isar3 = 0x01102131;
 726     cpu->id_isar4 = 0x141;
 727     cpu->reset_auxcr = 1;
 728 }
 729
 730 static void cortex_m3_initfn(Object *obj)
 731 {
 732     ARMCPU *cpu = ARM_CPU(obj);
 733     set_feature(&cpu->env, ARM_FEATURE_V7);
 734     set_feature(&cpu->env, ARM_FEATURE_M);
 735     cpu->midr = 0x410fc231;
 736 }
 737
 738 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 739 {
 740     CPUClass *cc = CPU_CLASS(oc);
 741
 742 #ifndef CONFIG_USER_ONLY
 743     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 744 #endif
 745
 746     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 747 }
 748
 749 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 750     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 751       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 752     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 753       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 754     REGINFO_SENTINEL
 755 };
 756
 757 static void cortex_a8_initfn(Object *obj)
 758 {
 759     ARMCPU *cpu = ARM_CPU(obj);
 760
 761     cpu->dtb_compatible = "arm,cortex-a8";
 762     set_feature(&cpu->env, ARM_FEATURE_V7);
 763     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 764     set_feature(&cpu->env, ARM_FEATURE_NEON);
 765     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 766     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 767     set_feature(&cpu->env, ARM_FEATURE_EL3);
 768     cpu->midr = 0x410fc080;
 769     cpu->reset_fpsid = 0x410330c0;
 770     cpu->mvfr0 = 0x11110222;
 771     cpu->mvfr1 = 0x00011100;
 772     cpu->ctr = 0x82048004;
 773     cpu->reset_sctlr = 0x00c50078;
 774     cpu->id_pfr0 = 0x1031;
 775     cpu->id_pfr1 = 0x11;
 776     cpu->id_dfr0 = 0x400;
 777     cpu->id_afr0 = 0;
 778     cpu->id_mmfr0 = 0x31100003;
 779     cpu->id_mmfr1 = 0x20000000;
 780     cpu->id_mmfr2 = 0x01202000;
 781     cpu->id_mmfr3 = 0x11;
 782     cpu->id_isar0 = 0x00101111;
 783     cpu->id_isar1 = 0x12112111;
 784     cpu->id_isar2 = 0x21232031;
 785     cpu->id_isar3 = 0x11112131;
 786     cpu->id_isar4 = 0x00111142;
 787     cpu->dbgdidr = 0x15141000;
 788     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 789     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 790     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 791     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 792     cpu->reset_auxcr = 2;
 793     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 794 }
 795
 796 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 797     /* power_control should be set to maximum latency. Again,
 798      * default to 0 and set by private hook
 799      */
 800     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 801       .access = PL1_RW, .resetvalue = 0,
 802       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 803     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 804       .access = PL1_RW, .resetvalue = 0,
 805       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 806     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 807       .access = PL1_RW, .resetvalue = 0,
 808       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 809     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 810       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 811     /* TLB lockdown control */
 812     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 813       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 814     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 815       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 816     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 817       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 818     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 819       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 820     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 821       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 822     REGINFO_SENTINEL
 823 };
 824
 825 static void cortex_a9_initfn(Object *obj)
 826 {
 827     ARMCPU *cpu = ARM_CPU(obj);
 828
 829     cpu->dtb_compatible = "arm,cortex-a9";
 830     set_feature(&cpu->env, ARM_FEATURE_V7);
 831     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 832     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 833     set_feature(&cpu->env, ARM_FEATURE_NEON);
 834     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 835     set_feature(&cpu->env, ARM_FEATURE_EL3);
 836     /* Note that A9 supports the MP extensions even for
 837      * A9UP and single-core A9MP (which are both different
 838      * and valid configurations; we don't model A9UP).
 839      */
 840     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 841     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 842     cpu->midr = 0x410fc090;
 843     cpu->reset_fpsid = 0x41033090;
 844     cpu->mvfr0 = 0x11110222;
 845     cpu->mvfr1 = 0x01111111;
 846     cpu->ctr = 0x80038003;
 847     cpu->reset_sctlr = 0x00c50078;
 848     cpu->id_pfr0 = 0x1031;
 849     cpu->id_pfr1 = 0x11;
 850     cpu->id_dfr0 = 0x000;
 851     cpu->id_afr0 = 0;
 852     cpu->id_mmfr0 = 0x00100103;
 853     cpu->id_mmfr1 = 0x20000000;
 854     cpu->id_mmfr2 = 0x01230000;
 855     cpu->id_mmfr3 = 0x00002111;
 856     cpu->id_isar0 = 0x00101111;
 857     cpu->id_isar1 = 0x13112111;
 858     cpu->id_isar2 = 0x21232041;
 859     cpu->id_isar3 = 0x11112131;
 860     cpu->id_isar4 = 0x00111142;
 861     cpu->dbgdidr = 0x35141000;
 862     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 863     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 864     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 865     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 866 }
 867
 868 #ifndef CONFIG_USER_ONLY
 869 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 870 {
 871     /* Linux wants the number of processors from here.
 872      * Might as well set the interrupt-controller bit too.
 873      */
 874     return ((smp_cpus - 1) << 24) | (1 << 23);
 875 }
 876 #endif
 877
 878 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 879 #ifndef CONFIG_USER_ONLY
 880     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 881       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 882       .writefn = arm_cp_write_ignore, },
 883 #endif
 884     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 885       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 886     REGINFO_SENTINEL
 887 };
 888
 889 static void cortex_a15_initfn(Object *obj)
 890 {
 891     ARMCPU *cpu = ARM_CPU(obj);
 892
 893     cpu->dtb_compatible = "arm,cortex-a15";
 894     set_feature(&cpu->env, ARM_FEATURE_V7);
 895     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 896     set_feature(&cpu->env, ARM_FEATURE_NEON);
 897     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 898     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 899     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 900     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 901     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 902     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 903     set_feature(&cpu->env, ARM_FEATURE_EL3);
 904     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 905     cpu->midr = 0x412fc0f1;
 906     cpu->reset_fpsid = 0x410430f0;
 907     cpu->mvfr0 = 0x10110222;
 908     cpu->mvfr1 = 0x11111111;
 909     cpu->ctr = 0x8444c004;
 910     cpu->reset_sctlr = 0x00c50078;
 911     cpu->id_pfr0 = 0x00001131;
 912     cpu->id_pfr1 = 0x00011011;
 913     cpu->id_dfr0 = 0x02010555;
 914     cpu->id_afr0 = 0x00000000;
 915     cpu->id_mmfr0 = 0x10201105;
 916     cpu->id_mmfr1 = 0x20000000;
 917     cpu->id_mmfr2 = 0x01240000;
 918     cpu->id_mmfr3 = 0x02102211;
 919     cpu->id_isar0 = 0x02101110;
 920     cpu->id_isar1 = 0x13112111;
 921     cpu->id_isar2 = 0x21232041;
 922     cpu->id_isar3 = 0x11112131;
 923     cpu->id_isar4 = 0x10011142;
 924     cpu->dbgdidr = 0x3515f021;
 925     cpu->clidr = 0x0a200023;
 926     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 927     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 928     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 929     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 930 }
 931
 932 static void ti925t_initfn(Object *obj)
 933 {
 934     ARMCPU *cpu = ARM_CPU(obj);
 935     set_feature(&cpu->env, ARM_FEATURE_V4T);
 936     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 937     cpu->midr = ARM_CPUID_TI925T;
 938     cpu->ctr = 0x5109149;
 939     cpu->reset_sctlr = 0x00000070;
 940 }
 941
 942 static void sa1100_initfn(Object *obj)
 943 {
 944     ARMCPU *cpu = ARM_CPU(obj);
 945
 946     cpu->dtb_compatible = "intel,sa1100";
 947     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 948     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 949     cpu->midr = 0x4401A11B;
 950     cpu->reset_sctlr = 0x00000070;
 951 }
 952
 953 static void sa1110_initfn(Object *obj)
 954 {
 955     ARMCPU *cpu = ARM_CPU(obj);
 956     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 957     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 958     cpu->midr = 0x6901B119;
 959     cpu->reset_sctlr = 0x00000070;
 960 }
 961
 962 static void pxa250_initfn(Object *obj)
 963 {
 964     ARMCPU *cpu = ARM_CPU(obj);
 965
 966     cpu->dtb_compatible = "marvell,xscale";
 967     set_feature(&cpu->env, ARM_FEATURE_V5);
 968     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 969     cpu->midr = 0x69052100;
 970     cpu->ctr = 0xd172172;
 971     cpu->reset_sctlr = 0x00000078;
 972 }
 973
 974 static void pxa255_initfn(Object *obj)
 975 {
 976     ARMCPU *cpu = ARM_CPU(obj);
 977
 978     cpu->dtb_compatible = "marvell,xscale";
 979     set_feature(&cpu->env, ARM_FEATURE_V5);
 980     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 981     cpu->midr = 0x69052d00;
 982     cpu->ctr = 0xd172172;
 983     cpu->reset_sctlr = 0x00000078;
 984 }
 985
 986 static void pxa260_initfn(Object *obj)
 987 {
 988     ARMCPU *cpu = ARM_CPU(obj);
 989
 990     cpu->dtb_compatible = "marvell,xscale";
 991     set_feature(&cpu->env, ARM_FEATURE_V5);
 992     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 993     cpu->midr = 0x69052903;
 994     cpu->ctr = 0xd172172;
 995     cpu->reset_sctlr = 0x00000078;
 996 }
 997
 998 static void pxa261_initfn(Object *obj)
 999 {
1000     ARMCPU *cpu = ARM_CPU(obj);
1001
1002     cpu->dtb_compatible = "marvell,xscale";
1003     set_feature(&cpu->env, ARM_FEATURE_V5);
1004     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1005     cpu->midr = 0x69052d05;
1006     cpu->ctr = 0xd172172;
1007     cpu->reset_sctlr = 0x00000078;
1008 }
1009
1010 static void pxa262_initfn(Object *obj)
1011 {
1012     ARMCPU *cpu = ARM_CPU(obj);
1013
1014     cpu->dtb_compatible = "marvell,xscale";
1015     set_feature(&cpu->env, ARM_FEATURE_V5);
1016     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1017     cpu->midr = 0x69052d06;
1018     cpu->ctr = 0xd172172;
1019     cpu->reset_sctlr = 0x00000078;
1020 }
1021
1022 static void pxa270a0_initfn(Object *obj)
1023 {
1024     ARMCPU *cpu = ARM_CPU(obj);
1025
1026     cpu->dtb_compatible = "marvell,xscale";
1027     set_feature(&cpu->env, ARM_FEATURE_V5);
1028     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1029     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1030     cpu->midr = 0x69054110;
1031     cpu->ctr = 0xd172172;
1032     cpu->reset_sctlr = 0x00000078;
1033 }
1034
1035 static void pxa270a1_initfn(Object *obj)
1036 {
1037     ARMCPU *cpu = ARM_CPU(obj);
1038
1039     cpu->dtb_compatible = "marvell,xscale";
1040     set_feature(&cpu->env, ARM_FEATURE_V5);
1041     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1042     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1043     cpu->midr = 0x69054111;
1044     cpu->ctr = 0xd172172;
1045     cpu->reset_sctlr = 0x00000078;
1046 }
1047
1048 static void pxa270b0_initfn(Object *obj)
1049 {
1050     ARMCPU *cpu = ARM_CPU(obj);
1051
1052     cpu->dtb_compatible = "marvell,xscale";
1053     set_feature(&cpu->env, ARM_FEATURE_V5);
1054     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1055     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1056     cpu->midr = 0x69054112;
1057     cpu->ctr = 0xd172172;
1058     cpu->reset_sctlr = 0x00000078;
1059 }
1060
1061 static void pxa270b1_initfn(Object *obj)
1062 {
1063     ARMCPU *cpu = ARM_CPU(obj);
1064
1065     cpu->dtb_compatible = "marvell,xscale";
1066     set_feature(&cpu->env, ARM_FEATURE_V5);
1067     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1068     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1069     cpu->midr = 0x69054113;
1070     cpu->ctr = 0xd172172;
1071     cpu->reset_sctlr = 0x00000078;
1072 }
1073
1074 static void pxa270c0_initfn(Object *obj)
1075 {
1076     ARMCPU *cpu = ARM_CPU(obj);
1077
1078     cpu->dtb_compatible = "marvell,xscale";
1079     set_feature(&cpu->env, ARM_FEATURE_V5);
1080     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1081     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1082     cpu->midr = 0x69054114;
1083     cpu->ctr = 0xd172172;
1084     cpu->reset_sctlr = 0x00000078;
1085 }
1086
1087 static void pxa270c5_initfn(Object *obj)
1088 {
1089     ARMCPU *cpu = ARM_CPU(obj);
1090
1091     cpu->dtb_compatible = "marvell,xscale";
1092     set_feature(&cpu->env, ARM_FEATURE_V5);
1093     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1094     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1095     cpu->midr = 0x69054117;
1096     cpu->ctr = 0xd172172;
1097     cpu->reset_sctlr = 0x00000078;
1098 }
1099
1100 #ifdef CONFIG_USER_ONLY
1101 static void arm_any_initfn(Object *obj)
1102 {
1103     ARMCPU *cpu = ARM_CPU(obj);
1104     set_feature(&cpu->env, ARM_FEATURE_V8);
1105     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1106     set_feature(&cpu->env, ARM_FEATURE_NEON);
1107     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1108     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1109     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1110     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1111     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1112     set_feature(&cpu->env, ARM_FEATURE_CRC);
1113     cpu->midr = 0xffffffff;
1114 }
1115 #endif
1116
1117 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1118
1119 typedef struct ARMCPUInfo {
1120     const char *name;
1121     void (*initfn)(Object *obj);
1122     void (*class_init)(ObjectClass *oc, void *data);
1123 } ARMCPUInfo;
1124
1125 static const ARMCPUInfo arm_cpus[] = {
1126 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1127     { .name = "arm926",      .initfn = arm926_initfn },
1128     { .name = "arm946",      .initfn = arm946_initfn },
1129     { .name = "arm1026",     .initfn = arm1026_initfn },
1130     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1131      * older core than plain "arm1136". In particular this does not
1132      * have the v6K features.
1133      */
1134     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1135     { .name = "arm1136",     .initfn = arm1136_initfn },
1136     { .name = "arm1176",     .initfn = arm1176_initfn },
1137     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1138     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1139                              .class_init = arm_v7m_class_init },
1140     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1141     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1142     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1143     { .name = "ti925t",      .initfn = ti925t_initfn },
1144     { .name = "sa1100",      .initfn = sa1100_initfn },
1145     { .name = "sa1110",      .initfn = sa1110_initfn },
1146     { .name = "pxa250",      .initfn = pxa250_initfn },
1147     { .name = "pxa255",      .initfn = pxa255_initfn },
1148     { .name = "pxa260",      .initfn = pxa260_initfn },
1149     { .name = "pxa261",      .initfn = pxa261_initfn },
1150     { .name = "pxa262",      .initfn = pxa262_initfn },
1151     /* "pxa270" is an alias for "pxa270-a0" */
1152     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1153     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1154     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1155     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1156     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1157     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1158     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1159 #ifdef CONFIG_USER_ONLY
1160     { .name = "any",         .initfn = arm_any_initfn },
1161 #endif
1162 #endif
1163     { .name = NULL }
1164 };
1165
1166 static Property arm_cpu_properties[] = {
1167     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1168     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1169     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1170     DEFINE_PROP_END_OF_LIST()
1171 };
1172
1173 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1174 {
1175     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1176     CPUClass *cc = CPU_CLASS(acc);
1177     DeviceClass *dc = DEVICE_CLASS(oc);
1178
1179     acc->parent_realize = dc->realize;
1180     dc->realize = arm_cpu_realizefn;
1181     dc->props = arm_cpu_properties;
1182
1183     acc->parent_reset = cc->reset;
1184     cc->reset = arm_cpu_reset;
1185
1186     cc->class_by_name = arm_cpu_class_by_name;
1187     cc->has_work = arm_cpu_has_work;
1188     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1189     cc->dump_state = arm_cpu_dump_state;
1190     cc->set_pc = arm_cpu_set_pc;
1191     cc->gdb_read_register = arm_cpu_gdb_read_register;
1192     cc->gdb_write_register = arm_cpu_gdb_write_register;
1193 #ifdef CONFIG_USER_ONLY
1194     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1195 #else
1196     cc->do_interrupt = arm_cpu_do_interrupt;
1197     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1198     cc->vmsd = &vmstate_arm_cpu;
1199 #endif
1200     cc->gdb_num_core_regs = 26;
1201     cc->gdb_core_xml_file = "arm-core.xml";
1202     cc->gdb_stop_before_watchpoint = true;
1203     cc->debug_excp_handler = arm_debug_excp_handler;
1204 }
1205
1206 static void cpu_register(const ARMCPUInfo *info)
1207 {
1208     TypeInfo type_info = {
1209         .parent = TYPE_ARM_CPU,
1210         .instance_size = sizeof(ARMCPU),
1211         .instance_init = info->initfn,
1212         .class_size = sizeof(ARMCPUClass),
1213         .class_init = info->class_init,
1214     };
1215
1216     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1217     type_register(&type_info);
1218     g_free((void *)type_info.name);
1219 }
1220
1221 static const TypeInfo arm_cpu_type_info = {
1222     .name = TYPE_ARM_CPU,
1223     .parent = TYPE_CPU,
1224     .instance_size = sizeof(ARMCPU),
1225     .instance_init = arm_cpu_initfn,
1226     .instance_post_init = arm_cpu_post_init,
1227     .instance_finalize = arm_cpu_finalizefn,
1228     .abstract = true,
1229     .class_size = sizeof(ARMCPUClass),
1230     .class_init = arm_cpu_class_init,
1231 };
1232
1233 static void arm_cpu_register_types(void)
1234 {
1235     const ARMCPUInfo *info = arm_cpus;
1236
1237     type_register_static(&arm_cpu_type_info);
1238
1239     while (info->name) {
1240         cpu_register(info);
1241         info++;
1242     }
1243 }
1244
1245 type_init(arm_cpu_register_types)