vga: Add mechanism to force the use of a shadow surface
[qemu.git] / target-arm / translate-a64.c
blob80d2c07e8249eaed601095b9120c701d31bea7ba
1 /*
2 * AArch64 translation
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
25 #include "cpu.h"
26 #include "tcg-op.h"
27 #include "qemu/log.h"
28 #include "arm_ldst.h"
29 #include "translate.h"
30 #include "internals.h"
31 #include "qemu/host-utils.h"
33 #include "exec/gen-icount.h"
35 #include "exec/helper-proto.h"
36 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
40 static TCGv_i64 cpu_X[32];
41 static TCGv_i64 cpu_pc;
42 static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
44 /* Load/store exclusive handling */
45 static TCGv_i64 cpu_exclusive_addr;
46 static TCGv_i64 cpu_exclusive_val;
47 static TCGv_i64 cpu_exclusive_high;
48 #ifdef CONFIG_USER_ONLY
49 static TCGv_i64 cpu_exclusive_test;
50 static TCGv_i32 cpu_exclusive_info;
51 #endif
53 static const char *regnames[] = {
54 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
55 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
56 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
57 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
60 enum a64_shift_type {
61 A64_SHIFT_TYPE_LSL = 0,
62 A64_SHIFT_TYPE_LSR = 1,
63 A64_SHIFT_TYPE_ASR = 2,
64 A64_SHIFT_TYPE_ROR = 3
67 /* Table based decoder typedefs - used when the relevant bits for decode
68 * are too awkwardly scattered across the instruction (eg SIMD).
70 typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
72 typedef struct AArch64DecodeTable {
73 uint32_t pattern;
74 uint32_t mask;
75 AArch64DecodeFn *disas_fn;
76 } AArch64DecodeTable;
78 /* Function prototype for gen_ functions for calling Neon helpers */
79 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
80 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
81 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
82 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
83 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
84 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
85 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
86 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
87 typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
88 typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
89 typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
90 typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);
91 typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
93 /* initialize TCG globals. */
94 void a64_translate_init(void)
96 int i;
98 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
99 offsetof(CPUARMState, pc),
100 "pc");
101 for (i = 0; i < 32; i++) {
102 cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
103 offsetof(CPUARMState, xregs[i]),
104 regnames[i]);
107 cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");
108 cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");
109 cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");
110 cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");
112 cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
113 offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
114 cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUARMState, exclusive_val), "exclusive_val");
116 cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUARMState, exclusive_high), "exclusive_high");
118 #ifdef CONFIG_USER_ONLY
119 cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
120 offsetof(CPUARMState, exclusive_test), "exclusive_test");
121 cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
122 offsetof(CPUARMState, exclusive_info), "exclusive_info");
123 #endif
126 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
127 fprintf_function cpu_fprintf, int flags)
129 ARMCPU *cpu = ARM_CPU(cs);
130 CPUARMState *env = &cpu->env;
131 uint32_t psr = pstate_read(env);
132 int i;
134 cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
135 env->pc, env->xregs[31]);
136 for (i = 0; i < 31; i++) {
137 cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
138 if ((i % 4) == 3) {
139 cpu_fprintf(f, "\n");
140 } else {
141 cpu_fprintf(f, " ");
144 cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",
145 psr,
146 psr & PSTATE_N ? 'N' : '-',
147 psr & PSTATE_Z ? 'Z' : '-',
148 psr & PSTATE_C ? 'C' : '-',
149 psr & PSTATE_V ? 'V' : '-');
150 cpu_fprintf(f, "\n");
152 if (flags & CPU_DUMP_FPU) {
153 int numvfpregs = 32;
154 for (i = 0; i < numvfpregs; i += 2) {
155 uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
156 uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
157 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
158 i, vhi, vlo);
159 vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
160 vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
161 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
162 i + 1, vhi, vlo);
164 cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
165 vfp_get_fpcr(env), vfp_get_fpsr(env));
169 void gen_a64_set_pc_im(uint64_t val)
171 tcg_gen_movi_i64(cpu_pc, val);
174 static void gen_exception_internal(int excp)
176 TCGv_i32 tcg_excp = tcg_const_i32(excp);
178 assert(excp_is_internal(excp));
179 gen_helper_exception_internal(cpu_env, tcg_excp);
180 tcg_temp_free_i32(tcg_excp);
183 static void gen_exception(int excp, uint32_t syndrome)
185 TCGv_i32 tcg_excp = tcg_const_i32(excp);
186 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
188 gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn);
189 tcg_temp_free_i32(tcg_syn);
190 tcg_temp_free_i32(tcg_excp);
193 static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
195 gen_a64_set_pc_im(s->pc - offset);
196 gen_exception_internal(excp);
197 s->is_jmp = DISAS_EXC;
200 static void gen_exception_insn(DisasContext *s, int offset, int excp,
201 uint32_t syndrome)
203 gen_a64_set_pc_im(s->pc - offset);
204 gen_exception(excp, syndrome);
205 s->is_jmp = DISAS_EXC;
208 static void gen_ss_advance(DisasContext *s)
210 /* If the singlestep state is Active-not-pending, advance to
211 * Active-pending.
213 if (s->ss_active) {
214 s->pstate_ss = 0;
215 gen_helper_clear_pstate_ss(cpu_env);
219 static void gen_step_complete_exception(DisasContext *s)
221 /* We just completed step of an insn. Move from Active-not-pending
222 * to Active-pending, and then also take the swstep exception.
223 * This corresponds to making the (IMPDEF) choice to prioritize
224 * swstep exceptions over asynchronous exceptions taken to an exception
225 * level where debug is disabled. This choice has the advantage that
226 * we do not need to maintain internal state corresponding to the
227 * ISV/EX syndrome bits between completion of the step and generation
228 * of the exception, and our syndrome information is always correct.
230 gen_ss_advance(s);
231 gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex));
232 s->is_jmp = DISAS_EXC;
235 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
237 /* No direct tb linking with singlestep (either QEMU's or the ARM
238 * debug architecture kind) or deterministic io
240 if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_IO)) {
241 return false;
244 /* Only link tbs from inside the same guest page */
245 if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
246 return false;
249 return true;
252 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
254 TranslationBlock *tb;
256 tb = s->tb;
257 if (use_goto_tb(s, n, dest)) {
258 tcg_gen_goto_tb(n);
259 gen_a64_set_pc_im(dest);
260 tcg_gen_exit_tb((intptr_t)tb + n);
261 s->is_jmp = DISAS_TB_JUMP;
262 } else {
263 gen_a64_set_pc_im(dest);
264 if (s->ss_active) {
265 gen_step_complete_exception(s);
266 } else if (s->singlestep_enabled) {
267 gen_exception_internal(EXCP_DEBUG);
268 } else {
269 tcg_gen_exit_tb(0);
270 s->is_jmp = DISAS_TB_JUMP;
275 static void unallocated_encoding(DisasContext *s)
277 /* Unallocated and reserved encodings are uncategorized */
278 gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized());
281 #define unsupported_encoding(s, insn) \
282 do { \
283 qemu_log_mask(LOG_UNIMP, \
284 "%s:%d: unsupported instruction encoding 0x%08x " \
285 "at pc=%016" PRIx64 "\n", \
286 __FILE__, __LINE__, insn, s->pc - 4); \
287 unallocated_encoding(s); \
288 } while (0);
290 static void init_tmp_a64_array(DisasContext *s)
292 #ifdef CONFIG_DEBUG_TCG
293 int i;
294 for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
295 TCGV_UNUSED_I64(s->tmp_a64[i]);
297 #endif
298 s->tmp_a64_count = 0;
301 static void free_tmp_a64(DisasContext *s)
303 int i;
304 for (i = 0; i < s->tmp_a64_count; i++) {
305 tcg_temp_free_i64(s->tmp_a64[i]);
307 init_tmp_a64_array(s);
310 static TCGv_i64 new_tmp_a64(DisasContext *s)
312 assert(s->tmp_a64_count < TMP_A64_MAX);
313 return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
316 static TCGv_i64 new_tmp_a64_zero(DisasContext *s)
318 TCGv_i64 t = new_tmp_a64(s);
319 tcg_gen_movi_i64(t, 0);
320 return t;
324 * Register access functions
326 * These functions are used for directly accessing a register in where
327 * changes to the final register value are likely to be made. If you
328 * need to use a register for temporary calculation (e.g. index type
329 * operations) use the read_* form.
331 * B1.2.1 Register mappings
333 * In instruction register encoding 31 can refer to ZR (zero register) or
334 * the SP (stack pointer) depending on context. In QEMU's case we map SP
335 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
336 * This is the point of the _sp forms.
338 static TCGv_i64 cpu_reg(DisasContext *s, int reg)
340 if (reg == 31) {
341 return new_tmp_a64_zero(s);
342 } else {
343 return cpu_X[reg];
347 /* register access for when 31 == SP */
348 static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
350 return cpu_X[reg];
353 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
354 * representing the register contents. This TCGv is an auto-freed
355 * temporary so it need not be explicitly freed, and may be modified.
357 static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
359 TCGv_i64 v = new_tmp_a64(s);
360 if (reg != 31) {
361 if (sf) {
362 tcg_gen_mov_i64(v, cpu_X[reg]);
363 } else {
364 tcg_gen_ext32u_i64(v, cpu_X[reg]);
366 } else {
367 tcg_gen_movi_i64(v, 0);
369 return v;
372 static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
374 TCGv_i64 v = new_tmp_a64(s);
375 if (sf) {
376 tcg_gen_mov_i64(v, cpu_X[reg]);
377 } else {
378 tcg_gen_ext32u_i64(v, cpu_X[reg]);
380 return v;
383 /* We should have at some point before trying to access an FP register
384 * done the necessary access check, so assert that
385 * (a) we did the check and
386 * (b) we didn't then just plough ahead anyway if it failed.
387 * Print the instruction pattern in the abort message so we can figure
388 * out what we need to fix if a user encounters this problem in the wild.
390 static inline void assert_fp_access_checked(DisasContext *s)
392 #ifdef CONFIG_DEBUG_TCG
393 if (unlikely(!s->fp_access_checked || !s->cpacr_fpen)) {
394 fprintf(stderr, "target-arm: FP access check missing for "
395 "instruction 0x%08x\n", s->insn);
396 abort();
398 #endif
401 /* Return the offset into CPUARMState of an element of specified
402 * size, 'element' places in from the least significant end of
403 * the FP/vector register Qn.
405 static inline int vec_reg_offset(DisasContext *s, int regno,
406 int element, TCGMemOp size)
408 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
409 #ifdef HOST_WORDS_BIGENDIAN
410 /* This is complicated slightly because vfp.regs[2n] is
411 * still the low half and vfp.regs[2n+1] the high half
412 * of the 128 bit vector, even on big endian systems.
413 * Calculate the offset assuming a fully bigendian 128 bits,
414 * then XOR to account for the order of the two 64 bit halves.
416 offs += (16 - ((element + 1) * (1 << size)));
417 offs ^= 8;
418 #else
419 offs += element * (1 << size);
420 #endif
421 assert_fp_access_checked(s);
422 return offs;
425 /* Return the offset into CPUARMState of a slice (from
426 * the least significant end) of FP register Qn (ie
427 * Dn, Sn, Hn or Bn).
428 * (Note that this is not the same mapping as for A32; see cpu.h)
430 static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)
432 int offs = offsetof(CPUARMState, vfp.regs[regno * 2]);
433 #ifdef HOST_WORDS_BIGENDIAN
434 offs += (8 - (1 << size));
435 #endif
436 assert_fp_access_checked(s);
437 return offs;
440 /* Offset of the high half of the 128 bit vector Qn */
441 static inline int fp_reg_hi_offset(DisasContext *s, int regno)
443 assert_fp_access_checked(s);
444 return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]);
447 /* Convenience accessors for reading and writing single and double
448 * FP registers. Writing clears the upper parts of the associated
449 * 128 bit vector register, as required by the architecture.
450 * Note that unlike the GP register accessors, the values returned
451 * by the read functions must be manually freed.
453 static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
455 TCGv_i64 v = tcg_temp_new_i64();
457 tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));
458 return v;
461 static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
463 TCGv_i32 v = tcg_temp_new_i32();
465 tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32));
466 return v;
469 static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
471 TCGv_i64 tcg_zero = tcg_const_i64(0);
473 tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));
474 tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg));
475 tcg_temp_free_i64(tcg_zero);
478 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
480 TCGv_i64 tmp = tcg_temp_new_i64();
482 tcg_gen_extu_i32_i64(tmp, v);
483 write_fp_dreg(s, reg, tmp);
484 tcg_temp_free_i64(tmp);
487 static TCGv_ptr get_fpstatus_ptr(void)
489 TCGv_ptr statusptr = tcg_temp_new_ptr();
490 int offset;
492 /* In A64 all instructions (both FP and Neon) use the FPCR;
493 * there is no equivalent of the A32 Neon "standard FPSCR value"
494 * and all operations use vfp.fp_status.
496 offset = offsetof(CPUARMState, vfp.fp_status);
497 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
498 return statusptr;
501 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
502 * than the 32 bit equivalent.
504 static inline void gen_set_NZ64(TCGv_i64 result)
506 TCGv_i64 flag = tcg_temp_new_i64();
508 tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);
509 tcg_gen_trunc_i64_i32(cpu_ZF, flag);
510 tcg_gen_shri_i64(flag, result, 32);
511 tcg_gen_trunc_i64_i32(cpu_NF, flag);
512 tcg_temp_free_i64(flag);
515 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
516 static inline void gen_logic_CC(int sf, TCGv_i64 result)
518 if (sf) {
519 gen_set_NZ64(result);
520 } else {
521 tcg_gen_trunc_i64_i32(cpu_ZF, result);
522 tcg_gen_trunc_i64_i32(cpu_NF, result);
524 tcg_gen_movi_i32(cpu_CF, 0);
525 tcg_gen_movi_i32(cpu_VF, 0);
528 /* dest = T0 + T1; compute C, N, V and Z flags */
529 static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
531 if (sf) {
532 TCGv_i64 result, flag, tmp;
533 result = tcg_temp_new_i64();
534 flag = tcg_temp_new_i64();
535 tmp = tcg_temp_new_i64();
537 tcg_gen_movi_i64(tmp, 0);
538 tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp);
540 tcg_gen_trunc_i64_i32(cpu_CF, flag);
542 gen_set_NZ64(result);
544 tcg_gen_xor_i64(flag, result, t0);
545 tcg_gen_xor_i64(tmp, t0, t1);
546 tcg_gen_andc_i64(flag, flag, tmp);
547 tcg_temp_free_i64(tmp);
548 tcg_gen_shri_i64(flag, flag, 32);
549 tcg_gen_trunc_i64_i32(cpu_VF, flag);
551 tcg_gen_mov_i64(dest, result);
552 tcg_temp_free_i64(result);
553 tcg_temp_free_i64(flag);
554 } else {
555 /* 32 bit arithmetic */
556 TCGv_i32 t0_32 = tcg_temp_new_i32();
557 TCGv_i32 t1_32 = tcg_temp_new_i32();
558 TCGv_i32 tmp = tcg_temp_new_i32();
560 tcg_gen_movi_i32(tmp, 0);
561 tcg_gen_trunc_i64_i32(t0_32, t0);
562 tcg_gen_trunc_i64_i32(t1_32, t1);
563 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp);
564 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
565 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
566 tcg_gen_xor_i32(tmp, t0_32, t1_32);
567 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
568 tcg_gen_extu_i32_i64(dest, cpu_NF);
570 tcg_temp_free_i32(tmp);
571 tcg_temp_free_i32(t0_32);
572 tcg_temp_free_i32(t1_32);
576 /* dest = T0 - T1; compute C, N, V and Z flags */
577 static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
579 if (sf) {
580 /* 64 bit arithmetic */
581 TCGv_i64 result, flag, tmp;
583 result = tcg_temp_new_i64();
584 flag = tcg_temp_new_i64();
585 tcg_gen_sub_i64(result, t0, t1);
587 gen_set_NZ64(result);
589 tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1);
590 tcg_gen_trunc_i64_i32(cpu_CF, flag);
592 tcg_gen_xor_i64(flag, result, t0);
593 tmp = tcg_temp_new_i64();
594 tcg_gen_xor_i64(tmp, t0, t1);
595 tcg_gen_and_i64(flag, flag, tmp);
596 tcg_temp_free_i64(tmp);
597 tcg_gen_shri_i64(flag, flag, 32);
598 tcg_gen_trunc_i64_i32(cpu_VF, flag);
599 tcg_gen_mov_i64(dest, result);
600 tcg_temp_free_i64(flag);
601 tcg_temp_free_i64(result);
602 } else {
603 /* 32 bit arithmetic */
604 TCGv_i32 t0_32 = tcg_temp_new_i32();
605 TCGv_i32 t1_32 = tcg_temp_new_i32();
606 TCGv_i32 tmp;
608 tcg_gen_trunc_i64_i32(t0_32, t0);
609 tcg_gen_trunc_i64_i32(t1_32, t1);
610 tcg_gen_sub_i32(cpu_NF, t0_32, t1_32);
611 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
612 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32);
613 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
614 tmp = tcg_temp_new_i32();
615 tcg_gen_xor_i32(tmp, t0_32, t1_32);
616 tcg_temp_free_i32(t0_32);
617 tcg_temp_free_i32(t1_32);
618 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
619 tcg_temp_free_i32(tmp);
620 tcg_gen_extu_i32_i64(dest, cpu_NF);
624 /* dest = T0 + T1 + CF; do not compute flags. */
625 static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
627 TCGv_i64 flag = tcg_temp_new_i64();
628 tcg_gen_extu_i32_i64(flag, cpu_CF);
629 tcg_gen_add_i64(dest, t0, t1);
630 tcg_gen_add_i64(dest, dest, flag);
631 tcg_temp_free_i64(flag);
633 if (!sf) {
634 tcg_gen_ext32u_i64(dest, dest);
638 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
639 static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
641 if (sf) {
642 TCGv_i64 result, cf_64, vf_64, tmp;
643 result = tcg_temp_new_i64();
644 cf_64 = tcg_temp_new_i64();
645 vf_64 = tcg_temp_new_i64();
646 tmp = tcg_const_i64(0);
648 tcg_gen_extu_i32_i64(cf_64, cpu_CF);
649 tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
650 tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
651 tcg_gen_trunc_i64_i32(cpu_CF, cf_64);
652 gen_set_NZ64(result);
654 tcg_gen_xor_i64(vf_64, result, t0);
655 tcg_gen_xor_i64(tmp, t0, t1);
656 tcg_gen_andc_i64(vf_64, vf_64, tmp);
657 tcg_gen_shri_i64(vf_64, vf_64, 32);
658 tcg_gen_trunc_i64_i32(cpu_VF, vf_64);
660 tcg_gen_mov_i64(dest, result);
662 tcg_temp_free_i64(tmp);
663 tcg_temp_free_i64(vf_64);
664 tcg_temp_free_i64(cf_64);
665 tcg_temp_free_i64(result);
666 } else {
667 TCGv_i32 t0_32, t1_32, tmp;
668 t0_32 = tcg_temp_new_i32();
669 t1_32 = tcg_temp_new_i32();
670 tmp = tcg_const_i32(0);
672 tcg_gen_trunc_i64_i32(t0_32, t0);
673 tcg_gen_trunc_i64_i32(t1_32, t1);
674 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
675 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
677 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
678 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
679 tcg_gen_xor_i32(tmp, t0_32, t1_32);
680 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
681 tcg_gen_extu_i32_i64(dest, cpu_NF);
683 tcg_temp_free_i32(tmp);
684 tcg_temp_free_i32(t1_32);
685 tcg_temp_free_i32(t0_32);
690 * Load/Store generators
694 * Store from GPR register to memory.
696 static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
697 TCGv_i64 tcg_addr, int size, int memidx)
699 g_assert(size <= 3);
700 tcg_gen_qemu_st_i64(source, tcg_addr, memidx, MO_TE + size);
703 static void do_gpr_st(DisasContext *s, TCGv_i64 source,
704 TCGv_i64 tcg_addr, int size)
706 do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s));
710 * Load from memory to GPR register
712 static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
713 int size, bool is_signed, bool extend, int memidx)
715 TCGMemOp memop = MO_TE + size;
717 g_assert(size <= 3);
719 if (is_signed) {
720 memop += MO_SIGN;
723 tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
725 if (extend && is_signed) {
726 g_assert(size < 3);
727 tcg_gen_ext32u_i64(dest, dest);
731 static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
732 int size, bool is_signed, bool extend)
734 do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
735 get_mem_index(s));
739 * Store from FP register to memory
741 static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
743 /* This writes the bottom N bits of a 128 bit wide vector to memory */
744 TCGv_i64 tmp = tcg_temp_new_i64();
745 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64));
746 if (size < 4) {
747 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TE + size);
748 } else {
749 TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
750 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), MO_TEQ);
751 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx));
752 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
753 tcg_gen_qemu_st_i64(tmp, tcg_hiaddr, get_mem_index(s), MO_TEQ);
754 tcg_temp_free_i64(tcg_hiaddr);
757 tcg_temp_free_i64(tmp);
761 * Load from memory to FP register
763 static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
765 /* This always zero-extends and writes to a full 128 bit wide vector */
766 TCGv_i64 tmplo = tcg_temp_new_i64();
767 TCGv_i64 tmphi;
769 if (size < 4) {
770 TCGMemOp memop = MO_TE + size;
771 tmphi = tcg_const_i64(0);
772 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
773 } else {
774 TCGv_i64 tcg_hiaddr;
775 tmphi = tcg_temp_new_i64();
776 tcg_hiaddr = tcg_temp_new_i64();
778 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), MO_TEQ);
779 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
780 tcg_gen_qemu_ld_i64(tmphi, tcg_hiaddr, get_mem_index(s), MO_TEQ);
781 tcg_temp_free_i64(tcg_hiaddr);
784 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
785 tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
787 tcg_temp_free_i64(tmplo);
788 tcg_temp_free_i64(tmphi);
792 * Vector load/store helpers.
794 * The principal difference between this and a FP load is that we don't
795 * zero extend as we are filling a partial chunk of the vector register.
796 * These functions don't support 128 bit loads/stores, which would be
797 * normal load/store operations.
799 * The _i32 versions are useful when operating on 32 bit quantities
800 * (eg for floating point single or using Neon helper functions).
803 /* Get value of an element within a vector register */
804 static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
805 int element, TCGMemOp memop)
807 int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
808 switch (memop) {
809 case MO_8:
810 tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
811 break;
812 case MO_16:
813 tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
814 break;
815 case MO_32:
816 tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
817 break;
818 case MO_8|MO_SIGN:
819 tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
820 break;
821 case MO_16|MO_SIGN:
822 tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
823 break;
824 case MO_32|MO_SIGN:
825 tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
826 break;
827 case MO_64:
828 case MO_64|MO_SIGN:
829 tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
830 break;
831 default:
832 g_assert_not_reached();
836 static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
837 int element, TCGMemOp memop)
839 int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
840 switch (memop) {
841 case MO_8:
842 tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
843 break;
844 case MO_16:
845 tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
846 break;
847 case MO_8|MO_SIGN:
848 tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
849 break;
850 case MO_16|MO_SIGN:
851 tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
852 break;
853 case MO_32:
854 case MO_32|MO_SIGN:
855 tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
856 break;
857 default:
858 g_assert_not_reached();
862 /* Set value of an element within a vector register */
863 static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
864 int element, TCGMemOp memop)
866 int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
867 switch (memop) {
868 case MO_8:
869 tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
870 break;
871 case MO_16:
872 tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
873 break;
874 case MO_32:
875 tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
876 break;
877 case MO_64:
878 tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
879 break;
880 default:
881 g_assert_not_reached();
885 static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
886 int destidx, int element, TCGMemOp memop)
888 int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
889 switch (memop) {
890 case MO_8:
891 tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
892 break;
893 case MO_16:
894 tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
895 break;
896 case MO_32:
897 tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
898 break;
899 default:
900 g_assert_not_reached();
904 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
905 * vector ops all need to do this).
907 static void clear_vec_high(DisasContext *s, int rd)
909 TCGv_i64 tcg_zero = tcg_const_i64(0);
911 write_vec_element(s, tcg_zero, rd, 1, MO_64);
912 tcg_temp_free_i64(tcg_zero);
915 /* Store from vector register to memory */
916 static void do_vec_st(DisasContext *s, int srcidx, int element,
917 TCGv_i64 tcg_addr, int size)
919 TCGMemOp memop = MO_TE + size;
920 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
922 read_vec_element(s, tcg_tmp, srcidx, element, size);
923 tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
925 tcg_temp_free_i64(tcg_tmp);
928 /* Load from memory to vector register */
929 static void do_vec_ld(DisasContext *s, int destidx, int element,
930 TCGv_i64 tcg_addr, int size)
932 TCGMemOp memop = MO_TE + size;
933 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
935 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
936 write_vec_element(s, tcg_tmp, destidx, element, size);
938 tcg_temp_free_i64(tcg_tmp);
941 /* Check that FP/Neon access is enabled. If it is, return
942 * true. If not, emit code to generate an appropriate exception,
943 * and return false; the caller should not emit any code for
944 * the instruction. Note that this check must happen after all
945 * unallocated-encoding checks (otherwise the syndrome information
946 * for the resulting exception will be incorrect).
948 static inline bool fp_access_check(DisasContext *s)
950 assert(!s->fp_access_checked);
951 s->fp_access_checked = true;
953 if (s->cpacr_fpen) {
954 return true;
957 gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false));
958 return false;
962 * This utility function is for doing register extension with an
963 * optional shift. You will likely want to pass a temporary for the
964 * destination register. See DecodeRegExtend() in the ARM ARM.
966 static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in,
967 int option, unsigned int shift)
969 int extsize = extract32(option, 0, 2);
970 bool is_signed = extract32(option, 2, 1);
972 if (is_signed) {
973 switch (extsize) {
974 case 0:
975 tcg_gen_ext8s_i64(tcg_out, tcg_in);
976 break;
977 case 1:
978 tcg_gen_ext16s_i64(tcg_out, tcg_in);
979 break;
980 case 2:
981 tcg_gen_ext32s_i64(tcg_out, tcg_in);
982 break;
983 case 3:
984 tcg_gen_mov_i64(tcg_out, tcg_in);
985 break;
987 } else {
988 switch (extsize) {
989 case 0:
990 tcg_gen_ext8u_i64(tcg_out, tcg_in);
991 break;
992 case 1:
993 tcg_gen_ext16u_i64(tcg_out, tcg_in);
994 break;
995 case 2:
996 tcg_gen_ext32u_i64(tcg_out, tcg_in);
997 break;
998 case 3:
999 tcg_gen_mov_i64(tcg_out, tcg_in);
1000 break;
1004 if (shift) {
1005 tcg_gen_shli_i64(tcg_out, tcg_out, shift);
1009 static inline void gen_check_sp_alignment(DisasContext *s)
1011 /* The AArch64 architecture mandates that (if enabled via PSTATE
1012 * or SCTLR bits) there is a check that SP is 16-aligned on every
1013 * SP-relative load or store (with an exception generated if it is not).
1014 * In line with general QEMU practice regarding misaligned accesses,
1015 * we omit these checks for the sake of guest program performance.
1016 * This function is provided as a hook so we can more easily add these
1017 * checks in future (possibly as a "favour catching guest program bugs
1018 * over speed" user selectable option).
1023 * This provides a simple table based table lookup decoder. It is
1024 * intended to be used when the relevant bits for decode are too
1025 * awkwardly placed and switch/if based logic would be confusing and
1026 * deeply nested. Since it's a linear search through the table, tables
1027 * should be kept small.
1029 * It returns the first handler where insn & mask == pattern, or
1030 * NULL if there is no match.
1031 * The table is terminated by an empty mask (i.e. 0)
1033 static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
1034 uint32_t insn)
1036 const AArch64DecodeTable *tptr = table;
1038 while (tptr->mask) {
1039 if ((insn & tptr->mask) == tptr->pattern) {
1040 return tptr->disas_fn;
1042 tptr++;
1044 return NULL;
1048 * the instruction disassembly implemented here matches
1049 * the instruction encoding classifications in chapter 3 (C3)
1050 * of the ARM Architecture Reference Manual (DDI0487A_a)
1053 /* C3.2.7 Unconditional branch (immediate)
1054 * 31 30 26 25 0
1055 * +----+-----------+-------------------------------------+
1056 * | op | 0 0 1 0 1 | imm26 |
1057 * +----+-----------+-------------------------------------+
1059 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
1061 uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
1063 if (insn & (1 << 31)) {
1064 /* C5.6.26 BL Branch with link */
1065 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1068 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1069 gen_goto_tb(s, 0, addr);
1072 /* C3.2.1 Compare & branch (immediate)
1073 * 31 30 25 24 23 5 4 0
1074 * +----+-------------+----+---------------------+--------+
1075 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1076 * +----+-------------+----+---------------------+--------+
1078 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
1080 unsigned int sf, op, rt;
1081 uint64_t addr;
1082 int label_match;
1083 TCGv_i64 tcg_cmp;
1085 sf = extract32(insn, 31, 1);
1086 op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
1087 rt = extract32(insn, 0, 5);
1088 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1090 tcg_cmp = read_cpu_reg(s, rt, sf);
1091 label_match = gen_new_label();
1093 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1094 tcg_cmp, 0, label_match);
1096 gen_goto_tb(s, 0, s->pc);
1097 gen_set_label(label_match);
1098 gen_goto_tb(s, 1, addr);
1101 /* C3.2.5 Test & branch (immediate)
1102 * 31 30 25 24 23 19 18 5 4 0
1103 * +----+-------------+----+-------+-------------+------+
1104 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1105 * +----+-------------+----+-------+-------------+------+
1107 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
1109 unsigned int bit_pos, op, rt;
1110 uint64_t addr;
1111 int label_match;
1112 TCGv_i64 tcg_cmp;
1114 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
1115 op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
1116 addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
1117 rt = extract32(insn, 0, 5);
1119 tcg_cmp = tcg_temp_new_i64();
1120 tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
1121 label_match = gen_new_label();
1122 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1123 tcg_cmp, 0, label_match);
1124 tcg_temp_free_i64(tcg_cmp);
1125 gen_goto_tb(s, 0, s->pc);
1126 gen_set_label(label_match);
1127 gen_goto_tb(s, 1, addr);
1130 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1131 * 31 25 24 23 5 4 3 0
1132 * +---------------+----+---------------------+----+------+
1133 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1134 * +---------------+----+---------------------+----+------+
1136 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
1138 unsigned int cond;
1139 uint64_t addr;
1141 if ((insn & (1 << 4)) || (insn & (1 << 24))) {
1142 unallocated_encoding(s);
1143 return;
1145 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1146 cond = extract32(insn, 0, 4);
1148 if (cond < 0x0e) {
1149 /* genuinely conditional branches */
1150 int label_match = gen_new_label();
1151 arm_gen_test_cc(cond, label_match);
1152 gen_goto_tb(s, 0, s->pc);
1153 gen_set_label(label_match);
1154 gen_goto_tb(s, 1, addr);
1155 } else {
1156 /* 0xe and 0xf are both "always" conditions */
1157 gen_goto_tb(s, 0, addr);
1161 /* C5.6.68 HINT */
1162 static void handle_hint(DisasContext *s, uint32_t insn,
1163 unsigned int op1, unsigned int op2, unsigned int crm)
1165 unsigned int selector = crm << 3 | op2;
1167 if (op1 != 3) {
1168 unallocated_encoding(s);
1169 return;
1172 switch (selector) {
1173 case 0: /* NOP */
1174 return;
1175 case 3: /* WFI */
1176 s->is_jmp = DISAS_WFI;
1177 return;
1178 case 1: /* YIELD */
1179 case 2: /* WFE */
1180 s->is_jmp = DISAS_WFE;
1181 return;
1182 case 4: /* SEV */
1183 case 5: /* SEVL */
1184 /* we treat all as NOP at least for now */
1185 return;
1186 default:
1187 /* default specified as NOP equivalent */
1188 return;
1192 static void gen_clrex(DisasContext *s, uint32_t insn)
1194 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1197 /* CLREX, DSB, DMB, ISB */
1198 static void handle_sync(DisasContext *s, uint32_t insn,
1199 unsigned int op1, unsigned int op2, unsigned int crm)
1201 if (op1 != 3) {
1202 unallocated_encoding(s);
1203 return;
1206 switch (op2) {
1207 case 2: /* CLREX */
1208 gen_clrex(s, insn);
1209 return;
1210 case 4: /* DSB */
1211 case 5: /* DMB */
1212 case 6: /* ISB */
1213 /* We don't emulate caches so barriers are no-ops */
1214 return;
1215 default:
1216 unallocated_encoding(s);
1217 return;
1221 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1222 static void handle_msr_i(DisasContext *s, uint32_t insn,
1223 unsigned int op1, unsigned int op2, unsigned int crm)
1225 int op = op1 << 3 | op2;
1226 switch (op) {
1227 case 0x05: /* SPSel */
1228 if (s->current_el == 0) {
1229 unallocated_encoding(s);
1230 return;
1232 /* fall through */
1233 case 0x1e: /* DAIFSet */
1234 case 0x1f: /* DAIFClear */
1236 TCGv_i32 tcg_imm = tcg_const_i32(crm);
1237 TCGv_i32 tcg_op = tcg_const_i32(op);
1238 gen_a64_set_pc_im(s->pc - 4);
1239 gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
1240 tcg_temp_free_i32(tcg_imm);
1241 tcg_temp_free_i32(tcg_op);
1242 s->is_jmp = DISAS_UPDATE;
1243 break;
1245 default:
1246 unallocated_encoding(s);
1247 return;
1251 static void gen_get_nzcv(TCGv_i64 tcg_rt)
1253 TCGv_i32 tmp = tcg_temp_new_i32();
1254 TCGv_i32 nzcv = tcg_temp_new_i32();
1256 /* build bit 31, N */
1257 tcg_gen_andi_i32(nzcv, cpu_NF, (1 << 31));
1258 /* build bit 30, Z */
1259 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);
1260 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1);
1261 /* build bit 29, C */
1262 tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1);
1263 /* build bit 28, V */
1264 tcg_gen_shri_i32(tmp, cpu_VF, 31);
1265 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1);
1266 /* generate result */
1267 tcg_gen_extu_i32_i64(tcg_rt, nzcv);
1269 tcg_temp_free_i32(nzcv);
1270 tcg_temp_free_i32(tmp);
1273 static void gen_set_nzcv(TCGv_i64 tcg_rt)
1276 TCGv_i32 nzcv = tcg_temp_new_i32();
1278 /* take NZCV from R[t] */
1279 tcg_gen_trunc_i64_i32(nzcv, tcg_rt);
1281 /* bit 31, N */
1282 tcg_gen_andi_i32(cpu_NF, nzcv, (1 << 31));
1283 /* bit 30, Z */
1284 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30));
1285 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
1286 /* bit 29, C */
1287 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29));
1288 tcg_gen_shri_i32(cpu_CF, cpu_CF, 29);
1289 /* bit 28, V */
1290 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28));
1291 tcg_gen_shli_i32(cpu_VF, cpu_VF, 3);
1292 tcg_temp_free_i32(nzcv);
1295 /* C5.6.129 MRS - move from system register
1296 * C5.6.131 MSR (register) - move to system register
1297 * C5.6.204 SYS
1298 * C5.6.205 SYSL
1299 * These are all essentially the same insn in 'read' and 'write'
1300 * versions, with varying op0 fields.
1302 static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
1303 unsigned int op0, unsigned int op1, unsigned int op2,
1304 unsigned int crn, unsigned int crm, unsigned int rt)
1306 const ARMCPRegInfo *ri;
1307 TCGv_i64 tcg_rt;
1309 ri = get_arm_cp_reginfo(s->cp_regs,
1310 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
1311 crn, crm, op0, op1, op2));
1313 if (!ri) {
1314 /* Unknown register; this might be a guest error or a QEMU
1315 * unimplemented feature.
1317 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
1318 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1319 isread ? "read" : "write", op0, op1, crn, crm, op2);
1320 unallocated_encoding(s);
1321 return;
1324 /* Check access permissions */
1325 if (!cp_access_ok(s->current_el, ri, isread)) {
1326 unallocated_encoding(s);
1327 return;
1330 if (ri->accessfn) {
1331 /* Emit code to perform further access permissions checks at
1332 * runtime; this may result in an exception.
1334 TCGv_ptr tmpptr;
1335 TCGv_i32 tcg_syn;
1336 uint32_t syndrome;
1338 gen_a64_set_pc_im(s->pc - 4);
1339 tmpptr = tcg_const_ptr(ri);
1340 syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
1341 tcg_syn = tcg_const_i32(syndrome);
1342 gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn);
1343 tcg_temp_free_ptr(tmpptr);
1344 tcg_temp_free_i32(tcg_syn);
1347 /* Handle special cases first */
1348 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
1349 case ARM_CP_NOP:
1350 return;
1351 case ARM_CP_NZCV:
1352 tcg_rt = cpu_reg(s, rt);
1353 if (isread) {
1354 gen_get_nzcv(tcg_rt);
1355 } else {
1356 gen_set_nzcv(tcg_rt);
1358 return;
1359 case ARM_CP_CURRENTEL:
1360 /* Reads as current EL value from pstate, which is
1361 * guaranteed to be constant by the tb flags.
1363 tcg_rt = cpu_reg(s, rt);
1364 tcg_gen_movi_i64(tcg_rt, s->current_el << 2);
1365 return;
1366 case ARM_CP_DC_ZVA:
1367 /* Writes clear the aligned block of memory which rt points into. */
1368 tcg_rt = cpu_reg(s, rt);
1369 gen_helper_dc_zva(cpu_env, tcg_rt);
1370 return;
1371 default:
1372 break;
1375 if (use_icount && (ri->type & ARM_CP_IO)) {
1376 gen_io_start();
1379 tcg_rt = cpu_reg(s, rt);
1381 if (isread) {
1382 if (ri->type & ARM_CP_CONST) {
1383 tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
1384 } else if (ri->readfn) {
1385 TCGv_ptr tmpptr;
1386 tmpptr = tcg_const_ptr(ri);
1387 gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
1388 tcg_temp_free_ptr(tmpptr);
1389 } else {
1390 tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
1392 } else {
1393 if (ri->type & ARM_CP_CONST) {
1394 /* If not forbidden by access permissions, treat as WI */
1395 return;
1396 } else if (ri->writefn) {
1397 TCGv_ptr tmpptr;
1398 tmpptr = tcg_const_ptr(ri);
1399 gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
1400 tcg_temp_free_ptr(tmpptr);
1401 } else {
1402 tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
1406 if (use_icount && (ri->type & ARM_CP_IO)) {
1407 /* I/O operations must end the TB here (whether read or write) */
1408 gen_io_end();
1409 s->is_jmp = DISAS_UPDATE;
1410 } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
1411 /* We default to ending the TB on a coprocessor register write,
1412 * but allow this to be suppressed by the register definition
1413 * (usually only necessary to work around guest bugs).
1415 s->is_jmp = DISAS_UPDATE;
1419 /* C3.2.4 System
1420 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1421 * +---------------------+---+-----+-----+-------+-------+-----+------+
1422 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1423 * +---------------------+---+-----+-----+-------+-------+-----+------+
1425 static void disas_system(DisasContext *s, uint32_t insn)
1427 unsigned int l, op0, op1, crn, crm, op2, rt;
1428 l = extract32(insn, 21, 1);
1429 op0 = extract32(insn, 19, 2);
1430 op1 = extract32(insn, 16, 3);
1431 crn = extract32(insn, 12, 4);
1432 crm = extract32(insn, 8, 4);
1433 op2 = extract32(insn, 5, 3);
1434 rt = extract32(insn, 0, 5);
1436 if (op0 == 0) {
1437 if (l || rt != 31) {
1438 unallocated_encoding(s);
1439 return;
1441 switch (crn) {
1442 case 2: /* C5.6.68 HINT */
1443 handle_hint(s, insn, op1, op2, crm);
1444 break;
1445 case 3: /* CLREX, DSB, DMB, ISB */
1446 handle_sync(s, insn, op1, op2, crm);
1447 break;
1448 case 4: /* C5.6.130 MSR (immediate) */
1449 handle_msr_i(s, insn, op1, op2, crm);
1450 break;
1451 default:
1452 unallocated_encoding(s);
1453 break;
1455 return;
1457 handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
1460 /* C3.2.3 Exception generation
1462 * 31 24 23 21 20 5 4 2 1 0
1463 * +-----------------+-----+------------------------+-----+----+
1464 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1465 * +-----------------------+------------------------+----------+
1467 static void disas_exc(DisasContext *s, uint32_t insn)
1469 int opc = extract32(insn, 21, 3);
1470 int op2_ll = extract32(insn, 0, 5);
1471 int imm16 = extract32(insn, 5, 16);
1472 TCGv_i32 tmp;
1474 switch (opc) {
1475 case 0:
1476 /* For SVC, HVC and SMC we advance the single-step state
1477 * machine before taking the exception. This is architecturally
1478 * mandated, to ensure that single-stepping a system call
1479 * instruction works properly.
1481 switch (op2_ll) {
1482 case 1:
1483 gen_ss_advance(s);
1484 gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16));
1485 break;
1486 case 2:
1487 if (s->current_el == 0) {
1488 unallocated_encoding(s);
1489 break;
1491 /* The pre HVC helper handles cases when HVC gets trapped
1492 * as an undefined insn by runtime configuration.
1494 gen_a64_set_pc_im(s->pc - 4);
1495 gen_helper_pre_hvc(cpu_env);
1496 gen_ss_advance(s);
1497 gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16));
1498 break;
1499 case 3:
1500 if (s->current_el == 0) {
1501 unallocated_encoding(s);
1502 break;
1504 gen_a64_set_pc_im(s->pc - 4);
1505 tmp = tcg_const_i32(syn_aa64_smc(imm16));
1506 gen_helper_pre_smc(cpu_env, tmp);
1507 tcg_temp_free_i32(tmp);
1508 gen_ss_advance(s);
1509 gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16));
1510 break;
1511 default:
1512 unallocated_encoding(s);
1513 break;
1515 break;
1516 case 1:
1517 if (op2_ll != 0) {
1518 unallocated_encoding(s);
1519 break;
1521 /* BRK */
1522 gen_exception_insn(s, 4, EXCP_BKPT, syn_aa64_bkpt(imm16));
1523 break;
1524 case 2:
1525 if (op2_ll != 0) {
1526 unallocated_encoding(s);
1527 break;
1529 /* HLT */
1530 unsupported_encoding(s, insn);
1531 break;
1532 case 5:
1533 if (op2_ll < 1 || op2_ll > 3) {
1534 unallocated_encoding(s);
1535 break;
1537 /* DCPS1, DCPS2, DCPS3 */
1538 unsupported_encoding(s, insn);
1539 break;
1540 default:
1541 unallocated_encoding(s);
1542 break;
1546 /* C3.2.7 Unconditional branch (register)
1547 * 31 25 24 21 20 16 15 10 9 5 4 0
1548 * +---------------+-------+-------+-------+------+-------+
1549 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1550 * +---------------+-------+-------+-------+------+-------+
1552 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
1554 unsigned int opc, op2, op3, rn, op4;
1556 opc = extract32(insn, 21, 4);
1557 op2 = extract32(insn, 16, 5);
1558 op3 = extract32(insn, 10, 6);
1559 rn = extract32(insn, 5, 5);
1560 op4 = extract32(insn, 0, 5);
1562 if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
1563 unallocated_encoding(s);
1564 return;
1567 switch (opc) {
1568 case 0: /* BR */
1569 case 2: /* RET */
1570 tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
1571 break;
1572 case 1: /* BLR */
1573 tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
1574 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1575 break;
1576 case 4: /* ERET */
1577 if (s->current_el == 0) {
1578 unallocated_encoding(s);
1579 return;
1581 gen_helper_exception_return(cpu_env);
1582 s->is_jmp = DISAS_JUMP;
1583 return;
1584 case 5: /* DRPS */
1585 if (rn != 0x1f) {
1586 unallocated_encoding(s);
1587 } else {
1588 unsupported_encoding(s, insn);
1590 return;
1591 default:
1592 unallocated_encoding(s);
1593 return;
1596 s->is_jmp = DISAS_JUMP;
1599 /* C3.2 Branches, exception generating and system instructions */
1600 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
1602 switch (extract32(insn, 25, 7)) {
1603 case 0x0a: case 0x0b:
1604 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1605 disas_uncond_b_imm(s, insn);
1606 break;
1607 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1608 disas_comp_b_imm(s, insn);
1609 break;
1610 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1611 disas_test_b_imm(s, insn);
1612 break;
1613 case 0x2a: /* Conditional branch (immediate) */
1614 disas_cond_b_imm(s, insn);
1615 break;
1616 case 0x6a: /* Exception generation / System */
1617 if (insn & (1 << 24)) {
1618 disas_system(s, insn);
1619 } else {
1620 disas_exc(s, insn);
1622 break;
1623 case 0x6b: /* Unconditional branch (register) */
1624 disas_uncond_b_reg(s, insn);
1625 break;
1626 default:
1627 unallocated_encoding(s);
1628 break;
1633 * Load/Store exclusive instructions are implemented by remembering
1634 * the value/address loaded, and seeing if these are the same
1635 * when the store is performed. This is not actually the architecturally
1636 * mandated semantics, but it works for typical guest code sequences
1637 * and avoids having to monitor regular stores.
1639 * In system emulation mode only one CPU will be running at once, so
1640 * this sequence is effectively atomic. In user emulation mode we
1641 * throw an exception and handle the atomic operation elsewhere.
1643 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
1644 TCGv_i64 addr, int size, bool is_pair)
1646 TCGv_i64 tmp = tcg_temp_new_i64();
1647 TCGMemOp memop = MO_TE + size;
1649 g_assert(size <= 3);
1650 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop);
1652 if (is_pair) {
1653 TCGv_i64 addr2 = tcg_temp_new_i64();
1654 TCGv_i64 hitmp = tcg_temp_new_i64();
1656 g_assert(size >= 2);
1657 tcg_gen_addi_i64(addr2, addr, 1 << size);
1658 tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop);
1659 tcg_temp_free_i64(addr2);
1660 tcg_gen_mov_i64(cpu_exclusive_high, hitmp);
1661 tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp);
1662 tcg_temp_free_i64(hitmp);
1665 tcg_gen_mov_i64(cpu_exclusive_val, tmp);
1666 tcg_gen_mov_i64(cpu_reg(s, rt), tmp);
1668 tcg_temp_free_i64(tmp);
1669 tcg_gen_mov_i64(cpu_exclusive_addr, addr);
1672 #ifdef CONFIG_USER_ONLY
1673 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1674 TCGv_i64 addr, int size, int is_pair)
1676 tcg_gen_mov_i64(cpu_exclusive_test, addr);
1677 tcg_gen_movi_i32(cpu_exclusive_info,
1678 size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14));
1679 gen_exception_internal_insn(s, 4, EXCP_STREX);
1681 #else
1682 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1683 TCGv_i64 inaddr, int size, int is_pair)
1685 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1686 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1687 * [addr] = {Rt};
1688 * if (is_pair) {
1689 * [addr + datasize] = {Rt2};
1691 * {Rd} = 0;
1692 * } else {
1693 * {Rd} = 1;
1695 * env->exclusive_addr = -1;
1697 int fail_label = gen_new_label();
1698 int done_label = gen_new_label();
1699 TCGv_i64 addr = tcg_temp_local_new_i64();
1700 TCGv_i64 tmp;
1702 /* Copy input into a local temp so it is not trashed when the
1703 * basic block ends at the branch insn.
1705 tcg_gen_mov_i64(addr, inaddr);
1706 tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
1708 tmp = tcg_temp_new_i64();
1709 tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), MO_TE + size);
1710 tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label);
1711 tcg_temp_free_i64(tmp);
1713 if (is_pair) {
1714 TCGv_i64 addrhi = tcg_temp_new_i64();
1715 TCGv_i64 tmphi = tcg_temp_new_i64();
1717 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1718 tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), MO_TE + size);
1719 tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label);
1721 tcg_temp_free_i64(tmphi);
1722 tcg_temp_free_i64(addrhi);
1725 /* We seem to still have the exclusive monitor, so do the store */
1726 tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), MO_TE + size);
1727 if (is_pair) {
1728 TCGv_i64 addrhi = tcg_temp_new_i64();
1730 tcg_gen_addi_i64(addrhi, addr, 1 << size);
1731 tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi,
1732 get_mem_index(s), MO_TE + size);
1733 tcg_temp_free_i64(addrhi);
1736 tcg_temp_free_i64(addr);
1738 tcg_gen_movi_i64(cpu_reg(s, rd), 0);
1739 tcg_gen_br(done_label);
1740 gen_set_label(fail_label);
1741 tcg_gen_movi_i64(cpu_reg(s, rd), 1);
1742 gen_set_label(done_label);
1743 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1746 #endif
1748 /* C3.3.6 Load/store exclusive
1750 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1751 * +-----+-------------+----+---+----+------+----+-------+------+------+
1752 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1753 * +-----+-------------+----+---+----+------+----+-------+------+------+
1755 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1756 * L: 0 -> store, 1 -> load
1757 * o2: 0 -> exclusive, 1 -> not
1758 * o1: 0 -> single register, 1 -> register pair
1759 * o0: 1 -> load-acquire/store-release, 0 -> not
1761 * o0 == 0 AND o2 == 1 is un-allocated
1762 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1764 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
1766 int rt = extract32(insn, 0, 5);
1767 int rn = extract32(insn, 5, 5);
1768 int rt2 = extract32(insn, 10, 5);
1769 int is_lasr = extract32(insn, 15, 1);
1770 int rs = extract32(insn, 16, 5);
1771 int is_pair = extract32(insn, 21, 1);
1772 int is_store = !extract32(insn, 22, 1);
1773 int is_excl = !extract32(insn, 23, 1);
1774 int size = extract32(insn, 30, 2);
1775 TCGv_i64 tcg_addr;
1777 if ((!is_excl && !is_lasr) ||
1778 (is_pair && size < 2)) {
1779 unallocated_encoding(s);
1780 return;
1783 if (rn == 31) {
1784 gen_check_sp_alignment(s);
1786 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1788 /* Note that since TCG is single threaded load-acquire/store-release
1789 * semantics require no extra if (is_lasr) { ... } handling.
1792 if (is_excl) {
1793 if (!is_store) {
1794 s->is_ldex = true;
1795 gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
1796 } else {
1797 gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
1799 } else {
1800 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1801 if (is_store) {
1802 do_gpr_st(s, tcg_rt, tcg_addr, size);
1803 } else {
1804 do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
1806 if (is_pair) {
1807 TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
1808 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
1809 if (is_store) {
1810 do_gpr_st(s, tcg_rt2, tcg_addr, size);
1811 } else {
1812 do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);
1819 * C3.3.5 Load register (literal)
1821 * 31 30 29 27 26 25 24 23 5 4 0
1822 * +-----+-------+---+-----+-------------------+-------+
1823 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1824 * +-----+-------+---+-----+-------------------+-------+
1826 * V: 1 -> vector (simd/fp)
1827 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1828 * 10-> 32 bit signed, 11 -> prefetch
1829 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1831 static void disas_ld_lit(DisasContext *s, uint32_t insn)
1833 int rt = extract32(insn, 0, 5);
1834 int64_t imm = sextract32(insn, 5, 19) << 2;
1835 bool is_vector = extract32(insn, 26, 1);
1836 int opc = extract32(insn, 30, 2);
1837 bool is_signed = false;
1838 int size = 2;
1839 TCGv_i64 tcg_rt, tcg_addr;
1841 if (is_vector) {
1842 if (opc == 3) {
1843 unallocated_encoding(s);
1844 return;
1846 size = 2 + opc;
1847 if (!fp_access_check(s)) {
1848 return;
1850 } else {
1851 if (opc == 3) {
1852 /* PRFM (literal) : prefetch */
1853 return;
1855 size = 2 + extract32(opc, 0, 1);
1856 is_signed = extract32(opc, 1, 1);
1859 tcg_rt = cpu_reg(s, rt);
1861 tcg_addr = tcg_const_i64((s->pc - 4) + imm);
1862 if (is_vector) {
1863 do_fp_ld(s, rt, tcg_addr, size);
1864 } else {
1865 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1867 tcg_temp_free_i64(tcg_addr);
1871 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1872 * C5.6.81 LDP (Load Pair - non vector)
1873 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1874 * C5.6.176 STNP (Store Pair - non-temporal hint)
1875 * C5.6.177 STP (Store Pair - non vector)
1876 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1877 * C6.3.165 LDP (Load Pair of SIMD&FP)
1878 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1879 * C6.3.284 STP (Store Pair of SIMD&FP)
1881 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1882 * +-----+-------+---+---+-------+---+-----------------------------+
1883 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1884 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1886 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1887 * LDPSW 01
1888 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1889 * V: 0 -> GPR, 1 -> Vector
1890 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1891 * 10 -> signed offset, 11 -> pre-index
1892 * L: 0 -> Store 1 -> Load
1894 * Rt, Rt2 = GPR or SIMD registers to be stored
1895 * Rn = general purpose register containing address
1896 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1898 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
1900 int rt = extract32(insn, 0, 5);
1901 int rn = extract32(insn, 5, 5);
1902 int rt2 = extract32(insn, 10, 5);
1903 int64_t offset = sextract32(insn, 15, 7);
1904 int index = extract32(insn, 23, 2);
1905 bool is_vector = extract32(insn, 26, 1);
1906 bool is_load = extract32(insn, 22, 1);
1907 int opc = extract32(insn, 30, 2);
1909 bool is_signed = false;
1910 bool postindex = false;
1911 bool wback = false;
1913 TCGv_i64 tcg_addr; /* calculated address */
1914 int size;
1916 if (opc == 3) {
1917 unallocated_encoding(s);
1918 return;
1921 if (is_vector) {
1922 size = 2 + opc;
1923 } else {
1924 size = 2 + extract32(opc, 1, 1);
1925 is_signed = extract32(opc, 0, 1);
1926 if (!is_load && is_signed) {
1927 unallocated_encoding(s);
1928 return;
1932 switch (index) {
1933 case 1: /* post-index */
1934 postindex = true;
1935 wback = true;
1936 break;
1937 case 0:
1938 /* signed offset with "non-temporal" hint. Since we don't emulate
1939 * caches we don't care about hints to the cache system about
1940 * data access patterns, and handle this identically to plain
1941 * signed offset.
1943 if (is_signed) {
1944 /* There is no non-temporal-hint version of LDPSW */
1945 unallocated_encoding(s);
1946 return;
1948 postindex = false;
1949 break;
1950 case 2: /* signed offset, rn not updated */
1951 postindex = false;
1952 break;
1953 case 3: /* pre-index */
1954 postindex = false;
1955 wback = true;
1956 break;
1959 if (is_vector && !fp_access_check(s)) {
1960 return;
1963 offset <<= size;
1965 if (rn == 31) {
1966 gen_check_sp_alignment(s);
1969 tcg_addr = read_cpu_reg_sp(s, rn, 1);
1971 if (!postindex) {
1972 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
1975 if (is_vector) {
1976 if (is_load) {
1977 do_fp_ld(s, rt, tcg_addr, size);
1978 } else {
1979 do_fp_st(s, rt, tcg_addr, size);
1981 } else {
1982 TCGv_i64 tcg_rt = cpu_reg(s, rt);
1983 if (is_load) {
1984 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false);
1985 } else {
1986 do_gpr_st(s, tcg_rt, tcg_addr, size);
1989 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
1990 if (is_vector) {
1991 if (is_load) {
1992 do_fp_ld(s, rt2, tcg_addr, size);
1993 } else {
1994 do_fp_st(s, rt2, tcg_addr, size);
1996 } else {
1997 TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
1998 if (is_load) {
1999 do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false);
2000 } else {
2001 do_gpr_st(s, tcg_rt2, tcg_addr, size);
2005 if (wback) {
2006 if (postindex) {
2007 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
2008 } else {
2009 tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
2011 tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
2016 * C3.3.8 Load/store (immediate post-indexed)
2017 * C3.3.9 Load/store (immediate pre-indexed)
2018 * C3.3.12 Load/store (unscaled immediate)
2020 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2021 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2022 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2023 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2025 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2026 10 -> unprivileged
2027 * V = 0 -> non-vector
2028 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2029 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2031 static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn)
2033 int rt = extract32(insn, 0, 5);
2034 int rn = extract32(insn, 5, 5);
2035 int imm9 = sextract32(insn, 12, 9);
2036 int opc = extract32(insn, 22, 2);
2037 int size = extract32(insn, 30, 2);
2038 int idx = extract32(insn, 10, 2);
2039 bool is_signed = false;
2040 bool is_store = false;
2041 bool is_extended = false;
2042 bool is_unpriv = (idx == 2);
2043 bool is_vector = extract32(insn, 26, 1);
2044 bool post_index;
2045 bool writeback;
2047 TCGv_i64 tcg_addr;
2049 if (is_vector) {
2050 size |= (opc & 2) << 1;
2051 if (size > 4 || is_unpriv) {
2052 unallocated_encoding(s);
2053 return;
2055 is_store = ((opc & 1) == 0);
2056 if (!fp_access_check(s)) {
2057 return;
2059 } else {
2060 if (size == 3 && opc == 2) {
2061 /* PRFM - prefetch */
2062 if (is_unpriv) {
2063 unallocated_encoding(s);
2064 return;
2066 return;
2068 if (opc == 3 && size > 1) {
2069 unallocated_encoding(s);
2070 return;
2072 is_store = (opc == 0);
2073 is_signed = opc & (1<<1);
2074 is_extended = (size < 3) && (opc & 1);
2077 switch (idx) {
2078 case 0:
2079 case 2:
2080 post_index = false;
2081 writeback = false;
2082 break;
2083 case 1:
2084 post_index = true;
2085 writeback = true;
2086 break;
2087 case 3:
2088 post_index = false;
2089 writeback = true;
2090 break;
2093 if (rn == 31) {
2094 gen_check_sp_alignment(s);
2096 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2098 if (!post_index) {
2099 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
2102 if (is_vector) {
2103 if (is_store) {
2104 do_fp_st(s, rt, tcg_addr, size);
2105 } else {
2106 do_fp_ld(s, rt, tcg_addr, size);
2108 } else {
2109 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2110 int memidx = is_unpriv ? 1 : get_mem_index(s);
2112 if (is_store) {
2113 do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx);
2114 } else {
2115 do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
2116 is_signed, is_extended, memidx);
2120 if (writeback) {
2121 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2122 if (post_index) {
2123 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
2125 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2130 * C3.3.10 Load/store (register offset)
2132 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2133 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2134 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2135 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2137 * For non-vector:
2138 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2139 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2140 * For vector:
2141 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2142 * opc<0>: 0 -> store, 1 -> load
2143 * V: 1 -> vector/simd
2144 * opt: extend encoding (see DecodeRegExtend)
2145 * S: if S=1 then scale (essentially index by sizeof(size))
2146 * Rt: register to transfer into/out of
2147 * Rn: address register or SP for base
2148 * Rm: offset register or ZR for offset
2150 static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn)
2152 int rt = extract32(insn, 0, 5);
2153 int rn = extract32(insn, 5, 5);
2154 int shift = extract32(insn, 12, 1);
2155 int rm = extract32(insn, 16, 5);
2156 int opc = extract32(insn, 22, 2);
2157 int opt = extract32(insn, 13, 3);
2158 int size = extract32(insn, 30, 2);
2159 bool is_signed = false;
2160 bool is_store = false;
2161 bool is_extended = false;
2162 bool is_vector = extract32(insn, 26, 1);
2164 TCGv_i64 tcg_rm;
2165 TCGv_i64 tcg_addr;
2167 if (extract32(opt, 1, 1) == 0) {
2168 unallocated_encoding(s);
2169 return;
2172 if (is_vector) {
2173 size |= (opc & 2) << 1;
2174 if (size > 4) {
2175 unallocated_encoding(s);
2176 return;
2178 is_store = !extract32(opc, 0, 1);
2179 if (!fp_access_check(s)) {
2180 return;
2182 } else {
2183 if (size == 3 && opc == 2) {
2184 /* PRFM - prefetch */
2185 return;
2187 if (opc == 3 && size > 1) {
2188 unallocated_encoding(s);
2189 return;
2191 is_store = (opc == 0);
2192 is_signed = extract32(opc, 1, 1);
2193 is_extended = (size < 3) && extract32(opc, 0, 1);
2196 if (rn == 31) {
2197 gen_check_sp_alignment(s);
2199 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2201 tcg_rm = read_cpu_reg(s, rm, 1);
2202 ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
2204 tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm);
2206 if (is_vector) {
2207 if (is_store) {
2208 do_fp_st(s, rt, tcg_addr, size);
2209 } else {
2210 do_fp_ld(s, rt, tcg_addr, size);
2212 } else {
2213 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2214 if (is_store) {
2215 do_gpr_st(s, tcg_rt, tcg_addr, size);
2216 } else {
2217 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2223 * C3.3.13 Load/store (unsigned immediate)
2225 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2226 * +----+-------+---+-----+-----+------------+-------+------+
2227 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2228 * +----+-------+---+-----+-----+------------+-------+------+
2230 * For non-vector:
2231 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2232 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2233 * For vector:
2234 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2235 * opc<0>: 0 -> store, 1 -> load
2236 * Rn: base address register (inc SP)
2237 * Rt: target register
2239 static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn)
2241 int rt = extract32(insn, 0, 5);
2242 int rn = extract32(insn, 5, 5);
2243 unsigned int imm12 = extract32(insn, 10, 12);
2244 bool is_vector = extract32(insn, 26, 1);
2245 int size = extract32(insn, 30, 2);
2246 int opc = extract32(insn, 22, 2);
2247 unsigned int offset;
2249 TCGv_i64 tcg_addr;
2251 bool is_store;
2252 bool is_signed = false;
2253 bool is_extended = false;
2255 if (is_vector) {
2256 size |= (opc & 2) << 1;
2257 if (size > 4) {
2258 unallocated_encoding(s);
2259 return;
2261 is_store = !extract32(opc, 0, 1);
2262 if (!fp_access_check(s)) {
2263 return;
2265 } else {
2266 if (size == 3 && opc == 2) {
2267 /* PRFM - prefetch */
2268 return;
2270 if (opc == 3 && size > 1) {
2271 unallocated_encoding(s);
2272 return;
2274 is_store = (opc == 0);
2275 is_signed = extract32(opc, 1, 1);
2276 is_extended = (size < 3) && extract32(opc, 0, 1);
2279 if (rn == 31) {
2280 gen_check_sp_alignment(s);
2282 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2283 offset = imm12 << size;
2284 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
2286 if (is_vector) {
2287 if (is_store) {
2288 do_fp_st(s, rt, tcg_addr, size);
2289 } else {
2290 do_fp_ld(s, rt, tcg_addr, size);
2292 } else {
2293 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2294 if (is_store) {
2295 do_gpr_st(s, tcg_rt, tcg_addr, size);
2296 } else {
2297 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended);
2302 /* Load/store register (all forms) */
2303 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
2305 switch (extract32(insn, 24, 2)) {
2306 case 0:
2307 if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) {
2308 disas_ldst_reg_roffset(s, insn);
2309 } else {
2310 /* Load/store register (unscaled immediate)
2311 * Load/store immediate pre/post-indexed
2312 * Load/store register unprivileged
2314 disas_ldst_reg_imm9(s, insn);
2316 break;
2317 case 1:
2318 disas_ldst_reg_unsigned_imm(s, insn);
2319 break;
2320 default:
2321 unallocated_encoding(s);
2322 break;
2326 /* C3.3.1 AdvSIMD load/store multiple structures
2328 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2329 * +---+---+---------------+---+-------------+--------+------+------+------+
2330 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2331 * +---+---+---------------+---+-------------+--------+------+------+------+
2333 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2335 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2336 * +---+---+---------------+---+---+---------+--------+------+------+------+
2337 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2338 * +---+---+---------------+---+---+---------+--------+------+------+------+
2340 * Rt: first (or only) SIMD&FP register to be transferred
2341 * Rn: base address or SP
2342 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2344 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
2346 int rt = extract32(insn, 0, 5);
2347 int rn = extract32(insn, 5, 5);
2348 int size = extract32(insn, 10, 2);
2349 int opcode = extract32(insn, 12, 4);
2350 bool is_store = !extract32(insn, 22, 1);
2351 bool is_postidx = extract32(insn, 23, 1);
2352 bool is_q = extract32(insn, 30, 1);
2353 TCGv_i64 tcg_addr, tcg_rn;
2355 int ebytes = 1 << size;
2356 int elements = (is_q ? 128 : 64) / (8 << size);
2357 int rpt; /* num iterations */
2358 int selem; /* structure elements */
2359 int r;
2361 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) {
2362 unallocated_encoding(s);
2363 return;
2366 /* From the shared decode logic */
2367 switch (opcode) {
2368 case 0x0:
2369 rpt = 1;
2370 selem = 4;
2371 break;
2372 case 0x2:
2373 rpt = 4;
2374 selem = 1;
2375 break;
2376 case 0x4:
2377 rpt = 1;
2378 selem = 3;
2379 break;
2380 case 0x6:
2381 rpt = 3;
2382 selem = 1;
2383 break;
2384 case 0x7:
2385 rpt = 1;
2386 selem = 1;
2387 break;
2388 case 0x8:
2389 rpt = 1;
2390 selem = 2;
2391 break;
2392 case 0xa:
2393 rpt = 2;
2394 selem = 1;
2395 break;
2396 default:
2397 unallocated_encoding(s);
2398 return;
2401 if (size == 3 && !is_q && selem != 1) {
2402 /* reserved */
2403 unallocated_encoding(s);
2404 return;
2407 if (!fp_access_check(s)) {
2408 return;
2411 if (rn == 31) {
2412 gen_check_sp_alignment(s);
2415 tcg_rn = cpu_reg_sp(s, rn);
2416 tcg_addr = tcg_temp_new_i64();
2417 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2419 for (r = 0; r < rpt; r++) {
2420 int e;
2421 for (e = 0; e < elements; e++) {
2422 int tt = (rt + r) % 32;
2423 int xs;
2424 for (xs = 0; xs < selem; xs++) {
2425 if (is_store) {
2426 do_vec_st(s, tt, e, tcg_addr, size);
2427 } else {
2428 do_vec_ld(s, tt, e, tcg_addr, size);
2430 /* For non-quad operations, setting a slice of the low
2431 * 64 bits of the register clears the high 64 bits (in
2432 * the ARM ARM pseudocode this is implicit in the fact
2433 * that 'rval' is a 64 bit wide variable). We optimize
2434 * by noticing that we only need to do this the first
2435 * time we touch a register.
2437 if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) {
2438 clear_vec_high(s, tt);
2441 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2442 tt = (tt + 1) % 32;
2447 if (is_postidx) {
2448 int rm = extract32(insn, 16, 5);
2449 if (rm == 31) {
2450 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2451 } else {
2452 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2455 tcg_temp_free_i64(tcg_addr);
2458 /* C3.3.3 AdvSIMD load/store single structure
2460 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2461 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2462 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2463 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2465 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2467 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2468 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2469 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2470 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2472 * Rt: first (or only) SIMD&FP register to be transferred
2473 * Rn: base address or SP
2474 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2475 * index = encoded in Q:S:size dependent on size
2477 * lane_size = encoded in R, opc
2478 * transfer width = encoded in opc, S, size
2480 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
2482 int rt = extract32(insn, 0, 5);
2483 int rn = extract32(insn, 5, 5);
2484 int size = extract32(insn, 10, 2);
2485 int S = extract32(insn, 12, 1);
2486 int opc = extract32(insn, 13, 3);
2487 int R = extract32(insn, 21, 1);
2488 int is_load = extract32(insn, 22, 1);
2489 int is_postidx = extract32(insn, 23, 1);
2490 int is_q = extract32(insn, 30, 1);
2492 int scale = extract32(opc, 1, 2);
2493 int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
2494 bool replicate = false;
2495 int index = is_q << 3 | S << 2 | size;
2496 int ebytes, xs;
2497 TCGv_i64 tcg_addr, tcg_rn;
2499 switch (scale) {
2500 case 3:
2501 if (!is_load || S) {
2502 unallocated_encoding(s);
2503 return;
2505 scale = size;
2506 replicate = true;
2507 break;
2508 case 0:
2509 break;
2510 case 1:
2511 if (extract32(size, 0, 1)) {
2512 unallocated_encoding(s);
2513 return;
2515 index >>= 1;
2516 break;
2517 case 2:
2518 if (extract32(size, 1, 1)) {
2519 unallocated_encoding(s);
2520 return;
2522 if (!extract32(size, 0, 1)) {
2523 index >>= 2;
2524 } else {
2525 if (S) {
2526 unallocated_encoding(s);
2527 return;
2529 index >>= 3;
2530 scale = 3;
2532 break;
2533 default:
2534 g_assert_not_reached();
2537 if (!fp_access_check(s)) {
2538 return;
2541 ebytes = 1 << scale;
2543 if (rn == 31) {
2544 gen_check_sp_alignment(s);
2547 tcg_rn = cpu_reg_sp(s, rn);
2548 tcg_addr = tcg_temp_new_i64();
2549 tcg_gen_mov_i64(tcg_addr, tcg_rn);
2551 for (xs = 0; xs < selem; xs++) {
2552 if (replicate) {
2553 /* Load and replicate to all elements */
2554 uint64_t mulconst;
2555 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
2557 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
2558 get_mem_index(s), MO_TE + scale);
2559 switch (scale) {
2560 case 0:
2561 mulconst = 0x0101010101010101ULL;
2562 break;
2563 case 1:
2564 mulconst = 0x0001000100010001ULL;
2565 break;
2566 case 2:
2567 mulconst = 0x0000000100000001ULL;
2568 break;
2569 case 3:
2570 mulconst = 0;
2571 break;
2572 default:
2573 g_assert_not_reached();
2575 if (mulconst) {
2576 tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
2578 write_vec_element(s, tcg_tmp, rt, 0, MO_64);
2579 if (is_q) {
2580 write_vec_element(s, tcg_tmp, rt, 1, MO_64);
2581 } else {
2582 clear_vec_high(s, rt);
2584 tcg_temp_free_i64(tcg_tmp);
2585 } else {
2586 /* Load/store one element per register */
2587 if (is_load) {
2588 do_vec_ld(s, rt, index, tcg_addr, MO_TE + scale);
2589 } else {
2590 do_vec_st(s, rt, index, tcg_addr, MO_TE + scale);
2593 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
2594 rt = (rt + 1) % 32;
2597 if (is_postidx) {
2598 int rm = extract32(insn, 16, 5);
2599 if (rm == 31) {
2600 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2601 } else {
2602 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
2605 tcg_temp_free_i64(tcg_addr);
2608 /* C3.3 Loads and stores */
2609 static void disas_ldst(DisasContext *s, uint32_t insn)
2611 switch (extract32(insn, 24, 6)) {
2612 case 0x08: /* Load/store exclusive */
2613 disas_ldst_excl(s, insn);
2614 break;
2615 case 0x18: case 0x1c: /* Load register (literal) */
2616 disas_ld_lit(s, insn);
2617 break;
2618 case 0x28: case 0x29:
2619 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2620 disas_ldst_pair(s, insn);
2621 break;
2622 case 0x38: case 0x39:
2623 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2624 disas_ldst_reg(s, insn);
2625 break;
2626 case 0x0c: /* AdvSIMD load/store multiple structures */
2627 disas_ldst_multiple_struct(s, insn);
2628 break;
2629 case 0x0d: /* AdvSIMD load/store single structure */
2630 disas_ldst_single_struct(s, insn);
2631 break;
2632 default:
2633 unallocated_encoding(s);
2634 break;
2638 /* C3.4.6 PC-rel. addressing
2639 * 31 30 29 28 24 23 5 4 0
2640 * +----+-------+-----------+-------------------+------+
2641 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2642 * +----+-------+-----------+-------------------+------+
2644 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
2646 unsigned int page, rd;
2647 uint64_t base;
2648 int64_t offset;
2650 page = extract32(insn, 31, 1);
2651 /* SignExtend(immhi:immlo) -> offset */
2652 offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);
2653 rd = extract32(insn, 0, 5);
2654 base = s->pc - 4;
2656 if (page) {
2657 /* ADRP (page based) */
2658 base &= ~0xfff;
2659 offset <<= 12;
2662 tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
2666 * C3.4.1 Add/subtract (immediate)
2668 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2669 * +--+--+--+-----------+-----+-------------+-----+-----+
2670 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2671 * +--+--+--+-----------+-----+-------------+-----+-----+
2673 * sf: 0 -> 32bit, 1 -> 64bit
2674 * op: 0 -> add , 1 -> sub
2675 * S: 1 -> set flags
2676 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2678 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
2680 int rd = extract32(insn, 0, 5);
2681 int rn = extract32(insn, 5, 5);
2682 uint64_t imm = extract32(insn, 10, 12);
2683 int shift = extract32(insn, 22, 2);
2684 bool setflags = extract32(insn, 29, 1);
2685 bool sub_op = extract32(insn, 30, 1);
2686 bool is_64bit = extract32(insn, 31, 1);
2688 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2689 TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
2690 TCGv_i64 tcg_result;
2692 switch (shift) {
2693 case 0x0:
2694 break;
2695 case 0x1:
2696 imm <<= 12;
2697 break;
2698 default:
2699 unallocated_encoding(s);
2700 return;
2703 tcg_result = tcg_temp_new_i64();
2704 if (!setflags) {
2705 if (sub_op) {
2706 tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
2707 } else {
2708 tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
2710 } else {
2711 TCGv_i64 tcg_imm = tcg_const_i64(imm);
2712 if (sub_op) {
2713 gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2714 } else {
2715 gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
2717 tcg_temp_free_i64(tcg_imm);
2720 if (is_64bit) {
2721 tcg_gen_mov_i64(tcg_rd, tcg_result);
2722 } else {
2723 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
2726 tcg_temp_free_i64(tcg_result);
2729 /* The input should be a value in the bottom e bits (with higher
2730 * bits zero); returns that value replicated into every element
2731 * of size e in a 64 bit integer.
2733 static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
2735 assert(e != 0);
2736 while (e < 64) {
2737 mask |= mask << e;
2738 e *= 2;
2740 return mask;
2743 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2744 static inline uint64_t bitmask64(unsigned int length)
2746 assert(length > 0 && length <= 64);
2747 return ~0ULL >> (64 - length);
2750 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2751 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2752 * value (ie should cause a guest UNDEF exception), and true if they are
2753 * valid, in which case the decoded bit pattern is written to result.
2755 static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
2756 unsigned int imms, unsigned int immr)
2758 uint64_t mask;
2759 unsigned e, levels, s, r;
2760 int len;
2762 assert(immn < 2 && imms < 64 && immr < 64);
2764 /* The bit patterns we create here are 64 bit patterns which
2765 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2766 * 64 bits each. Each element contains the same value: a run
2767 * of between 1 and e-1 non-zero bits, rotated within the
2768 * element by between 0 and e-1 bits.
2770 * The element size and run length are encoded into immn (1 bit)
2771 * and imms (6 bits) as follows:
2772 * 64 bit elements: immn = 1, imms = <length of run - 1>
2773 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2774 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2775 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2776 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2777 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2778 * Notice that immn = 0, imms = 11111x is the only combination
2779 * not covered by one of the above options; this is reserved.
2780 * Further, <length of run - 1> all-ones is a reserved pattern.
2782 * In all cases the rotation is by immr % e (and immr is 6 bits).
2785 /* First determine the element size */
2786 len = 31 - clz32((immn << 6) | (~imms & 0x3f));
2787 if (len < 1) {
2788 /* This is the immn == 0, imms == 0x11111x case */
2789 return false;
2791 e = 1 << len;
2793 levels = e - 1;
2794 s = imms & levels;
2795 r = immr & levels;
2797 if (s == levels) {
2798 /* <length of run - 1> mustn't be all-ones. */
2799 return false;
2802 /* Create the value of one element: s+1 set bits rotated
2803 * by r within the element (which is e bits wide)...
2805 mask = bitmask64(s + 1);
2806 mask = (mask >> r) | (mask << (e - r));
2807 /* ...then replicate the element over the whole 64 bit value */
2808 mask = bitfield_replicate(mask, e);
2809 *result = mask;
2810 return true;
2813 /* C3.4.4 Logical (immediate)
2814 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2815 * +----+-----+-------------+---+------+------+------+------+
2816 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2817 * +----+-----+-------------+---+------+------+------+------+
2819 static void disas_logic_imm(DisasContext *s, uint32_t insn)
2821 unsigned int sf, opc, is_n, immr, imms, rn, rd;
2822 TCGv_i64 tcg_rd, tcg_rn;
2823 uint64_t wmask;
2824 bool is_and = false;
2826 sf = extract32(insn, 31, 1);
2827 opc = extract32(insn, 29, 2);
2828 is_n = extract32(insn, 22, 1);
2829 immr = extract32(insn, 16, 6);
2830 imms = extract32(insn, 10, 6);
2831 rn = extract32(insn, 5, 5);
2832 rd = extract32(insn, 0, 5);
2834 if (!sf && is_n) {
2835 unallocated_encoding(s);
2836 return;
2839 if (opc == 0x3) { /* ANDS */
2840 tcg_rd = cpu_reg(s, rd);
2841 } else {
2842 tcg_rd = cpu_reg_sp(s, rd);
2844 tcg_rn = cpu_reg(s, rn);
2846 if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
2847 /* some immediate field values are reserved */
2848 unallocated_encoding(s);
2849 return;
2852 if (!sf) {
2853 wmask &= 0xffffffff;
2856 switch (opc) {
2857 case 0x3: /* ANDS */
2858 case 0x0: /* AND */
2859 tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
2860 is_and = true;
2861 break;
2862 case 0x1: /* ORR */
2863 tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
2864 break;
2865 case 0x2: /* EOR */
2866 tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
2867 break;
2868 default:
2869 assert(FALSE); /* must handle all above */
2870 break;
2873 if (!sf && !is_and) {
2874 /* zero extend final result; we know we can skip this for AND
2875 * since the immediate had the high 32 bits clear.
2877 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2880 if (opc == 3) { /* ANDS */
2881 gen_logic_CC(sf, tcg_rd);
2886 * C3.4.5 Move wide (immediate)
2888 * 31 30 29 28 23 22 21 20 5 4 0
2889 * +--+-----+-------------+-----+----------------+------+
2890 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2891 * +--+-----+-------------+-----+----------------+------+
2893 * sf: 0 -> 32 bit, 1 -> 64 bit
2894 * opc: 00 -> N, 10 -> Z, 11 -> K
2895 * hw: shift/16 (0,16, and sf only 32, 48)
2897 static void disas_movw_imm(DisasContext *s, uint32_t insn)
2899 int rd = extract32(insn, 0, 5);
2900 uint64_t imm = extract32(insn, 5, 16);
2901 int sf = extract32(insn, 31, 1);
2902 int opc = extract32(insn, 29, 2);
2903 int pos = extract32(insn, 21, 2) << 4;
2904 TCGv_i64 tcg_rd = cpu_reg(s, rd);
2905 TCGv_i64 tcg_imm;
2907 if (!sf && (pos >= 32)) {
2908 unallocated_encoding(s);
2909 return;
2912 switch (opc) {
2913 case 0: /* MOVN */
2914 case 2: /* MOVZ */
2915 imm <<= pos;
2916 if (opc == 0) {
2917 imm = ~imm;
2919 if (!sf) {
2920 imm &= 0xffffffffu;
2922 tcg_gen_movi_i64(tcg_rd, imm);
2923 break;
2924 case 3: /* MOVK */
2925 tcg_imm = tcg_const_i64(imm);
2926 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
2927 tcg_temp_free_i64(tcg_imm);
2928 if (!sf) {
2929 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2931 break;
2932 default:
2933 unallocated_encoding(s);
2934 break;
2938 /* C3.4.2 Bitfield
2939 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2940 * +----+-----+-------------+---+------+------+------+------+
2941 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2942 * +----+-----+-------------+---+------+------+------+------+
2944 static void disas_bitfield(DisasContext *s, uint32_t insn)
2946 unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
2947 TCGv_i64 tcg_rd, tcg_tmp;
2949 sf = extract32(insn, 31, 1);
2950 opc = extract32(insn, 29, 2);
2951 n = extract32(insn, 22, 1);
2952 ri = extract32(insn, 16, 6);
2953 si = extract32(insn, 10, 6);
2954 rn = extract32(insn, 5, 5);
2955 rd = extract32(insn, 0, 5);
2956 bitsize = sf ? 64 : 32;
2958 if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
2959 unallocated_encoding(s);
2960 return;
2963 tcg_rd = cpu_reg(s, rd);
2964 tcg_tmp = read_cpu_reg(s, rn, sf);
2966 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2968 if (opc != 1) { /* SBFM or UBFM */
2969 tcg_gen_movi_i64(tcg_rd, 0);
2972 /* do the bit move operation */
2973 if (si >= ri) {
2974 /* Wd<s-r:0> = Wn<s:r> */
2975 tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
2976 pos = 0;
2977 len = (si - ri) + 1;
2978 } else {
2979 /* Wd<32+s-r,32-r> = Wn<s:0> */
2980 pos = bitsize - ri;
2981 len = si + 1;
2984 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
2986 if (opc == 0) { /* SBFM - sign extend the destination field */
2987 tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
2988 tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
2991 if (!sf) { /* zero extend final result */
2992 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
2996 /* C3.4.3 Extract
2997 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2998 * +----+------+-------------+---+----+------+--------+------+------+
2999 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3000 * +----+------+-------------+---+----+------+--------+------+------+
3002 static void disas_extract(DisasContext *s, uint32_t insn)
3004 unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
3006 sf = extract32(insn, 31, 1);
3007 n = extract32(insn, 22, 1);
3008 rm = extract32(insn, 16, 5);
3009 imm = extract32(insn, 10, 6);
3010 rn = extract32(insn, 5, 5);
3011 rd = extract32(insn, 0, 5);
3012 op21 = extract32(insn, 29, 2);
3013 op0 = extract32(insn, 21, 1);
3014 bitsize = sf ? 64 : 32;
3016 if (sf != n || op21 || op0 || imm >= bitsize) {
3017 unallocated_encoding(s);
3018 } else {
3019 TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
3021 tcg_rd = cpu_reg(s, rd);
3023 if (imm) {
3024 /* OPTME: we can special case rm==rn as a rotate */
3025 tcg_rm = read_cpu_reg(s, rm, sf);
3026 tcg_rn = read_cpu_reg(s, rn, sf);
3027 tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
3028 tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
3029 tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
3030 if (!sf) {
3031 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3033 } else {
3034 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3035 * so an extract from bit 0 is a special case.
3037 if (sf) {
3038 tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
3039 } else {
3040 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
3047 /* C3.4 Data processing - immediate */
3048 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
3050 switch (extract32(insn, 23, 6)) {
3051 case 0x20: case 0x21: /* PC-rel. addressing */
3052 disas_pc_rel_adr(s, insn);
3053 break;
3054 case 0x22: case 0x23: /* Add/subtract (immediate) */
3055 disas_add_sub_imm(s, insn);
3056 break;
3057 case 0x24: /* Logical (immediate) */
3058 disas_logic_imm(s, insn);
3059 break;
3060 case 0x25: /* Move wide (immediate) */
3061 disas_movw_imm(s, insn);
3062 break;
3063 case 0x26: /* Bitfield */
3064 disas_bitfield(s, insn);
3065 break;
3066 case 0x27: /* Extract */
3067 disas_extract(s, insn);
3068 break;
3069 default:
3070 unallocated_encoding(s);
3071 break;
3075 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3076 * Note that it is the caller's responsibility to ensure that the
3077 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3078 * mandated semantics for out of range shifts.
3080 static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,
3081 enum a64_shift_type shift_type, TCGv_i64 shift_amount)
3083 switch (shift_type) {
3084 case A64_SHIFT_TYPE_LSL:
3085 tcg_gen_shl_i64(dst, src, shift_amount);
3086 break;
3087 case A64_SHIFT_TYPE_LSR:
3088 tcg_gen_shr_i64(dst, src, shift_amount);
3089 break;
3090 case A64_SHIFT_TYPE_ASR:
3091 if (!sf) {
3092 tcg_gen_ext32s_i64(dst, src);
3094 tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);
3095 break;
3096 case A64_SHIFT_TYPE_ROR:
3097 if (sf) {
3098 tcg_gen_rotr_i64(dst, src, shift_amount);
3099 } else {
3100 TCGv_i32 t0, t1;
3101 t0 = tcg_temp_new_i32();
3102 t1 = tcg_temp_new_i32();
3103 tcg_gen_trunc_i64_i32(t0, src);
3104 tcg_gen_trunc_i64_i32(t1, shift_amount);
3105 tcg_gen_rotr_i32(t0, t0, t1);
3106 tcg_gen_extu_i32_i64(dst, t0);
3107 tcg_temp_free_i32(t0);
3108 tcg_temp_free_i32(t1);
3110 break;
3111 default:
3112 assert(FALSE); /* all shift types should be handled */
3113 break;
3116 if (!sf) { /* zero extend final result */
3117 tcg_gen_ext32u_i64(dst, dst);
3121 /* Shift a TCGv src by immediate, put result in dst.
3122 * The shift amount must be in range (this should always be true as the
3123 * relevant instructions will UNDEF on bad shift immediates).
3125 static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
3126 enum a64_shift_type shift_type, unsigned int shift_i)
3128 assert(shift_i < (sf ? 64 : 32));
3130 if (shift_i == 0) {
3131 tcg_gen_mov_i64(dst, src);
3132 } else {
3133 TCGv_i64 shift_const;
3135 shift_const = tcg_const_i64(shift_i);
3136 shift_reg(dst, src, sf, shift_type, shift_const);
3137 tcg_temp_free_i64(shift_const);
3141 /* C3.5.10 Logical (shifted register)
3142 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3143 * +----+-----+-----------+-------+---+------+--------+------+------+
3144 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3145 * +----+-----+-----------+-------+---+------+--------+------+------+
3147 static void disas_logic_reg(DisasContext *s, uint32_t insn)
3149 TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
3150 unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
3152 sf = extract32(insn, 31, 1);
3153 opc = extract32(insn, 29, 2);
3154 shift_type = extract32(insn, 22, 2);
3155 invert = extract32(insn, 21, 1);
3156 rm = extract32(insn, 16, 5);
3157 shift_amount = extract32(insn, 10, 6);
3158 rn = extract32(insn, 5, 5);
3159 rd = extract32(insn, 0, 5);
3161 if (!sf && (shift_amount & (1 << 5))) {
3162 unallocated_encoding(s);
3163 return;
3166 tcg_rd = cpu_reg(s, rd);
3168 if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
3169 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3170 * register-register MOV and MVN, so it is worth special casing.
3172 tcg_rm = cpu_reg(s, rm);
3173 if (invert) {
3174 tcg_gen_not_i64(tcg_rd, tcg_rm);
3175 if (!sf) {
3176 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3178 } else {
3179 if (sf) {
3180 tcg_gen_mov_i64(tcg_rd, tcg_rm);
3181 } else {
3182 tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
3185 return;
3188 tcg_rm = read_cpu_reg(s, rm, sf);
3190 if (shift_amount) {
3191 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
3194 tcg_rn = cpu_reg(s, rn);
3196 switch (opc | (invert << 2)) {
3197 case 0: /* AND */
3198 case 3: /* ANDS */
3199 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
3200 break;
3201 case 1: /* ORR */
3202 tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
3203 break;
3204 case 2: /* EOR */
3205 tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
3206 break;
3207 case 4: /* BIC */
3208 case 7: /* BICS */
3209 tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
3210 break;
3211 case 5: /* ORN */
3212 tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
3213 break;
3214 case 6: /* EON */
3215 tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
3216 break;
3217 default:
3218 assert(FALSE);
3219 break;
3222 if (!sf) {
3223 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3226 if (opc == 3) {
3227 gen_logic_CC(sf, tcg_rd);
3232 * C3.5.1 Add/subtract (extended register)
3234 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3235 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3236 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3237 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3239 * sf: 0 -> 32bit, 1 -> 64bit
3240 * op: 0 -> add , 1 -> sub
3241 * S: 1 -> set flags
3242 * opt: 00
3243 * option: extension type (see DecodeRegExtend)
3244 * imm3: optional shift to Rm
3246 * Rd = Rn + LSL(extend(Rm), amount)
3248 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
3250 int rd = extract32(insn, 0, 5);
3251 int rn = extract32(insn, 5, 5);
3252 int imm3 = extract32(insn, 10, 3);
3253 int option = extract32(insn, 13, 3);
3254 int rm = extract32(insn, 16, 5);
3255 bool setflags = extract32(insn, 29, 1);
3256 bool sub_op = extract32(insn, 30, 1);
3257 bool sf = extract32(insn, 31, 1);
3259 TCGv_i64 tcg_rm, tcg_rn; /* temps */
3260 TCGv_i64 tcg_rd;
3261 TCGv_i64 tcg_result;
3263 if (imm3 > 4) {
3264 unallocated_encoding(s);
3265 return;
3268 /* non-flag setting ops may use SP */
3269 if (!setflags) {
3270 tcg_rd = cpu_reg_sp(s, rd);
3271 } else {
3272 tcg_rd = cpu_reg(s, rd);
3274 tcg_rn = read_cpu_reg_sp(s, rn, sf);
3276 tcg_rm = read_cpu_reg(s, rm, sf);
3277 ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
3279 tcg_result = tcg_temp_new_i64();
3281 if (!setflags) {
3282 if (sub_op) {
3283 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3284 } else {
3285 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3287 } else {
3288 if (sub_op) {
3289 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3290 } else {
3291 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3295 if (sf) {
3296 tcg_gen_mov_i64(tcg_rd, tcg_result);
3297 } else {
3298 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3301 tcg_temp_free_i64(tcg_result);
3305 * C3.5.2 Add/subtract (shifted register)
3307 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3308 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3309 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3310 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3312 * sf: 0 -> 32bit, 1 -> 64bit
3313 * op: 0 -> add , 1 -> sub
3314 * S: 1 -> set flags
3315 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3316 * imm6: Shift amount to apply to Rm before the add/sub
3318 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
3320 int rd = extract32(insn, 0, 5);
3321 int rn = extract32(insn, 5, 5);
3322 int imm6 = extract32(insn, 10, 6);
3323 int rm = extract32(insn, 16, 5);
3324 int shift_type = extract32(insn, 22, 2);
3325 bool setflags = extract32(insn, 29, 1);
3326 bool sub_op = extract32(insn, 30, 1);
3327 bool sf = extract32(insn, 31, 1);
3329 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3330 TCGv_i64 tcg_rn, tcg_rm;
3331 TCGv_i64 tcg_result;
3333 if ((shift_type == 3) || (!sf && (imm6 > 31))) {
3334 unallocated_encoding(s);
3335 return;
3338 tcg_rn = read_cpu_reg(s, rn, sf);
3339 tcg_rm = read_cpu_reg(s, rm, sf);
3341 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
3343 tcg_result = tcg_temp_new_i64();
3345 if (!setflags) {
3346 if (sub_op) {
3347 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3348 } else {
3349 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3351 } else {
3352 if (sub_op) {
3353 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3354 } else {
3355 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3359 if (sf) {
3360 tcg_gen_mov_i64(tcg_rd, tcg_result);
3361 } else {
3362 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3365 tcg_temp_free_i64(tcg_result);
3368 /* C3.5.9 Data-processing (3 source)
3370 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3371 +--+------+-----------+------+------+----+------+------+------+
3372 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3373 +--+------+-----------+------+------+----+------+------+------+
3376 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
3378 int rd = extract32(insn, 0, 5);
3379 int rn = extract32(insn, 5, 5);
3380 int ra = extract32(insn, 10, 5);
3381 int rm = extract32(insn, 16, 5);
3382 int op_id = (extract32(insn, 29, 3) << 4) |
3383 (extract32(insn, 21, 3) << 1) |
3384 extract32(insn, 15, 1);
3385 bool sf = extract32(insn, 31, 1);
3386 bool is_sub = extract32(op_id, 0, 1);
3387 bool is_high = extract32(op_id, 2, 1);
3388 bool is_signed = false;
3389 TCGv_i64 tcg_op1;
3390 TCGv_i64 tcg_op2;
3391 TCGv_i64 tcg_tmp;
3393 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3394 switch (op_id) {
3395 case 0x42: /* SMADDL */
3396 case 0x43: /* SMSUBL */
3397 case 0x44: /* SMULH */
3398 is_signed = true;
3399 break;
3400 case 0x0: /* MADD (32bit) */
3401 case 0x1: /* MSUB (32bit) */
3402 case 0x40: /* MADD (64bit) */
3403 case 0x41: /* MSUB (64bit) */
3404 case 0x4a: /* UMADDL */
3405 case 0x4b: /* UMSUBL */
3406 case 0x4c: /* UMULH */
3407 break;
3408 default:
3409 unallocated_encoding(s);
3410 return;
3413 if (is_high) {
3414 TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
3415 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3416 TCGv_i64 tcg_rn = cpu_reg(s, rn);
3417 TCGv_i64 tcg_rm = cpu_reg(s, rm);
3419 if (is_signed) {
3420 tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
3421 } else {
3422 tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
3425 tcg_temp_free_i64(low_bits);
3426 return;
3429 tcg_op1 = tcg_temp_new_i64();
3430 tcg_op2 = tcg_temp_new_i64();
3431 tcg_tmp = tcg_temp_new_i64();
3433 if (op_id < 0x42) {
3434 tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn));
3435 tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm));
3436 } else {
3437 if (is_signed) {
3438 tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn));
3439 tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm));
3440 } else {
3441 tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn));
3442 tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm));
3446 if (ra == 31 && !is_sub) {
3447 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3448 tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2);
3449 } else {
3450 tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
3451 if (is_sub) {
3452 tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
3453 } else {
3454 tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
3458 if (!sf) {
3459 tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd));
3462 tcg_temp_free_i64(tcg_op1);
3463 tcg_temp_free_i64(tcg_op2);
3464 tcg_temp_free_i64(tcg_tmp);
3467 /* C3.5.3 - Add/subtract (with carry)
3468 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3469 * +--+--+--+------------------------+------+---------+------+-----+
3470 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3471 * +--+--+--+------------------------+------+---------+------+-----+
3472 * [000000]
3475 static void disas_adc_sbc(DisasContext *s, uint32_t insn)
3477 unsigned int sf, op, setflags, rm, rn, rd;
3478 TCGv_i64 tcg_y, tcg_rn, tcg_rd;
3480 if (extract32(insn, 10, 6) != 0) {
3481 unallocated_encoding(s);
3482 return;
3485 sf = extract32(insn, 31, 1);
3486 op = extract32(insn, 30, 1);
3487 setflags = extract32(insn, 29, 1);
3488 rm = extract32(insn, 16, 5);
3489 rn = extract32(insn, 5, 5);
3490 rd = extract32(insn, 0, 5);
3492 tcg_rd = cpu_reg(s, rd);
3493 tcg_rn = cpu_reg(s, rn);
3495 if (op) {
3496 tcg_y = new_tmp_a64(s);
3497 tcg_gen_not_i64(tcg_y, cpu_reg(s, rm));
3498 } else {
3499 tcg_y = cpu_reg(s, rm);
3502 if (setflags) {
3503 gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y);
3504 } else {
3505 gen_adc(sf, tcg_rd, tcg_rn, tcg_y);
3509 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3510 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3511 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3512 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3513 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3514 * [1] y [0] [0]
3516 static void disas_cc(DisasContext *s, uint32_t insn)
3518 unsigned int sf, op, y, cond, rn, nzcv, is_imm;
3519 int label_continue = -1;
3520 TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
3522 if (!extract32(insn, 29, 1)) {
3523 unallocated_encoding(s);
3524 return;
3526 if (insn & (1 << 10 | 1 << 4)) {
3527 unallocated_encoding(s);
3528 return;
3530 sf = extract32(insn, 31, 1);
3531 op = extract32(insn, 30, 1);
3532 is_imm = extract32(insn, 11, 1);
3533 y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
3534 cond = extract32(insn, 12, 4);
3535 rn = extract32(insn, 5, 5);
3536 nzcv = extract32(insn, 0, 4);
3538 if (cond < 0x0e) { /* not always */
3539 int label_match = gen_new_label();
3540 label_continue = gen_new_label();
3541 arm_gen_test_cc(cond, label_match);
3542 /* nomatch: */
3543 tcg_tmp = tcg_temp_new_i64();
3544 tcg_gen_movi_i64(tcg_tmp, nzcv << 28);
3545 gen_set_nzcv(tcg_tmp);
3546 tcg_temp_free_i64(tcg_tmp);
3547 tcg_gen_br(label_continue);
3548 gen_set_label(label_match);
3550 /* match, or condition is always */
3551 if (is_imm) {
3552 tcg_y = new_tmp_a64(s);
3553 tcg_gen_movi_i64(tcg_y, y);
3554 } else {
3555 tcg_y = cpu_reg(s, y);
3557 tcg_rn = cpu_reg(s, rn);
3559 tcg_tmp = tcg_temp_new_i64();
3560 if (op) {
3561 gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
3562 } else {
3563 gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
3565 tcg_temp_free_i64(tcg_tmp);
3567 if (cond < 0x0e) { /* continue */
3568 gen_set_label(label_continue);
3572 /* C3.5.6 Conditional select
3573 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3574 * +----+----+---+-----------------+------+------+-----+------+------+
3575 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3576 * +----+----+---+-----------------+------+------+-----+------+------+
3578 static void disas_cond_select(DisasContext *s, uint32_t insn)
3580 unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
3581 TCGv_i64 tcg_rd, tcg_src;
3583 if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
3584 /* S == 1 or op2<1> == 1 */
3585 unallocated_encoding(s);
3586 return;
3588 sf = extract32(insn, 31, 1);
3589 else_inv = extract32(insn, 30, 1);
3590 rm = extract32(insn, 16, 5);
3591 cond = extract32(insn, 12, 4);
3592 else_inc = extract32(insn, 10, 1);
3593 rn = extract32(insn, 5, 5);
3594 rd = extract32(insn, 0, 5);
3596 if (rd == 31) {
3597 /* silly no-op write; until we use movcond we must special-case
3598 * this to avoid a dead temporary across basic blocks.
3600 return;
3603 tcg_rd = cpu_reg(s, rd);
3605 if (cond >= 0x0e) { /* condition "always" */
3606 tcg_src = read_cpu_reg(s, rn, sf);
3607 tcg_gen_mov_i64(tcg_rd, tcg_src);
3608 } else {
3609 /* OPTME: we could use movcond here, at the cost of duplicating
3610 * a lot of the arm_gen_test_cc() logic.
3612 int label_match = gen_new_label();
3613 int label_continue = gen_new_label();
3615 arm_gen_test_cc(cond, label_match);
3616 /* nomatch: */
3617 tcg_src = cpu_reg(s, rm);
3619 if (else_inv && else_inc) {
3620 tcg_gen_neg_i64(tcg_rd, tcg_src);
3621 } else if (else_inv) {
3622 tcg_gen_not_i64(tcg_rd, tcg_src);
3623 } else if (else_inc) {
3624 tcg_gen_addi_i64(tcg_rd, tcg_src, 1);
3625 } else {
3626 tcg_gen_mov_i64(tcg_rd, tcg_src);
3628 if (!sf) {
3629 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3631 tcg_gen_br(label_continue);
3632 /* match: */
3633 gen_set_label(label_match);
3634 tcg_src = read_cpu_reg(s, rn, sf);
3635 tcg_gen_mov_i64(tcg_rd, tcg_src);
3636 /* continue: */
3637 gen_set_label(label_continue);
3641 static void handle_clz(DisasContext *s, unsigned int sf,
3642 unsigned int rn, unsigned int rd)
3644 TCGv_i64 tcg_rd, tcg_rn;
3645 tcg_rd = cpu_reg(s, rd);
3646 tcg_rn = cpu_reg(s, rn);
3648 if (sf) {
3649 gen_helper_clz64(tcg_rd, tcg_rn);
3650 } else {
3651 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
3652 tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn);
3653 gen_helper_clz(tcg_tmp32, tcg_tmp32);
3654 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
3655 tcg_temp_free_i32(tcg_tmp32);
3659 static void handle_cls(DisasContext *s, unsigned int sf,
3660 unsigned int rn, unsigned int rd)
3662 TCGv_i64 tcg_rd, tcg_rn;
3663 tcg_rd = cpu_reg(s, rd);
3664 tcg_rn = cpu_reg(s, rn);
3666 if (sf) {
3667 gen_helper_cls64(tcg_rd, tcg_rn);
3668 } else {
3669 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
3670 tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn);
3671 gen_helper_cls32(tcg_tmp32, tcg_tmp32);
3672 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
3673 tcg_temp_free_i32(tcg_tmp32);
3677 static void handle_rbit(DisasContext *s, unsigned int sf,
3678 unsigned int rn, unsigned int rd)
3680 TCGv_i64 tcg_rd, tcg_rn;
3681 tcg_rd = cpu_reg(s, rd);
3682 tcg_rn = cpu_reg(s, rn);
3684 if (sf) {
3685 gen_helper_rbit64(tcg_rd, tcg_rn);
3686 } else {
3687 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
3688 tcg_gen_trunc_i64_i32(tcg_tmp32, tcg_rn);
3689 gen_helper_rbit(tcg_tmp32, tcg_tmp32);
3690 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
3691 tcg_temp_free_i32(tcg_tmp32);
3695 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3696 static void handle_rev64(DisasContext *s, unsigned int sf,
3697 unsigned int rn, unsigned int rd)
3699 if (!sf) {
3700 unallocated_encoding(s);
3701 return;
3703 tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
3706 /* C5.6.149 REV with sf==0, opcode==2
3707 * C5.6.151 REV32 (sf==1, opcode==2)
3709 static void handle_rev32(DisasContext *s, unsigned int sf,
3710 unsigned int rn, unsigned int rd)
3712 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3714 if (sf) {
3715 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
3716 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
3718 /* bswap32_i64 requires zero high word */
3719 tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
3720 tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
3721 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
3722 tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
3723 tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
3725 tcg_temp_free_i64(tcg_tmp);
3726 } else {
3727 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
3728 tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
3732 /* C5.6.150 REV16 (opcode==1) */
3733 static void handle_rev16(DisasContext *s, unsigned int sf,
3734 unsigned int rn, unsigned int rd)
3736 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3737 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
3738 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
3740 tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
3741 tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
3743 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
3744 tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
3745 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
3746 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
3748 if (sf) {
3749 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
3750 tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
3751 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
3752 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
3754 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
3755 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
3756 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16);
3759 tcg_temp_free_i64(tcg_tmp);
3762 /* C3.5.7 Data-processing (1 source)
3763 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3764 * +----+---+---+-----------------+---------+--------+------+------+
3765 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3766 * +----+---+---+-----------------+---------+--------+------+------+
3768 static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
3770 unsigned int sf, opcode, rn, rd;
3772 if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) {
3773 unallocated_encoding(s);
3774 return;
3777 sf = extract32(insn, 31, 1);
3778 opcode = extract32(insn, 10, 6);
3779 rn = extract32(insn, 5, 5);
3780 rd = extract32(insn, 0, 5);
3782 switch (opcode) {
3783 case 0: /* RBIT */
3784 handle_rbit(s, sf, rn, rd);
3785 break;
3786 case 1: /* REV16 */
3787 handle_rev16(s, sf, rn, rd);
3788 break;
3789 case 2: /* REV32 */
3790 handle_rev32(s, sf, rn, rd);
3791 break;
3792 case 3: /* REV64 */
3793 handle_rev64(s, sf, rn, rd);
3794 break;
3795 case 4: /* CLZ */
3796 handle_clz(s, sf, rn, rd);
3797 break;
3798 case 5: /* CLS */
3799 handle_cls(s, sf, rn, rd);
3800 break;
3804 static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
3805 unsigned int rm, unsigned int rn, unsigned int rd)
3807 TCGv_i64 tcg_n, tcg_m, tcg_rd;
3808 tcg_rd = cpu_reg(s, rd);
3810 if (!sf && is_signed) {
3811 tcg_n = new_tmp_a64(s);
3812 tcg_m = new_tmp_a64(s);
3813 tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
3814 tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
3815 } else {
3816 tcg_n = read_cpu_reg(s, rn, sf);
3817 tcg_m = read_cpu_reg(s, rm, sf);
3820 if (is_signed) {
3821 gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
3822 } else {
3823 gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
3826 if (!sf) { /* zero extend final result */
3827 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3831 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3832 static void handle_shift_reg(DisasContext *s,
3833 enum a64_shift_type shift_type, unsigned int sf,
3834 unsigned int rm, unsigned int rn, unsigned int rd)
3836 TCGv_i64 tcg_shift = tcg_temp_new_i64();
3837 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3838 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
3840 tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31);
3841 shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift);
3842 tcg_temp_free_i64(tcg_shift);
3845 /* CRC32[BHWX], CRC32C[BHWX] */
3846 static void handle_crc32(DisasContext *s,
3847 unsigned int sf, unsigned int sz, bool crc32c,
3848 unsigned int rm, unsigned int rn, unsigned int rd)
3850 TCGv_i64 tcg_acc, tcg_val;
3851 TCGv_i32 tcg_bytes;
3853 if (!arm_dc_feature(s, ARM_FEATURE_CRC)
3854 || (sf == 1 && sz != 3)
3855 || (sf == 0 && sz == 3)) {
3856 unallocated_encoding(s);
3857 return;
3860 if (sz == 3) {
3861 tcg_val = cpu_reg(s, rm);
3862 } else {
3863 uint64_t mask;
3864 switch (sz) {
3865 case 0:
3866 mask = 0xFF;
3867 break;
3868 case 1:
3869 mask = 0xFFFF;
3870 break;
3871 case 2:
3872 mask = 0xFFFFFFFF;
3873 break;
3874 default:
3875 g_assert_not_reached();
3877 tcg_val = new_tmp_a64(s);
3878 tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask);
3881 tcg_acc = cpu_reg(s, rn);
3882 tcg_bytes = tcg_const_i32(1 << sz);
3884 if (crc32c) {
3885 gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
3886 } else {
3887 gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
3890 tcg_temp_free_i32(tcg_bytes);
3893 /* C3.5.8 Data-processing (2 source)
3894 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3895 * +----+---+---+-----------------+------+--------+------+------+
3896 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3897 * +----+---+---+-----------------+------+--------+------+------+
3899 static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
3901 unsigned int sf, rm, opcode, rn, rd;
3902 sf = extract32(insn, 31, 1);
3903 rm = extract32(insn, 16, 5);
3904 opcode = extract32(insn, 10, 6);
3905 rn = extract32(insn, 5, 5);
3906 rd = extract32(insn, 0, 5);
3908 if (extract32(insn, 29, 1)) {
3909 unallocated_encoding(s);
3910 return;
3913 switch (opcode) {
3914 case 2: /* UDIV */
3915 handle_div(s, false, sf, rm, rn, rd);
3916 break;
3917 case 3: /* SDIV */
3918 handle_div(s, true, sf, rm, rn, rd);
3919 break;
3920 case 8: /* LSLV */
3921 handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
3922 break;
3923 case 9: /* LSRV */
3924 handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd);
3925 break;
3926 case 10: /* ASRV */
3927 handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd);
3928 break;
3929 case 11: /* RORV */
3930 handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
3931 break;
3932 case 16:
3933 case 17:
3934 case 18:
3935 case 19:
3936 case 20:
3937 case 21:
3938 case 22:
3939 case 23: /* CRC32 */
3941 int sz = extract32(opcode, 0, 2);
3942 bool crc32c = extract32(opcode, 2, 1);
3943 handle_crc32(s, sf, sz, crc32c, rm, rn, rd);
3944 break;
3946 default:
3947 unallocated_encoding(s);
3948 break;
3952 /* C3.5 Data processing - register */
3953 static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
3955 switch (extract32(insn, 24, 5)) {
3956 case 0x0a: /* Logical (shifted register) */
3957 disas_logic_reg(s, insn);
3958 break;
3959 case 0x0b: /* Add/subtract */
3960 if (insn & (1 << 21)) { /* (extended register) */
3961 disas_add_sub_ext_reg(s, insn);
3962 } else {
3963 disas_add_sub_reg(s, insn);
3965 break;
3966 case 0x1b: /* Data-processing (3 source) */
3967 disas_data_proc_3src(s, insn);
3968 break;
3969 case 0x1a:
3970 switch (extract32(insn, 21, 3)) {
3971 case 0x0: /* Add/subtract (with carry) */
3972 disas_adc_sbc(s, insn);
3973 break;
3974 case 0x2: /* Conditional compare */
3975 disas_cc(s, insn); /* both imm and reg forms */
3976 break;
3977 case 0x4: /* Conditional select */
3978 disas_cond_select(s, insn);
3979 break;
3980 case 0x6: /* Data-processing */
3981 if (insn & (1 << 30)) { /* (1 source) */
3982 disas_data_proc_1src(s, insn);
3983 } else { /* (2 source) */
3984 disas_data_proc_2src(s, insn);
3986 break;
3987 default:
3988 unallocated_encoding(s);
3989 break;
3991 break;
3992 default:
3993 unallocated_encoding(s);
3994 break;
3998 static void handle_fp_compare(DisasContext *s, bool is_double,
3999 unsigned int rn, unsigned int rm,
4000 bool cmp_with_zero, bool signal_all_nans)
4002 TCGv_i64 tcg_flags = tcg_temp_new_i64();
4003 TCGv_ptr fpst = get_fpstatus_ptr();
4005 if (is_double) {
4006 TCGv_i64 tcg_vn, tcg_vm;
4008 tcg_vn = read_fp_dreg(s, rn);
4009 if (cmp_with_zero) {
4010 tcg_vm = tcg_const_i64(0);
4011 } else {
4012 tcg_vm = read_fp_dreg(s, rm);
4014 if (signal_all_nans) {
4015 gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4016 } else {
4017 gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4019 tcg_temp_free_i64(tcg_vn);
4020 tcg_temp_free_i64(tcg_vm);
4021 } else {
4022 TCGv_i32 tcg_vn, tcg_vm;
4024 tcg_vn = read_fp_sreg(s, rn);
4025 if (cmp_with_zero) {
4026 tcg_vm = tcg_const_i32(0);
4027 } else {
4028 tcg_vm = read_fp_sreg(s, rm);
4030 if (signal_all_nans) {
4031 gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4032 } else {
4033 gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4035 tcg_temp_free_i32(tcg_vn);
4036 tcg_temp_free_i32(tcg_vm);
4039 tcg_temp_free_ptr(fpst);
4041 gen_set_nzcv(tcg_flags);
4043 tcg_temp_free_i64(tcg_flags);
4046 /* C3.6.22 Floating point compare
4047 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4048 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4049 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4050 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4052 static void disas_fp_compare(DisasContext *s, uint32_t insn)
4054 unsigned int mos, type, rm, op, rn, opc, op2r;
4056 mos = extract32(insn, 29, 3);
4057 type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
4058 rm = extract32(insn, 16, 5);
4059 op = extract32(insn, 14, 2);
4060 rn = extract32(insn, 5, 5);
4061 opc = extract32(insn, 3, 2);
4062 op2r = extract32(insn, 0, 3);
4064 if (mos || op || op2r || type > 1) {
4065 unallocated_encoding(s);
4066 return;
4069 if (!fp_access_check(s)) {
4070 return;
4073 handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
4076 /* C3.6.23 Floating point conditional compare
4077 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4078 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4079 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4080 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4082 static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
4084 unsigned int mos, type, rm, cond, rn, op, nzcv;
4085 TCGv_i64 tcg_flags;
4086 int label_continue = -1;
4088 mos = extract32(insn, 29, 3);
4089 type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
4090 rm = extract32(insn, 16, 5);
4091 cond = extract32(insn, 12, 4);
4092 rn = extract32(insn, 5, 5);
4093 op = extract32(insn, 4, 1);
4094 nzcv = extract32(insn, 0, 4);
4096 if (mos || type > 1) {
4097 unallocated_encoding(s);
4098 return;
4101 if (!fp_access_check(s)) {
4102 return;
4105 if (cond < 0x0e) { /* not always */
4106 int label_match = gen_new_label();
4107 label_continue = gen_new_label();
4108 arm_gen_test_cc(cond, label_match);
4109 /* nomatch: */
4110 tcg_flags = tcg_const_i64(nzcv << 28);
4111 gen_set_nzcv(tcg_flags);
4112 tcg_temp_free_i64(tcg_flags);
4113 tcg_gen_br(label_continue);
4114 gen_set_label(label_match);
4117 handle_fp_compare(s, type, rn, rm, false, op);
4119 if (cond < 0x0e) {
4120 gen_set_label(label_continue);
4124 /* copy src FP register to dst FP register; type specifies single or double */
4125 static void gen_mov_fp2fp(DisasContext *s, int type, int dst, int src)
4127 if (type) {
4128 TCGv_i64 v = read_fp_dreg(s, src);
4129 write_fp_dreg(s, dst, v);
4130 tcg_temp_free_i64(v);
4131 } else {
4132 TCGv_i32 v = read_fp_sreg(s, src);
4133 write_fp_sreg(s, dst, v);
4134 tcg_temp_free_i32(v);
4138 /* C3.6.24 Floating point conditional select
4139 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4140 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4141 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4142 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4144 static void disas_fp_csel(DisasContext *s, uint32_t insn)
4146 unsigned int mos, type, rm, cond, rn, rd;
4147 int label_continue = -1;
4149 mos = extract32(insn, 29, 3);
4150 type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
4151 rm = extract32(insn, 16, 5);
4152 cond = extract32(insn, 12, 4);
4153 rn = extract32(insn, 5, 5);
4154 rd = extract32(insn, 0, 5);
4156 if (mos || type > 1) {
4157 unallocated_encoding(s);
4158 return;
4161 if (!fp_access_check(s)) {
4162 return;
4165 if (cond < 0x0e) { /* not always */
4166 int label_match = gen_new_label();
4167 label_continue = gen_new_label();
4168 arm_gen_test_cc(cond, label_match);
4169 /* nomatch: */
4170 gen_mov_fp2fp(s, type, rd, rm);
4171 tcg_gen_br(label_continue);
4172 gen_set_label(label_match);
4175 gen_mov_fp2fp(s, type, rd, rn);
4177 if (cond < 0x0e) { /* continue */
4178 gen_set_label(label_continue);
4182 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4183 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
4185 TCGv_ptr fpst;
4186 TCGv_i32 tcg_op;
4187 TCGv_i32 tcg_res;
4189 fpst = get_fpstatus_ptr();
4190 tcg_op = read_fp_sreg(s, rn);
4191 tcg_res = tcg_temp_new_i32();
4193 switch (opcode) {
4194 case 0x0: /* FMOV */
4195 tcg_gen_mov_i32(tcg_res, tcg_op);
4196 break;
4197 case 0x1: /* FABS */
4198 gen_helper_vfp_abss(tcg_res, tcg_op);
4199 break;
4200 case 0x2: /* FNEG */
4201 gen_helper_vfp_negs(tcg_res, tcg_op);
4202 break;
4203 case 0x3: /* FSQRT */
4204 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
4205 break;
4206 case 0x8: /* FRINTN */
4207 case 0x9: /* FRINTP */
4208 case 0xa: /* FRINTM */
4209 case 0xb: /* FRINTZ */
4210 case 0xc: /* FRINTA */
4212 TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
4214 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4215 gen_helper_rints(tcg_res, tcg_op, fpst);
4217 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4218 tcg_temp_free_i32(tcg_rmode);
4219 break;
4221 case 0xe: /* FRINTX */
4222 gen_helper_rints_exact(tcg_res, tcg_op, fpst);
4223 break;
4224 case 0xf: /* FRINTI */
4225 gen_helper_rints(tcg_res, tcg_op, fpst);
4226 break;
4227 default:
4228 abort();
4231 write_fp_sreg(s, rd, tcg_res);
4233 tcg_temp_free_ptr(fpst);
4234 tcg_temp_free_i32(tcg_op);
4235 tcg_temp_free_i32(tcg_res);
4238 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4239 static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
4241 TCGv_ptr fpst;
4242 TCGv_i64 tcg_op;
4243 TCGv_i64 tcg_res;
4245 fpst = get_fpstatus_ptr();
4246 tcg_op = read_fp_dreg(s, rn);
4247 tcg_res = tcg_temp_new_i64();
4249 switch (opcode) {
4250 case 0x0: /* FMOV */
4251 tcg_gen_mov_i64(tcg_res, tcg_op);
4252 break;
4253 case 0x1: /* FABS */
4254 gen_helper_vfp_absd(tcg_res, tcg_op);
4255 break;
4256 case 0x2: /* FNEG */
4257 gen_helper_vfp_negd(tcg_res, tcg_op);
4258 break;
4259 case 0x3: /* FSQRT */
4260 gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
4261 break;
4262 case 0x8: /* FRINTN */
4263 case 0x9: /* FRINTP */
4264 case 0xa: /* FRINTM */
4265 case 0xb: /* FRINTZ */
4266 case 0xc: /* FRINTA */
4268 TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
4270 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4271 gen_helper_rintd(tcg_res, tcg_op, fpst);
4273 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4274 tcg_temp_free_i32(tcg_rmode);
4275 break;
4277 case 0xe: /* FRINTX */
4278 gen_helper_rintd_exact(tcg_res, tcg_op, fpst);
4279 break;
4280 case 0xf: /* FRINTI */
4281 gen_helper_rintd(tcg_res, tcg_op, fpst);
4282 break;
4283 default:
4284 abort();
4287 write_fp_dreg(s, rd, tcg_res);
4289 tcg_temp_free_ptr(fpst);
4290 tcg_temp_free_i64(tcg_op);
4291 tcg_temp_free_i64(tcg_res);
4294 static void handle_fp_fcvt(DisasContext *s, int opcode,
4295 int rd, int rn, int dtype, int ntype)
4297 switch (ntype) {
4298 case 0x0:
4300 TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
4301 if (dtype == 1) {
4302 /* Single to double */
4303 TCGv_i64 tcg_rd = tcg_temp_new_i64();
4304 gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env);
4305 write_fp_dreg(s, rd, tcg_rd);
4306 tcg_temp_free_i64(tcg_rd);
4307 } else {
4308 /* Single to half */
4309 TCGv_i32 tcg_rd = tcg_temp_new_i32();
4310 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, cpu_env);
4311 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4312 write_fp_sreg(s, rd, tcg_rd);
4313 tcg_temp_free_i32(tcg_rd);
4315 tcg_temp_free_i32(tcg_rn);
4316 break;
4318 case 0x1:
4320 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
4321 TCGv_i32 tcg_rd = tcg_temp_new_i32();
4322 if (dtype == 0) {
4323 /* Double to single */
4324 gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env);
4325 } else {
4326 /* Double to half */
4327 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, cpu_env);
4328 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4330 write_fp_sreg(s, rd, tcg_rd);
4331 tcg_temp_free_i32(tcg_rd);
4332 tcg_temp_free_i64(tcg_rn);
4333 break;
4335 case 0x3:
4337 TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
4338 tcg_gen_ext16u_i32(tcg_rn, tcg_rn);
4339 if (dtype == 0) {
4340 /* Half to single */
4341 TCGv_i32 tcg_rd = tcg_temp_new_i32();
4342 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, cpu_env);
4343 write_fp_sreg(s, rd, tcg_rd);
4344 tcg_temp_free_i32(tcg_rd);
4345 } else {
4346 /* Half to double */
4347 TCGv_i64 tcg_rd = tcg_temp_new_i64();
4348 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, cpu_env);
4349 write_fp_dreg(s, rd, tcg_rd);
4350 tcg_temp_free_i64(tcg_rd);
4352 tcg_temp_free_i32(tcg_rn);
4353 break;
4355 default:
4356 abort();
4360 /* C3.6.25 Floating point data-processing (1 source)
4361 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4362 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4363 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4364 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4366 static void disas_fp_1src(DisasContext *s, uint32_t insn)
4368 int type = extract32(insn, 22, 2);
4369 int opcode = extract32(insn, 15, 6);
4370 int rn = extract32(insn, 5, 5);
4371 int rd = extract32(insn, 0, 5);
4373 switch (opcode) {
4374 case 0x4: case 0x5: case 0x7:
4376 /* FCVT between half, single and double precision */
4377 int dtype = extract32(opcode, 0, 2);
4378 if (type == 2 || dtype == type) {
4379 unallocated_encoding(s);
4380 return;
4382 if (!fp_access_check(s)) {
4383 return;
4386 handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
4387 break;
4389 case 0x0 ... 0x3:
4390 case 0x8 ... 0xc:
4391 case 0xe ... 0xf:
4392 /* 32-to-32 and 64-to-64 ops */
4393 switch (type) {
4394 case 0:
4395 if (!fp_access_check(s)) {
4396 return;
4399 handle_fp_1src_single(s, opcode, rd, rn);
4400 break;
4401 case 1:
4402 if (!fp_access_check(s)) {
4403 return;
4406 handle_fp_1src_double(s, opcode, rd, rn);
4407 break;
4408 default:
4409 unallocated_encoding(s);
4411 break;
4412 default:
4413 unallocated_encoding(s);
4414 break;
4418 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4419 static void handle_fp_2src_single(DisasContext *s, int opcode,
4420 int rd, int rn, int rm)
4422 TCGv_i32 tcg_op1;
4423 TCGv_i32 tcg_op2;
4424 TCGv_i32 tcg_res;
4425 TCGv_ptr fpst;
4427 tcg_res = tcg_temp_new_i32();
4428 fpst = get_fpstatus_ptr();
4429 tcg_op1 = read_fp_sreg(s, rn);
4430 tcg_op2 = read_fp_sreg(s, rm);
4432 switch (opcode) {
4433 case 0x0: /* FMUL */
4434 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
4435 break;
4436 case 0x1: /* FDIV */
4437 gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
4438 break;
4439 case 0x2: /* FADD */
4440 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
4441 break;
4442 case 0x3: /* FSUB */
4443 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
4444 break;
4445 case 0x4: /* FMAX */
4446 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
4447 break;
4448 case 0x5: /* FMIN */
4449 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
4450 break;
4451 case 0x6: /* FMAXNM */
4452 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
4453 break;
4454 case 0x7: /* FMINNM */
4455 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
4456 break;
4457 case 0x8: /* FNMUL */
4458 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
4459 gen_helper_vfp_negs(tcg_res, tcg_res);
4460 break;
4463 write_fp_sreg(s, rd, tcg_res);
4465 tcg_temp_free_ptr(fpst);
4466 tcg_temp_free_i32(tcg_op1);
4467 tcg_temp_free_i32(tcg_op2);
4468 tcg_temp_free_i32(tcg_res);
4471 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4472 static void handle_fp_2src_double(DisasContext *s, int opcode,
4473 int rd, int rn, int rm)
4475 TCGv_i64 tcg_op1;
4476 TCGv_i64 tcg_op2;
4477 TCGv_i64 tcg_res;
4478 TCGv_ptr fpst;
4480 tcg_res = tcg_temp_new_i64();
4481 fpst = get_fpstatus_ptr();
4482 tcg_op1 = read_fp_dreg(s, rn);
4483 tcg_op2 = read_fp_dreg(s, rm);
4485 switch (opcode) {
4486 case 0x0: /* FMUL */
4487 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
4488 break;
4489 case 0x1: /* FDIV */
4490 gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
4491 break;
4492 case 0x2: /* FADD */
4493 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
4494 break;
4495 case 0x3: /* FSUB */
4496 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
4497 break;
4498 case 0x4: /* FMAX */
4499 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
4500 break;
4501 case 0x5: /* FMIN */
4502 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
4503 break;
4504 case 0x6: /* FMAXNM */
4505 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
4506 break;
4507 case 0x7: /* FMINNM */
4508 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
4509 break;
4510 case 0x8: /* FNMUL */
4511 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
4512 gen_helper_vfp_negd(tcg_res, tcg_res);
4513 break;
4516 write_fp_dreg(s, rd, tcg_res);
4518 tcg_temp_free_ptr(fpst);
4519 tcg_temp_free_i64(tcg_op1);
4520 tcg_temp_free_i64(tcg_op2);
4521 tcg_temp_free_i64(tcg_res);
4524 /* C3.6.26 Floating point data-processing (2 source)
4525 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4526 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4527 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4528 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4530 static void disas_fp_2src(DisasContext *s, uint32_t insn)
4532 int type = extract32(insn, 22, 2);
4533 int rd = extract32(insn, 0, 5);
4534 int rn = extract32(insn, 5, 5);
4535 int rm = extract32(insn, 16, 5);
4536 int opcode = extract32(insn, 12, 4);
4538 if (opcode > 8) {
4539 unallocated_encoding(s);
4540 return;
4543 switch (type) {
4544 case 0:
4545 if (!fp_access_check(s)) {
4546 return;
4548 handle_fp_2src_single(s, opcode, rd, rn, rm);
4549 break;
4550 case 1:
4551 if (!fp_access_check(s)) {
4552 return;
4554 handle_fp_2src_double(s, opcode, rd, rn, rm);
4555 break;
4556 default:
4557 unallocated_encoding(s);
4561 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4562 static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
4563 int rd, int rn, int rm, int ra)
4565 TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
4566 TCGv_i32 tcg_res = tcg_temp_new_i32();
4567 TCGv_ptr fpst = get_fpstatus_ptr();
4569 tcg_op1 = read_fp_sreg(s, rn);
4570 tcg_op2 = read_fp_sreg(s, rm);
4571 tcg_op3 = read_fp_sreg(s, ra);
4573 /* These are fused multiply-add, and must be done as one
4574 * floating point operation with no rounding between the
4575 * multiplication and addition steps.
4576 * NB that doing the negations here as separate steps is
4577 * correct : an input NaN should come out with its sign bit
4578 * flipped if it is a negated-input.
4580 if (o1 == true) {
4581 gen_helper_vfp_negs(tcg_op3, tcg_op3);
4584 if (o0 != o1) {
4585 gen_helper_vfp_negs(tcg_op1, tcg_op1);
4588 gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
4590 write_fp_sreg(s, rd, tcg_res);
4592 tcg_temp_free_ptr(fpst);
4593 tcg_temp_free_i32(tcg_op1);
4594 tcg_temp_free_i32(tcg_op2);
4595 tcg_temp_free_i32(tcg_op3);
4596 tcg_temp_free_i32(tcg_res);
4599 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4600 static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
4601 int rd, int rn, int rm, int ra)
4603 TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
4604 TCGv_i64 tcg_res = tcg_temp_new_i64();
4605 TCGv_ptr fpst = get_fpstatus_ptr();
4607 tcg_op1 = read_fp_dreg(s, rn);
4608 tcg_op2 = read_fp_dreg(s, rm);
4609 tcg_op3 = read_fp_dreg(s, ra);
4611 /* These are fused multiply-add, and must be done as one
4612 * floating point operation with no rounding between the
4613 * multiplication and addition steps.
4614 * NB that doing the negations here as separate steps is
4615 * correct : an input NaN should come out with its sign bit
4616 * flipped if it is a negated-input.
4618 if (o1 == true) {
4619 gen_helper_vfp_negd(tcg_op3, tcg_op3);
4622 if (o0 != o1) {
4623 gen_helper_vfp_negd(tcg_op1, tcg_op1);
4626 gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
4628 write_fp_dreg(s, rd, tcg_res);
4630 tcg_temp_free_ptr(fpst);
4631 tcg_temp_free_i64(tcg_op1);
4632 tcg_temp_free_i64(tcg_op2);
4633 tcg_temp_free_i64(tcg_op3);
4634 tcg_temp_free_i64(tcg_res);
4637 /* C3.6.27 Floating point data-processing (3 source)
4638 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4639 * +---+---+---+-----------+------+----+------+----+------+------+------+
4640 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4641 * +---+---+---+-----------+------+----+------+----+------+------+------+
4643 static void disas_fp_3src(DisasContext *s, uint32_t insn)
4645 int type = extract32(insn, 22, 2);
4646 int rd = extract32(insn, 0, 5);
4647 int rn = extract32(insn, 5, 5);
4648 int ra = extract32(insn, 10, 5);
4649 int rm = extract32(insn, 16, 5);
4650 bool o0 = extract32(insn, 15, 1);
4651 bool o1 = extract32(insn, 21, 1);
4653 switch (type) {
4654 case 0:
4655 if (!fp_access_check(s)) {
4656 return;
4658 handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra);
4659 break;
4660 case 1:
4661 if (!fp_access_check(s)) {
4662 return;
4664 handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
4665 break;
4666 default:
4667 unallocated_encoding(s);
4671 /* C3.6.28 Floating point immediate
4672 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4673 * +---+---+---+-----------+------+---+------------+-------+------+------+
4674 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4675 * +---+---+---+-----------+------+---+------------+-------+------+------+
4677 static void disas_fp_imm(DisasContext *s, uint32_t insn)
4679 int rd = extract32(insn, 0, 5);
4680 int imm8 = extract32(insn, 13, 8);
4681 int is_double = extract32(insn, 22, 2);
4682 uint64_t imm;
4683 TCGv_i64 tcg_res;
4685 if (is_double > 1) {
4686 unallocated_encoding(s);
4687 return;
4690 if (!fp_access_check(s)) {
4691 return;
4694 /* The imm8 encodes the sign bit, enough bits to represent
4695 * an exponent in the range 01....1xx to 10....0xx,
4696 * and the most significant 4 bits of the mantissa; see
4697 * VFPExpandImm() in the v8 ARM ARM.
4699 if (is_double) {
4700 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
4701 (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
4702 extract32(imm8, 0, 6);
4703 imm <<= 48;
4704 } else {
4705 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
4706 (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
4707 (extract32(imm8, 0, 6) << 3);
4708 imm <<= 16;
4711 tcg_res = tcg_const_i64(imm);
4712 write_fp_dreg(s, rd, tcg_res);
4713 tcg_temp_free_i64(tcg_res);
4716 /* Handle floating point <=> fixed point conversions. Note that we can
4717 * also deal with fp <=> integer conversions as a special case (scale == 64)
4718 * OPTME: consider handling that special case specially or at least skipping
4719 * the call to scalbn in the helpers for zero shifts.
4721 static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
4722 bool itof, int rmode, int scale, int sf, int type)
4724 bool is_signed = !(opcode & 1);
4725 bool is_double = type;
4726 TCGv_ptr tcg_fpstatus;
4727 TCGv_i32 tcg_shift;
4729 tcg_fpstatus = get_fpstatus_ptr();
4731 tcg_shift = tcg_const_i32(64 - scale);
4733 if (itof) {
4734 TCGv_i64 tcg_int = cpu_reg(s, rn);
4735 if (!sf) {
4736 TCGv_i64 tcg_extend = new_tmp_a64(s);
4738 if (is_signed) {
4739 tcg_gen_ext32s_i64(tcg_extend, tcg_int);
4740 } else {
4741 tcg_gen_ext32u_i64(tcg_extend, tcg_int);
4744 tcg_int = tcg_extend;
4747 if (is_double) {
4748 TCGv_i64 tcg_double = tcg_temp_new_i64();
4749 if (is_signed) {
4750 gen_helper_vfp_sqtod(tcg_double, tcg_int,
4751 tcg_shift, tcg_fpstatus);
4752 } else {
4753 gen_helper_vfp_uqtod(tcg_double, tcg_int,
4754 tcg_shift, tcg_fpstatus);
4756 write_fp_dreg(s, rd, tcg_double);
4757 tcg_temp_free_i64(tcg_double);
4758 } else {
4759 TCGv_i32 tcg_single = tcg_temp_new_i32();
4760 if (is_signed) {
4761 gen_helper_vfp_sqtos(tcg_single, tcg_int,
4762 tcg_shift, tcg_fpstatus);
4763 } else {
4764 gen_helper_vfp_uqtos(tcg_single, tcg_int,
4765 tcg_shift, tcg_fpstatus);
4767 write_fp_sreg(s, rd, tcg_single);
4768 tcg_temp_free_i32(tcg_single);
4770 } else {
4771 TCGv_i64 tcg_int = cpu_reg(s, rd);
4772 TCGv_i32 tcg_rmode;
4774 if (extract32(opcode, 2, 1)) {
4775 /* There are too many rounding modes to all fit into rmode,
4776 * so FCVTA[US] is a special case.
4778 rmode = FPROUNDING_TIEAWAY;
4781 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
4783 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4785 if (is_double) {
4786 TCGv_i64 tcg_double = read_fp_dreg(s, rn);
4787 if (is_signed) {
4788 if (!sf) {
4789 gen_helper_vfp_tosld(tcg_int, tcg_double,
4790 tcg_shift, tcg_fpstatus);
4791 } else {
4792 gen_helper_vfp_tosqd(tcg_int, tcg_double,
4793 tcg_shift, tcg_fpstatus);
4795 } else {
4796 if (!sf) {
4797 gen_helper_vfp_tould(tcg_int, tcg_double,
4798 tcg_shift, tcg_fpstatus);
4799 } else {
4800 gen_helper_vfp_touqd(tcg_int, tcg_double,
4801 tcg_shift, tcg_fpstatus);
4804 tcg_temp_free_i64(tcg_double);
4805 } else {
4806 TCGv_i32 tcg_single = read_fp_sreg(s, rn);
4807 if (sf) {
4808 if (is_signed) {
4809 gen_helper_vfp_tosqs(tcg_int, tcg_single,
4810 tcg_shift, tcg_fpstatus);
4811 } else {
4812 gen_helper_vfp_touqs(tcg_int, tcg_single,
4813 tcg_shift, tcg_fpstatus);
4815 } else {
4816 TCGv_i32 tcg_dest = tcg_temp_new_i32();
4817 if (is_signed) {
4818 gen_helper_vfp_tosls(tcg_dest, tcg_single,
4819 tcg_shift, tcg_fpstatus);
4820 } else {
4821 gen_helper_vfp_touls(tcg_dest, tcg_single,
4822 tcg_shift, tcg_fpstatus);
4824 tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
4825 tcg_temp_free_i32(tcg_dest);
4827 tcg_temp_free_i32(tcg_single);
4830 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
4831 tcg_temp_free_i32(tcg_rmode);
4833 if (!sf) {
4834 tcg_gen_ext32u_i64(tcg_int, tcg_int);
4838 tcg_temp_free_ptr(tcg_fpstatus);
4839 tcg_temp_free_i32(tcg_shift);
4842 /* C3.6.29 Floating point <-> fixed point conversions
4843 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4844 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4845 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4846 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4848 static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
4850 int rd = extract32(insn, 0, 5);
4851 int rn = extract32(insn, 5, 5);
4852 int scale = extract32(insn, 10, 6);
4853 int opcode = extract32(insn, 16, 3);
4854 int rmode = extract32(insn, 19, 2);
4855 int type = extract32(insn, 22, 2);
4856 bool sbit = extract32(insn, 29, 1);
4857 bool sf = extract32(insn, 31, 1);
4858 bool itof;
4860 if (sbit || (type > 1)
4861 || (!sf && scale < 32)) {
4862 unallocated_encoding(s);
4863 return;
4866 switch ((rmode << 3) | opcode) {
4867 case 0x2: /* SCVTF */
4868 case 0x3: /* UCVTF */
4869 itof = true;
4870 break;
4871 case 0x18: /* FCVTZS */
4872 case 0x19: /* FCVTZU */
4873 itof = false;
4874 break;
4875 default:
4876 unallocated_encoding(s);
4877 return;
4880 if (!fp_access_check(s)) {
4881 return;
4884 handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type);
4887 static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
4889 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4890 * without conversion.
4893 if (itof) {
4894 TCGv_i64 tcg_rn = cpu_reg(s, rn);
4896 switch (type) {
4897 case 0:
4899 /* 32 bit */
4900 TCGv_i64 tmp = tcg_temp_new_i64();
4901 tcg_gen_ext32u_i64(tmp, tcg_rn);
4902 tcg_gen_st_i64(tmp, cpu_env, fp_reg_offset(s, rd, MO_64));
4903 tcg_gen_movi_i64(tmp, 0);
4904 tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
4905 tcg_temp_free_i64(tmp);
4906 break;
4908 case 1:
4910 /* 64 bit */
4911 TCGv_i64 tmp = tcg_const_i64(0);
4912 tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_offset(s, rd, MO_64));
4913 tcg_gen_st_i64(tmp, cpu_env, fp_reg_hi_offset(s, rd));
4914 tcg_temp_free_i64(tmp);
4915 break;
4917 case 2:
4918 /* 64 bit to top half. */
4919 tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
4920 break;
4922 } else {
4923 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4925 switch (type) {
4926 case 0:
4927 /* 32 bit */
4928 tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32));
4929 break;
4930 case 1:
4931 /* 64 bit */
4932 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64));
4933 break;
4934 case 2:
4935 /* 64 bits from top half */
4936 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
4937 break;
4942 /* C3.6.30 Floating point <-> integer conversions
4943 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4944 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4945 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4946 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4948 static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
4950 int rd = extract32(insn, 0, 5);
4951 int rn = extract32(insn, 5, 5);
4952 int opcode = extract32(insn, 16, 3);
4953 int rmode = extract32(insn, 19, 2);
4954 int type = extract32(insn, 22, 2);
4955 bool sbit = extract32(insn, 29, 1);
4956 bool sf = extract32(insn, 31, 1);
4958 if (sbit) {
4959 unallocated_encoding(s);
4960 return;
4963 if (opcode > 5) {
4964 /* FMOV */
4965 bool itof = opcode & 1;
4967 if (rmode >= 2) {
4968 unallocated_encoding(s);
4969 return;
4972 switch (sf << 3 | type << 1 | rmode) {
4973 case 0x0: /* 32 bit */
4974 case 0xa: /* 64 bit */
4975 case 0xd: /* 64 bit to top half of quad */
4976 break;
4977 default:
4978 /* all other sf/type/rmode combinations are invalid */
4979 unallocated_encoding(s);
4980 break;
4983 if (!fp_access_check(s)) {
4984 return;
4986 handle_fmov(s, rd, rn, type, itof);
4987 } else {
4988 /* actual FP conversions */
4989 bool itof = extract32(opcode, 1, 1);
4991 if (type > 1 || (rmode != 0 && opcode > 1)) {
4992 unallocated_encoding(s);
4993 return;
4996 if (!fp_access_check(s)) {
4997 return;
4999 handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
5003 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
5004 * 31 30 29 28 25 24 0
5005 * +---+---+---+---------+-----------------------------+
5006 * | | 0 | | 1 1 1 1 | |
5007 * +---+---+---+---------+-----------------------------+
5009 static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
5011 if (extract32(insn, 24, 1)) {
5012 /* Floating point data-processing (3 source) */
5013 disas_fp_3src(s, insn);
5014 } else if (extract32(insn, 21, 1) == 0) {
5015 /* Floating point to fixed point conversions */
5016 disas_fp_fixed_conv(s, insn);
5017 } else {
5018 switch (extract32(insn, 10, 2)) {
5019 case 1:
5020 /* Floating point conditional compare */
5021 disas_fp_ccomp(s, insn);
5022 break;
5023 case 2:
5024 /* Floating point data-processing (2 source) */
5025 disas_fp_2src(s, insn);
5026 break;
5027 case 3:
5028 /* Floating point conditional select */
5029 disas_fp_csel(s, insn);
5030 break;
5031 case 0:
5032 switch (ctz32(extract32(insn, 12, 4))) {
5033 case 0: /* [15:12] == xxx1 */
5034 /* Floating point immediate */
5035 disas_fp_imm(s, insn);
5036 break;
5037 case 1: /* [15:12] == xx10 */
5038 /* Floating point compare */
5039 disas_fp_compare(s, insn);
5040 break;
5041 case 2: /* [15:12] == x100 */
5042 /* Floating point data-processing (1 source) */
5043 disas_fp_1src(s, insn);
5044 break;
5045 case 3: /* [15:12] == 1000 */
5046 unallocated_encoding(s);
5047 break;
5048 default: /* [15:12] == 0000 */
5049 /* Floating point <-> integer conversions */
5050 disas_fp_int_conv(s, insn);
5051 break;
5053 break;
5058 static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
5059 int pos)
5061 /* Extract 64 bits from the middle of two concatenated 64 bit
5062 * vector register slices left:right. The extracted bits start
5063 * at 'pos' bits into the right (least significant) side.
5064 * We return the result in tcg_right, and guarantee not to
5065 * trash tcg_left.
5067 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
5068 assert(pos > 0 && pos < 64);
5070 tcg_gen_shri_i64(tcg_right, tcg_right, pos);
5071 tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos);
5072 tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp);
5074 tcg_temp_free_i64(tcg_tmp);
5077 /* C3.6.1 EXT
5078 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
5079 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5080 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
5081 * +---+---+-------------+-----+---+------+---+------+---+------+------+
5083 static void disas_simd_ext(DisasContext *s, uint32_t insn)
5085 int is_q = extract32(insn, 30, 1);
5086 int op2 = extract32(insn, 22, 2);
5087 int imm4 = extract32(insn, 11, 4);
5088 int rm = extract32(insn, 16, 5);
5089 int rn = extract32(insn, 5, 5);
5090 int rd = extract32(insn, 0, 5);
5091 int pos = imm4 << 3;
5092 TCGv_i64 tcg_resl, tcg_resh;
5094 if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) {
5095 unallocated_encoding(s);
5096 return;
5099 if (!fp_access_check(s)) {
5100 return;
5103 tcg_resh = tcg_temp_new_i64();
5104 tcg_resl = tcg_temp_new_i64();
5106 /* Vd gets bits starting at pos bits into Vm:Vn. This is
5107 * either extracting 128 bits from a 128:128 concatenation, or
5108 * extracting 64 bits from a 64:64 concatenation.
5110 if (!is_q) {
5111 read_vec_element(s, tcg_resl, rn, 0, MO_64);
5112 if (pos != 0) {
5113 read_vec_element(s, tcg_resh, rm, 0, MO_64);
5114 do_ext64(s, tcg_resh, tcg_resl, pos);
5116 tcg_gen_movi_i64(tcg_resh, 0);
5117 } else {
5118 TCGv_i64 tcg_hh;
5119 typedef struct {
5120 int reg;
5121 int elt;
5122 } EltPosns;
5123 EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} };
5124 EltPosns *elt = eltposns;
5126 if (pos >= 64) {
5127 elt++;
5128 pos -= 64;
5131 read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64);
5132 elt++;
5133 read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64);
5134 elt++;
5135 if (pos != 0) {
5136 do_ext64(s, tcg_resh, tcg_resl, pos);
5137 tcg_hh = tcg_temp_new_i64();
5138 read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64);
5139 do_ext64(s, tcg_hh, tcg_resh, pos);
5140 tcg_temp_free_i64(tcg_hh);
5144 write_vec_element(s, tcg_resl, rd, 0, MO_64);
5145 tcg_temp_free_i64(tcg_resl);
5146 write_vec_element(s, tcg_resh, rd, 1, MO_64);
5147 tcg_temp_free_i64(tcg_resh);
5150 /* C3.6.2 TBL/TBX
5151 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5152 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5153 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5154 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5156 static void disas_simd_tb(DisasContext *s, uint32_t insn)
5158 int op2 = extract32(insn, 22, 2);
5159 int is_q = extract32(insn, 30, 1);
5160 int rm = extract32(insn, 16, 5);
5161 int rn = extract32(insn, 5, 5);
5162 int rd = extract32(insn, 0, 5);
5163 int is_tblx = extract32(insn, 12, 1);
5164 int len = extract32(insn, 13, 2);
5165 TCGv_i64 tcg_resl, tcg_resh, tcg_idx;
5166 TCGv_i32 tcg_regno, tcg_numregs;
5168 if (op2 != 0) {
5169 unallocated_encoding(s);
5170 return;
5173 if (!fp_access_check(s)) {
5174 return;
5177 /* This does a table lookup: for every byte element in the input
5178 * we index into a table formed from up to four vector registers,
5179 * and then the output is the result of the lookups. Our helper
5180 * function does the lookup operation for a single 64 bit part of
5181 * the input.
5183 tcg_resl = tcg_temp_new_i64();
5184 tcg_resh = tcg_temp_new_i64();
5186 if (is_tblx) {
5187 read_vec_element(s, tcg_resl, rd, 0, MO_64);
5188 } else {
5189 tcg_gen_movi_i64(tcg_resl, 0);
5191 if (is_tblx && is_q) {
5192 read_vec_element(s, tcg_resh, rd, 1, MO_64);
5193 } else {
5194 tcg_gen_movi_i64(tcg_resh, 0);
5197 tcg_idx = tcg_temp_new_i64();
5198 tcg_regno = tcg_const_i32(rn);
5199 tcg_numregs = tcg_const_i32(len + 1);
5200 read_vec_element(s, tcg_idx, rm, 0, MO_64);
5201 gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,
5202 tcg_regno, tcg_numregs);
5203 if (is_q) {
5204 read_vec_element(s, tcg_idx, rm, 1, MO_64);
5205 gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,
5206 tcg_regno, tcg_numregs);
5208 tcg_temp_free_i64(tcg_idx);
5209 tcg_temp_free_i32(tcg_regno);
5210 tcg_temp_free_i32(tcg_numregs);
5212 write_vec_element(s, tcg_resl, rd, 0, MO_64);
5213 tcg_temp_free_i64(tcg_resl);
5214 write_vec_element(s, tcg_resh, rd, 1, MO_64);
5215 tcg_temp_free_i64(tcg_resh);
5218 /* C3.6.3 ZIP/UZP/TRN
5219 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5220 * +---+---+-------------+------+---+------+---+------------------+------+
5221 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5222 * +---+---+-------------+------+---+------+---+------------------+------+
5224 static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
5226 int rd = extract32(insn, 0, 5);
5227 int rn = extract32(insn, 5, 5);
5228 int rm = extract32(insn, 16, 5);
5229 int size = extract32(insn, 22, 2);
5230 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5231 * bit 2 indicates 1 vs 2 variant of the insn.
5233 int opcode = extract32(insn, 12, 2);
5234 bool part = extract32(insn, 14, 1);
5235 bool is_q = extract32(insn, 30, 1);
5236 int esize = 8 << size;
5237 int i, ofs;
5238 int datasize = is_q ? 128 : 64;
5239 int elements = datasize / esize;
5240 TCGv_i64 tcg_res, tcg_resl, tcg_resh;
5242 if (opcode == 0 || (size == 3 && !is_q)) {
5243 unallocated_encoding(s);
5244 return;
5247 if (!fp_access_check(s)) {
5248 return;
5251 tcg_resl = tcg_const_i64(0);
5252 tcg_resh = tcg_const_i64(0);
5253 tcg_res = tcg_temp_new_i64();
5255 for (i = 0; i < elements; i++) {
5256 switch (opcode) {
5257 case 1: /* UZP1/2 */
5259 int midpoint = elements / 2;
5260 if (i < midpoint) {
5261 read_vec_element(s, tcg_res, rn, 2 * i + part, size);
5262 } else {
5263 read_vec_element(s, tcg_res, rm,
5264 2 * (i - midpoint) + part, size);
5266 break;
5268 case 2: /* TRN1/2 */
5269 if (i & 1) {
5270 read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
5271 } else {
5272 read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
5274 break;
5275 case 3: /* ZIP1/2 */
5277 int base = part * elements / 2;
5278 if (i & 1) {
5279 read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
5280 } else {
5281 read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
5283 break;
5285 default:
5286 g_assert_not_reached();
5289 ofs = i * esize;
5290 if (ofs < 64) {
5291 tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
5292 tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
5293 } else {
5294 tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
5295 tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
5299 tcg_temp_free_i64(tcg_res);
5301 write_vec_element(s, tcg_resl, rd, 0, MO_64);
5302 tcg_temp_free_i64(tcg_resl);
5303 write_vec_element(s, tcg_resh, rd, 1, MO_64);
5304 tcg_temp_free_i64(tcg_resh);
5307 static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
5308 int opc, bool is_min, TCGv_ptr fpst)
5310 /* Helper function for disas_simd_across_lanes: do a single precision
5311 * min/max operation on the specified two inputs,
5312 * and return the result in tcg_elt1.
5314 if (opc == 0xc) {
5315 if (is_min) {
5316 gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
5317 } else {
5318 gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
5320 } else {
5321 assert(opc == 0xf);
5322 if (is_min) {
5323 gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
5324 } else {
5325 gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
5330 /* C3.6.4 AdvSIMD across lanes
5331 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5332 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5333 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5334 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5336 static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
5338 int rd = extract32(insn, 0, 5);
5339 int rn = extract32(insn, 5, 5);
5340 int size = extract32(insn, 22, 2);
5341 int opcode = extract32(insn, 12, 5);
5342 bool is_q = extract32(insn, 30, 1);
5343 bool is_u = extract32(insn, 29, 1);
5344 bool is_fp = false;
5345 bool is_min = false;
5346 int esize;
5347 int elements;
5348 int i;
5349 TCGv_i64 tcg_res, tcg_elt;
5351 switch (opcode) {
5352 case 0x1b: /* ADDV */
5353 if (is_u) {
5354 unallocated_encoding(s);
5355 return;
5357 /* fall through */
5358 case 0x3: /* SADDLV, UADDLV */
5359 case 0xa: /* SMAXV, UMAXV */
5360 case 0x1a: /* SMINV, UMINV */
5361 if (size == 3 || (size == 2 && !is_q)) {
5362 unallocated_encoding(s);
5363 return;
5365 break;
5366 case 0xc: /* FMAXNMV, FMINNMV */
5367 case 0xf: /* FMAXV, FMINV */
5368 if (!is_u || !is_q || extract32(size, 0, 1)) {
5369 unallocated_encoding(s);
5370 return;
5372 /* Bit 1 of size field encodes min vs max, and actual size is always
5373 * 32 bits: adjust the size variable so following code can rely on it
5375 is_min = extract32(size, 1, 1);
5376 is_fp = true;
5377 size = 2;
5378 break;
5379 default:
5380 unallocated_encoding(s);
5381 return;
5384 if (!fp_access_check(s)) {
5385 return;
5388 esize = 8 << size;
5389 elements = (is_q ? 128 : 64) / esize;
5391 tcg_res = tcg_temp_new_i64();
5392 tcg_elt = tcg_temp_new_i64();
5394 /* These instructions operate across all lanes of a vector
5395 * to produce a single result. We can guarantee that a 64
5396 * bit intermediate is sufficient:
5397 * + for [US]ADDLV the maximum element size is 32 bits, and
5398 * the result type is 64 bits
5399 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5400 * same as the element size, which is 32 bits at most
5401 * For the integer operations we can choose to work at 64
5402 * or 32 bits and truncate at the end; for simplicity
5403 * we use 64 bits always. The floating point
5404 * ops do require 32 bit intermediates, though.
5406 if (!is_fp) {
5407 read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN));
5409 for (i = 1; i < elements; i++) {
5410 read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN));
5412 switch (opcode) {
5413 case 0x03: /* SADDLV / UADDLV */
5414 case 0x1b: /* ADDV */
5415 tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt);
5416 break;
5417 case 0x0a: /* SMAXV / UMAXV */
5418 tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
5419 tcg_res,
5420 tcg_res, tcg_elt, tcg_res, tcg_elt);
5421 break;
5422 case 0x1a: /* SMINV / UMINV */
5423 tcg_gen_movcond_i64(is_u ? TCG_COND_LEU : TCG_COND_LE,
5424 tcg_res,
5425 tcg_res, tcg_elt, tcg_res, tcg_elt);
5426 break;
5427 break;
5428 default:
5429 g_assert_not_reached();
5433 } else {
5434 /* Floating point ops which work on 32 bit (single) intermediates.
5435 * Note that correct NaN propagation requires that we do these
5436 * operations in exactly the order specified by the pseudocode.
5438 TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
5439 TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
5440 TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
5441 TCGv_ptr fpst = get_fpstatus_ptr();
5443 assert(esize == 32);
5444 assert(elements == 4);
5446 read_vec_element(s, tcg_elt, rn, 0, MO_32);
5447 tcg_gen_trunc_i64_i32(tcg_elt1, tcg_elt);
5448 read_vec_element(s, tcg_elt, rn, 1, MO_32);
5449 tcg_gen_trunc_i64_i32(tcg_elt2, tcg_elt);
5451 do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
5453 read_vec_element(s, tcg_elt, rn, 2, MO_32);
5454 tcg_gen_trunc_i64_i32(tcg_elt2, tcg_elt);
5455 read_vec_element(s, tcg_elt, rn, 3, MO_32);
5456 tcg_gen_trunc_i64_i32(tcg_elt3, tcg_elt);
5458 do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
5460 do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
5462 tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
5463 tcg_temp_free_i32(tcg_elt1);
5464 tcg_temp_free_i32(tcg_elt2);
5465 tcg_temp_free_i32(tcg_elt3);
5466 tcg_temp_free_ptr(fpst);
5469 tcg_temp_free_i64(tcg_elt);
5471 /* Now truncate the result to the width required for the final output */
5472 if (opcode == 0x03) {
5473 /* SADDLV, UADDLV: result is 2*esize */
5474 size++;
5477 switch (size) {
5478 case 0:
5479 tcg_gen_ext8u_i64(tcg_res, tcg_res);
5480 break;
5481 case 1:
5482 tcg_gen_ext16u_i64(tcg_res, tcg_res);
5483 break;
5484 case 2:
5485 tcg_gen_ext32u_i64(tcg_res, tcg_res);
5486 break;
5487 case 3:
5488 break;
5489 default:
5490 g_assert_not_reached();
5493 write_fp_dreg(s, rd, tcg_res);
5494 tcg_temp_free_i64(tcg_res);
5497 /* C6.3.31 DUP (Element, Vector)
5499 * 31 30 29 21 20 16 15 10 9 5 4 0
5500 * +---+---+-------------------+--------+-------------+------+------+
5501 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5502 * +---+---+-------------------+--------+-------------+------+------+
5504 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5506 static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
5507 int imm5)
5509 int size = ctz32(imm5);
5510 int esize = 8 << size;
5511 int elements = (is_q ? 128 : 64) / esize;
5512 int index, i;
5513 TCGv_i64 tmp;
5515 if (size > 3 || (size == 3 && !is_q)) {
5516 unallocated_encoding(s);
5517 return;
5520 if (!fp_access_check(s)) {
5521 return;
5524 index = imm5 >> (size + 1);
5526 tmp = tcg_temp_new_i64();
5527 read_vec_element(s, tmp, rn, index, size);
5529 for (i = 0; i < elements; i++) {
5530 write_vec_element(s, tmp, rd, i, size);
5533 if (!is_q) {
5534 clear_vec_high(s, rd);
5537 tcg_temp_free_i64(tmp);
5540 /* C6.3.31 DUP (element, scalar)
5541 * 31 21 20 16 15 10 9 5 4 0
5542 * +-----------------------+--------+-------------+------+------+
5543 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5544 * +-----------------------+--------+-------------+------+------+
5546 static void handle_simd_dupes(DisasContext *s, int rd, int rn,
5547 int imm5)
5549 int size = ctz32(imm5);
5550 int index;
5551 TCGv_i64 tmp;
5553 if (size > 3) {
5554 unallocated_encoding(s);
5555 return;
5558 if (!fp_access_check(s)) {
5559 return;
5562 index = imm5 >> (size + 1);
5564 /* This instruction just extracts the specified element and
5565 * zero-extends it into the bottom of the destination register.
5567 tmp = tcg_temp_new_i64();
5568 read_vec_element(s, tmp, rn, index, size);
5569 write_fp_dreg(s, rd, tmp);
5570 tcg_temp_free_i64(tmp);
5573 /* C6.3.32 DUP (General)
5575 * 31 30 29 21 20 16 15 10 9 5 4 0
5576 * +---+---+-------------------+--------+-------------+------+------+
5577 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5578 * +---+---+-------------------+--------+-------------+------+------+
5580 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5582 static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
5583 int imm5)
5585 int size = ctz32(imm5);
5586 int esize = 8 << size;
5587 int elements = (is_q ? 128 : 64)/esize;
5588 int i = 0;
5590 if (size > 3 || ((size == 3) && !is_q)) {
5591 unallocated_encoding(s);
5592 return;
5595 if (!fp_access_check(s)) {
5596 return;
5599 for (i = 0; i < elements; i++) {
5600 write_vec_element(s, cpu_reg(s, rn), rd, i, size);
5602 if (!is_q) {
5603 clear_vec_high(s, rd);
5607 /* C6.3.150 INS (Element)
5609 * 31 21 20 16 15 14 11 10 9 5 4 0
5610 * +-----------------------+--------+------------+---+------+------+
5611 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5612 * +-----------------------+--------+------------+---+------+------+
5614 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5615 * index: encoded in imm5<4:size+1>
5617 static void handle_simd_inse(DisasContext *s, int rd, int rn,
5618 int imm4, int imm5)
5620 int size = ctz32(imm5);
5621 int src_index, dst_index;
5622 TCGv_i64 tmp;
5624 if (size > 3) {
5625 unallocated_encoding(s);
5626 return;
5629 if (!fp_access_check(s)) {
5630 return;
5633 dst_index = extract32(imm5, 1+size, 5);
5634 src_index = extract32(imm4, size, 4);
5636 tmp = tcg_temp_new_i64();
5638 read_vec_element(s, tmp, rn, src_index, size);
5639 write_vec_element(s, tmp, rd, dst_index, size);
5641 tcg_temp_free_i64(tmp);
5645 /* C6.3.151 INS (General)
5647 * 31 21 20 16 15 10 9 5 4 0
5648 * +-----------------------+--------+-------------+------+------+
5649 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5650 * +-----------------------+--------+-------------+------+------+
5652 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5653 * index: encoded in imm5<4:size+1>
5655 static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
5657 int size = ctz32(imm5);
5658 int idx;
5660 if (size > 3) {
5661 unallocated_encoding(s);
5662 return;
5665 if (!fp_access_check(s)) {
5666 return;
5669 idx = extract32(imm5, 1 + size, 4 - size);
5670 write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
5674 * C6.3.321 UMOV (General)
5675 * C6.3.237 SMOV (General)
5677 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5678 * +---+---+-------------------+--------+-------------+------+------+
5679 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5680 * +---+---+-------------------+--------+-------------+------+------+
5682 * U: unsigned when set
5683 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5685 static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
5686 int rn, int rd, int imm5)
5688 int size = ctz32(imm5);
5689 int element;
5690 TCGv_i64 tcg_rd;
5692 /* Check for UnallocatedEncodings */
5693 if (is_signed) {
5694 if (size > 2 || (size == 2 && !is_q)) {
5695 unallocated_encoding(s);
5696 return;
5698 } else {
5699 if (size > 3
5700 || (size < 3 && is_q)
5701 || (size == 3 && !is_q)) {
5702 unallocated_encoding(s);
5703 return;
5707 if (!fp_access_check(s)) {
5708 return;
5711 element = extract32(imm5, 1+size, 4);
5713 tcg_rd = cpu_reg(s, rd);
5714 read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0));
5715 if (is_signed && !is_q) {
5716 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
5720 /* C3.6.5 AdvSIMD copy
5721 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5722 * +---+---+----+-----------------+------+---+------+---+------+------+
5723 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5724 * +---+---+----+-----------------+------+---+------+---+------+------+
5726 static void disas_simd_copy(DisasContext *s, uint32_t insn)
5728 int rd = extract32(insn, 0, 5);
5729 int rn = extract32(insn, 5, 5);
5730 int imm4 = extract32(insn, 11, 4);
5731 int op = extract32(insn, 29, 1);
5732 int is_q = extract32(insn, 30, 1);
5733 int imm5 = extract32(insn, 16, 5);
5735 if (op) {
5736 if (is_q) {
5737 /* INS (element) */
5738 handle_simd_inse(s, rd, rn, imm4, imm5);
5739 } else {
5740 unallocated_encoding(s);
5742 } else {
5743 switch (imm4) {
5744 case 0:
5745 /* DUP (element - vector) */
5746 handle_simd_dupe(s, is_q, rd, rn, imm5);
5747 break;
5748 case 1:
5749 /* DUP (general) */
5750 handle_simd_dupg(s, is_q, rd, rn, imm5);
5751 break;
5752 case 3:
5753 if (is_q) {
5754 /* INS (general) */
5755 handle_simd_insg(s, rd, rn, imm5);
5756 } else {
5757 unallocated_encoding(s);
5759 break;
5760 case 5:
5761 case 7:
5762 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5763 handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5);
5764 break;
5765 default:
5766 unallocated_encoding(s);
5767 break;
5772 /* C3.6.6 AdvSIMD modified immediate
5773 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5774 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5775 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5776 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5778 * There are a number of operations that can be carried out here:
5779 * MOVI - move (shifted) imm into register
5780 * MVNI - move inverted (shifted) imm into register
5781 * ORR - bitwise OR of (shifted) imm with register
5782 * BIC - bitwise clear of (shifted) imm with register
5784 static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
5786 int rd = extract32(insn, 0, 5);
5787 int cmode = extract32(insn, 12, 4);
5788 int cmode_3_1 = extract32(cmode, 1, 3);
5789 int cmode_0 = extract32(cmode, 0, 1);
5790 int o2 = extract32(insn, 11, 1);
5791 uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
5792 bool is_neg = extract32(insn, 29, 1);
5793 bool is_q = extract32(insn, 30, 1);
5794 uint64_t imm = 0;
5795 TCGv_i64 tcg_rd, tcg_imm;
5796 int i;
5798 if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
5799 unallocated_encoding(s);
5800 return;
5803 if (!fp_access_check(s)) {
5804 return;
5807 /* See AdvSIMDExpandImm() in ARM ARM */
5808 switch (cmode_3_1) {
5809 case 0: /* Replicate(Zeros(24):imm8, 2) */
5810 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5811 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5812 case 3: /* Replicate(imm8:Zeros(24), 2) */
5814 int shift = cmode_3_1 * 8;
5815 imm = bitfield_replicate(abcdefgh << shift, 32);
5816 break;
5818 case 4: /* Replicate(Zeros(8):imm8, 4) */
5819 case 5: /* Replicate(imm8:Zeros(8), 4) */
5821 int shift = (cmode_3_1 & 0x1) * 8;
5822 imm = bitfield_replicate(abcdefgh << shift, 16);
5823 break;
5825 case 6:
5826 if (cmode_0) {
5827 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5828 imm = (abcdefgh << 16) | 0xffff;
5829 } else {
5830 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5831 imm = (abcdefgh << 8) | 0xff;
5833 imm = bitfield_replicate(imm, 32);
5834 break;
5835 case 7:
5836 if (!cmode_0 && !is_neg) {
5837 imm = bitfield_replicate(abcdefgh, 8);
5838 } else if (!cmode_0 && is_neg) {
5839 int i;
5840 imm = 0;
5841 for (i = 0; i < 8; i++) {
5842 if ((abcdefgh) & (1 << i)) {
5843 imm |= 0xffULL << (i * 8);
5846 } else if (cmode_0) {
5847 if (is_neg) {
5848 imm = (abcdefgh & 0x3f) << 48;
5849 if (abcdefgh & 0x80) {
5850 imm |= 0x8000000000000000ULL;
5852 if (abcdefgh & 0x40) {
5853 imm |= 0x3fc0000000000000ULL;
5854 } else {
5855 imm |= 0x4000000000000000ULL;
5857 } else {
5858 imm = (abcdefgh & 0x3f) << 19;
5859 if (abcdefgh & 0x80) {
5860 imm |= 0x80000000;
5862 if (abcdefgh & 0x40) {
5863 imm |= 0x3e000000;
5864 } else {
5865 imm |= 0x40000000;
5867 imm |= (imm << 32);
5870 break;
5873 if (cmode_3_1 != 7 && is_neg) {
5874 imm = ~imm;
5877 tcg_imm = tcg_const_i64(imm);
5878 tcg_rd = new_tmp_a64(s);
5880 for (i = 0; i < 2; i++) {
5881 int foffs = i ? fp_reg_hi_offset(s, rd) : fp_reg_offset(s, rd, MO_64);
5883 if (i == 1 && !is_q) {
5884 /* non-quad ops clear high half of vector */
5885 tcg_gen_movi_i64(tcg_rd, 0);
5886 } else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) {
5887 tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
5888 if (is_neg) {
5889 /* AND (BIC) */
5890 tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
5891 } else {
5892 /* ORR */
5893 tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
5895 } else {
5896 /* MOVI */
5897 tcg_gen_mov_i64(tcg_rd, tcg_imm);
5899 tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
5902 tcg_temp_free_i64(tcg_imm);
5905 /* C3.6.7 AdvSIMD scalar copy
5906 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5907 * +-----+----+-----------------+------+---+------+---+------+------+
5908 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5909 * +-----+----+-----------------+------+---+------+---+------+------+
5911 static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
5913 int rd = extract32(insn, 0, 5);
5914 int rn = extract32(insn, 5, 5);
5915 int imm4 = extract32(insn, 11, 4);
5916 int imm5 = extract32(insn, 16, 5);
5917 int op = extract32(insn, 29, 1);
5919 if (op != 0 || imm4 != 0) {
5920 unallocated_encoding(s);
5921 return;
5924 /* DUP (element, scalar) */
5925 handle_simd_dupes(s, rd, rn, imm5);
5928 /* C3.6.8 AdvSIMD scalar pairwise
5929 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5930 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5931 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5932 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5934 static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
5936 int u = extract32(insn, 29, 1);
5937 int size = extract32(insn, 22, 2);
5938 int opcode = extract32(insn, 12, 5);
5939 int rn = extract32(insn, 5, 5);
5940 int rd = extract32(insn, 0, 5);
5941 TCGv_ptr fpst;
5943 /* For some ops (the FP ones), size[1] is part of the encoding.
5944 * For ADDP strictly it is not but size[1] is always 1 for valid
5945 * encodings.
5947 opcode |= (extract32(size, 1, 1) << 5);
5949 switch (opcode) {
5950 case 0x3b: /* ADDP */
5951 if (u || size != 3) {
5952 unallocated_encoding(s);
5953 return;
5955 if (!fp_access_check(s)) {
5956 return;
5959 TCGV_UNUSED_PTR(fpst);
5960 break;
5961 case 0xc: /* FMAXNMP */
5962 case 0xd: /* FADDP */
5963 case 0xf: /* FMAXP */
5964 case 0x2c: /* FMINNMP */
5965 case 0x2f: /* FMINP */
5966 /* FP op, size[0] is 32 or 64 bit */
5967 if (!u) {
5968 unallocated_encoding(s);
5969 return;
5971 if (!fp_access_check(s)) {
5972 return;
5975 size = extract32(size, 0, 1) ? 3 : 2;
5976 fpst = get_fpstatus_ptr();
5977 break;
5978 default:
5979 unallocated_encoding(s);
5980 return;
5983 if (size == 3) {
5984 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
5985 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
5986 TCGv_i64 tcg_res = tcg_temp_new_i64();
5988 read_vec_element(s, tcg_op1, rn, 0, MO_64);
5989 read_vec_element(s, tcg_op2, rn, 1, MO_64);
5991 switch (opcode) {
5992 case 0x3b: /* ADDP */
5993 tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2);
5994 break;
5995 case 0xc: /* FMAXNMP */
5996 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
5997 break;
5998 case 0xd: /* FADDP */
5999 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
6000 break;
6001 case 0xf: /* FMAXP */
6002 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
6003 break;
6004 case 0x2c: /* FMINNMP */
6005 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
6006 break;
6007 case 0x2f: /* FMINP */
6008 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
6009 break;
6010 default:
6011 g_assert_not_reached();
6014 write_fp_dreg(s, rd, tcg_res);
6016 tcg_temp_free_i64(tcg_op1);
6017 tcg_temp_free_i64(tcg_op2);
6018 tcg_temp_free_i64(tcg_res);
6019 } else {
6020 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
6021 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
6022 TCGv_i32 tcg_res = tcg_temp_new_i32();
6024 read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
6025 read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
6027 switch (opcode) {
6028 case 0xc: /* FMAXNMP */
6029 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
6030 break;
6031 case 0xd: /* FADDP */
6032 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
6033 break;
6034 case 0xf: /* FMAXP */
6035 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
6036 break;
6037 case 0x2c: /* FMINNMP */
6038 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
6039 break;
6040 case 0x2f: /* FMINP */
6041 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
6042 break;
6043 default:
6044 g_assert_not_reached();
6047 write_fp_sreg(s, rd, tcg_res);
6049 tcg_temp_free_i32(tcg_op1);
6050 tcg_temp_free_i32(tcg_op2);
6051 tcg_temp_free_i32(tcg_res);
6054 if (!TCGV_IS_UNUSED_PTR(fpst)) {
6055 tcg_temp_free_ptr(fpst);
6060 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
6062 * This code is handles the common shifting code and is used by both
6063 * the vector and scalar code.
6065 static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
6066 TCGv_i64 tcg_rnd, bool accumulate,
6067 bool is_u, int size, int shift)
6069 bool extended_result = false;
6070 bool round = !TCGV_IS_UNUSED_I64(tcg_rnd);
6071 int ext_lshift = 0;
6072 TCGv_i64 tcg_src_hi;
6074 if (round && size == 3) {
6075 extended_result = true;
6076 ext_lshift = 64 - shift;
6077 tcg_src_hi = tcg_temp_new_i64();
6078 } else if (shift == 64) {
6079 if (!accumulate && is_u) {
6080 /* result is zero */
6081 tcg_gen_movi_i64(tcg_res, 0);
6082 return;
6086 /* Deal with the rounding step */
6087 if (round) {
6088 if (extended_result) {
6089 TCGv_i64 tcg_zero = tcg_const_i64(0);
6090 if (!is_u) {
6091 /* take care of sign extending tcg_res */
6092 tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
6093 tcg_gen_add2_i64(tcg_src, tcg_src_hi,
6094 tcg_src, tcg_src_hi,
6095 tcg_rnd, tcg_zero);
6096 } else {
6097 tcg_gen_add2_i64(tcg_src, tcg_src_hi,
6098 tcg_src, tcg_zero,
6099 tcg_rnd, tcg_zero);
6101 tcg_temp_free_i64(tcg_zero);
6102 } else {
6103 tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
6107 /* Now do the shift right */
6108 if (round && extended_result) {
6109 /* extended case, >64 bit precision required */
6110 if (ext_lshift == 0) {
6111 /* special case, only high bits matter */
6112 tcg_gen_mov_i64(tcg_src, tcg_src_hi);
6113 } else {
6114 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
6115 tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift);
6116 tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi);
6118 } else {
6119 if (is_u) {
6120 if (shift == 64) {
6121 /* essentially shifting in 64 zeros */
6122 tcg_gen_movi_i64(tcg_src, 0);
6123 } else {
6124 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
6126 } else {
6127 if (shift == 64) {
6128 /* effectively extending the sign-bit */
6129 tcg_gen_sari_i64(tcg_src, tcg_src, 63);
6130 } else {
6131 tcg_gen_sari_i64(tcg_src, tcg_src, shift);
6136 if (accumulate) {
6137 tcg_gen_add_i64(tcg_res, tcg_res, tcg_src);
6138 } else {
6139 tcg_gen_mov_i64(tcg_res, tcg_src);
6142 if (extended_result) {
6143 tcg_temp_free_i64(tcg_src_hi);
6147 /* Common SHL/SLI - Shift left with an optional insert */
6148 static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
6149 bool insert, int shift)
6151 if (insert) { /* SLI */
6152 tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift);
6153 } else { /* SHL */
6154 tcg_gen_shli_i64(tcg_res, tcg_src, shift);
6158 /* SRI: shift right with insert */
6159 static void handle_shri_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
6160 int size, int shift)
6162 int esize = 8 << size;
6164 /* shift count same as element size is valid but does nothing;
6165 * special case to avoid potential shift by 64.
6167 if (shift != esize) {
6168 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
6169 tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, 0, esize - shift);
6173 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6174 static void handle_scalar_simd_shri(DisasContext *s,
6175 bool is_u, int immh, int immb,
6176 int opcode, int rn, int rd)
6178 const int size = 3;
6179 int immhb = immh << 3 | immb;
6180 int shift = 2 * (8 << size) - immhb;
6181 bool accumulate = false;
6182 bool round = false;
6183 bool insert = false;
6184 TCGv_i64 tcg_rn;
6185 TCGv_i64 tcg_rd;
6186 TCGv_i64 tcg_round;
6188 if (!extract32(immh, 3, 1)) {
6189 unallocated_encoding(s);
6190 return;
6193 if (!fp_access_check(s)) {
6194 return;
6197 switch (opcode) {
6198 case 0x02: /* SSRA / USRA (accumulate) */
6199 accumulate = true;
6200 break;
6201 case 0x04: /* SRSHR / URSHR (rounding) */
6202 round = true;
6203 break;
6204 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6205 accumulate = round = true;
6206 break;
6207 case 0x08: /* SRI */
6208 insert = true;
6209 break;
6212 if (round) {
6213 uint64_t round_const = 1ULL << (shift - 1);
6214 tcg_round = tcg_const_i64(round_const);
6215 } else {
6216 TCGV_UNUSED_I64(tcg_round);
6219 tcg_rn = read_fp_dreg(s, rn);
6220 tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
6222 if (insert) {
6223 handle_shri_with_ins(tcg_rd, tcg_rn, size, shift);
6224 } else {
6225 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
6226 accumulate, is_u, size, shift);
6229 write_fp_dreg(s, rd, tcg_rd);
6231 tcg_temp_free_i64(tcg_rn);
6232 tcg_temp_free_i64(tcg_rd);
6233 if (round) {
6234 tcg_temp_free_i64(tcg_round);
6238 /* SHL/SLI - Scalar shift left */
6239 static void handle_scalar_simd_shli(DisasContext *s, bool insert,
6240 int immh, int immb, int opcode,
6241 int rn, int rd)
6243 int size = 32 - clz32(immh) - 1;
6244 int immhb = immh << 3 | immb;
6245 int shift = immhb - (8 << size);
6246 TCGv_i64 tcg_rn = new_tmp_a64(s);
6247 TCGv_i64 tcg_rd = new_tmp_a64(s);
6249 if (!extract32(immh, 3, 1)) {
6250 unallocated_encoding(s);
6251 return;
6254 if (!fp_access_check(s)) {
6255 return;
6258 tcg_rn = read_fp_dreg(s, rn);
6259 tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
6261 handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
6263 write_fp_dreg(s, rd, tcg_rd);
6265 tcg_temp_free_i64(tcg_rn);
6266 tcg_temp_free_i64(tcg_rd);
6269 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6270 * (signed/unsigned) narrowing */
6271 static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
6272 bool is_u_shift, bool is_u_narrow,
6273 int immh, int immb, int opcode,
6274 int rn, int rd)
6276 int immhb = immh << 3 | immb;
6277 int size = 32 - clz32(immh) - 1;
6278 int esize = 8 << size;
6279 int shift = (2 * esize) - immhb;
6280 int elements = is_scalar ? 1 : (64 / esize);
6281 bool round = extract32(opcode, 0, 1);
6282 TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);
6283 TCGv_i64 tcg_rn, tcg_rd, tcg_round;
6284 TCGv_i32 tcg_rd_narrowed;
6285 TCGv_i64 tcg_final;
6287 static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = {
6288 { gen_helper_neon_narrow_sat_s8,
6289 gen_helper_neon_unarrow_sat8 },
6290 { gen_helper_neon_narrow_sat_s16,
6291 gen_helper_neon_unarrow_sat16 },
6292 { gen_helper_neon_narrow_sat_s32,
6293 gen_helper_neon_unarrow_sat32 },
6294 { NULL, NULL },
6296 static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = {
6297 gen_helper_neon_narrow_sat_u8,
6298 gen_helper_neon_narrow_sat_u16,
6299 gen_helper_neon_narrow_sat_u32,
6300 NULL
6302 NeonGenNarrowEnvFn *narrowfn;
6304 int i;
6306 assert(size < 4);
6308 if (extract32(immh, 3, 1)) {
6309 unallocated_encoding(s);
6310 return;
6313 if (!fp_access_check(s)) {
6314 return;
6317 if (is_u_shift) {
6318 narrowfn = unsigned_narrow_fns[size];
6319 } else {
6320 narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0];
6323 tcg_rn = tcg_temp_new_i64();
6324 tcg_rd = tcg_temp_new_i64();
6325 tcg_rd_narrowed = tcg_temp_new_i32();
6326 tcg_final = tcg_const_i64(0);
6328 if (round) {
6329 uint64_t round_const = 1ULL << (shift - 1);
6330 tcg_round = tcg_const_i64(round_const);
6331 } else {
6332 TCGV_UNUSED_I64(tcg_round);
6335 for (i = 0; i < elements; i++) {
6336 read_vec_element(s, tcg_rn, rn, i, ldop);
6337 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
6338 false, is_u_shift, size+1, shift);
6339 narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
6340 tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
6341 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
6344 if (!is_q) {
6345 clear_vec_high(s, rd);
6346 write_vec_element(s, tcg_final, rd, 0, MO_64);
6347 } else {
6348 write_vec_element(s, tcg_final, rd, 1, MO_64);
6351 if (round) {
6352 tcg_temp_free_i64(tcg_round);
6354 tcg_temp_free_i64(tcg_rn);
6355 tcg_temp_free_i64(tcg_rd);
6356 tcg_temp_free_i32(tcg_rd_narrowed);
6357 tcg_temp_free_i64(tcg_final);
6358 return;
6361 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6362 static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
6363 bool src_unsigned, bool dst_unsigned,
6364 int immh, int immb, int rn, int rd)
6366 int immhb = immh << 3 | immb;
6367 int size = 32 - clz32(immh) - 1;
6368 int shift = immhb - (8 << size);
6369 int pass;
6371 assert(immh != 0);
6372 assert(!(scalar && is_q));
6374 if (!scalar) {
6375 if (!is_q && extract32(immh, 3, 1)) {
6376 unallocated_encoding(s);
6377 return;
6380 /* Since we use the variable-shift helpers we must
6381 * replicate the shift count into each element of
6382 * the tcg_shift value.
6384 switch (size) {
6385 case 0:
6386 shift |= shift << 8;
6387 /* fall through */
6388 case 1:
6389 shift |= shift << 16;
6390 break;
6391 case 2:
6392 case 3:
6393 break;
6394 default:
6395 g_assert_not_reached();
6399 if (!fp_access_check(s)) {
6400 return;
6403 if (size == 3) {
6404 TCGv_i64 tcg_shift = tcg_const_i64(shift);
6405 static NeonGenTwo64OpEnvFn * const fns[2][2] = {
6406 { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
6407 { NULL, gen_helper_neon_qshl_u64 },
6409 NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned];
6410 int maxpass = is_q ? 2 : 1;
6412 for (pass = 0; pass < maxpass; pass++) {
6413 TCGv_i64 tcg_op = tcg_temp_new_i64();
6415 read_vec_element(s, tcg_op, rn, pass, MO_64);
6416 genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
6417 write_vec_element(s, tcg_op, rd, pass, MO_64);
6419 tcg_temp_free_i64(tcg_op);
6421 tcg_temp_free_i64(tcg_shift);
6423 if (!is_q) {
6424 clear_vec_high(s, rd);
6426 } else {
6427 TCGv_i32 tcg_shift = tcg_const_i32(shift);
6428 static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
6430 { gen_helper_neon_qshl_s8,
6431 gen_helper_neon_qshl_s16,
6432 gen_helper_neon_qshl_s32 },
6433 { gen_helper_neon_qshlu_s8,
6434 gen_helper_neon_qshlu_s16,
6435 gen_helper_neon_qshlu_s32 }
6436 }, {
6437 { NULL, NULL, NULL },
6438 { gen_helper_neon_qshl_u8,
6439 gen_helper_neon_qshl_u16,
6440 gen_helper_neon_qshl_u32 }
6443 NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];
6444 TCGMemOp memop = scalar ? size : MO_32;
6445 int maxpass = scalar ? 1 : is_q ? 4 : 2;
6447 for (pass = 0; pass < maxpass; pass++) {
6448 TCGv_i32 tcg_op = tcg_temp_new_i32();
6450 read_vec_element_i32(s, tcg_op, rn, pass, memop);
6451 genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
6452 if (scalar) {
6453 switch (size) {
6454 case 0:
6455 tcg_gen_ext8u_i32(tcg_op, tcg_op);
6456 break;
6457 case 1:
6458 tcg_gen_ext16u_i32(tcg_op, tcg_op);
6459 break;
6460 case 2:
6461 break;
6462 default:
6463 g_assert_not_reached();
6465 write_fp_sreg(s, rd, tcg_op);
6466 } else {
6467 write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
6470 tcg_temp_free_i32(tcg_op);
6472 tcg_temp_free_i32(tcg_shift);
6474 if (!is_q && !scalar) {
6475 clear_vec_high(s, rd);
6480 /* Common vector code for handling integer to FP conversion */
6481 static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
6482 int elements, int is_signed,
6483 int fracbits, int size)
6485 bool is_double = size == 3 ? true : false;
6486 TCGv_ptr tcg_fpst = get_fpstatus_ptr();
6487 TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
6488 TCGv_i64 tcg_int = tcg_temp_new_i64();
6489 TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
6490 int pass;
6492 for (pass = 0; pass < elements; pass++) {
6493 read_vec_element(s, tcg_int, rn, pass, mop);
6495 if (is_double) {
6496 TCGv_i64 tcg_double = tcg_temp_new_i64();
6497 if (is_signed) {
6498 gen_helper_vfp_sqtod(tcg_double, tcg_int,
6499 tcg_shift, tcg_fpst);
6500 } else {
6501 gen_helper_vfp_uqtod(tcg_double, tcg_int,
6502 tcg_shift, tcg_fpst);
6504 if (elements == 1) {
6505 write_fp_dreg(s, rd, tcg_double);
6506 } else {
6507 write_vec_element(s, tcg_double, rd, pass, MO_64);
6509 tcg_temp_free_i64(tcg_double);
6510 } else {
6511 TCGv_i32 tcg_single = tcg_temp_new_i32();
6512 if (is_signed) {
6513 gen_helper_vfp_sqtos(tcg_single, tcg_int,
6514 tcg_shift, tcg_fpst);
6515 } else {
6516 gen_helper_vfp_uqtos(tcg_single, tcg_int,
6517 tcg_shift, tcg_fpst);
6519 if (elements == 1) {
6520 write_fp_sreg(s, rd, tcg_single);
6521 } else {
6522 write_vec_element_i32(s, tcg_single, rd, pass, MO_32);
6524 tcg_temp_free_i32(tcg_single);
6528 if (!is_double && elements == 2) {
6529 clear_vec_high(s, rd);
6532 tcg_temp_free_i64(tcg_int);
6533 tcg_temp_free_ptr(tcg_fpst);
6534 tcg_temp_free_i32(tcg_shift);
6537 /* UCVTF/SCVTF - Integer to FP conversion */
6538 static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
6539 bool is_q, bool is_u,
6540 int immh, int immb, int opcode,
6541 int rn, int rd)
6543 bool is_double = extract32(immh, 3, 1);
6544 int size = is_double ? MO_64 : MO_32;
6545 int elements;
6546 int immhb = immh << 3 | immb;
6547 int fracbits = (is_double ? 128 : 64) - immhb;
6549 if (!extract32(immh, 2, 2)) {
6550 unallocated_encoding(s);
6551 return;
6554 if (is_scalar) {
6555 elements = 1;
6556 } else {
6557 elements = is_double ? 2 : is_q ? 4 : 2;
6558 if (is_double && !is_q) {
6559 unallocated_encoding(s);
6560 return;
6564 if (!fp_access_check(s)) {
6565 return;
6568 /* immh == 0 would be a failure of the decode logic */
6569 g_assert(immh);
6571 handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
6574 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6575 static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
6576 bool is_q, bool is_u,
6577 int immh, int immb, int rn, int rd)
6579 bool is_double = extract32(immh, 3, 1);
6580 int immhb = immh << 3 | immb;
6581 int fracbits = (is_double ? 128 : 64) - immhb;
6582 int pass;
6583 TCGv_ptr tcg_fpstatus;
6584 TCGv_i32 tcg_rmode, tcg_shift;
6586 if (!extract32(immh, 2, 2)) {
6587 unallocated_encoding(s);
6588 return;
6591 if (!is_scalar && !is_q && is_double) {
6592 unallocated_encoding(s);
6593 return;
6596 if (!fp_access_check(s)) {
6597 return;
6600 assert(!(is_scalar && is_q));
6602 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
6603 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
6604 tcg_fpstatus = get_fpstatus_ptr();
6605 tcg_shift = tcg_const_i32(fracbits);
6607 if (is_double) {
6608 int maxpass = is_scalar ? 1 : 2;
6610 for (pass = 0; pass < maxpass; pass++) {
6611 TCGv_i64 tcg_op = tcg_temp_new_i64();
6613 read_vec_element(s, tcg_op, rn, pass, MO_64);
6614 if (is_u) {
6615 gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
6616 } else {
6617 gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
6619 write_vec_element(s, tcg_op, rd, pass, MO_64);
6620 tcg_temp_free_i64(tcg_op);
6622 if (!is_q) {
6623 clear_vec_high(s, rd);
6625 } else {
6626 int maxpass = is_scalar ? 1 : is_q ? 4 : 2;
6627 for (pass = 0; pass < maxpass; pass++) {
6628 TCGv_i32 tcg_op = tcg_temp_new_i32();
6630 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
6631 if (is_u) {
6632 gen_helper_vfp_touls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
6633 } else {
6634 gen_helper_vfp_tosls(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
6636 if (is_scalar) {
6637 write_fp_sreg(s, rd, tcg_op);
6638 } else {
6639 write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
6641 tcg_temp_free_i32(tcg_op);
6643 if (!is_q && !is_scalar) {
6644 clear_vec_high(s, rd);
6648 tcg_temp_free_ptr(tcg_fpstatus);
6649 tcg_temp_free_i32(tcg_shift);
6650 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
6651 tcg_temp_free_i32(tcg_rmode);
6654 /* C3.6.9 AdvSIMD scalar shift by immediate
6655 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6656 * +-----+---+-------------+------+------+--------+---+------+------+
6657 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6658 * +-----+---+-------------+------+------+--------+---+------+------+
6660 * This is the scalar version so it works on a fixed sized registers
6662 static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
6664 int rd = extract32(insn, 0, 5);
6665 int rn = extract32(insn, 5, 5);
6666 int opcode = extract32(insn, 11, 5);
6667 int immb = extract32(insn, 16, 3);
6668 int immh = extract32(insn, 19, 4);
6669 bool is_u = extract32(insn, 29, 1);
6671 if (immh == 0) {
6672 unallocated_encoding(s);
6673 return;
6676 switch (opcode) {
6677 case 0x08: /* SRI */
6678 if (!is_u) {
6679 unallocated_encoding(s);
6680 return;
6682 /* fall through */
6683 case 0x00: /* SSHR / USHR */
6684 case 0x02: /* SSRA / USRA */
6685 case 0x04: /* SRSHR / URSHR */
6686 case 0x06: /* SRSRA / URSRA */
6687 handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd);
6688 break;
6689 case 0x0a: /* SHL / SLI */
6690 handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd);
6691 break;
6692 case 0x1c: /* SCVTF, UCVTF */
6693 handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
6694 opcode, rn, rd);
6695 break;
6696 case 0x10: /* SQSHRUN, SQSHRUN2 */
6697 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6698 if (!is_u) {
6699 unallocated_encoding(s);
6700 return;
6702 handle_vec_simd_sqshrn(s, true, false, false, true,
6703 immh, immb, opcode, rn, rd);
6704 break;
6705 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6706 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6707 handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
6708 immh, immb, opcode, rn, rd);
6709 break;
6710 case 0xc: /* SQSHLU */
6711 if (!is_u) {
6712 unallocated_encoding(s);
6713 return;
6715 handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd);
6716 break;
6717 case 0xe: /* SQSHL, UQSHL */
6718 handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd);
6719 break;
6720 case 0x1f: /* FCVTZS, FCVTZU */
6721 handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
6722 break;
6723 default:
6724 unallocated_encoding(s);
6725 break;
6729 /* C3.6.10 AdvSIMD scalar three different
6730 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6731 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6732 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6733 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6735 static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
6737 bool is_u = extract32(insn, 29, 1);
6738 int size = extract32(insn, 22, 2);
6739 int opcode = extract32(insn, 12, 4);
6740 int rm = extract32(insn, 16, 5);
6741 int rn = extract32(insn, 5, 5);
6742 int rd = extract32(insn, 0, 5);
6744 if (is_u) {
6745 unallocated_encoding(s);
6746 return;
6749 switch (opcode) {
6750 case 0x9: /* SQDMLAL, SQDMLAL2 */
6751 case 0xb: /* SQDMLSL, SQDMLSL2 */
6752 case 0xd: /* SQDMULL, SQDMULL2 */
6753 if (size == 0 || size == 3) {
6754 unallocated_encoding(s);
6755 return;
6757 break;
6758 default:
6759 unallocated_encoding(s);
6760 return;
6763 if (!fp_access_check(s)) {
6764 return;
6767 if (size == 2) {
6768 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
6769 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
6770 TCGv_i64 tcg_res = tcg_temp_new_i64();
6772 read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);
6773 read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
6775 tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);
6776 gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res);
6778 switch (opcode) {
6779 case 0xd: /* SQDMULL, SQDMULL2 */
6780 break;
6781 case 0xb: /* SQDMLSL, SQDMLSL2 */
6782 tcg_gen_neg_i64(tcg_res, tcg_res);
6783 /* fall through */
6784 case 0x9: /* SQDMLAL, SQDMLAL2 */
6785 read_vec_element(s, tcg_op1, rd, 0, MO_64);
6786 gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env,
6787 tcg_res, tcg_op1);
6788 break;
6789 default:
6790 g_assert_not_reached();
6793 write_fp_dreg(s, rd, tcg_res);
6795 tcg_temp_free_i64(tcg_op1);
6796 tcg_temp_free_i64(tcg_op2);
6797 tcg_temp_free_i64(tcg_res);
6798 } else {
6799 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
6800 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
6801 TCGv_i64 tcg_res = tcg_temp_new_i64();
6803 read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
6804 read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
6806 gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
6807 gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
6809 switch (opcode) {
6810 case 0xd: /* SQDMULL, SQDMULL2 */
6811 break;
6812 case 0xb: /* SQDMLSL, SQDMLSL2 */
6813 gen_helper_neon_negl_u32(tcg_res, tcg_res);
6814 /* fall through */
6815 case 0x9: /* SQDMLAL, SQDMLAL2 */
6817 TCGv_i64 tcg_op3 = tcg_temp_new_i64();
6818 read_vec_element(s, tcg_op3, rd, 0, MO_32);
6819 gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env,
6820 tcg_res, tcg_op3);
6821 tcg_temp_free_i64(tcg_op3);
6822 break;
6824 default:
6825 g_assert_not_reached();
6828 tcg_gen_ext32u_i64(tcg_res, tcg_res);
6829 write_fp_dreg(s, rd, tcg_res);
6831 tcg_temp_free_i32(tcg_op1);
6832 tcg_temp_free_i32(tcg_op2);
6833 tcg_temp_free_i64(tcg_res);
6837 static void handle_3same_64(DisasContext *s, int opcode, bool u,
6838 TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
6840 /* Handle 64x64->64 opcodes which are shared between the scalar
6841 * and vector 3-same groups. We cover every opcode where size == 3
6842 * is valid in either the three-reg-same (integer, not pairwise)
6843 * or scalar-three-reg-same groups. (Some opcodes are not yet
6844 * implemented.)
6846 TCGCond cond;
6848 switch (opcode) {
6849 case 0x1: /* SQADD */
6850 if (u) {
6851 gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6852 } else {
6853 gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6855 break;
6856 case 0x5: /* SQSUB */
6857 if (u) {
6858 gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6859 } else {
6860 gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6862 break;
6863 case 0x6: /* CMGT, CMHI */
6864 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6865 * We implement this using setcond (test) and then negating.
6867 cond = u ? TCG_COND_GTU : TCG_COND_GT;
6868 do_cmop:
6869 tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm);
6870 tcg_gen_neg_i64(tcg_rd, tcg_rd);
6871 break;
6872 case 0x7: /* CMGE, CMHS */
6873 cond = u ? TCG_COND_GEU : TCG_COND_GE;
6874 goto do_cmop;
6875 case 0x11: /* CMTST, CMEQ */
6876 if (u) {
6877 cond = TCG_COND_EQ;
6878 goto do_cmop;
6880 /* CMTST : test is "if (X & Y != 0)". */
6881 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
6882 tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0);
6883 tcg_gen_neg_i64(tcg_rd, tcg_rd);
6884 break;
6885 case 0x8: /* SSHL, USHL */
6886 if (u) {
6887 gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm);
6888 } else {
6889 gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm);
6891 break;
6892 case 0x9: /* SQSHL, UQSHL */
6893 if (u) {
6894 gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6895 } else {
6896 gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6898 break;
6899 case 0xa: /* SRSHL, URSHL */
6900 if (u) {
6901 gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm);
6902 } else {
6903 gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm);
6905 break;
6906 case 0xb: /* SQRSHL, UQRSHL */
6907 if (u) {
6908 gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6909 } else {
6910 gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
6912 break;
6913 case 0x10: /* ADD, SUB */
6914 if (u) {
6915 tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm);
6916 } else {
6917 tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm);
6919 break;
6920 default:
6921 g_assert_not_reached();
6925 /* Handle the 3-same-operands float operations; shared by the scalar
6926 * and vector encodings. The caller must filter out any encodings
6927 * not allocated for the encoding it is dealing with.
6929 static void handle_3same_float(DisasContext *s, int size, int elements,
6930 int fpopcode, int rd, int rn, int rm)
6932 int pass;
6933 TCGv_ptr fpst = get_fpstatus_ptr();
6935 for (pass = 0; pass < elements; pass++) {
6936 if (size) {
6937 /* Double */
6938 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
6939 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
6940 TCGv_i64 tcg_res = tcg_temp_new_i64();
6942 read_vec_element(s, tcg_op1, rn, pass, MO_64);
6943 read_vec_element(s, tcg_op2, rm, pass, MO_64);
6945 switch (fpopcode) {
6946 case 0x39: /* FMLS */
6947 /* As usual for ARM, separate negation for fused multiply-add */
6948 gen_helper_vfp_negd(tcg_op1, tcg_op1);
6949 /* fall through */
6950 case 0x19: /* FMLA */
6951 read_vec_element(s, tcg_res, rd, pass, MO_64);
6952 gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2,
6953 tcg_res, fpst);
6954 break;
6955 case 0x18: /* FMAXNM */
6956 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
6957 break;
6958 case 0x1a: /* FADD */
6959 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
6960 break;
6961 case 0x1b: /* FMULX */
6962 gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst);
6963 break;
6964 case 0x1c: /* FCMEQ */
6965 gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst);
6966 break;
6967 case 0x1e: /* FMAX */
6968 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
6969 break;
6970 case 0x1f: /* FRECPS */
6971 gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
6972 break;
6973 case 0x38: /* FMINNM */
6974 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
6975 break;
6976 case 0x3a: /* FSUB */
6977 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
6978 break;
6979 case 0x3e: /* FMIN */
6980 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
6981 break;
6982 case 0x3f: /* FRSQRTS */
6983 gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
6984 break;
6985 case 0x5b: /* FMUL */
6986 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
6987 break;
6988 case 0x5c: /* FCMGE */
6989 gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
6990 break;
6991 case 0x5d: /* FACGE */
6992 gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
6993 break;
6994 case 0x5f: /* FDIV */
6995 gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
6996 break;
6997 case 0x7a: /* FABD */
6998 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
6999 gen_helper_vfp_absd(tcg_res, tcg_res);
7000 break;
7001 case 0x7c: /* FCMGT */
7002 gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7003 break;
7004 case 0x7d: /* FACGT */
7005 gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
7006 break;
7007 default:
7008 g_assert_not_reached();
7011 write_vec_element(s, tcg_res, rd, pass, MO_64);
7013 tcg_temp_free_i64(tcg_res);
7014 tcg_temp_free_i64(tcg_op1);
7015 tcg_temp_free_i64(tcg_op2);
7016 } else {
7017 /* Single */
7018 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
7019 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
7020 TCGv_i32 tcg_res = tcg_temp_new_i32();
7022 read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
7023 read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
7025 switch (fpopcode) {
7026 case 0x39: /* FMLS */
7027 /* As usual for ARM, separate negation for fused multiply-add */
7028 gen_helper_vfp_negs(tcg_op1, tcg_op1);
7029 /* fall through */
7030 case 0x19: /* FMLA */
7031 read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
7032 gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2,
7033 tcg_res, fpst);
7034 break;
7035 case 0x1a: /* FADD */
7036 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
7037 break;
7038 case 0x1b: /* FMULX */
7039 gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst);
7040 break;
7041 case 0x1c: /* FCMEQ */
7042 gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7043 break;
7044 case 0x1e: /* FMAX */
7045 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
7046 break;
7047 case 0x1f: /* FRECPS */
7048 gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7049 break;
7050 case 0x18: /* FMAXNM */
7051 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
7052 break;
7053 case 0x38: /* FMINNM */
7054 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
7055 break;
7056 case 0x3a: /* FSUB */
7057 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
7058 break;
7059 case 0x3e: /* FMIN */
7060 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
7061 break;
7062 case 0x3f: /* FRSQRTS */
7063 gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7064 break;
7065 case 0x5b: /* FMUL */
7066 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
7067 break;
7068 case 0x5c: /* FCMGE */
7069 gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7070 break;
7071 case 0x5d: /* FACGE */
7072 gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7073 break;
7074 case 0x5f: /* FDIV */
7075 gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
7076 break;
7077 case 0x7a: /* FABD */
7078 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
7079 gen_helper_vfp_abss(tcg_res, tcg_res);
7080 break;
7081 case 0x7c: /* FCMGT */
7082 gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7083 break;
7084 case 0x7d: /* FACGT */
7085 gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
7086 break;
7087 default:
7088 g_assert_not_reached();
7091 if (elements == 1) {
7092 /* scalar single so clear high part */
7093 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
7095 tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);
7096 write_vec_element(s, tcg_tmp, rd, pass, MO_64);
7097 tcg_temp_free_i64(tcg_tmp);
7098 } else {
7099 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
7102 tcg_temp_free_i32(tcg_res);
7103 tcg_temp_free_i32(tcg_op1);
7104 tcg_temp_free_i32(tcg_op2);
7108 tcg_temp_free_ptr(fpst);
7110 if ((elements << size) < 4) {
7111 /* scalar, or non-quad vector op */
7112 clear_vec_high(s, rd);
7116 /* C3.6.11 AdvSIMD scalar three same
7117 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
7118 * +-----+---+-----------+------+---+------+--------+---+------+------+
7119 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
7120 * +-----+---+-----------+------+---+------+--------+---+------+------+
7122 static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
7124 int rd = extract32(insn, 0, 5);
7125 int rn = extract32(insn, 5, 5);
7126 int opcode = extract32(insn, 11, 5);
7127 int rm = extract32(insn, 16, 5);
7128 int size = extract32(insn, 22, 2);
7129 bool u = extract32(insn, 29, 1);
7130 TCGv_i64 tcg_rd;
7132 if (opcode >= 0x18) {
7133 /* Floating point: U, size[1] and opcode indicate operation */
7134 int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6);
7135 switch (fpopcode) {
7136 case 0x1b: /* FMULX */
7137 case 0x1f: /* FRECPS */
7138 case 0x3f: /* FRSQRTS */
7139 case 0x5d: /* FACGE */
7140 case 0x7d: /* FACGT */
7141 case 0x1c: /* FCMEQ */
7142 case 0x5c: /* FCMGE */
7143 case 0x7c: /* FCMGT */
7144 case 0x7a: /* FABD */
7145 break;
7146 default:
7147 unallocated_encoding(s);
7148 return;
7151 if (!fp_access_check(s)) {
7152 return;
7155 handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm);
7156 return;
7159 switch (opcode) {
7160 case 0x1: /* SQADD, UQADD */
7161 case 0x5: /* SQSUB, UQSUB */
7162 case 0x9: /* SQSHL, UQSHL */
7163 case 0xb: /* SQRSHL, UQRSHL */
7164 break;
7165 case 0x8: /* SSHL, USHL */
7166 case 0xa: /* SRSHL, URSHL */
7167 case 0x6: /* CMGT, CMHI */
7168 case 0x7: /* CMGE, CMHS */
7169 case 0x11: /* CMTST, CMEQ */
7170 case 0x10: /* ADD, SUB (vector) */
7171 if (size != 3) {
7172 unallocated_encoding(s);
7173 return;
7175 break;
7176 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7177 if (size != 1 && size != 2) {
7178 unallocated_encoding(s);
7179 return;
7181 break;
7182 default:
7183 unallocated_encoding(s);
7184 return;
7187 if (!fp_access_check(s)) {
7188 return;
7191 tcg_rd = tcg_temp_new_i64();
7193 if (size == 3) {
7194 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
7195 TCGv_i64 tcg_rm = read_fp_dreg(s, rm);
7197 handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm);
7198 tcg_temp_free_i64(tcg_rn);
7199 tcg_temp_free_i64(tcg_rm);
7200 } else {
7201 /* Do a single operation on the lowest element in the vector.
7202 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7203 * no side effects for all these operations.
7204 * OPTME: special-purpose helpers would avoid doing some
7205 * unnecessary work in the helper for the 8 and 16 bit cases.
7207 NeonGenTwoOpEnvFn *genenvfn;
7208 TCGv_i32 tcg_rn = tcg_temp_new_i32();
7209 TCGv_i32 tcg_rm = tcg_temp_new_i32();
7210 TCGv_i32 tcg_rd32 = tcg_temp_new_i32();
7212 read_vec_element_i32(s, tcg_rn, rn, 0, size);
7213 read_vec_element_i32(s, tcg_rm, rm, 0, size);
7215 switch (opcode) {
7216 case 0x1: /* SQADD, UQADD */
7218 static NeonGenTwoOpEnvFn * const fns[3][2] = {
7219 { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
7220 { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
7221 { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
7223 genenvfn = fns[size][u];
7224 break;
7226 case 0x5: /* SQSUB, UQSUB */
7228 static NeonGenTwoOpEnvFn * const fns[3][2] = {
7229 { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
7230 { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
7231 { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
7233 genenvfn = fns[size][u];
7234 break;
7236 case 0x9: /* SQSHL, UQSHL */
7238 static NeonGenTwoOpEnvFn * const fns[3][2] = {
7239 { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
7240 { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
7241 { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
7243 genenvfn = fns[size][u];
7244 break;
7246 case 0xb: /* SQRSHL, UQRSHL */
7248 static NeonGenTwoOpEnvFn * const fns[3][2] = {
7249 { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
7250 { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
7251 { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
7253 genenvfn = fns[size][u];
7254 break;
7256 case 0x16: /* SQDMULH, SQRDMULH */
7258 static NeonGenTwoOpEnvFn * const fns[2][2] = {
7259 { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
7260 { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
7262 assert(size == 1 || size == 2);
7263 genenvfn = fns[size - 1][u];
7264 break;
7266 default:
7267 g_assert_not_reached();
7270 genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm);
7271 tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32);
7272 tcg_temp_free_i32(tcg_rd32);
7273 tcg_temp_free_i32(tcg_rn);
7274 tcg_temp_free_i32(tcg_rm);
7277 write_fp_dreg(s, rd, tcg_rd);
7279 tcg_temp_free_i64(tcg_rd);
7282 static void handle_2misc_64(DisasContext *s, int opcode, bool u,
7283 TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
7284 TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
7286 /* Handle 64->64 opcodes which are shared between the scalar and
7287 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7288 * is valid in either group and also the double-precision fp ops.
7289 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7290 * requires them.
7292 TCGCond cond;
7294 switch (opcode) {
7295 case 0x4: /* CLS, CLZ */
7296 if (u) {
7297 gen_helper_clz64(tcg_rd, tcg_rn);
7298 } else {
7299 gen_helper_cls64(tcg_rd, tcg_rn);
7301 break;
7302 case 0x5: /* NOT */
7303 /* This opcode is shared with CNT and RBIT but we have earlier
7304 * enforced that size == 3 if and only if this is the NOT insn.
7306 tcg_gen_not_i64(tcg_rd, tcg_rn);
7307 break;
7308 case 0x7: /* SQABS, SQNEG */
7309 if (u) {
7310 gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn);
7311 } else {
7312 gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn);
7314 break;
7315 case 0xa: /* CMLT */
7316 /* 64 bit integer comparison against zero, result is
7317 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7318 * subtracting 1.
7320 cond = TCG_COND_LT;
7321 do_cmop:
7322 tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0);
7323 tcg_gen_neg_i64(tcg_rd, tcg_rd);
7324 break;
7325 case 0x8: /* CMGT, CMGE */
7326 cond = u ? TCG_COND_GE : TCG_COND_GT;
7327 goto do_cmop;
7328 case 0x9: /* CMEQ, CMLE */
7329 cond = u ? TCG_COND_LE : TCG_COND_EQ;
7330 goto do_cmop;
7331 case 0xb: /* ABS, NEG */
7332 if (u) {
7333 tcg_gen_neg_i64(tcg_rd, tcg_rn);
7334 } else {
7335 TCGv_i64 tcg_zero = tcg_const_i64(0);
7336 tcg_gen_neg_i64(tcg_rd, tcg_rn);
7337 tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero,
7338 tcg_rn, tcg_rd);
7339 tcg_temp_free_i64(tcg_zero);
7341 break;
7342 case 0x2f: /* FABS */
7343 gen_helper_vfp_absd(tcg_rd, tcg_rn);
7344 break;
7345 case 0x6f: /* FNEG */
7346 gen_helper_vfp_negd(tcg_rd, tcg_rn);
7347 break;
7348 case 0x7f: /* FSQRT */
7349 gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env);
7350 break;
7351 case 0x1a: /* FCVTNS */
7352 case 0x1b: /* FCVTMS */
7353 case 0x1c: /* FCVTAS */
7354 case 0x3a: /* FCVTPS */
7355 case 0x3b: /* FCVTZS */
7357 TCGv_i32 tcg_shift = tcg_const_i32(0);
7358 gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
7359 tcg_temp_free_i32(tcg_shift);
7360 break;
7362 case 0x5a: /* FCVTNU */
7363 case 0x5b: /* FCVTMU */
7364 case 0x5c: /* FCVTAU */
7365 case 0x7a: /* FCVTPU */
7366 case 0x7b: /* FCVTZU */
7368 TCGv_i32 tcg_shift = tcg_const_i32(0);
7369 gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
7370 tcg_temp_free_i32(tcg_shift);
7371 break;
7373 case 0x18: /* FRINTN */
7374 case 0x19: /* FRINTM */
7375 case 0x38: /* FRINTP */
7376 case 0x39: /* FRINTZ */
7377 case 0x58: /* FRINTA */
7378 case 0x79: /* FRINTI */
7379 gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus);
7380 break;
7381 case 0x59: /* FRINTX */
7382 gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus);
7383 break;
7384 default:
7385 g_assert_not_reached();
7389 static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
7390 bool is_scalar, bool is_u, bool is_q,
7391 int size, int rn, int rd)
7393 bool is_double = (size == 3);
7394 TCGv_ptr fpst;
7396 if (!fp_access_check(s)) {
7397 return;
7400 fpst = get_fpstatus_ptr();
7402 if (is_double) {
7403 TCGv_i64 tcg_op = tcg_temp_new_i64();
7404 TCGv_i64 tcg_zero = tcg_const_i64(0);
7405 TCGv_i64 tcg_res = tcg_temp_new_i64();
7406 NeonGenTwoDoubleOPFn *genfn;
7407 bool swap = false;
7408 int pass;
7410 switch (opcode) {
7411 case 0x2e: /* FCMLT (zero) */
7412 swap = true;
7413 /* fallthrough */
7414 case 0x2c: /* FCMGT (zero) */
7415 genfn = gen_helper_neon_cgt_f64;
7416 break;
7417 case 0x2d: /* FCMEQ (zero) */
7418 genfn = gen_helper_neon_ceq_f64;
7419 break;
7420 case 0x6d: /* FCMLE (zero) */
7421 swap = true;
7422 /* fall through */
7423 case 0x6c: /* FCMGE (zero) */
7424 genfn = gen_helper_neon_cge_f64;
7425 break;
7426 default:
7427 g_assert_not_reached();
7430 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
7431 read_vec_element(s, tcg_op, rn, pass, MO_64);
7432 if (swap) {
7433 genfn(tcg_res, tcg_zero, tcg_op, fpst);
7434 } else {
7435 genfn(tcg_res, tcg_op, tcg_zero, fpst);
7437 write_vec_element(s, tcg_res, rd, pass, MO_64);
7439 if (is_scalar) {
7440 clear_vec_high(s, rd);
7443 tcg_temp_free_i64(tcg_res);
7444 tcg_temp_free_i64(tcg_zero);
7445 tcg_temp_free_i64(tcg_op);
7446 } else {
7447 TCGv_i32 tcg_op = tcg_temp_new_i32();
7448 TCGv_i32 tcg_zero = tcg_const_i32(0);
7449 TCGv_i32 tcg_res = tcg_temp_new_i32();
7450 NeonGenTwoSingleOPFn *genfn;
7451 bool swap = false;
7452 int pass, maxpasses;
7454 switch (opcode) {
7455 case 0x2e: /* FCMLT (zero) */
7456 swap = true;
7457 /* fall through */
7458 case 0x2c: /* FCMGT (zero) */
7459 genfn = gen_helper_neon_cgt_f32;
7460 break;
7461 case 0x2d: /* FCMEQ (zero) */
7462 genfn = gen_helper_neon_ceq_f32;
7463 break;
7464 case 0x6d: /* FCMLE (zero) */
7465 swap = true;
7466 /* fall through */
7467 case 0x6c: /* FCMGE (zero) */
7468 genfn = gen_helper_neon_cge_f32;
7469 break;
7470 default:
7471 g_assert_not_reached();
7474 if (is_scalar) {
7475 maxpasses = 1;
7476 } else {
7477 maxpasses = is_q ? 4 : 2;
7480 for (pass = 0; pass < maxpasses; pass++) {
7481 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
7482 if (swap) {
7483 genfn(tcg_res, tcg_zero, tcg_op, fpst);
7484 } else {
7485 genfn(tcg_res, tcg_op, tcg_zero, fpst);
7487 if (is_scalar) {
7488 write_fp_sreg(s, rd, tcg_res);
7489 } else {
7490 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
7493 tcg_temp_free_i32(tcg_res);
7494 tcg_temp_free_i32(tcg_zero);
7495 tcg_temp_free_i32(tcg_op);
7496 if (!is_q && !is_scalar) {
7497 clear_vec_high(s, rd);
7501 tcg_temp_free_ptr(fpst);
7504 static void handle_2misc_reciprocal(DisasContext *s, int opcode,
7505 bool is_scalar, bool is_u, bool is_q,
7506 int size, int rn, int rd)
7508 bool is_double = (size == 3);
7509 TCGv_ptr fpst = get_fpstatus_ptr();
7511 if (is_double) {
7512 TCGv_i64 tcg_op = tcg_temp_new_i64();
7513 TCGv_i64 tcg_res = tcg_temp_new_i64();
7514 int pass;
7516 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
7517 read_vec_element(s, tcg_op, rn, pass, MO_64);
7518 switch (opcode) {
7519 case 0x3d: /* FRECPE */
7520 gen_helper_recpe_f64(tcg_res, tcg_op, fpst);
7521 break;
7522 case 0x3f: /* FRECPX */
7523 gen_helper_frecpx_f64(tcg_res, tcg_op, fpst);
7524 break;
7525 case 0x7d: /* FRSQRTE */
7526 gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst);
7527 break;
7528 default:
7529 g_assert_not_reached();
7531 write_vec_element(s, tcg_res, rd, pass, MO_64);
7533 if (is_scalar) {
7534 clear_vec_high(s, rd);
7537 tcg_temp_free_i64(tcg_res);
7538 tcg_temp_free_i64(tcg_op);
7539 } else {
7540 TCGv_i32 tcg_op = tcg_temp_new_i32();
7541 TCGv_i32 tcg_res = tcg_temp_new_i32();
7542 int pass, maxpasses;
7544 if (is_scalar) {
7545 maxpasses = 1;
7546 } else {
7547 maxpasses = is_q ? 4 : 2;
7550 for (pass = 0; pass < maxpasses; pass++) {
7551 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
7553 switch (opcode) {
7554 case 0x3c: /* URECPE */
7555 gen_helper_recpe_u32(tcg_res, tcg_op, fpst);
7556 break;
7557 case 0x3d: /* FRECPE */
7558 gen_helper_recpe_f32(tcg_res, tcg_op, fpst);
7559 break;
7560 case 0x3f: /* FRECPX */
7561 gen_helper_frecpx_f32(tcg_res, tcg_op, fpst);
7562 break;
7563 case 0x7d: /* FRSQRTE */
7564 gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst);
7565 break;
7566 default:
7567 g_assert_not_reached();
7570 if (is_scalar) {
7571 write_fp_sreg(s, rd, tcg_res);
7572 } else {
7573 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
7576 tcg_temp_free_i32(tcg_res);
7577 tcg_temp_free_i32(tcg_op);
7578 if (!is_q && !is_scalar) {
7579 clear_vec_high(s, rd);
7582 tcg_temp_free_ptr(fpst);
7585 static void handle_2misc_narrow(DisasContext *s, bool scalar,
7586 int opcode, bool u, bool is_q,
7587 int size, int rn, int rd)
7589 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7590 * in the source becomes a size element in the destination).
7592 int pass;
7593 TCGv_i32 tcg_res[2];
7594 int destelt = is_q ? 2 : 0;
7595 int passes = scalar ? 1 : 2;
7597 if (scalar) {
7598 tcg_res[1] = tcg_const_i32(0);
7601 for (pass = 0; pass < passes; pass++) {
7602 TCGv_i64 tcg_op = tcg_temp_new_i64();
7603 NeonGenNarrowFn *genfn = NULL;
7604 NeonGenNarrowEnvFn *genenvfn = NULL;
7606 if (scalar) {
7607 read_vec_element(s, tcg_op, rn, pass, size + 1);
7608 } else {
7609 read_vec_element(s, tcg_op, rn, pass, MO_64);
7611 tcg_res[pass] = tcg_temp_new_i32();
7613 switch (opcode) {
7614 case 0x12: /* XTN, SQXTUN */
7616 static NeonGenNarrowFn * const xtnfns[3] = {
7617 gen_helper_neon_narrow_u8,
7618 gen_helper_neon_narrow_u16,
7619 tcg_gen_trunc_i64_i32,
7621 static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
7622 gen_helper_neon_unarrow_sat8,
7623 gen_helper_neon_unarrow_sat16,
7624 gen_helper_neon_unarrow_sat32,
7626 if (u) {
7627 genenvfn = sqxtunfns[size];
7628 } else {
7629 genfn = xtnfns[size];
7631 break;
7633 case 0x14: /* SQXTN, UQXTN */
7635 static NeonGenNarrowEnvFn * const fns[3][2] = {
7636 { gen_helper_neon_narrow_sat_s8,
7637 gen_helper_neon_narrow_sat_u8 },
7638 { gen_helper_neon_narrow_sat_s16,
7639 gen_helper_neon_narrow_sat_u16 },
7640 { gen_helper_neon_narrow_sat_s32,
7641 gen_helper_neon_narrow_sat_u32 },
7643 genenvfn = fns[size][u];
7644 break;
7646 case 0x16: /* FCVTN, FCVTN2 */
7647 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7648 if (size == 2) {
7649 gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
7650 } else {
7651 TCGv_i32 tcg_lo = tcg_temp_new_i32();
7652 TCGv_i32 tcg_hi = tcg_temp_new_i32();
7653 tcg_gen_trunc_i64_i32(tcg_lo, tcg_op);
7654 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, cpu_env);
7655 tcg_gen_shri_i64(tcg_op, tcg_op, 32);
7656 tcg_gen_trunc_i64_i32(tcg_hi, tcg_op);
7657 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, cpu_env);
7658 tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
7659 tcg_temp_free_i32(tcg_lo);
7660 tcg_temp_free_i32(tcg_hi);
7662 break;
7663 case 0x56: /* FCVTXN, FCVTXN2 */
7664 /* 64 bit to 32 bit float conversion
7665 * with von Neumann rounding (round to odd)
7667 assert(size == 2);
7668 gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env);
7669 break;
7670 default:
7671 g_assert_not_reached();
7674 if (genfn) {
7675 genfn(tcg_res[pass], tcg_op);
7676 } else if (genenvfn) {
7677 genenvfn(tcg_res[pass], cpu_env, tcg_op);
7680 tcg_temp_free_i64(tcg_op);
7683 for (pass = 0; pass < 2; pass++) {
7684 write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);
7685 tcg_temp_free_i32(tcg_res[pass]);
7687 if (!is_q) {
7688 clear_vec_high(s, rd);
7692 /* Remaining saturating accumulating ops */
7693 static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
7694 bool is_q, int size, int rn, int rd)
7696 bool is_double = (size == 3);
7698 if (is_double) {
7699 TCGv_i64 tcg_rn = tcg_temp_new_i64();
7700 TCGv_i64 tcg_rd = tcg_temp_new_i64();
7701 int pass;
7703 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
7704 read_vec_element(s, tcg_rn, rn, pass, MO_64);
7705 read_vec_element(s, tcg_rd, rd, pass, MO_64);
7707 if (is_u) { /* USQADD */
7708 gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7709 } else { /* SUQADD */
7710 gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7712 write_vec_element(s, tcg_rd, rd, pass, MO_64);
7714 if (is_scalar) {
7715 clear_vec_high(s, rd);
7718 tcg_temp_free_i64(tcg_rd);
7719 tcg_temp_free_i64(tcg_rn);
7720 } else {
7721 TCGv_i32 tcg_rn = tcg_temp_new_i32();
7722 TCGv_i32 tcg_rd = tcg_temp_new_i32();
7723 int pass, maxpasses;
7725 if (is_scalar) {
7726 maxpasses = 1;
7727 } else {
7728 maxpasses = is_q ? 4 : 2;
7731 for (pass = 0; pass < maxpasses; pass++) {
7732 if (is_scalar) {
7733 read_vec_element_i32(s, tcg_rn, rn, pass, size);
7734 read_vec_element_i32(s, tcg_rd, rd, pass, size);
7735 } else {
7736 read_vec_element_i32(s, tcg_rn, rn, pass, MO_32);
7737 read_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
7740 if (is_u) { /* USQADD */
7741 switch (size) {
7742 case 0:
7743 gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7744 break;
7745 case 1:
7746 gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7747 break;
7748 case 2:
7749 gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7750 break;
7751 default:
7752 g_assert_not_reached();
7754 } else { /* SUQADD */
7755 switch (size) {
7756 case 0:
7757 gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7758 break;
7759 case 1:
7760 gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7761 break;
7762 case 2:
7763 gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
7764 break;
7765 default:
7766 g_assert_not_reached();
7770 if (is_scalar) {
7771 TCGv_i64 tcg_zero = tcg_const_i64(0);
7772 write_vec_element(s, tcg_zero, rd, 0, MO_64);
7773 tcg_temp_free_i64(tcg_zero);
7775 write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
7778 if (!is_q) {
7779 clear_vec_high(s, rd);
7782 tcg_temp_free_i32(tcg_rd);
7783 tcg_temp_free_i32(tcg_rn);
7787 /* C3.6.12 AdvSIMD scalar two reg misc
7788 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7789 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7790 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7791 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7793 static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
7795 int rd = extract32(insn, 0, 5);
7796 int rn = extract32(insn, 5, 5);
7797 int opcode = extract32(insn, 12, 5);
7798 int size = extract32(insn, 22, 2);
7799 bool u = extract32(insn, 29, 1);
7800 bool is_fcvt = false;
7801 int rmode;
7802 TCGv_i32 tcg_rmode;
7803 TCGv_ptr tcg_fpstatus;
7805 switch (opcode) {
7806 case 0x3: /* USQADD / SUQADD*/
7807 if (!fp_access_check(s)) {
7808 return;
7810 handle_2misc_satacc(s, true, u, false, size, rn, rd);
7811 return;
7812 case 0x7: /* SQABS / SQNEG */
7813 break;
7814 case 0xa: /* CMLT */
7815 if (u) {
7816 unallocated_encoding(s);
7817 return;
7819 /* fall through */
7820 case 0x8: /* CMGT, CMGE */
7821 case 0x9: /* CMEQ, CMLE */
7822 case 0xb: /* ABS, NEG */
7823 if (size != 3) {
7824 unallocated_encoding(s);
7825 return;
7827 break;
7828 case 0x12: /* SQXTUN */
7829 if (!u) {
7830 unallocated_encoding(s);
7831 return;
7833 /* fall through */
7834 case 0x14: /* SQXTN, UQXTN */
7835 if (size == 3) {
7836 unallocated_encoding(s);
7837 return;
7839 if (!fp_access_check(s)) {
7840 return;
7842 handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
7843 return;
7844 case 0xc ... 0xf:
7845 case 0x16 ... 0x1d:
7846 case 0x1f:
7847 /* Floating point: U, size[1] and opcode indicate operation;
7848 * size[0] indicates single or double precision.
7850 opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
7851 size = extract32(size, 0, 1) ? 3 : 2;
7852 switch (opcode) {
7853 case 0x2c: /* FCMGT (zero) */
7854 case 0x2d: /* FCMEQ (zero) */
7855 case 0x2e: /* FCMLT (zero) */
7856 case 0x6c: /* FCMGE (zero) */
7857 case 0x6d: /* FCMLE (zero) */
7858 handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
7859 return;
7860 case 0x1d: /* SCVTF */
7861 case 0x5d: /* UCVTF */
7863 bool is_signed = (opcode == 0x1d);
7864 if (!fp_access_check(s)) {
7865 return;
7867 handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size);
7868 return;
7870 case 0x3d: /* FRECPE */
7871 case 0x3f: /* FRECPX */
7872 case 0x7d: /* FRSQRTE */
7873 if (!fp_access_check(s)) {
7874 return;
7876 handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd);
7877 return;
7878 case 0x1a: /* FCVTNS */
7879 case 0x1b: /* FCVTMS */
7880 case 0x3a: /* FCVTPS */
7881 case 0x3b: /* FCVTZS */
7882 case 0x5a: /* FCVTNU */
7883 case 0x5b: /* FCVTMU */
7884 case 0x7a: /* FCVTPU */
7885 case 0x7b: /* FCVTZU */
7886 is_fcvt = true;
7887 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
7888 break;
7889 case 0x1c: /* FCVTAS */
7890 case 0x5c: /* FCVTAU */
7891 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7892 is_fcvt = true;
7893 rmode = FPROUNDING_TIEAWAY;
7894 break;
7895 case 0x56: /* FCVTXN, FCVTXN2 */
7896 if (size == 2) {
7897 unallocated_encoding(s);
7898 return;
7900 if (!fp_access_check(s)) {
7901 return;
7903 handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd);
7904 return;
7905 default:
7906 unallocated_encoding(s);
7907 return;
7909 break;
7910 default:
7911 unallocated_encoding(s);
7912 return;
7915 if (!fp_access_check(s)) {
7916 return;
7919 if (is_fcvt) {
7920 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
7921 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
7922 tcg_fpstatus = get_fpstatus_ptr();
7923 } else {
7924 TCGV_UNUSED_I32(tcg_rmode);
7925 TCGV_UNUSED_PTR(tcg_fpstatus);
7928 if (size == 3) {
7929 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
7930 TCGv_i64 tcg_rd = tcg_temp_new_i64();
7932 handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
7933 write_fp_dreg(s, rd, tcg_rd);
7934 tcg_temp_free_i64(tcg_rd);
7935 tcg_temp_free_i64(tcg_rn);
7936 } else {
7937 TCGv_i32 tcg_rn = tcg_temp_new_i32();
7938 TCGv_i32 tcg_rd = tcg_temp_new_i32();
7940 read_vec_element_i32(s, tcg_rn, rn, 0, size);
7942 switch (opcode) {
7943 case 0x7: /* SQABS, SQNEG */
7945 NeonGenOneOpEnvFn *genfn;
7946 static NeonGenOneOpEnvFn * const fns[3][2] = {
7947 { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
7948 { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
7949 { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
7951 genfn = fns[size][u];
7952 genfn(tcg_rd, cpu_env, tcg_rn);
7953 break;
7955 case 0x1a: /* FCVTNS */
7956 case 0x1b: /* FCVTMS */
7957 case 0x1c: /* FCVTAS */
7958 case 0x3a: /* FCVTPS */
7959 case 0x3b: /* FCVTZS */
7961 TCGv_i32 tcg_shift = tcg_const_i32(0);
7962 gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
7963 tcg_temp_free_i32(tcg_shift);
7964 break;
7966 case 0x5a: /* FCVTNU */
7967 case 0x5b: /* FCVTMU */
7968 case 0x5c: /* FCVTAU */
7969 case 0x7a: /* FCVTPU */
7970 case 0x7b: /* FCVTZU */
7972 TCGv_i32 tcg_shift = tcg_const_i32(0);
7973 gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
7974 tcg_temp_free_i32(tcg_shift);
7975 break;
7977 default:
7978 g_assert_not_reached();
7981 write_fp_sreg(s, rd, tcg_rd);
7982 tcg_temp_free_i32(tcg_rd);
7983 tcg_temp_free_i32(tcg_rn);
7986 if (is_fcvt) {
7987 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
7988 tcg_temp_free_i32(tcg_rmode);
7989 tcg_temp_free_ptr(tcg_fpstatus);
7993 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
7994 static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
7995 int immh, int immb, int opcode, int rn, int rd)
7997 int size = 32 - clz32(immh) - 1;
7998 int immhb = immh << 3 | immb;
7999 int shift = 2 * (8 << size) - immhb;
8000 bool accumulate = false;
8001 bool round = false;
8002 bool insert = false;
8003 int dsize = is_q ? 128 : 64;
8004 int esize = 8 << size;
8005 int elements = dsize/esize;
8006 TCGMemOp memop = size | (is_u ? 0 : MO_SIGN);
8007 TCGv_i64 tcg_rn = new_tmp_a64(s);
8008 TCGv_i64 tcg_rd = new_tmp_a64(s);
8009 TCGv_i64 tcg_round;
8010 int i;
8012 if (extract32(immh, 3, 1) && !is_q) {
8013 unallocated_encoding(s);
8014 return;
8017 if (size > 3 && !is_q) {
8018 unallocated_encoding(s);
8019 return;
8022 if (!fp_access_check(s)) {
8023 return;
8026 switch (opcode) {
8027 case 0x02: /* SSRA / USRA (accumulate) */
8028 accumulate = true;
8029 break;
8030 case 0x04: /* SRSHR / URSHR (rounding) */
8031 round = true;
8032 break;
8033 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8034 accumulate = round = true;
8035 break;
8036 case 0x08: /* SRI */
8037 insert = true;
8038 break;
8041 if (round) {
8042 uint64_t round_const = 1ULL << (shift - 1);
8043 tcg_round = tcg_const_i64(round_const);
8044 } else {
8045 TCGV_UNUSED_I64(tcg_round);
8048 for (i = 0; i < elements; i++) {
8049 read_vec_element(s, tcg_rn, rn, i, memop);
8050 if (accumulate || insert) {
8051 read_vec_element(s, tcg_rd, rd, i, memop);
8054 if (insert) {
8055 handle_shri_with_ins(tcg_rd, tcg_rn, size, shift);
8056 } else {
8057 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
8058 accumulate, is_u, size, shift);
8061 write_vec_element(s, tcg_rd, rd, i, size);
8064 if (!is_q) {
8065 clear_vec_high(s, rd);
8068 if (round) {
8069 tcg_temp_free_i64(tcg_round);
8073 /* SHL/SLI - Vector shift left */
8074 static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
8075 int immh, int immb, int opcode, int rn, int rd)
8077 int size = 32 - clz32(immh) - 1;
8078 int immhb = immh << 3 | immb;
8079 int shift = immhb - (8 << size);
8080 int dsize = is_q ? 128 : 64;
8081 int esize = 8 << size;
8082 int elements = dsize/esize;
8083 TCGv_i64 tcg_rn = new_tmp_a64(s);
8084 TCGv_i64 tcg_rd = new_tmp_a64(s);
8085 int i;
8087 if (extract32(immh, 3, 1) && !is_q) {
8088 unallocated_encoding(s);
8089 return;
8092 if (size > 3 && !is_q) {
8093 unallocated_encoding(s);
8094 return;
8097 if (!fp_access_check(s)) {
8098 return;
8101 for (i = 0; i < elements; i++) {
8102 read_vec_element(s, tcg_rn, rn, i, size);
8103 if (insert) {
8104 read_vec_element(s, tcg_rd, rd, i, size);
8107 handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
8109 write_vec_element(s, tcg_rd, rd, i, size);
8112 if (!is_q) {
8113 clear_vec_high(s, rd);
8117 /* USHLL/SHLL - Vector shift left with widening */
8118 static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
8119 int immh, int immb, int opcode, int rn, int rd)
8121 int size = 32 - clz32(immh) - 1;
8122 int immhb = immh << 3 | immb;
8123 int shift = immhb - (8 << size);
8124 int dsize = 64;
8125 int esize = 8 << size;
8126 int elements = dsize/esize;
8127 TCGv_i64 tcg_rn = new_tmp_a64(s);
8128 TCGv_i64 tcg_rd = new_tmp_a64(s);
8129 int i;
8131 if (size >= 3) {
8132 unallocated_encoding(s);
8133 return;
8136 if (!fp_access_check(s)) {
8137 return;
8140 /* For the LL variants the store is larger than the load,
8141 * so if rd == rn we would overwrite parts of our input.
8142 * So load everything right now and use shifts in the main loop.
8144 read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);
8146 for (i = 0; i < elements; i++) {
8147 tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);
8148 ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0);
8149 tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
8150 write_vec_element(s, tcg_rd, rd, i, size + 1);
8154 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8155 static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
8156 int immh, int immb, int opcode, int rn, int rd)
8158 int immhb = immh << 3 | immb;
8159 int size = 32 - clz32(immh) - 1;
8160 int dsize = 64;
8161 int esize = 8 << size;
8162 int elements = dsize/esize;
8163 int shift = (2 * esize) - immhb;
8164 bool round = extract32(opcode, 0, 1);
8165 TCGv_i64 tcg_rn, tcg_rd, tcg_final;
8166 TCGv_i64 tcg_round;
8167 int i;
8169 if (extract32(immh, 3, 1)) {
8170 unallocated_encoding(s);
8171 return;
8174 if (!fp_access_check(s)) {
8175 return;
8178 tcg_rn = tcg_temp_new_i64();
8179 tcg_rd = tcg_temp_new_i64();
8180 tcg_final = tcg_temp_new_i64();
8181 read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
8183 if (round) {
8184 uint64_t round_const = 1ULL << (shift - 1);
8185 tcg_round = tcg_const_i64(round_const);
8186 } else {
8187 TCGV_UNUSED_I64(tcg_round);
8190 for (i = 0; i < elements; i++) {
8191 read_vec_element(s, tcg_rn, rn, i, size+1);
8192 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
8193 false, true, size+1, shift);
8195 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
8198 if (!is_q) {
8199 clear_vec_high(s, rd);
8200 write_vec_element(s, tcg_final, rd, 0, MO_64);
8201 } else {
8202 write_vec_element(s, tcg_final, rd, 1, MO_64);
8205 if (round) {
8206 tcg_temp_free_i64(tcg_round);
8208 tcg_temp_free_i64(tcg_rn);
8209 tcg_temp_free_i64(tcg_rd);
8210 tcg_temp_free_i64(tcg_final);
8211 return;
8215 /* C3.6.14 AdvSIMD shift by immediate
8216 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8217 * +---+---+---+-------------+------+------+--------+---+------+------+
8218 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8219 * +---+---+---+-------------+------+------+--------+---+------+------+
8221 static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
8223 int rd = extract32(insn, 0, 5);
8224 int rn = extract32(insn, 5, 5);
8225 int opcode = extract32(insn, 11, 5);
8226 int immb = extract32(insn, 16, 3);
8227 int immh = extract32(insn, 19, 4);
8228 bool is_u = extract32(insn, 29, 1);
8229 bool is_q = extract32(insn, 30, 1);
8231 switch (opcode) {
8232 case 0x08: /* SRI */
8233 if (!is_u) {
8234 unallocated_encoding(s);
8235 return;
8237 /* fall through */
8238 case 0x00: /* SSHR / USHR */
8239 case 0x02: /* SSRA / USRA (accumulate) */
8240 case 0x04: /* SRSHR / URSHR (rounding) */
8241 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8242 handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd);
8243 break;
8244 case 0x0a: /* SHL / SLI */
8245 handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd);
8246 break;
8247 case 0x10: /* SHRN */
8248 case 0x11: /* RSHRN / SQRSHRUN */
8249 if (is_u) {
8250 handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb,
8251 opcode, rn, rd);
8252 } else {
8253 handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd);
8255 break;
8256 case 0x12: /* SQSHRN / UQSHRN */
8257 case 0x13: /* SQRSHRN / UQRSHRN */
8258 handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb,
8259 opcode, rn, rd);
8260 break;
8261 case 0x14: /* SSHLL / USHLL */
8262 handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd);
8263 break;
8264 case 0x1c: /* SCVTF / UCVTF */
8265 handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
8266 opcode, rn, rd);
8267 break;
8268 case 0xc: /* SQSHLU */
8269 if (!is_u) {
8270 unallocated_encoding(s);
8271 return;
8273 handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd);
8274 break;
8275 case 0xe: /* SQSHL, UQSHL */
8276 handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd);
8277 break;
8278 case 0x1f: /* FCVTZS/ FCVTZU */
8279 handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd);
8280 return;
8281 default:
8282 unallocated_encoding(s);
8283 return;
8287 /* Generate code to do a "long" addition or subtraction, ie one done in
8288 * TCGv_i64 on vector lanes twice the width specified by size.
8290 static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res,
8291 TCGv_i64 tcg_op1, TCGv_i64 tcg_op2)
8293 static NeonGenTwo64OpFn * const fns[3][2] = {
8294 { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 },
8295 { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 },
8296 { tcg_gen_add_i64, tcg_gen_sub_i64 },
8298 NeonGenTwo64OpFn *genfn;
8299 assert(size < 3);
8301 genfn = fns[size][is_sub];
8302 genfn(tcg_res, tcg_op1, tcg_op2);
8305 static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
8306 int opcode, int rd, int rn, int rm)
8308 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8309 TCGv_i64 tcg_res[2];
8310 int pass, accop;
8312 tcg_res[0] = tcg_temp_new_i64();
8313 tcg_res[1] = tcg_temp_new_i64();
8315 /* Does this op do an adding accumulate, a subtracting accumulate,
8316 * or no accumulate at all?
8318 switch (opcode) {
8319 case 5:
8320 case 8:
8321 case 9:
8322 accop = 1;
8323 break;
8324 case 10:
8325 case 11:
8326 accop = -1;
8327 break;
8328 default:
8329 accop = 0;
8330 break;
8333 if (accop != 0) {
8334 read_vec_element(s, tcg_res[0], rd, 0, MO_64);
8335 read_vec_element(s, tcg_res[1], rd, 1, MO_64);
8338 /* size == 2 means two 32x32->64 operations; this is worth special
8339 * casing because we can generally handle it inline.
8341 if (size == 2) {
8342 for (pass = 0; pass < 2; pass++) {
8343 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8344 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8345 TCGv_i64 tcg_passres;
8346 TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
8348 int elt = pass + is_q * 2;
8350 read_vec_element(s, tcg_op1, rn, elt, memop);
8351 read_vec_element(s, tcg_op2, rm, elt, memop);
8353 if (accop == 0) {
8354 tcg_passres = tcg_res[pass];
8355 } else {
8356 tcg_passres = tcg_temp_new_i64();
8359 switch (opcode) {
8360 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8361 tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2);
8362 break;
8363 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8364 tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2);
8365 break;
8366 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8367 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8369 TCGv_i64 tcg_tmp1 = tcg_temp_new_i64();
8370 TCGv_i64 tcg_tmp2 = tcg_temp_new_i64();
8372 tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2);
8373 tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1);
8374 tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
8375 tcg_passres,
8376 tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
8377 tcg_temp_free_i64(tcg_tmp1);
8378 tcg_temp_free_i64(tcg_tmp2);
8379 break;
8381 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8382 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8383 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8384 tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
8385 break;
8386 case 9: /* SQDMLAL, SQDMLAL2 */
8387 case 11: /* SQDMLSL, SQDMLSL2 */
8388 case 13: /* SQDMULL, SQDMULL2 */
8389 tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
8390 gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
8391 tcg_passres, tcg_passres);
8392 break;
8393 default:
8394 g_assert_not_reached();
8397 if (opcode == 9 || opcode == 11) {
8398 /* saturating accumulate ops */
8399 if (accop < 0) {
8400 tcg_gen_neg_i64(tcg_passres, tcg_passres);
8402 gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
8403 tcg_res[pass], tcg_passres);
8404 } else if (accop > 0) {
8405 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
8406 } else if (accop < 0) {
8407 tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
8410 if (accop != 0) {
8411 tcg_temp_free_i64(tcg_passres);
8414 tcg_temp_free_i64(tcg_op1);
8415 tcg_temp_free_i64(tcg_op2);
8417 } else {
8418 /* size 0 or 1, generally helper functions */
8419 for (pass = 0; pass < 2; pass++) {
8420 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
8421 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
8422 TCGv_i64 tcg_passres;
8423 int elt = pass + is_q * 2;
8425 read_vec_element_i32(s, tcg_op1, rn, elt, MO_32);
8426 read_vec_element_i32(s, tcg_op2, rm, elt, MO_32);
8428 if (accop == 0) {
8429 tcg_passres = tcg_res[pass];
8430 } else {
8431 tcg_passres = tcg_temp_new_i64();
8434 switch (opcode) {
8435 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8436 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8438 TCGv_i64 tcg_op2_64 = tcg_temp_new_i64();
8439 static NeonGenWidenFn * const widenfns[2][2] = {
8440 { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
8441 { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
8443 NeonGenWidenFn *widenfn = widenfns[size][is_u];
8445 widenfn(tcg_op2_64, tcg_op2);
8446 widenfn(tcg_passres, tcg_op1);
8447 gen_neon_addl(size, (opcode == 2), tcg_passres,
8448 tcg_passres, tcg_op2_64);
8449 tcg_temp_free_i64(tcg_op2_64);
8450 break;
8452 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8453 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8454 if (size == 0) {
8455 if (is_u) {
8456 gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2);
8457 } else {
8458 gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2);
8460 } else {
8461 if (is_u) {
8462 gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2);
8463 } else {
8464 gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2);
8467 break;
8468 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8469 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8470 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8471 if (size == 0) {
8472 if (is_u) {
8473 gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2);
8474 } else {
8475 gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2);
8477 } else {
8478 if (is_u) {
8479 gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2);
8480 } else {
8481 gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
8484 break;
8485 case 9: /* SQDMLAL, SQDMLAL2 */
8486 case 11: /* SQDMLSL, SQDMLSL2 */
8487 case 13: /* SQDMULL, SQDMULL2 */
8488 assert(size == 1);
8489 gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
8490 gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
8491 tcg_passres, tcg_passres);
8492 break;
8493 case 14: /* PMULL */
8494 assert(size == 0);
8495 gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2);
8496 break;
8497 default:
8498 g_assert_not_reached();
8500 tcg_temp_free_i32(tcg_op1);
8501 tcg_temp_free_i32(tcg_op2);
8503 if (accop != 0) {
8504 if (opcode == 9 || opcode == 11) {
8505 /* saturating accumulate ops */
8506 if (accop < 0) {
8507 gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
8509 gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
8510 tcg_res[pass],
8511 tcg_passres);
8512 } else {
8513 gen_neon_addl(size, (accop < 0), tcg_res[pass],
8514 tcg_res[pass], tcg_passres);
8516 tcg_temp_free_i64(tcg_passres);
8521 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
8522 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
8523 tcg_temp_free_i64(tcg_res[0]);
8524 tcg_temp_free_i64(tcg_res[1]);
8527 static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
8528 int opcode, int rd, int rn, int rm)
8530 TCGv_i64 tcg_res[2];
8531 int part = is_q ? 2 : 0;
8532 int pass;
8534 for (pass = 0; pass < 2; pass++) {
8535 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8536 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
8537 TCGv_i64 tcg_op2_wide = tcg_temp_new_i64();
8538 static NeonGenWidenFn * const widenfns[3][2] = {
8539 { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
8540 { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
8541 { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 },
8543 NeonGenWidenFn *widenfn = widenfns[size][is_u];
8545 read_vec_element(s, tcg_op1, rn, pass, MO_64);
8546 read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32);
8547 widenfn(tcg_op2_wide, tcg_op2);
8548 tcg_temp_free_i32(tcg_op2);
8549 tcg_res[pass] = tcg_temp_new_i64();
8550 gen_neon_addl(size, (opcode == 3),
8551 tcg_res[pass], tcg_op1, tcg_op2_wide);
8552 tcg_temp_free_i64(tcg_op1);
8553 tcg_temp_free_i64(tcg_op2_wide);
8556 for (pass = 0; pass < 2; pass++) {
8557 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
8558 tcg_temp_free_i64(tcg_res[pass]);
8562 static void do_narrow_high_u32(TCGv_i32 res, TCGv_i64 in)
8564 tcg_gen_shri_i64(in, in, 32);
8565 tcg_gen_trunc_i64_i32(res, in);
8568 static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in)
8570 tcg_gen_addi_i64(in, in, 1U << 31);
8571 do_narrow_high_u32(res, in);
8574 static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
8575 int opcode, int rd, int rn, int rm)
8577 TCGv_i32 tcg_res[2];
8578 int part = is_q ? 2 : 0;
8579 int pass;
8581 for (pass = 0; pass < 2; pass++) {
8582 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8583 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8584 TCGv_i64 tcg_wideres = tcg_temp_new_i64();
8585 static NeonGenNarrowFn * const narrowfns[3][2] = {
8586 { gen_helper_neon_narrow_high_u8,
8587 gen_helper_neon_narrow_round_high_u8 },
8588 { gen_helper_neon_narrow_high_u16,
8589 gen_helper_neon_narrow_round_high_u16 },
8590 { do_narrow_high_u32, do_narrow_round_high_u32 },
8592 NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];
8594 read_vec_element(s, tcg_op1, rn, pass, MO_64);
8595 read_vec_element(s, tcg_op2, rm, pass, MO_64);
8597 gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2);
8599 tcg_temp_free_i64(tcg_op1);
8600 tcg_temp_free_i64(tcg_op2);
8602 tcg_res[pass] = tcg_temp_new_i32();
8603 gennarrow(tcg_res[pass], tcg_wideres);
8604 tcg_temp_free_i64(tcg_wideres);
8607 for (pass = 0; pass < 2; pass++) {
8608 write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);
8609 tcg_temp_free_i32(tcg_res[pass]);
8611 if (!is_q) {
8612 clear_vec_high(s, rd);
8616 static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
8618 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8619 * is the only three-reg-diff instruction which produces a
8620 * 128-bit wide result from a single operation. However since
8621 * it's possible to calculate the two halves more or less
8622 * separately we just use two helper calls.
8624 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8625 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8626 TCGv_i64 tcg_res = tcg_temp_new_i64();
8628 read_vec_element(s, tcg_op1, rn, is_q, MO_64);
8629 read_vec_element(s, tcg_op2, rm, is_q, MO_64);
8630 gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2);
8631 write_vec_element(s, tcg_res, rd, 0, MO_64);
8632 gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2);
8633 write_vec_element(s, tcg_res, rd, 1, MO_64);
8635 tcg_temp_free_i64(tcg_op1);
8636 tcg_temp_free_i64(tcg_op2);
8637 tcg_temp_free_i64(tcg_res);
8640 /* C3.6.15 AdvSIMD three different
8641 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8642 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8643 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8644 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8646 static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
8648 /* Instructions in this group fall into three basic classes
8649 * (in each case with the operation working on each element in
8650 * the input vectors):
8651 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8652 * 128 bit input)
8653 * (2) wide 64 x 128 -> 128
8654 * (3) narrowing 128 x 128 -> 64
8655 * Here we do initial decode, catch unallocated cases and
8656 * dispatch to separate functions for each class.
8658 int is_q = extract32(insn, 30, 1);
8659 int is_u = extract32(insn, 29, 1);
8660 int size = extract32(insn, 22, 2);
8661 int opcode = extract32(insn, 12, 4);
8662 int rm = extract32(insn, 16, 5);
8663 int rn = extract32(insn, 5, 5);
8664 int rd = extract32(insn, 0, 5);
8666 switch (opcode) {
8667 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8668 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8669 /* 64 x 128 -> 128 */
8670 if (size == 3) {
8671 unallocated_encoding(s);
8672 return;
8674 if (!fp_access_check(s)) {
8675 return;
8677 handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm);
8678 break;
8679 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8680 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8681 /* 128 x 128 -> 64 */
8682 if (size == 3) {
8683 unallocated_encoding(s);
8684 return;
8686 if (!fp_access_check(s)) {
8687 return;
8689 handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm);
8690 break;
8691 case 14: /* PMULL, PMULL2 */
8692 if (is_u || size == 1 || size == 2) {
8693 unallocated_encoding(s);
8694 return;
8696 if (size == 3) {
8697 if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
8698 unallocated_encoding(s);
8699 return;
8701 if (!fp_access_check(s)) {
8702 return;
8704 handle_pmull_64(s, is_q, rd, rn, rm);
8705 return;
8707 goto is_widening;
8708 case 9: /* SQDMLAL, SQDMLAL2 */
8709 case 11: /* SQDMLSL, SQDMLSL2 */
8710 case 13: /* SQDMULL, SQDMULL2 */
8711 if (is_u || size == 0) {
8712 unallocated_encoding(s);
8713 return;
8715 /* fall through */
8716 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8717 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8718 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8719 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8720 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8721 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8722 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8723 /* 64 x 64 -> 128 */
8724 if (size == 3) {
8725 unallocated_encoding(s);
8726 return;
8728 is_widening:
8729 if (!fp_access_check(s)) {
8730 return;
8733 handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
8734 break;
8735 default:
8736 /* opcode 15 not allocated */
8737 unallocated_encoding(s);
8738 break;
8742 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8743 static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
8745 int rd = extract32(insn, 0, 5);
8746 int rn = extract32(insn, 5, 5);
8747 int rm = extract32(insn, 16, 5);
8748 int size = extract32(insn, 22, 2);
8749 bool is_u = extract32(insn, 29, 1);
8750 bool is_q = extract32(insn, 30, 1);
8751 TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
8752 int pass;
8754 if (!fp_access_check(s)) {
8755 return;
8758 tcg_op1 = tcg_temp_new_i64();
8759 tcg_op2 = tcg_temp_new_i64();
8760 tcg_res[0] = tcg_temp_new_i64();
8761 tcg_res[1] = tcg_temp_new_i64();
8763 for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
8764 read_vec_element(s, tcg_op1, rn, pass, MO_64);
8765 read_vec_element(s, tcg_op2, rm, pass, MO_64);
8767 if (!is_u) {
8768 switch (size) {
8769 case 0: /* AND */
8770 tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2);
8771 break;
8772 case 1: /* BIC */
8773 tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2);
8774 break;
8775 case 2: /* ORR */
8776 tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2);
8777 break;
8778 case 3: /* ORN */
8779 tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2);
8780 break;
8782 } else {
8783 if (size != 0) {
8784 /* B* ops need res loaded to operate on */
8785 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
8788 switch (size) {
8789 case 0: /* EOR */
8790 tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);
8791 break;
8792 case 1: /* BSL bitwise select */
8793 tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2);
8794 tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]);
8795 tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1);
8796 break;
8797 case 2: /* BIT, bitwise insert if true */
8798 tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);
8799 tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2);
8800 tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
8801 break;
8802 case 3: /* BIF, bitwise insert if false */
8803 tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);
8804 tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2);
8805 tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
8806 break;
8811 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
8812 if (!is_q) {
8813 tcg_gen_movi_i64(tcg_res[1], 0);
8815 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
8817 tcg_temp_free_i64(tcg_op1);
8818 tcg_temp_free_i64(tcg_op2);
8819 tcg_temp_free_i64(tcg_res[0]);
8820 tcg_temp_free_i64(tcg_res[1]);
8823 /* Helper functions for 32 bit comparisons */
8824 static void gen_max_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
8826 tcg_gen_movcond_i32(TCG_COND_GE, res, op1, op2, op1, op2);
8829 static void gen_max_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
8831 tcg_gen_movcond_i32(TCG_COND_GEU, res, op1, op2, op1, op2);
8834 static void gen_min_s32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
8836 tcg_gen_movcond_i32(TCG_COND_LE, res, op1, op2, op1, op2);
8839 static void gen_min_u32(TCGv_i32 res, TCGv_i32 op1, TCGv_i32 op2)
8841 tcg_gen_movcond_i32(TCG_COND_LEU, res, op1, op2, op1, op2);
8844 /* Pairwise op subgroup of C3.6.16.
8846 * This is called directly or via the handle_3same_float for float pairwise
8847 * operations where the opcode and size are calculated differently.
8849 static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
8850 int size, int rn, int rm, int rd)
8852 TCGv_ptr fpst;
8853 int pass;
8855 /* Floating point operations need fpst */
8856 if (opcode >= 0x58) {
8857 fpst = get_fpstatus_ptr();
8858 } else {
8859 TCGV_UNUSED_PTR(fpst);
8862 if (!fp_access_check(s)) {
8863 return;
8866 /* These operations work on the concatenated rm:rn, with each pair of
8867 * adjacent elements being operated on to produce an element in the result.
8869 if (size == 3) {
8870 TCGv_i64 tcg_res[2];
8872 for (pass = 0; pass < 2; pass++) {
8873 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8874 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8875 int passreg = (pass == 0) ? rn : rm;
8877 read_vec_element(s, tcg_op1, passreg, 0, MO_64);
8878 read_vec_element(s, tcg_op2, passreg, 1, MO_64);
8879 tcg_res[pass] = tcg_temp_new_i64();
8881 switch (opcode) {
8882 case 0x17: /* ADDP */
8883 tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
8884 break;
8885 case 0x58: /* FMAXNMP */
8886 gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8887 break;
8888 case 0x5a: /* FADDP */
8889 gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8890 break;
8891 case 0x5e: /* FMAXP */
8892 gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8893 break;
8894 case 0x78: /* FMINNMP */
8895 gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8896 break;
8897 case 0x7e: /* FMINP */
8898 gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8899 break;
8900 default:
8901 g_assert_not_reached();
8904 tcg_temp_free_i64(tcg_op1);
8905 tcg_temp_free_i64(tcg_op2);
8908 for (pass = 0; pass < 2; pass++) {
8909 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
8910 tcg_temp_free_i64(tcg_res[pass]);
8912 } else {
8913 int maxpass = is_q ? 4 : 2;
8914 TCGv_i32 tcg_res[4];
8916 for (pass = 0; pass < maxpass; pass++) {
8917 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
8918 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
8919 NeonGenTwoOpFn *genfn = NULL;
8920 int passreg = pass < (maxpass / 2) ? rn : rm;
8921 int passelt = (is_q && (pass & 1)) ? 2 : 0;
8923 read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32);
8924 read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32);
8925 tcg_res[pass] = tcg_temp_new_i32();
8927 switch (opcode) {
8928 case 0x17: /* ADDP */
8930 static NeonGenTwoOpFn * const fns[3] = {
8931 gen_helper_neon_padd_u8,
8932 gen_helper_neon_padd_u16,
8933 tcg_gen_add_i32,
8935 genfn = fns[size];
8936 break;
8938 case 0x14: /* SMAXP, UMAXP */
8940 static NeonGenTwoOpFn * const fns[3][2] = {
8941 { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 },
8942 { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 },
8943 { gen_max_s32, gen_max_u32 },
8945 genfn = fns[size][u];
8946 break;
8948 case 0x15: /* SMINP, UMINP */
8950 static NeonGenTwoOpFn * const fns[3][2] = {
8951 { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 },
8952 { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 },
8953 { gen_min_s32, gen_min_u32 },
8955 genfn = fns[size][u];
8956 break;
8958 /* The FP operations are all on single floats (32 bit) */
8959 case 0x58: /* FMAXNMP */
8960 gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8961 break;
8962 case 0x5a: /* FADDP */
8963 gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8964 break;
8965 case 0x5e: /* FMAXP */
8966 gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8967 break;
8968 case 0x78: /* FMINNMP */
8969 gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8970 break;
8971 case 0x7e: /* FMINP */
8972 gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst);
8973 break;
8974 default:
8975 g_assert_not_reached();
8978 /* FP ops called directly, otherwise call now */
8979 if (genfn) {
8980 genfn(tcg_res[pass], tcg_op1, tcg_op2);
8983 tcg_temp_free_i32(tcg_op1);
8984 tcg_temp_free_i32(tcg_op2);
8987 for (pass = 0; pass < maxpass; pass++) {
8988 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
8989 tcg_temp_free_i32(tcg_res[pass]);
8991 if (!is_q) {
8992 clear_vec_high(s, rd);
8996 if (!TCGV_IS_UNUSED_PTR(fpst)) {
8997 tcg_temp_free_ptr(fpst);
9001 /* Floating point op subgroup of C3.6.16. */
9002 static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
9004 /* For floating point ops, the U, size[1] and opcode bits
9005 * together indicate the operation. size[0] indicates single
9006 * or double.
9008 int fpopcode = extract32(insn, 11, 5)
9009 | (extract32(insn, 23, 1) << 5)
9010 | (extract32(insn, 29, 1) << 6);
9011 int is_q = extract32(insn, 30, 1);
9012 int size = extract32(insn, 22, 1);
9013 int rm = extract32(insn, 16, 5);
9014 int rn = extract32(insn, 5, 5);
9015 int rd = extract32(insn, 0, 5);
9017 int datasize = is_q ? 128 : 64;
9018 int esize = 32 << size;
9019 int elements = datasize / esize;
9021 if (size == 1 && !is_q) {
9022 unallocated_encoding(s);
9023 return;
9026 switch (fpopcode) {
9027 case 0x58: /* FMAXNMP */
9028 case 0x5a: /* FADDP */
9029 case 0x5e: /* FMAXP */
9030 case 0x78: /* FMINNMP */
9031 case 0x7e: /* FMINP */
9032 if (size && !is_q) {
9033 unallocated_encoding(s);
9034 return;
9036 handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32,
9037 rn, rm, rd);
9038 return;
9039 case 0x1b: /* FMULX */
9040 case 0x1f: /* FRECPS */
9041 case 0x3f: /* FRSQRTS */
9042 case 0x5d: /* FACGE */
9043 case 0x7d: /* FACGT */
9044 case 0x19: /* FMLA */
9045 case 0x39: /* FMLS */
9046 case 0x18: /* FMAXNM */
9047 case 0x1a: /* FADD */
9048 case 0x1c: /* FCMEQ */
9049 case 0x1e: /* FMAX */
9050 case 0x38: /* FMINNM */
9051 case 0x3a: /* FSUB */
9052 case 0x3e: /* FMIN */
9053 case 0x5b: /* FMUL */
9054 case 0x5c: /* FCMGE */
9055 case 0x5f: /* FDIV */
9056 case 0x7a: /* FABD */
9057 case 0x7c: /* FCMGT */
9058 if (!fp_access_check(s)) {
9059 return;
9062 handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
9063 return;
9064 default:
9065 unallocated_encoding(s);
9066 return;
9070 /* Integer op subgroup of C3.6.16. */
9071 static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
9073 int is_q = extract32(insn, 30, 1);
9074 int u = extract32(insn, 29, 1);
9075 int size = extract32(insn, 22, 2);
9076 int opcode = extract32(insn, 11, 5);
9077 int rm = extract32(insn, 16, 5);
9078 int rn = extract32(insn, 5, 5);
9079 int rd = extract32(insn, 0, 5);
9080 int pass;
9082 switch (opcode) {
9083 case 0x13: /* MUL, PMUL */
9084 if (u && size != 0) {
9085 unallocated_encoding(s);
9086 return;
9088 /* fall through */
9089 case 0x0: /* SHADD, UHADD */
9090 case 0x2: /* SRHADD, URHADD */
9091 case 0x4: /* SHSUB, UHSUB */
9092 case 0xc: /* SMAX, UMAX */
9093 case 0xd: /* SMIN, UMIN */
9094 case 0xe: /* SABD, UABD */
9095 case 0xf: /* SABA, UABA */
9096 case 0x12: /* MLA, MLS */
9097 if (size == 3) {
9098 unallocated_encoding(s);
9099 return;
9101 break;
9102 case 0x16: /* SQDMULH, SQRDMULH */
9103 if (size == 0 || size == 3) {
9104 unallocated_encoding(s);
9105 return;
9107 break;
9108 default:
9109 if (size == 3 && !is_q) {
9110 unallocated_encoding(s);
9111 return;
9113 break;
9116 if (!fp_access_check(s)) {
9117 return;
9120 if (size == 3) {
9121 assert(is_q);
9122 for (pass = 0; pass < 2; pass++) {
9123 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
9124 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
9125 TCGv_i64 tcg_res = tcg_temp_new_i64();
9127 read_vec_element(s, tcg_op1, rn, pass, MO_64);
9128 read_vec_element(s, tcg_op2, rm, pass, MO_64);
9130 handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2);
9132 write_vec_element(s, tcg_res, rd, pass, MO_64);
9134 tcg_temp_free_i64(tcg_res);
9135 tcg_temp_free_i64(tcg_op1);
9136 tcg_temp_free_i64(tcg_op2);
9138 } else {
9139 for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
9140 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
9141 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
9142 TCGv_i32 tcg_res = tcg_temp_new_i32();
9143 NeonGenTwoOpFn *genfn = NULL;
9144 NeonGenTwoOpEnvFn *genenvfn = NULL;
9146 read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
9147 read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
9149 switch (opcode) {
9150 case 0x0: /* SHADD, UHADD */
9152 static NeonGenTwoOpFn * const fns[3][2] = {
9153 { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 },
9154 { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 },
9155 { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 },
9157 genfn = fns[size][u];
9158 break;
9160 case 0x1: /* SQADD, UQADD */
9162 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9163 { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
9164 { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
9165 { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
9167 genenvfn = fns[size][u];
9168 break;
9170 case 0x2: /* SRHADD, URHADD */
9172 static NeonGenTwoOpFn * const fns[3][2] = {
9173 { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 },
9174 { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 },
9175 { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 },
9177 genfn = fns[size][u];
9178 break;
9180 case 0x4: /* SHSUB, UHSUB */
9182 static NeonGenTwoOpFn * const fns[3][2] = {
9183 { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 },
9184 { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 },
9185 { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 },
9187 genfn = fns[size][u];
9188 break;
9190 case 0x5: /* SQSUB, UQSUB */
9192 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9193 { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
9194 { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
9195 { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
9197 genenvfn = fns[size][u];
9198 break;
9200 case 0x6: /* CMGT, CMHI */
9202 static NeonGenTwoOpFn * const fns[3][2] = {
9203 { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 },
9204 { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 },
9205 { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 },
9207 genfn = fns[size][u];
9208 break;
9210 case 0x7: /* CMGE, CMHS */
9212 static NeonGenTwoOpFn * const fns[3][2] = {
9213 { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 },
9214 { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 },
9215 { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 },
9217 genfn = fns[size][u];
9218 break;
9220 case 0x8: /* SSHL, USHL */
9222 static NeonGenTwoOpFn * const fns[3][2] = {
9223 { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
9224 { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
9225 { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
9227 genfn = fns[size][u];
9228 break;
9230 case 0x9: /* SQSHL, UQSHL */
9232 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9233 { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
9234 { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
9235 { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
9237 genenvfn = fns[size][u];
9238 break;
9240 case 0xa: /* SRSHL, URSHL */
9242 static NeonGenTwoOpFn * const fns[3][2] = {
9243 { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 },
9244 { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 },
9245 { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 },
9247 genfn = fns[size][u];
9248 break;
9250 case 0xb: /* SQRSHL, UQRSHL */
9252 static NeonGenTwoOpEnvFn * const fns[3][2] = {
9253 { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
9254 { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
9255 { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
9257 genenvfn = fns[size][u];
9258 break;
9260 case 0xc: /* SMAX, UMAX */
9262 static NeonGenTwoOpFn * const fns[3][2] = {
9263 { gen_helper_neon_max_s8, gen_helper_neon_max_u8 },
9264 { gen_helper_neon_max_s16, gen_helper_neon_max_u16 },
9265 { gen_max_s32, gen_max_u32 },
9267 genfn = fns[size][u];
9268 break;
9271 case 0xd: /* SMIN, UMIN */
9273 static NeonGenTwoOpFn * const fns[3][2] = {
9274 { gen_helper_neon_min_s8, gen_helper_neon_min_u8 },
9275 { gen_helper_neon_min_s16, gen_helper_neon_min_u16 },
9276 { gen_min_s32, gen_min_u32 },
9278 genfn = fns[size][u];
9279 break;
9281 case 0xe: /* SABD, UABD */
9282 case 0xf: /* SABA, UABA */
9284 static NeonGenTwoOpFn * const fns[3][2] = {
9285 { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 },
9286 { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 },
9287 { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 },
9289 genfn = fns[size][u];
9290 break;
9292 case 0x10: /* ADD, SUB */
9294 static NeonGenTwoOpFn * const fns[3][2] = {
9295 { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
9296 { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
9297 { tcg_gen_add_i32, tcg_gen_sub_i32 },
9299 genfn = fns[size][u];
9300 break;
9302 case 0x11: /* CMTST, CMEQ */
9304 static NeonGenTwoOpFn * const fns[3][2] = {
9305 { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 },
9306 { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 },
9307 { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 },
9309 genfn = fns[size][u];
9310 break;
9312 case 0x13: /* MUL, PMUL */
9313 if (u) {
9314 /* PMUL */
9315 assert(size == 0);
9316 genfn = gen_helper_neon_mul_p8;
9317 break;
9319 /* fall through : MUL */
9320 case 0x12: /* MLA, MLS */
9322 static NeonGenTwoOpFn * const fns[3] = {
9323 gen_helper_neon_mul_u8,
9324 gen_helper_neon_mul_u16,
9325 tcg_gen_mul_i32,
9327 genfn = fns[size];
9328 break;
9330 case 0x16: /* SQDMULH, SQRDMULH */
9332 static NeonGenTwoOpEnvFn * const fns[2][2] = {
9333 { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
9334 { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
9336 assert(size == 1 || size == 2);
9337 genenvfn = fns[size - 1][u];
9338 break;
9340 default:
9341 g_assert_not_reached();
9344 if (genenvfn) {
9345 genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2);
9346 } else {
9347 genfn(tcg_res, tcg_op1, tcg_op2);
9350 if (opcode == 0xf || opcode == 0x12) {
9351 /* SABA, UABA, MLA, MLS: accumulating ops */
9352 static NeonGenTwoOpFn * const fns[3][2] = {
9353 { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
9354 { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
9355 { tcg_gen_add_i32, tcg_gen_sub_i32 },
9357 bool is_sub = (opcode == 0x12 && u); /* MLS */
9359 genfn = fns[size][is_sub];
9360 read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
9361 genfn(tcg_res, tcg_op1, tcg_res);
9364 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
9366 tcg_temp_free_i32(tcg_res);
9367 tcg_temp_free_i32(tcg_op1);
9368 tcg_temp_free_i32(tcg_op2);
9372 if (!is_q) {
9373 clear_vec_high(s, rd);
9377 /* C3.6.16 AdvSIMD three same
9378 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9379 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9380 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9381 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9383 static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
9385 int opcode = extract32(insn, 11, 5);
9387 switch (opcode) {
9388 case 0x3: /* logic ops */
9389 disas_simd_3same_logic(s, insn);
9390 break;
9391 case 0x17: /* ADDP */
9392 case 0x14: /* SMAXP, UMAXP */
9393 case 0x15: /* SMINP, UMINP */
9395 /* Pairwise operations */
9396 int is_q = extract32(insn, 30, 1);
9397 int u = extract32(insn, 29, 1);
9398 int size = extract32(insn, 22, 2);
9399 int rm = extract32(insn, 16, 5);
9400 int rn = extract32(insn, 5, 5);
9401 int rd = extract32(insn, 0, 5);
9402 if (opcode == 0x17) {
9403 if (u || (size == 3 && !is_q)) {
9404 unallocated_encoding(s);
9405 return;
9407 } else {
9408 if (size == 3) {
9409 unallocated_encoding(s);
9410 return;
9413 handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd);
9414 break;
9416 case 0x18 ... 0x31:
9417 /* floating point ops, sz[1] and U are part of opcode */
9418 disas_simd_3same_float(s, insn);
9419 break;
9420 default:
9421 disas_simd_3same_int(s, insn);
9422 break;
9426 static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
9427 int size, int rn, int rd)
9429 /* Handle 2-reg-misc ops which are widening (so each size element
9430 * in the source becomes a 2*size element in the destination.
9431 * The only instruction like this is FCVTL.
9433 int pass;
9435 if (size == 3) {
9436 /* 32 -> 64 bit fp conversion */
9437 TCGv_i64 tcg_res[2];
9438 int srcelt = is_q ? 2 : 0;
9440 for (pass = 0; pass < 2; pass++) {
9441 TCGv_i32 tcg_op = tcg_temp_new_i32();
9442 tcg_res[pass] = tcg_temp_new_i64();
9444 read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);
9445 gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env);
9446 tcg_temp_free_i32(tcg_op);
9448 for (pass = 0; pass < 2; pass++) {
9449 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
9450 tcg_temp_free_i64(tcg_res[pass]);
9452 } else {
9453 /* 16 -> 32 bit fp conversion */
9454 int srcelt = is_q ? 4 : 0;
9455 TCGv_i32 tcg_res[4];
9457 for (pass = 0; pass < 4; pass++) {
9458 tcg_res[pass] = tcg_temp_new_i32();
9460 read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);
9461 gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass],
9462 cpu_env);
9464 for (pass = 0; pass < 4; pass++) {
9465 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
9466 tcg_temp_free_i32(tcg_res[pass]);
9471 static void handle_rev(DisasContext *s, int opcode, bool u,
9472 bool is_q, int size, int rn, int rd)
9474 int op = (opcode << 1) | u;
9475 int opsz = op + size;
9476 int grp_size = 3 - opsz;
9477 int dsize = is_q ? 128 : 64;
9478 int i;
9480 if (opsz >= 3) {
9481 unallocated_encoding(s);
9482 return;
9485 if (!fp_access_check(s)) {
9486 return;
9489 if (size == 0) {
9490 /* Special case bytes, use bswap op on each group of elements */
9491 int groups = dsize / (8 << grp_size);
9493 for (i = 0; i < groups; i++) {
9494 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
9496 read_vec_element(s, tcg_tmp, rn, i, grp_size);
9497 switch (grp_size) {
9498 case MO_16:
9499 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
9500 break;
9501 case MO_32:
9502 tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
9503 break;
9504 case MO_64:
9505 tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
9506 break;
9507 default:
9508 g_assert_not_reached();
9510 write_vec_element(s, tcg_tmp, rd, i, grp_size);
9511 tcg_temp_free_i64(tcg_tmp);
9513 if (!is_q) {
9514 clear_vec_high(s, rd);
9516 } else {
9517 int revmask = (1 << grp_size) - 1;
9518 int esize = 8 << size;
9519 int elements = dsize / esize;
9520 TCGv_i64 tcg_rn = tcg_temp_new_i64();
9521 TCGv_i64 tcg_rd = tcg_const_i64(0);
9522 TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
9524 for (i = 0; i < elements; i++) {
9525 int e_rev = (i & 0xf) ^ revmask;
9526 int off = e_rev * esize;
9527 read_vec_element(s, tcg_rn, rn, i, size);
9528 if (off >= 64) {
9529 tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
9530 tcg_rn, off - 64, esize);
9531 } else {
9532 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
9535 write_vec_element(s, tcg_rd, rd, 0, MO_64);
9536 write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
9538 tcg_temp_free_i64(tcg_rd_hi);
9539 tcg_temp_free_i64(tcg_rd);
9540 tcg_temp_free_i64(tcg_rn);
9544 static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
9545 bool is_q, int size, int rn, int rd)
9547 /* Implement the pairwise operations from 2-misc:
9548 * SADDLP, UADDLP, SADALP, UADALP.
9549 * These all add pairs of elements in the input to produce a
9550 * double-width result element in the output (possibly accumulating).
9552 bool accum = (opcode == 0x6);
9553 int maxpass = is_q ? 2 : 1;
9554 int pass;
9555 TCGv_i64 tcg_res[2];
9557 if (size == 2) {
9558 /* 32 + 32 -> 64 op */
9559 TCGMemOp memop = size + (u ? 0 : MO_SIGN);
9561 for (pass = 0; pass < maxpass; pass++) {
9562 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
9563 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
9565 tcg_res[pass] = tcg_temp_new_i64();
9567 read_vec_element(s, tcg_op1, rn, pass * 2, memop);
9568 read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop);
9569 tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
9570 if (accum) {
9571 read_vec_element(s, tcg_op1, rd, pass, MO_64);
9572 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
9575 tcg_temp_free_i64(tcg_op1);
9576 tcg_temp_free_i64(tcg_op2);
9578 } else {
9579 for (pass = 0; pass < maxpass; pass++) {
9580 TCGv_i64 tcg_op = tcg_temp_new_i64();
9581 NeonGenOneOpFn *genfn;
9582 static NeonGenOneOpFn * const fns[2][2] = {
9583 { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 },
9584 { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 },
9587 genfn = fns[size][u];
9589 tcg_res[pass] = tcg_temp_new_i64();
9591 read_vec_element(s, tcg_op, rn, pass, MO_64);
9592 genfn(tcg_res[pass], tcg_op);
9594 if (accum) {
9595 read_vec_element(s, tcg_op, rd, pass, MO_64);
9596 if (size == 0) {
9597 gen_helper_neon_addl_u16(tcg_res[pass],
9598 tcg_res[pass], tcg_op);
9599 } else {
9600 gen_helper_neon_addl_u32(tcg_res[pass],
9601 tcg_res[pass], tcg_op);
9604 tcg_temp_free_i64(tcg_op);
9607 if (!is_q) {
9608 tcg_res[1] = tcg_const_i64(0);
9610 for (pass = 0; pass < 2; pass++) {
9611 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
9612 tcg_temp_free_i64(tcg_res[pass]);
9616 static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
9618 /* Implement SHLL and SHLL2 */
9619 int pass;
9620 int part = is_q ? 2 : 0;
9621 TCGv_i64 tcg_res[2];
9623 for (pass = 0; pass < 2; pass++) {
9624 static NeonGenWidenFn * const widenfns[3] = {
9625 gen_helper_neon_widen_u8,
9626 gen_helper_neon_widen_u16,
9627 tcg_gen_extu_i32_i64,
9629 NeonGenWidenFn *widenfn = widenfns[size];
9630 TCGv_i32 tcg_op = tcg_temp_new_i32();
9632 read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);
9633 tcg_res[pass] = tcg_temp_new_i64();
9634 widenfn(tcg_res[pass], tcg_op);
9635 tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);
9637 tcg_temp_free_i32(tcg_op);
9640 for (pass = 0; pass < 2; pass++) {
9641 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
9642 tcg_temp_free_i64(tcg_res[pass]);
9646 /* C3.6.17 AdvSIMD two reg misc
9647 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9648 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9649 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9650 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9652 static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
9654 int size = extract32(insn, 22, 2);
9655 int opcode = extract32(insn, 12, 5);
9656 bool u = extract32(insn, 29, 1);
9657 bool is_q = extract32(insn, 30, 1);
9658 int rn = extract32(insn, 5, 5);
9659 int rd = extract32(insn, 0, 5);
9660 bool need_fpstatus = false;
9661 bool need_rmode = false;
9662 int rmode = -1;
9663 TCGv_i32 tcg_rmode;
9664 TCGv_ptr tcg_fpstatus;
9666 switch (opcode) {
9667 case 0x0: /* REV64, REV32 */
9668 case 0x1: /* REV16 */
9669 handle_rev(s, opcode, u, is_q, size, rn, rd);
9670 return;
9671 case 0x5: /* CNT, NOT, RBIT */
9672 if (u && size == 0) {
9673 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9674 size = 3;
9675 break;
9676 } else if (u && size == 1) {
9677 /* RBIT */
9678 break;
9679 } else if (!u && size == 0) {
9680 /* CNT */
9681 break;
9683 unallocated_encoding(s);
9684 return;
9685 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9686 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9687 if (size == 3) {
9688 unallocated_encoding(s);
9689 return;
9691 if (!fp_access_check(s)) {
9692 return;
9695 handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
9696 return;
9697 case 0x4: /* CLS, CLZ */
9698 if (size == 3) {
9699 unallocated_encoding(s);
9700 return;
9702 break;
9703 case 0x2: /* SADDLP, UADDLP */
9704 case 0x6: /* SADALP, UADALP */
9705 if (size == 3) {
9706 unallocated_encoding(s);
9707 return;
9709 if (!fp_access_check(s)) {
9710 return;
9712 handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd);
9713 return;
9714 case 0x13: /* SHLL, SHLL2 */
9715 if (u == 0 || size == 3) {
9716 unallocated_encoding(s);
9717 return;
9719 if (!fp_access_check(s)) {
9720 return;
9722 handle_shll(s, is_q, size, rn, rd);
9723 return;
9724 case 0xa: /* CMLT */
9725 if (u == 1) {
9726 unallocated_encoding(s);
9727 return;
9729 /* fall through */
9730 case 0x8: /* CMGT, CMGE */
9731 case 0x9: /* CMEQ, CMLE */
9732 case 0xb: /* ABS, NEG */
9733 if (size == 3 && !is_q) {
9734 unallocated_encoding(s);
9735 return;
9737 break;
9738 case 0x3: /* SUQADD, USQADD */
9739 if (size == 3 && !is_q) {
9740 unallocated_encoding(s);
9741 return;
9743 if (!fp_access_check(s)) {
9744 return;
9746 handle_2misc_satacc(s, false, u, is_q, size, rn, rd);
9747 return;
9748 case 0x7: /* SQABS, SQNEG */
9749 if (size == 3 && !is_q) {
9750 unallocated_encoding(s);
9751 return;
9753 break;
9754 case 0xc ... 0xf:
9755 case 0x16 ... 0x1d:
9756 case 0x1f:
9758 /* Floating point: U, size[1] and opcode indicate operation;
9759 * size[0] indicates single or double precision.
9761 int is_double = extract32(size, 0, 1);
9762 opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
9763 size = is_double ? 3 : 2;
9764 switch (opcode) {
9765 case 0x2f: /* FABS */
9766 case 0x6f: /* FNEG */
9767 if (size == 3 && !is_q) {
9768 unallocated_encoding(s);
9769 return;
9771 break;
9772 case 0x1d: /* SCVTF */
9773 case 0x5d: /* UCVTF */
9775 bool is_signed = (opcode == 0x1d) ? true : false;
9776 int elements = is_double ? 2 : is_q ? 4 : 2;
9777 if (is_double && !is_q) {
9778 unallocated_encoding(s);
9779 return;
9781 if (!fp_access_check(s)) {
9782 return;
9784 handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size);
9785 return;
9787 case 0x2c: /* FCMGT (zero) */
9788 case 0x2d: /* FCMEQ (zero) */
9789 case 0x2e: /* FCMLT (zero) */
9790 case 0x6c: /* FCMGE (zero) */
9791 case 0x6d: /* FCMLE (zero) */
9792 if (size == 3 && !is_q) {
9793 unallocated_encoding(s);
9794 return;
9796 handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
9797 return;
9798 case 0x7f: /* FSQRT */
9799 if (size == 3 && !is_q) {
9800 unallocated_encoding(s);
9801 return;
9803 break;
9804 case 0x1a: /* FCVTNS */
9805 case 0x1b: /* FCVTMS */
9806 case 0x3a: /* FCVTPS */
9807 case 0x3b: /* FCVTZS */
9808 case 0x5a: /* FCVTNU */
9809 case 0x5b: /* FCVTMU */
9810 case 0x7a: /* FCVTPU */
9811 case 0x7b: /* FCVTZU */
9812 need_fpstatus = true;
9813 need_rmode = true;
9814 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
9815 if (size == 3 && !is_q) {
9816 unallocated_encoding(s);
9817 return;
9819 break;
9820 case 0x5c: /* FCVTAU */
9821 case 0x1c: /* FCVTAS */
9822 need_fpstatus = true;
9823 need_rmode = true;
9824 rmode = FPROUNDING_TIEAWAY;
9825 if (size == 3 && !is_q) {
9826 unallocated_encoding(s);
9827 return;
9829 break;
9830 case 0x3c: /* URECPE */
9831 if (size == 3) {
9832 unallocated_encoding(s);
9833 return;
9835 /* fall through */
9836 case 0x3d: /* FRECPE */
9837 case 0x7d: /* FRSQRTE */
9838 if (size == 3 && !is_q) {
9839 unallocated_encoding(s);
9840 return;
9842 if (!fp_access_check(s)) {
9843 return;
9845 handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd);
9846 return;
9847 case 0x56: /* FCVTXN, FCVTXN2 */
9848 if (size == 2) {
9849 unallocated_encoding(s);
9850 return;
9852 /* fall through */
9853 case 0x16: /* FCVTN, FCVTN2 */
9854 /* handle_2misc_narrow does a 2*size -> size operation, but these
9855 * instructions encode the source size rather than dest size.
9857 if (!fp_access_check(s)) {
9858 return;
9860 handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
9861 return;
9862 case 0x17: /* FCVTL, FCVTL2 */
9863 if (!fp_access_check(s)) {
9864 return;
9866 handle_2misc_widening(s, opcode, is_q, size, rn, rd);
9867 return;
9868 case 0x18: /* FRINTN */
9869 case 0x19: /* FRINTM */
9870 case 0x38: /* FRINTP */
9871 case 0x39: /* FRINTZ */
9872 need_rmode = true;
9873 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
9874 /* fall through */
9875 case 0x59: /* FRINTX */
9876 case 0x79: /* FRINTI */
9877 need_fpstatus = true;
9878 if (size == 3 && !is_q) {
9879 unallocated_encoding(s);
9880 return;
9882 break;
9883 case 0x58: /* FRINTA */
9884 need_rmode = true;
9885 rmode = FPROUNDING_TIEAWAY;
9886 need_fpstatus = true;
9887 if (size == 3 && !is_q) {
9888 unallocated_encoding(s);
9889 return;
9891 break;
9892 case 0x7c: /* URSQRTE */
9893 if (size == 3) {
9894 unallocated_encoding(s);
9895 return;
9897 need_fpstatus = true;
9898 break;
9899 default:
9900 unallocated_encoding(s);
9901 return;
9903 break;
9905 default:
9906 unallocated_encoding(s);
9907 return;
9910 if (!fp_access_check(s)) {
9911 return;
9914 if (need_fpstatus) {
9915 tcg_fpstatus = get_fpstatus_ptr();
9916 } else {
9917 TCGV_UNUSED_PTR(tcg_fpstatus);
9919 if (need_rmode) {
9920 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
9921 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
9922 } else {
9923 TCGV_UNUSED_I32(tcg_rmode);
9926 if (size == 3) {
9927 /* All 64-bit element operations can be shared with scalar 2misc */
9928 int pass;
9930 for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
9931 TCGv_i64 tcg_op = tcg_temp_new_i64();
9932 TCGv_i64 tcg_res = tcg_temp_new_i64();
9934 read_vec_element(s, tcg_op, rn, pass, MO_64);
9936 handle_2misc_64(s, opcode, u, tcg_res, tcg_op,
9937 tcg_rmode, tcg_fpstatus);
9939 write_vec_element(s, tcg_res, rd, pass, MO_64);
9941 tcg_temp_free_i64(tcg_res);
9942 tcg_temp_free_i64(tcg_op);
9944 } else {
9945 int pass;
9947 for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
9948 TCGv_i32 tcg_op = tcg_temp_new_i32();
9949 TCGv_i32 tcg_res = tcg_temp_new_i32();
9950 TCGCond cond;
9952 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
9954 if (size == 2) {
9955 /* Special cases for 32 bit elements */
9956 switch (opcode) {
9957 case 0xa: /* CMLT */
9958 /* 32 bit integer comparison against zero, result is
9959 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9960 * and inverting.
9962 cond = TCG_COND_LT;
9963 do_cmop:
9964 tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0);
9965 tcg_gen_neg_i32(tcg_res, tcg_res);
9966 break;
9967 case 0x8: /* CMGT, CMGE */
9968 cond = u ? TCG_COND_GE : TCG_COND_GT;
9969 goto do_cmop;
9970 case 0x9: /* CMEQ, CMLE */
9971 cond = u ? TCG_COND_LE : TCG_COND_EQ;
9972 goto do_cmop;
9973 case 0x4: /* CLS */
9974 if (u) {
9975 gen_helper_clz32(tcg_res, tcg_op);
9976 } else {
9977 gen_helper_cls32(tcg_res, tcg_op);
9979 break;
9980 case 0x7: /* SQABS, SQNEG */
9981 if (u) {
9982 gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op);
9983 } else {
9984 gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
9986 break;
9987 case 0xb: /* ABS, NEG */
9988 if (u) {
9989 tcg_gen_neg_i32(tcg_res, tcg_op);
9990 } else {
9991 TCGv_i32 tcg_zero = tcg_const_i32(0);
9992 tcg_gen_neg_i32(tcg_res, tcg_op);
9993 tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op,
9994 tcg_zero, tcg_op, tcg_res);
9995 tcg_temp_free_i32(tcg_zero);
9997 break;
9998 case 0x2f: /* FABS */
9999 gen_helper_vfp_abss(tcg_res, tcg_op);
10000 break;
10001 case 0x6f: /* FNEG */
10002 gen_helper_vfp_negs(tcg_res, tcg_op);
10003 break;
10004 case 0x7f: /* FSQRT */
10005 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
10006 break;
10007 case 0x1a: /* FCVTNS */
10008 case 0x1b: /* FCVTMS */
10009 case 0x1c: /* FCVTAS */
10010 case 0x3a: /* FCVTPS */
10011 case 0x3b: /* FCVTZS */
10013 TCGv_i32 tcg_shift = tcg_const_i32(0);
10014 gen_helper_vfp_tosls(tcg_res, tcg_op,
10015 tcg_shift, tcg_fpstatus);
10016 tcg_temp_free_i32(tcg_shift);
10017 break;
10019 case 0x5a: /* FCVTNU */
10020 case 0x5b: /* FCVTMU */
10021 case 0x5c: /* FCVTAU */
10022 case 0x7a: /* FCVTPU */
10023 case 0x7b: /* FCVTZU */
10025 TCGv_i32 tcg_shift = tcg_const_i32(0);
10026 gen_helper_vfp_touls(tcg_res, tcg_op,
10027 tcg_shift, tcg_fpstatus);
10028 tcg_temp_free_i32(tcg_shift);
10029 break;
10031 case 0x18: /* FRINTN */
10032 case 0x19: /* FRINTM */
10033 case 0x38: /* FRINTP */
10034 case 0x39: /* FRINTZ */
10035 case 0x58: /* FRINTA */
10036 case 0x79: /* FRINTI */
10037 gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus);
10038 break;
10039 case 0x59: /* FRINTX */
10040 gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus);
10041 break;
10042 case 0x7c: /* URSQRTE */
10043 gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus);
10044 break;
10045 default:
10046 g_assert_not_reached();
10048 } else {
10049 /* Use helpers for 8 and 16 bit elements */
10050 switch (opcode) {
10051 case 0x5: /* CNT, RBIT */
10052 /* For these two insns size is part of the opcode specifier
10053 * (handled earlier); they always operate on byte elements.
10055 if (u) {
10056 gen_helper_neon_rbit_u8(tcg_res, tcg_op);
10057 } else {
10058 gen_helper_neon_cnt_u8(tcg_res, tcg_op);
10060 break;
10061 case 0x7: /* SQABS, SQNEG */
10063 NeonGenOneOpEnvFn *genfn;
10064 static NeonGenOneOpEnvFn * const fns[2][2] = {
10065 { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
10066 { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
10068 genfn = fns[size][u];
10069 genfn(tcg_res, cpu_env, tcg_op);
10070 break;
10072 case 0x8: /* CMGT, CMGE */
10073 case 0x9: /* CMEQ, CMLE */
10074 case 0xa: /* CMLT */
10076 static NeonGenTwoOpFn * const fns[3][2] = {
10077 { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 },
10078 { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 },
10079 { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 },
10081 NeonGenTwoOpFn *genfn;
10082 int comp;
10083 bool reverse;
10084 TCGv_i32 tcg_zero = tcg_const_i32(0);
10086 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
10087 comp = (opcode - 0x8) * 2 + u;
10088 /* ...but LE, LT are implemented as reverse GE, GT */
10089 reverse = (comp > 2);
10090 if (reverse) {
10091 comp = 4 - comp;
10093 genfn = fns[comp][size];
10094 if (reverse) {
10095 genfn(tcg_res, tcg_zero, tcg_op);
10096 } else {
10097 genfn(tcg_res, tcg_op, tcg_zero);
10099 tcg_temp_free_i32(tcg_zero);
10100 break;
10102 case 0xb: /* ABS, NEG */
10103 if (u) {
10104 TCGv_i32 tcg_zero = tcg_const_i32(0);
10105 if (size) {
10106 gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op);
10107 } else {
10108 gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op);
10110 tcg_temp_free_i32(tcg_zero);
10111 } else {
10112 if (size) {
10113 gen_helper_neon_abs_s16(tcg_res, tcg_op);
10114 } else {
10115 gen_helper_neon_abs_s8(tcg_res, tcg_op);
10118 break;
10119 case 0x4: /* CLS, CLZ */
10120 if (u) {
10121 if (size == 0) {
10122 gen_helper_neon_clz_u8(tcg_res, tcg_op);
10123 } else {
10124 gen_helper_neon_clz_u16(tcg_res, tcg_op);
10126 } else {
10127 if (size == 0) {
10128 gen_helper_neon_cls_s8(tcg_res, tcg_op);
10129 } else {
10130 gen_helper_neon_cls_s16(tcg_res, tcg_op);
10133 break;
10134 default:
10135 g_assert_not_reached();
10139 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
10141 tcg_temp_free_i32(tcg_res);
10142 tcg_temp_free_i32(tcg_op);
10145 if (!is_q) {
10146 clear_vec_high(s, rd);
10149 if (need_rmode) {
10150 gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
10151 tcg_temp_free_i32(tcg_rmode);
10153 if (need_fpstatus) {
10154 tcg_temp_free_ptr(tcg_fpstatus);
10158 /* C3.6.13 AdvSIMD scalar x indexed element
10159 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10160 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10161 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10162 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10163 * C3.6.18 AdvSIMD vector x indexed element
10164 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10165 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10166 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10167 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10169 static void disas_simd_indexed(DisasContext *s, uint32_t insn)
10171 /* This encoding has two kinds of instruction:
10172 * normal, where we perform elt x idxelt => elt for each
10173 * element in the vector
10174 * long, where we perform elt x idxelt and generate a result of
10175 * double the width of the input element
10176 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10178 bool is_scalar = extract32(insn, 28, 1);
10179 bool is_q = extract32(insn, 30, 1);
10180 bool u = extract32(insn, 29, 1);
10181 int size = extract32(insn, 22, 2);
10182 int l = extract32(insn, 21, 1);
10183 int m = extract32(insn, 20, 1);
10184 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10185 int rm = extract32(insn, 16, 4);
10186 int opcode = extract32(insn, 12, 4);
10187 int h = extract32(insn, 11, 1);
10188 int rn = extract32(insn, 5, 5);
10189 int rd = extract32(insn, 0, 5);
10190 bool is_long = false;
10191 bool is_fp = false;
10192 int index;
10193 TCGv_ptr fpst;
10195 switch (opcode) {
10196 case 0x0: /* MLA */
10197 case 0x4: /* MLS */
10198 if (!u || is_scalar) {
10199 unallocated_encoding(s);
10200 return;
10202 break;
10203 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10204 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10205 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10206 if (is_scalar) {
10207 unallocated_encoding(s);
10208 return;
10210 is_long = true;
10211 break;
10212 case 0x3: /* SQDMLAL, SQDMLAL2 */
10213 case 0x7: /* SQDMLSL, SQDMLSL2 */
10214 case 0xb: /* SQDMULL, SQDMULL2 */
10215 is_long = true;
10216 /* fall through */
10217 case 0xc: /* SQDMULH */
10218 case 0xd: /* SQRDMULH */
10219 if (u) {
10220 unallocated_encoding(s);
10221 return;
10223 break;
10224 case 0x8: /* MUL */
10225 if (u || is_scalar) {
10226 unallocated_encoding(s);
10227 return;
10229 break;
10230 case 0x1: /* FMLA */
10231 case 0x5: /* FMLS */
10232 if (u) {
10233 unallocated_encoding(s);
10234 return;
10236 /* fall through */
10237 case 0x9: /* FMUL, FMULX */
10238 if (!extract32(size, 1, 1)) {
10239 unallocated_encoding(s);
10240 return;
10242 is_fp = true;
10243 break;
10244 default:
10245 unallocated_encoding(s);
10246 return;
10249 if (is_fp) {
10250 /* low bit of size indicates single/double */
10251 size = extract32(size, 0, 1) ? 3 : 2;
10252 if (size == 2) {
10253 index = h << 1 | l;
10254 } else {
10255 if (l || !is_q) {
10256 unallocated_encoding(s);
10257 return;
10259 index = h;
10261 rm |= (m << 4);
10262 } else {
10263 switch (size) {
10264 case 1:
10265 index = h << 2 | l << 1 | m;
10266 break;
10267 case 2:
10268 index = h << 1 | l;
10269 rm |= (m << 4);
10270 break;
10271 default:
10272 unallocated_encoding(s);
10273 return;
10277 if (!fp_access_check(s)) {
10278 return;
10281 if (is_fp) {
10282 fpst = get_fpstatus_ptr();
10283 } else {
10284 TCGV_UNUSED_PTR(fpst);
10287 if (size == 3) {
10288 TCGv_i64 tcg_idx = tcg_temp_new_i64();
10289 int pass;
10291 assert(is_fp && is_q && !is_long);
10293 read_vec_element(s, tcg_idx, rm, index, MO_64);
10295 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
10296 TCGv_i64 tcg_op = tcg_temp_new_i64();
10297 TCGv_i64 tcg_res = tcg_temp_new_i64();
10299 read_vec_element(s, tcg_op, rn, pass, MO_64);
10301 switch (opcode) {
10302 case 0x5: /* FMLS */
10303 /* As usual for ARM, separate negation for fused multiply-add */
10304 gen_helper_vfp_negd(tcg_op, tcg_op);
10305 /* fall through */
10306 case 0x1: /* FMLA */
10307 read_vec_element(s, tcg_res, rd, pass, MO_64);
10308 gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
10309 break;
10310 case 0x9: /* FMUL, FMULX */
10311 if (u) {
10312 gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst);
10313 } else {
10314 gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst);
10316 break;
10317 default:
10318 g_assert_not_reached();
10321 write_vec_element(s, tcg_res, rd, pass, MO_64);
10322 tcg_temp_free_i64(tcg_op);
10323 tcg_temp_free_i64(tcg_res);
10326 if (is_scalar) {
10327 clear_vec_high(s, rd);
10330 tcg_temp_free_i64(tcg_idx);
10331 } else if (!is_long) {
10332 /* 32 bit floating point, or 16 or 32 bit integer.
10333 * For the 16 bit scalar case we use the usual Neon helpers and
10334 * rely on the fact that 0 op 0 == 0 with no side effects.
10336 TCGv_i32 tcg_idx = tcg_temp_new_i32();
10337 int pass, maxpasses;
10339 if (is_scalar) {
10340 maxpasses = 1;
10341 } else {
10342 maxpasses = is_q ? 4 : 2;
10345 read_vec_element_i32(s, tcg_idx, rm, index, size);
10347 if (size == 1 && !is_scalar) {
10348 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10349 * the index into both halves of the 32 bit tcg_idx and then use
10350 * the usual Neon helpers.
10352 tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
10355 for (pass = 0; pass < maxpasses; pass++) {
10356 TCGv_i32 tcg_op = tcg_temp_new_i32();
10357 TCGv_i32 tcg_res = tcg_temp_new_i32();
10359 read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
10361 switch (opcode) {
10362 case 0x0: /* MLA */
10363 case 0x4: /* MLS */
10364 case 0x8: /* MUL */
10366 static NeonGenTwoOpFn * const fns[2][2] = {
10367 { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
10368 { tcg_gen_add_i32, tcg_gen_sub_i32 },
10370 NeonGenTwoOpFn *genfn;
10371 bool is_sub = opcode == 0x4;
10373 if (size == 1) {
10374 gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx);
10375 } else {
10376 tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx);
10378 if (opcode == 0x8) {
10379 break;
10381 read_vec_element_i32(s, tcg_op, rd, pass, MO_32);
10382 genfn = fns[size - 1][is_sub];
10383 genfn(tcg_res, tcg_op, tcg_res);
10384 break;
10386 case 0x5: /* FMLS */
10387 /* As usual for ARM, separate negation for fused multiply-add */
10388 gen_helper_vfp_negs(tcg_op, tcg_op);
10389 /* fall through */
10390 case 0x1: /* FMLA */
10391 read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
10392 gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
10393 break;
10394 case 0x9: /* FMUL, FMULX */
10395 if (u) {
10396 gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
10397 } else {
10398 gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
10400 break;
10401 case 0xc: /* SQDMULH */
10402 if (size == 1) {
10403 gen_helper_neon_qdmulh_s16(tcg_res, cpu_env,
10404 tcg_op, tcg_idx);
10405 } else {
10406 gen_helper_neon_qdmulh_s32(tcg_res, cpu_env,
10407 tcg_op, tcg_idx);
10409 break;
10410 case 0xd: /* SQRDMULH */
10411 if (size == 1) {
10412 gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
10413 tcg_op, tcg_idx);
10414 } else {
10415 gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
10416 tcg_op, tcg_idx);
10418 break;
10419 default:
10420 g_assert_not_reached();
10423 if (is_scalar) {
10424 write_fp_sreg(s, rd, tcg_res);
10425 } else {
10426 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
10429 tcg_temp_free_i32(tcg_op);
10430 tcg_temp_free_i32(tcg_res);
10433 tcg_temp_free_i32(tcg_idx);
10435 if (!is_q) {
10436 clear_vec_high(s, rd);
10438 } else {
10439 /* long ops: 16x16->32 or 32x32->64 */
10440 TCGv_i64 tcg_res[2];
10441 int pass;
10442 bool satop = extract32(opcode, 0, 1);
10443 TCGMemOp memop = MO_32;
10445 if (satop || !u) {
10446 memop |= MO_SIGN;
10449 if (size == 2) {
10450 TCGv_i64 tcg_idx = tcg_temp_new_i64();
10452 read_vec_element(s, tcg_idx, rm, index, memop);
10454 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
10455 TCGv_i64 tcg_op = tcg_temp_new_i64();
10456 TCGv_i64 tcg_passres;
10457 int passelt;
10459 if (is_scalar) {
10460 passelt = 0;
10461 } else {
10462 passelt = pass + (is_q * 2);
10465 read_vec_element(s, tcg_op, rn, passelt, memop);
10467 tcg_res[pass] = tcg_temp_new_i64();
10469 if (opcode == 0xa || opcode == 0xb) {
10470 /* Non-accumulating ops */
10471 tcg_passres = tcg_res[pass];
10472 } else {
10473 tcg_passres = tcg_temp_new_i64();
10476 tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx);
10477 tcg_temp_free_i64(tcg_op);
10479 if (satop) {
10480 /* saturating, doubling */
10481 gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
10482 tcg_passres, tcg_passres);
10485 if (opcode == 0xa || opcode == 0xb) {
10486 continue;
10489 /* Accumulating op: handle accumulate step */
10490 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10492 switch (opcode) {
10493 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10494 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
10495 break;
10496 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10497 tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
10498 break;
10499 case 0x7: /* SQDMLSL, SQDMLSL2 */
10500 tcg_gen_neg_i64(tcg_passres, tcg_passres);
10501 /* fall through */
10502 case 0x3: /* SQDMLAL, SQDMLAL2 */
10503 gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
10504 tcg_res[pass],
10505 tcg_passres);
10506 break;
10507 default:
10508 g_assert_not_reached();
10510 tcg_temp_free_i64(tcg_passres);
10512 tcg_temp_free_i64(tcg_idx);
10514 if (is_scalar) {
10515 clear_vec_high(s, rd);
10517 } else {
10518 TCGv_i32 tcg_idx = tcg_temp_new_i32();
10520 assert(size == 1);
10521 read_vec_element_i32(s, tcg_idx, rm, index, size);
10523 if (!is_scalar) {
10524 /* The simplest way to handle the 16x16 indexed ops is to
10525 * duplicate the index into both halves of the 32 bit tcg_idx
10526 * and then use the usual Neon helpers.
10528 tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
10531 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
10532 TCGv_i32 tcg_op = tcg_temp_new_i32();
10533 TCGv_i64 tcg_passres;
10535 if (is_scalar) {
10536 read_vec_element_i32(s, tcg_op, rn, pass, size);
10537 } else {
10538 read_vec_element_i32(s, tcg_op, rn,
10539 pass + (is_q * 2), MO_32);
10542 tcg_res[pass] = tcg_temp_new_i64();
10544 if (opcode == 0xa || opcode == 0xb) {
10545 /* Non-accumulating ops */
10546 tcg_passres = tcg_res[pass];
10547 } else {
10548 tcg_passres = tcg_temp_new_i64();
10551 if (memop & MO_SIGN) {
10552 gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx);
10553 } else {
10554 gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx);
10556 if (satop) {
10557 gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
10558 tcg_passres, tcg_passres);
10560 tcg_temp_free_i32(tcg_op);
10562 if (opcode == 0xa || opcode == 0xb) {
10563 continue;
10566 /* Accumulating op: handle accumulate step */
10567 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10569 switch (opcode) {
10570 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10571 gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass],
10572 tcg_passres);
10573 break;
10574 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10575 gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass],
10576 tcg_passres);
10577 break;
10578 case 0x7: /* SQDMLSL, SQDMLSL2 */
10579 gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
10580 /* fall through */
10581 case 0x3: /* SQDMLAL, SQDMLAL2 */
10582 gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
10583 tcg_res[pass],
10584 tcg_passres);
10585 break;
10586 default:
10587 g_assert_not_reached();
10589 tcg_temp_free_i64(tcg_passres);
10591 tcg_temp_free_i32(tcg_idx);
10593 if (is_scalar) {
10594 tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]);
10598 if (is_scalar) {
10599 tcg_res[1] = tcg_const_i64(0);
10602 for (pass = 0; pass < 2; pass++) {
10603 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10604 tcg_temp_free_i64(tcg_res[pass]);
10608 if (!TCGV_IS_UNUSED_PTR(fpst)) {
10609 tcg_temp_free_ptr(fpst);
10613 /* C3.6.19 Crypto AES
10614 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10615 * +-----------------+------+-----------+--------+-----+------+------+
10616 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10617 * +-----------------+------+-----------+--------+-----+------+------+
10619 static void disas_crypto_aes(DisasContext *s, uint32_t insn)
10621 int size = extract32(insn, 22, 2);
10622 int opcode = extract32(insn, 12, 5);
10623 int rn = extract32(insn, 5, 5);
10624 int rd = extract32(insn, 0, 5);
10625 int decrypt;
10626 TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_decrypt;
10627 CryptoThreeOpEnvFn *genfn;
10629 if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)
10630 || size != 0) {
10631 unallocated_encoding(s);
10632 return;
10635 switch (opcode) {
10636 case 0x4: /* AESE */
10637 decrypt = 0;
10638 genfn = gen_helper_crypto_aese;
10639 break;
10640 case 0x6: /* AESMC */
10641 decrypt = 0;
10642 genfn = gen_helper_crypto_aesmc;
10643 break;
10644 case 0x5: /* AESD */
10645 decrypt = 1;
10646 genfn = gen_helper_crypto_aese;
10647 break;
10648 case 0x7: /* AESIMC */
10649 decrypt = 1;
10650 genfn = gen_helper_crypto_aesmc;
10651 break;
10652 default:
10653 unallocated_encoding(s);
10654 return;
10657 /* Note that we convert the Vx register indexes into the
10658 * index within the vfp.regs[] array, so we can share the
10659 * helper with the AArch32 instructions.
10661 tcg_rd_regno = tcg_const_i32(rd << 1);
10662 tcg_rn_regno = tcg_const_i32(rn << 1);
10663 tcg_decrypt = tcg_const_i32(decrypt);
10665 genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_decrypt);
10667 tcg_temp_free_i32(tcg_rd_regno);
10668 tcg_temp_free_i32(tcg_rn_regno);
10669 tcg_temp_free_i32(tcg_decrypt);
10672 /* C3.6.20 Crypto three-reg SHA
10673 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10674 * +-----------------+------+---+------+---+--------+-----+------+------+
10675 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10676 * +-----------------+------+---+------+---+--------+-----+------+------+
10678 static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
10680 int size = extract32(insn, 22, 2);
10681 int opcode = extract32(insn, 12, 3);
10682 int rm = extract32(insn, 16, 5);
10683 int rn = extract32(insn, 5, 5);
10684 int rd = extract32(insn, 0, 5);
10685 CryptoThreeOpEnvFn *genfn;
10686 TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_rm_regno;
10687 int feature = ARM_FEATURE_V8_SHA256;
10689 if (size != 0) {
10690 unallocated_encoding(s);
10691 return;
10694 switch (opcode) {
10695 case 0: /* SHA1C */
10696 case 1: /* SHA1P */
10697 case 2: /* SHA1M */
10698 case 3: /* SHA1SU0 */
10699 genfn = NULL;
10700 feature = ARM_FEATURE_V8_SHA1;
10701 break;
10702 case 4: /* SHA256H */
10703 genfn = gen_helper_crypto_sha256h;
10704 break;
10705 case 5: /* SHA256H2 */
10706 genfn = gen_helper_crypto_sha256h2;
10707 break;
10708 case 6: /* SHA256SU1 */
10709 genfn = gen_helper_crypto_sha256su1;
10710 break;
10711 default:
10712 unallocated_encoding(s);
10713 return;
10716 if (!arm_dc_feature(s, feature)) {
10717 unallocated_encoding(s);
10718 return;
10721 tcg_rd_regno = tcg_const_i32(rd << 1);
10722 tcg_rn_regno = tcg_const_i32(rn << 1);
10723 tcg_rm_regno = tcg_const_i32(rm << 1);
10725 if (genfn) {
10726 genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_rm_regno);
10727 } else {
10728 TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
10730 gen_helper_crypto_sha1_3reg(cpu_env, tcg_rd_regno,
10731 tcg_rn_regno, tcg_rm_regno, tcg_opcode);
10732 tcg_temp_free_i32(tcg_opcode);
10735 tcg_temp_free_i32(tcg_rd_regno);
10736 tcg_temp_free_i32(tcg_rn_regno);
10737 tcg_temp_free_i32(tcg_rm_regno);
10740 /* C3.6.21 Crypto two-reg SHA
10741 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10742 * +-----------------+------+-----------+--------+-----+------+------+
10743 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10744 * +-----------------+------+-----------+--------+-----+------+------+
10746 static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
10748 int size = extract32(insn, 22, 2);
10749 int opcode = extract32(insn, 12, 5);
10750 int rn = extract32(insn, 5, 5);
10751 int rd = extract32(insn, 0, 5);
10752 CryptoTwoOpEnvFn *genfn;
10753 int feature;
10754 TCGv_i32 tcg_rd_regno, tcg_rn_regno;
10756 if (size != 0) {
10757 unallocated_encoding(s);
10758 return;
10761 switch (opcode) {
10762 case 0: /* SHA1H */
10763 feature = ARM_FEATURE_V8_SHA1;
10764 genfn = gen_helper_crypto_sha1h;
10765 break;
10766 case 1: /* SHA1SU1 */
10767 feature = ARM_FEATURE_V8_SHA1;
10768 genfn = gen_helper_crypto_sha1su1;
10769 break;
10770 case 2: /* SHA256SU0 */
10771 feature = ARM_FEATURE_V8_SHA256;
10772 genfn = gen_helper_crypto_sha256su0;
10773 break;
10774 default:
10775 unallocated_encoding(s);
10776 return;
10779 if (!arm_dc_feature(s, feature)) {
10780 unallocated_encoding(s);
10781 return;
10784 tcg_rd_regno = tcg_const_i32(rd << 1);
10785 tcg_rn_regno = tcg_const_i32(rn << 1);
10787 genfn(cpu_env, tcg_rd_regno, tcg_rn_regno);
10789 tcg_temp_free_i32(tcg_rd_regno);
10790 tcg_temp_free_i32(tcg_rn_regno);
10793 /* C3.6 Data processing - SIMD, inc Crypto
10795 * As the decode gets a little complex we are using a table based
10796 * approach for this part of the decode.
10798 static const AArch64DecodeTable data_proc_simd[] = {
10799 /* pattern , mask , fn */
10800 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same },
10801 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff },
10802 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
10803 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
10804 { 0x0e000400, 0x9fe08400, disas_simd_copy },
10805 { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */
10806 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10807 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm },
10808 { 0x0f000400, 0x9f800400, disas_simd_shift_imm },
10809 { 0x0e000000, 0xbf208c00, disas_simd_tb },
10810 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
10811 { 0x2e000000, 0xbf208400, disas_simd_ext },
10812 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same },
10813 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
10814 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
10815 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },
10816 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy },
10817 { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
10818 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
10819 { 0x4e280800, 0xff3e0c00, disas_crypto_aes },
10820 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
10821 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
10822 { 0x00000000, 0x00000000, NULL }
10825 static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
10827 /* Note that this is called with all non-FP cases from
10828 * table C3-6 so it must UNDEF for entries not specifically
10829 * allocated to instructions in that table.
10831 AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
10832 if (fn) {
10833 fn(s, insn);
10834 } else {
10835 unallocated_encoding(s);
10839 /* C3.6 Data processing - SIMD and floating point */
10840 static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
10842 if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
10843 disas_data_proc_fp(s, insn);
10844 } else {
10845 /* SIMD, including crypto */
10846 disas_data_proc_simd(s, insn);
10850 /* C3.1 A64 instruction index by encoding */
10851 static void disas_a64_insn(CPUARMState *env, DisasContext *s)
10853 uint32_t insn;
10855 insn = arm_ldl_code(env, s->pc, s->bswap_code);
10856 s->insn = insn;
10857 s->pc += 4;
10859 s->fp_access_checked = false;
10861 switch (extract32(insn, 25, 4)) {
10862 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10863 unallocated_encoding(s);
10864 break;
10865 case 0x8: case 0x9: /* Data processing - immediate */
10866 disas_data_proc_imm(s, insn);
10867 break;
10868 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10869 disas_b_exc_sys(s, insn);
10870 break;
10871 case 0x4:
10872 case 0x6:
10873 case 0xc:
10874 case 0xe: /* Loads and stores */
10875 disas_ldst(s, insn);
10876 break;
10877 case 0x5:
10878 case 0xd: /* Data processing - register */
10879 disas_data_proc_reg(s, insn);
10880 break;
10881 case 0x7:
10882 case 0xf: /* Data processing - SIMD and floating point */
10883 disas_data_proc_simd_fp(s, insn);
10884 break;
10885 default:
10886 assert(FALSE); /* all 15 cases should be handled above */
10887 break;
10890 /* if we allocated any temporaries, free them here */
10891 free_tmp_a64(s);
10894 void gen_intermediate_code_internal_a64(ARMCPU *cpu,
10895 TranslationBlock *tb,
10896 bool search_pc)
10898 CPUState *cs = CPU(cpu);
10899 CPUARMState *env = &cpu->env;
10900 DisasContext dc1, *dc = &dc1;
10901 CPUBreakpoint *bp;
10902 uint16_t *gen_opc_end;
10903 int j, lj;
10904 target_ulong pc_start;
10905 target_ulong next_page_start;
10906 int num_insns;
10907 int max_insns;
10909 pc_start = tb->pc;
10911 dc->tb = tb;
10913 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
10915 dc->is_jmp = DISAS_NEXT;
10916 dc->pc = pc_start;
10917 dc->singlestep_enabled = cs->singlestep_enabled;
10918 dc->condjmp = 0;
10920 dc->aarch64 = 1;
10921 dc->thumb = 0;
10922 dc->bswap_code = 0;
10923 dc->condexec_mask = 0;
10924 dc->condexec_cond = 0;
10925 #if !defined(CONFIG_USER_ONLY)
10926 dc->user = (ARM_TBFLAG_AA64_EL(tb->flags) == 0);
10927 #endif
10928 dc->cpacr_fpen = ARM_TBFLAG_AA64_FPEN(tb->flags);
10929 dc->vec_len = 0;
10930 dc->vec_stride = 0;
10931 dc->cp_regs = cpu->cp_regs;
10932 dc->current_el = arm_current_el(env);
10933 dc->features = env->features;
10935 /* Single step state. The code-generation logic here is:
10936 * SS_ACTIVE == 0:
10937 * generate code with no special handling for single-stepping (except
10938 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
10939 * this happens anyway because those changes are all system register or
10940 * PSTATE writes).
10941 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
10942 * emit code for one insn
10943 * emit code to clear PSTATE.SS
10944 * emit code to generate software step exception for completed step
10945 * end TB (as usual for having generated an exception)
10946 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
10947 * emit code to generate a software step exception
10948 * end the TB
10950 dc->ss_active = ARM_TBFLAG_AA64_SS_ACTIVE(tb->flags);
10951 dc->pstate_ss = ARM_TBFLAG_AA64_PSTATE_SS(tb->flags);
10952 dc->is_ldex = false;
10953 dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
10955 init_tmp_a64_array(dc);
10957 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
10958 lj = -1;
10959 num_insns = 0;
10960 max_insns = tb->cflags & CF_COUNT_MASK;
10961 if (max_insns == 0) {
10962 max_insns = CF_COUNT_MASK;
10965 gen_tb_start();
10967 tcg_clear_temp_count();
10969 do {
10970 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
10971 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
10972 if (bp->pc == dc->pc) {
10973 gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
10974 /* Advance PC so that clearing the breakpoint will
10975 invalidate this TB. */
10976 dc->pc += 2;
10977 goto done_generating;
10982 if (search_pc) {
10983 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10984 if (lj < j) {
10985 lj++;
10986 while (lj < j) {
10987 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10990 tcg_ctx.gen_opc_pc[lj] = dc->pc;
10991 tcg_ctx.gen_opc_instr_start[lj] = 1;
10992 tcg_ctx.gen_opc_icount[lj] = num_insns;
10995 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
10996 gen_io_start();
10999 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11000 tcg_gen_debug_insn_start(dc->pc);
11003 if (dc->ss_active && !dc->pstate_ss) {
11004 /* Singlestep state is Active-pending.
11005 * If we're in this state at the start of a TB then either
11006 * a) we just took an exception to an EL which is being debugged
11007 * and this is the first insn in the exception handler
11008 * b) debug exceptions were masked and we just unmasked them
11009 * without changing EL (eg by clearing PSTATE.D)
11010 * In either case we're going to take a swstep exception in the
11011 * "did not step an insn" case, and so the syndrome ISV and EX
11012 * bits should be zero.
11014 assert(num_insns == 0);
11015 gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0));
11016 dc->is_jmp = DISAS_EXC;
11017 break;
11020 disas_a64_insn(env, dc);
11022 if (tcg_check_temp_count()) {
11023 fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n",
11024 dc->pc);
11027 /* Translation stops when a conditional branch is encountered.
11028 * Otherwise the subsequent code could get translated several times.
11029 * Also stop translation when a page boundary is reached. This
11030 * ensures prefetch aborts occur at the right place.
11032 num_insns++;
11033 } while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
11034 !cs->singlestep_enabled &&
11035 !singlestep &&
11036 !dc->ss_active &&
11037 dc->pc < next_page_start &&
11038 num_insns < max_insns);
11040 if (tb->cflags & CF_LAST_IO) {
11041 gen_io_end();
11044 if (unlikely(cs->singlestep_enabled || dc->ss_active)
11045 && dc->is_jmp != DISAS_EXC) {
11046 /* Note that this means single stepping WFI doesn't halt the CPU.
11047 * For conditional branch insns this is harmless unreachable code as
11048 * gen_goto_tb() has already handled emitting the debug exception
11049 * (and thus a tb-jump is not possible when singlestepping).
11051 assert(dc->is_jmp != DISAS_TB_JUMP);
11052 if (dc->is_jmp != DISAS_JUMP) {
11053 gen_a64_set_pc_im(dc->pc);
11055 if (cs->singlestep_enabled) {
11056 gen_exception_internal(EXCP_DEBUG);
11057 } else {
11058 gen_step_complete_exception(dc);
11060 } else {
11061 switch (dc->is_jmp) {
11062 case DISAS_NEXT:
11063 gen_goto_tb(dc, 1, dc->pc);
11064 break;
11065 default:
11066 case DISAS_UPDATE:
11067 gen_a64_set_pc_im(dc->pc);
11068 /* fall through */
11069 case DISAS_JUMP:
11070 /* indicate that the hash table must be used to find the next TB */
11071 tcg_gen_exit_tb(0);
11072 break;
11073 case DISAS_TB_JUMP:
11074 case DISAS_EXC:
11075 case DISAS_SWI:
11076 break;
11077 case DISAS_WFE:
11078 gen_a64_set_pc_im(dc->pc);
11079 gen_helper_wfe(cpu_env);
11080 break;
11081 case DISAS_WFI:
11082 /* This is a special case because we don't want to just halt the CPU
11083 * if trying to debug across a WFI.
11085 gen_a64_set_pc_im(dc->pc);
11086 gen_helper_wfi(cpu_env);
11087 break;
11091 done_generating:
11092 gen_tb_end(tb, num_insns);
11093 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11095 #ifdef DEBUG_DISAS
11096 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11097 qemu_log("----------------\n");
11098 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11099 log_target_disas(env, pc_start, dc->pc - pc_start,
11100 4 | (dc->bswap_code << 1));
11101 qemu_log("\n");
11103 #endif
11104 if (search_pc) {
11105 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11106 lj++;
11107 while (lj <= j) {
11108 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11110 } else {
11111 tb->size = dc->pc - pc_start;
11112 tb->icount = num_insns;