2 * AArch64 specific helpers
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "exec/gdbstub.h"
22 #include "exec/helper-proto.h"
23 #include "qemu/host-utils.h"
24 #include "sysemu/sysemu.h"
25 #include "qemu/bitops.h"
26 #include "internals.h"
27 #include "qemu/crc32c.h"
28 #include <zlib.h> /* For crc32 */
30 /* C2.4.7 Multiply and divide */
31 /* special cases for 0 and LLONG_MIN are mandated by the standard */
32 uint64_t HELPER(udiv64
)(uint64_t num
, uint64_t den
)
40 int64_t HELPER(sdiv64
)(int64_t num
, int64_t den
)
45 if (num
== LLONG_MIN
&& den
== -1) {
51 uint64_t HELPER(clz64
)(uint64_t x
)
56 uint64_t HELPER(cls64
)(uint64_t x
)
61 uint32_t HELPER(cls32
)(uint32_t x
)
66 uint32_t HELPER(clz32
)(uint32_t x
)
71 uint64_t HELPER(rbit64
)(uint64_t x
)
73 /* assign the correct byte position */
76 /* assign the correct nibble position */
77 x
= ((x
& 0xf0f0f0f0f0f0f0f0ULL
) >> 4)
78 | ((x
& 0x0f0f0f0f0f0f0f0fULL
) << 4);
80 /* assign the correct bit position */
81 x
= ((x
& 0x8888888888888888ULL
) >> 3)
82 | ((x
& 0x4444444444444444ULL
) >> 1)
83 | ((x
& 0x2222222222222222ULL
) << 1)
84 | ((x
& 0x1111111111111111ULL
) << 3);
89 /* Convert a softfloat float_relation_ (as returned by
90 * the float*_compare functions) to the correct ARM
93 static inline uint32_t float_rel_to_flags(int res
)
97 case float_relation_equal
:
98 flags
= PSTATE_Z
| PSTATE_C
;
100 case float_relation_less
:
103 case float_relation_greater
:
106 case float_relation_unordered
:
108 flags
= PSTATE_C
| PSTATE_V
;
114 uint64_t HELPER(vfp_cmps_a64
)(float32 x
, float32 y
, void *fp_status
)
116 return float_rel_to_flags(float32_compare_quiet(x
, y
, fp_status
));
119 uint64_t HELPER(vfp_cmpes_a64
)(float32 x
, float32 y
, void *fp_status
)
121 return float_rel_to_flags(float32_compare(x
, y
, fp_status
));
124 uint64_t HELPER(vfp_cmpd_a64
)(float64 x
, float64 y
, void *fp_status
)
126 return float_rel_to_flags(float64_compare_quiet(x
, y
, fp_status
));
129 uint64_t HELPER(vfp_cmped_a64
)(float64 x
, float64 y
, void *fp_status
)
131 return float_rel_to_flags(float64_compare(x
, y
, fp_status
));
134 float32
HELPER(vfp_mulxs
)(float32 a
, float32 b
, void *fpstp
)
136 float_status
*fpst
= fpstp
;
138 if ((float32_is_zero(a
) && float32_is_infinity(b
)) ||
139 (float32_is_infinity(a
) && float32_is_zero(b
))) {
140 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
141 return make_float32((1U << 30) |
142 ((float32_val(a
) ^ float32_val(b
)) & (1U << 31)));
144 return float32_mul(a
, b
, fpst
);
147 float64
HELPER(vfp_mulxd
)(float64 a
, float64 b
, void *fpstp
)
149 float_status
*fpst
= fpstp
;
151 if ((float64_is_zero(a
) && float64_is_infinity(b
)) ||
152 (float64_is_infinity(a
) && float64_is_zero(b
))) {
153 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
154 return make_float64((1ULL << 62) |
155 ((float64_val(a
) ^ float64_val(b
)) & (1ULL << 63)));
157 return float64_mul(a
, b
, fpst
);
160 uint64_t HELPER(simd_tbl
)(CPUARMState
*env
, uint64_t result
, uint64_t indices
,
161 uint32_t rn
, uint32_t numregs
)
163 /* Helper function for SIMD TBL and TBX. We have to do the table
164 * lookup part for the 64 bits worth of indices we're passed in.
165 * result is the initial results vector (either zeroes for TBL
166 * or some guest values for TBX), rn the register number where
167 * the table starts, and numregs the number of registers in the table.
168 * We return the results of the lookups.
172 for (shift
= 0; shift
< 64; shift
+= 8) {
173 int index
= extract64(indices
, shift
, 8);
174 if (index
< 16 * numregs
) {
175 /* Convert index (a byte offset into the virtual table
176 * which is a series of 128-bit vectors concatenated)
177 * into the correct vfp.regs[] element plus a bit offset
178 * into that element, bearing in mind that the table
179 * can wrap around from V31 to V0.
181 int elt
= (rn
* 2 + (index
>> 3)) % 64;
182 int bitidx
= (index
& 7) * 8;
183 uint64_t val
= extract64(env
->vfp
.regs
[elt
], bitidx
, 8);
185 result
= deposit64(result
, shift
, 8, val
);
191 /* 64bit/double versions of the neon float compare functions */
192 uint64_t HELPER(neon_ceq_f64
)(float64 a
, float64 b
, void *fpstp
)
194 float_status
*fpst
= fpstp
;
195 return -float64_eq_quiet(a
, b
, fpst
);
198 uint64_t HELPER(neon_cge_f64
)(float64 a
, float64 b
, void *fpstp
)
200 float_status
*fpst
= fpstp
;
201 return -float64_le(b
, a
, fpst
);
204 uint64_t HELPER(neon_cgt_f64
)(float64 a
, float64 b
, void *fpstp
)
206 float_status
*fpst
= fpstp
;
207 return -float64_lt(b
, a
, fpst
);
210 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
211 * versions, these do a fully fused multiply-add or
212 * multiply-add-and-halve.
214 #define float32_two make_float32(0x40000000)
215 #define float32_three make_float32(0x40400000)
216 #define float32_one_point_five make_float32(0x3fc00000)
218 #define float64_two make_float64(0x4000000000000000ULL)
219 #define float64_three make_float64(0x4008000000000000ULL)
220 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
222 float32
HELPER(recpsf_f32
)(float32 a
, float32 b
, void *fpstp
)
224 float_status
*fpst
= fpstp
;
227 if ((float32_is_infinity(a
) && float32_is_zero(b
)) ||
228 (float32_is_infinity(b
) && float32_is_zero(a
))) {
231 return float32_muladd(a
, b
, float32_two
, 0, fpst
);
234 float64
HELPER(recpsf_f64
)(float64 a
, float64 b
, void *fpstp
)
236 float_status
*fpst
= fpstp
;
239 if ((float64_is_infinity(a
) && float64_is_zero(b
)) ||
240 (float64_is_infinity(b
) && float64_is_zero(a
))) {
243 return float64_muladd(a
, b
, float64_two
, 0, fpst
);
246 float32
HELPER(rsqrtsf_f32
)(float32 a
, float32 b
, void *fpstp
)
248 float_status
*fpst
= fpstp
;
251 if ((float32_is_infinity(a
) && float32_is_zero(b
)) ||
252 (float32_is_infinity(b
) && float32_is_zero(a
))) {
253 return float32_one_point_five
;
255 return float32_muladd(a
, b
, float32_three
, float_muladd_halve_result
, fpst
);
258 float64
HELPER(rsqrtsf_f64
)(float64 a
, float64 b
, void *fpstp
)
260 float_status
*fpst
= fpstp
;
263 if ((float64_is_infinity(a
) && float64_is_zero(b
)) ||
264 (float64_is_infinity(b
) && float64_is_zero(a
))) {
265 return float64_one_point_five
;
267 return float64_muladd(a
, b
, float64_three
, float_muladd_halve_result
, fpst
);
270 /* Pairwise long add: add pairs of adjacent elements into
271 * double-width elements in the result (eg _s8 is an 8x8->16 op)
273 uint64_t HELPER(neon_addlp_s8
)(uint64_t a
)
275 uint64_t nsignmask
= 0x0080008000800080ULL
;
276 uint64_t wsignmask
= 0x8000800080008000ULL
;
277 uint64_t elementmask
= 0x00ff00ff00ff00ffULL
;
279 uint64_t res
, signres
;
281 /* Extract odd elements, sign extend each to a 16 bit field */
282 tmp1
= a
& elementmask
;
285 tmp1
= (tmp1
- nsignmask
) ^ wsignmask
;
286 /* Ditto for the even elements */
287 tmp2
= (a
>> 8) & elementmask
;
290 tmp2
= (tmp2
- nsignmask
) ^ wsignmask
;
292 /* calculate the result by summing bits 0..14, 16..22, etc,
293 * and then adjusting the sign bits 15, 23, etc manually.
294 * This ensures the addition can't overflow the 16 bit field.
296 signres
= (tmp1
^ tmp2
) & wsignmask
;
297 res
= (tmp1
& ~wsignmask
) + (tmp2
& ~wsignmask
);
303 uint64_t HELPER(neon_addlp_u8
)(uint64_t a
)
307 tmp
= a
& 0x00ff00ff00ff00ffULL
;
308 tmp
+= (a
>> 8) & 0x00ff00ff00ff00ffULL
;
312 uint64_t HELPER(neon_addlp_s16
)(uint64_t a
)
314 int32_t reslo
, reshi
;
316 reslo
= (int32_t)(int16_t)a
+ (int32_t)(int16_t)(a
>> 16);
317 reshi
= (int32_t)(int16_t)(a
>> 32) + (int32_t)(int16_t)(a
>> 48);
319 return (uint32_t)reslo
| (((uint64_t)reshi
) << 32);
322 uint64_t HELPER(neon_addlp_u16
)(uint64_t a
)
326 tmp
= a
& 0x0000ffff0000ffffULL
;
327 tmp
+= (a
>> 16) & 0x0000ffff0000ffffULL
;
331 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
332 float32
HELPER(frecpx_f32
)(float32 a
, void *fpstp
)
334 float_status
*fpst
= fpstp
;
335 uint32_t val32
, sbit
;
338 if (float32_is_any_nan(a
)) {
340 if (float32_is_signaling_nan(a
)) {
341 float_raise(float_flag_invalid
, fpst
);
342 nan
= float32_maybe_silence_nan(a
);
344 if (fpst
->default_nan_mode
) {
345 nan
= float32_default_nan
;
350 val32
= float32_val(a
);
351 sbit
= 0x80000000ULL
& val32
;
352 exp
= extract32(val32
, 23, 8);
355 return make_float32(sbit
| (0xfe << 23));
357 return make_float32(sbit
| (~exp
& 0xff) << 23);
361 float64
HELPER(frecpx_f64
)(float64 a
, void *fpstp
)
363 float_status
*fpst
= fpstp
;
364 uint64_t val64
, sbit
;
367 if (float64_is_any_nan(a
)) {
369 if (float64_is_signaling_nan(a
)) {
370 float_raise(float_flag_invalid
, fpst
);
371 nan
= float64_maybe_silence_nan(a
);
373 if (fpst
->default_nan_mode
) {
374 nan
= float64_default_nan
;
379 val64
= float64_val(a
);
380 sbit
= 0x8000000000000000ULL
& val64
;
381 exp
= extract64(float64_val(a
), 52, 11);
384 return make_float64(sbit
| (0x7feULL
<< 52));
386 return make_float64(sbit
| (~exp
& 0x7ffULL
) << 52);
390 float32
HELPER(fcvtx_f64_to_f32
)(float64 a
, CPUARMState
*env
)
392 /* Von Neumann rounding is implemented by using round-to-zero
393 * and then setting the LSB of the result if Inexact was raised.
396 float_status
*fpst
= &env
->vfp
.fp_status
;
397 float_status tstat
= *fpst
;
400 set_float_rounding_mode(float_round_to_zero
, &tstat
);
401 set_float_exception_flags(0, &tstat
);
402 r
= float64_to_float32(a
, &tstat
);
403 r
= float32_maybe_silence_nan(r
);
404 exflags
= get_float_exception_flags(&tstat
);
405 if (exflags
& float_flag_inexact
) {
406 r
= make_float32(float32_val(r
) | 1);
408 exflags
|= get_float_exception_flags(fpst
);
409 set_float_exception_flags(exflags
, fpst
);
413 /* 64-bit versions of the CRC helpers. Note that although the operation
414 * (and the prototypes of crc32c() and crc32() mean that only the bottom
415 * 32 bits of the accumulator and result are used, we pass and return
416 * uint64_t for convenience of the generated code. Unlike the 32-bit
417 * instruction set versions, val may genuinely have 64 bits of data in it.
418 * The upper bytes of val (above the number specified by 'bytes') must have
419 * been zeroed out by the caller.
421 uint64_t HELPER(crc32_64
)(uint64_t acc
, uint64_t val
, uint32_t bytes
)
427 /* zlib crc32 converts the accumulator and output to one's complement. */
428 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
431 uint64_t HELPER(crc32c_64
)(uint64_t acc
, uint64_t val
, uint32_t bytes
)
437 /* Linux crc32c converts the output to one's complement. */
438 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
441 #if !defined(CONFIG_USER_ONLY)
443 /* Handle a CPU exception. */
444 void aarch64_cpu_do_interrupt(CPUState
*cs
)
446 ARMCPU
*cpu
= ARM_CPU(cs
);
447 CPUARMState
*env
= &cpu
->env
;
448 unsigned int new_el
= arm_excp_target_el(cs
, cs
->exception_index
);
449 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
450 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
453 if (arm_current_el(env
) < new_el
) {
459 } else if (pstate_read(env
) & PSTATE_SP
) {
463 arm_log_exception(cs
->exception_index
);
464 qemu_log_mask(CPU_LOG_INT
, "...from EL%d\n", arm_current_el(env
));
465 if (qemu_loglevel_mask(CPU_LOG_INT
)
466 && !excp_is_internal(cs
->exception_index
)) {
467 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%" PRIx32
"\n",
468 env
->exception
.syndrome
);
471 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
472 arm_handle_psci_call(cpu
);
473 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
477 switch (cs
->exception_index
) {
478 case EXCP_PREFETCH_ABORT
:
479 case EXCP_DATA_ABORT
:
480 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
481 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
482 env
->cp15
.far_el
[new_el
]);
490 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
501 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
505 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
506 aarch64_save_sp(env
, arm_current_el(env
));
507 env
->elr_el
[new_el
] = env
->pc
;
509 env
->banked_spsr
[0] = cpsr_read(env
);
511 env
->cp15
.esr_el
[new_el
] |= 1 << 25;
513 env
->elr_el
[new_el
] = env
->regs
[15];
515 for (i
= 0; i
< 15; i
++) {
516 env
->xregs
[i
] = env
->regs
[i
];
519 env
->condexec_bits
= 0;
522 pstate_write(env
, PSTATE_DAIF
| new_mode
);
524 aarch64_restore_sp(env
, new_el
);
527 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;