4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qemu/datadir.h"
28 #include "qemu/units.h"
30 #include "hw/pci/pci.h"
31 #include "hw/pci/pci_bridge.h"
32 #include "hw/pci/pci_bus.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/qdev-properties-system.h"
36 #include "migration/qemu-file-types.h"
37 #include "migration/vmstate.h"
38 #include "monitor/monitor.h"
40 #include "sysemu/numa.h"
41 #include "sysemu/sysemu.h"
42 #include "hw/loader.h"
43 #include "qemu/error-report.h"
44 #include "qemu/range.h"
46 #include "hw/pci/msi.h"
47 #include "hw/pci/msix.h"
48 #include "exec/address-spaces.h"
49 #include "hw/hotplug.h"
50 #include "hw/boards.h"
51 #include "qapi/error.h"
52 #include "qapi/qapi-commands-pci.h"
53 #include "qemu/cutils.h"
57 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
59 # define PCI_DPRINTF(format, ...) do { } while (0)
62 bool pci_available
= true;
64 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
65 static char *pcibus_get_dev_path(DeviceState
*dev
);
66 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
67 static void pcibus_reset(BusState
*qbus
);
69 static Property pci_props
[] = {
70 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
71 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
72 DEFINE_PROP_UINT32("romsize", PCIDevice
, romsize
, -1),
73 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
74 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
75 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
76 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice
, cap_present
,
77 QEMU_PCIE_LNKSTA_DLLLA_BITNR
, true),
78 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice
, cap_present
,
79 QEMU_PCIE_EXTCAP_INIT_BITNR
, true),
80 DEFINE_PROP_STRING("failover_pair_id", PCIDevice
,
82 DEFINE_PROP_END_OF_LIST()
85 static const VMStateDescription vmstate_pcibus
= {
88 .minimum_version_id
= 1,
89 .fields
= (VMStateField
[]) {
90 VMSTATE_INT32_EQUAL(nirq
, PCIBus
, NULL
),
91 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
,
92 nirq
, 0, vmstate_info_int32
,
98 static void pci_init_bus_master(PCIDevice
*pci_dev
)
100 AddressSpace
*dma_as
= pci_device_iommu_address_space(pci_dev
);
102 memory_region_init_alias(&pci_dev
->bus_master_enable_region
,
103 OBJECT(pci_dev
), "bus master",
104 dma_as
->root
, 0, memory_region_size(dma_as
->root
));
105 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
106 memory_region_add_subregion(&pci_dev
->bus_master_container_region
, 0,
107 &pci_dev
->bus_master_enable_region
);
110 static void pcibus_machine_done(Notifier
*notifier
, void *data
)
112 PCIBus
*bus
= container_of(notifier
, PCIBus
, machine_done
);
115 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
116 if (bus
->devices
[i
]) {
117 pci_init_bus_master(bus
->devices
[i
]);
122 static void pci_bus_realize(BusState
*qbus
, Error
**errp
)
124 PCIBus
*bus
= PCI_BUS(qbus
);
126 bus
->machine_done
.notify
= pcibus_machine_done
;
127 qemu_add_machine_init_done_notifier(&bus
->machine_done
);
129 vmstate_register(NULL
, VMSTATE_INSTANCE_ID_ANY
, &vmstate_pcibus
, bus
);
132 static void pcie_bus_realize(BusState
*qbus
, Error
**errp
)
134 PCIBus
*bus
= PCI_BUS(qbus
);
135 Error
*local_err
= NULL
;
137 pci_bus_realize(qbus
, &local_err
);
139 error_propagate(errp
, local_err
);
144 * A PCI-E bus can support extended config space if it's the root
145 * bus, or if the bus/bridge above it does as well
147 if (pci_bus_is_root(bus
)) {
148 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
150 PCIBus
*parent_bus
= pci_get_bus(bus
->parent_dev
);
152 if (pci_bus_allows_extended_config_space(parent_bus
)) {
153 bus
->flags
|= PCI_BUS_EXTENDED_CONFIG_SPACE
;
158 static void pci_bus_unrealize(BusState
*qbus
)
160 PCIBus
*bus
= PCI_BUS(qbus
);
162 qemu_remove_machine_init_done_notifier(&bus
->machine_done
);
164 vmstate_unregister(NULL
, &vmstate_pcibus
, bus
);
167 static int pcibus_num(PCIBus
*bus
)
169 if (pci_bus_is_root(bus
)) {
170 return 0; /* pci host bridge */
172 return bus
->parent_dev
->config
[PCI_SECONDARY_BUS
];
175 static uint16_t pcibus_numa_node(PCIBus
*bus
)
177 return NUMA_NODE_UNASSIGNED
;
180 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
182 BusClass
*k
= BUS_CLASS(klass
);
183 PCIBusClass
*pbc
= PCI_BUS_CLASS(klass
);
185 k
->print_dev
= pcibus_dev_print
;
186 k
->get_dev_path
= pcibus_get_dev_path
;
187 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
188 k
->realize
= pci_bus_realize
;
189 k
->unrealize
= pci_bus_unrealize
;
190 k
->reset
= pcibus_reset
;
192 pbc
->bus_num
= pcibus_num
;
193 pbc
->numa_node
= pcibus_numa_node
;
196 static const TypeInfo pci_bus_info
= {
197 .name
= TYPE_PCI_BUS
,
199 .instance_size
= sizeof(PCIBus
),
200 .class_size
= sizeof(PCIBusClass
),
201 .class_init
= pci_bus_class_init
,
204 static const TypeInfo pcie_interface_info
= {
205 .name
= INTERFACE_PCIE_DEVICE
,
206 .parent
= TYPE_INTERFACE
,
209 static const TypeInfo conventional_pci_interface_info
= {
210 .name
= INTERFACE_CONVENTIONAL_PCI_DEVICE
,
211 .parent
= TYPE_INTERFACE
,
214 static void pcie_bus_class_init(ObjectClass
*klass
, void *data
)
216 BusClass
*k
= BUS_CLASS(klass
);
218 k
->realize
= pcie_bus_realize
;
221 static const TypeInfo pcie_bus_info
= {
222 .name
= TYPE_PCIE_BUS
,
223 .parent
= TYPE_PCI_BUS
,
224 .class_init
= pcie_bus_class_init
,
227 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
228 static void pci_update_mappings(PCIDevice
*d
);
229 static void pci_irq_handler(void *opaque
, int irq_num
, int level
);
230 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
, Error
**);
231 static void pci_del_option_rom(PCIDevice
*pdev
);
233 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
234 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
236 static QLIST_HEAD(, PCIHostState
) pci_host_bridges
;
238 int pci_bar(PCIDevice
*d
, int reg
)
242 if (reg
!= PCI_ROM_SLOT
)
243 return PCI_BASE_ADDRESS_0
+ reg
* 4;
245 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
246 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
249 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
251 return (d
->irq_state
>> irq_num
) & 0x1;
254 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
256 d
->irq_state
&= ~(0x1 << irq_num
);
257 d
->irq_state
|= level
<< irq_num
;
260 static void pci_bus_change_irq_level(PCIBus
*bus
, int irq_num
, int change
)
262 assert(irq_num
>= 0);
263 assert(irq_num
< bus
->nirq
);
264 bus
->irq_count
[irq_num
] += change
;
265 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
268 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
272 bus
= pci_get_bus(pci_dev
);
273 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
276 pci_dev
= bus
->parent_dev
;
278 pci_bus_change_irq_level(bus
, irq_num
, change
);
281 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
283 assert(irq_num
>= 0);
284 assert(irq_num
< bus
->nirq
);
285 return !!bus
->irq_count
[irq_num
];
288 /* Update interrupt status bit in config space on interrupt
290 static void pci_update_irq_status(PCIDevice
*dev
)
292 if (dev
->irq_state
) {
293 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
295 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
299 void pci_device_deassert_intx(PCIDevice
*dev
)
302 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
303 pci_irq_handler(dev
, i
, 0);
307 static void pci_do_device_reset(PCIDevice
*dev
)
311 pci_device_deassert_intx(dev
);
312 assert(dev
->irq_state
== 0);
314 /* Clear all writable bits */
315 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
316 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
317 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
318 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
319 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
320 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
321 /* Some devices make bits of PCI_INTERRUPT_LINE read only */
322 pci_byte_test_and_clear_mask(dev
->config
+ PCI_INTERRUPT_LINE
,
323 pci_get_word(dev
->wmask
+ PCI_INTERRUPT_LINE
) |
324 pci_get_word(dev
->w1cmask
+ PCI_INTERRUPT_LINE
));
325 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
326 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
327 PCIIORegion
*region
= &dev
->io_regions
[r
];
332 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
333 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
334 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
336 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
339 pci_update_mappings(dev
);
346 * This function is called on #RST and FLR.
347 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
349 void pci_device_reset(PCIDevice
*dev
)
351 qdev_reset_all(&dev
->qdev
);
352 pci_do_device_reset(dev
);
356 * Trigger pci bus reset under a given bus.
357 * Called via qbus_reset_all on RST# assert, after the devices
358 * have been reset qdev_reset_all-ed already.
360 static void pcibus_reset(BusState
*qbus
)
362 PCIBus
*bus
= DO_UPCAST(PCIBus
, qbus
, qbus
);
365 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
366 if (bus
->devices
[i
]) {
367 pci_do_device_reset(bus
->devices
[i
]);
371 for (i
= 0; i
< bus
->nirq
; i
++) {
372 assert(bus
->irq_count
[i
] == 0);
376 static void pci_host_bus_register(DeviceState
*host
)
378 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
380 QLIST_INSERT_HEAD(&pci_host_bridges
, host_bridge
, next
);
383 static void pci_host_bus_unregister(DeviceState
*host
)
385 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(host
);
387 QLIST_REMOVE(host_bridge
, next
);
390 PCIBus
*pci_device_root_bus(const PCIDevice
*d
)
392 PCIBus
*bus
= pci_get_bus(d
);
394 while (!pci_bus_is_root(bus
)) {
398 bus
= pci_get_bus(d
);
404 const char *pci_root_bus_path(PCIDevice
*dev
)
406 PCIBus
*rootbus
= pci_device_root_bus(dev
);
407 PCIHostState
*host_bridge
= PCI_HOST_BRIDGE(rootbus
->qbus
.parent
);
408 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_GET_CLASS(host_bridge
);
410 assert(host_bridge
->bus
== rootbus
);
412 if (hc
->root_bus_path
) {
413 return (*hc
->root_bus_path
)(host_bridge
, rootbus
);
416 return rootbus
->qbus
.name
;
419 static void pci_root_bus_init(PCIBus
*bus
, DeviceState
*parent
,
420 MemoryRegion
*address_space_mem
,
421 MemoryRegion
*address_space_io
,
424 assert(PCI_FUNC(devfn_min
) == 0);
425 bus
->devfn_min
= devfn_min
;
426 bus
->slot_reserved_mask
= 0x0;
427 bus
->address_space_mem
= address_space_mem
;
428 bus
->address_space_io
= address_space_io
;
429 bus
->flags
|= PCI_BUS_IS_ROOT
;
432 QLIST_INIT(&bus
->child
);
434 pci_host_bus_register(parent
);
437 static void pci_bus_uninit(PCIBus
*bus
)
439 pci_host_bus_unregister(BUS(bus
)->parent
);
442 bool pci_bus_is_express(PCIBus
*bus
)
444 return object_dynamic_cast(OBJECT(bus
), TYPE_PCIE_BUS
);
447 void pci_root_bus_new_inplace(PCIBus
*bus
, size_t bus_size
, DeviceState
*parent
,
449 MemoryRegion
*address_space_mem
,
450 MemoryRegion
*address_space_io
,
451 uint8_t devfn_min
, const char *typename
)
453 qbus_create_inplace(bus
, bus_size
, typename
, parent
, name
);
454 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
458 PCIBus
*pci_root_bus_new(DeviceState
*parent
, const char *name
,
459 MemoryRegion
*address_space_mem
,
460 MemoryRegion
*address_space_io
,
461 uint8_t devfn_min
, const char *typename
)
465 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
466 pci_root_bus_init(bus
, parent
, address_space_mem
, address_space_io
,
471 void pci_root_bus_cleanup(PCIBus
*bus
)
474 /* the caller of the unplug hotplug handler will delete this device */
475 qbus_unrealize(BUS(bus
));
478 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
479 void *irq_opaque
, int nirq
)
481 bus
->set_irq
= set_irq
;
482 bus
->map_irq
= map_irq
;
483 bus
->irq_opaque
= irq_opaque
;
485 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
488 void pci_bus_irqs_cleanup(PCIBus
*bus
)
492 bus
->irq_opaque
= NULL
;
494 g_free(bus
->irq_count
);
497 PCIBus
*pci_register_root_bus(DeviceState
*parent
, const char *name
,
498 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
500 MemoryRegion
*address_space_mem
,
501 MemoryRegion
*address_space_io
,
502 uint8_t devfn_min
, int nirq
,
503 const char *typename
)
507 bus
= pci_root_bus_new(parent
, name
, address_space_mem
,
508 address_space_io
, devfn_min
, typename
);
509 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
513 void pci_unregister_root_bus(PCIBus
*bus
)
515 pci_bus_irqs_cleanup(bus
);
516 pci_root_bus_cleanup(bus
);
519 int pci_bus_num(PCIBus
*s
)
521 return PCI_BUS_GET_CLASS(s
)->bus_num(s
);
524 int pci_bus_numa_node(PCIBus
*bus
)
526 return PCI_BUS_GET_CLASS(bus
)->numa_node(bus
);
529 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
530 const VMStateField
*field
)
532 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
533 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(s
);
537 assert(size
== pci_config_size(s
));
538 config
= g_malloc(size
);
540 qemu_get_buffer(f
, config
, size
);
541 for (i
= 0; i
< size
; ++i
) {
542 if ((config
[i
] ^ s
->config
[i
]) &
543 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
544 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
545 "cmask: %x wmask: %x w1cmask:%x", __func__
,
546 i
, config
[i
], s
->config
[i
],
547 s
->cmask
[i
], s
->wmask
[i
], s
->w1cmask
[i
]);
552 memcpy(s
->config
, config
, size
);
554 pci_update_mappings(s
);
556 PCIBridge
*b
= PCI_BRIDGE(s
);
557 pci_bridge_update_mappings(b
);
560 memory_region_set_enabled(&s
->bus_master_enable_region
,
561 pci_get_word(s
->config
+ PCI_COMMAND
)
562 & PCI_COMMAND_MASTER
);
568 /* just put buffer */
569 static int put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
,
570 const VMStateField
*field
, JSONWriter
*vmdesc
)
572 const uint8_t **v
= pv
;
573 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
574 qemu_put_buffer(f
, *v
, size
);
579 static VMStateInfo vmstate_info_pci_config
= {
580 .name
= "pci config",
581 .get
= get_pci_config_device
,
582 .put
= put_pci_config_device
,
585 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
586 const VMStateField
*field
)
588 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
589 uint32_t irq_state
[PCI_NUM_PINS
];
591 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
592 irq_state
[i
] = qemu_get_be32(f
);
593 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
594 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
600 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
601 pci_set_irq_state(s
, i
, irq_state
[i
]);
607 static int put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
,
608 const VMStateField
*field
, JSONWriter
*vmdesc
)
611 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
613 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
614 qemu_put_be32(f
, pci_irq_state(s
, i
));
620 static VMStateInfo vmstate_info_pci_irq_state
= {
621 .name
= "pci irq state",
622 .get
= get_pci_irq_state
,
623 .put
= put_pci_irq_state
,
626 static bool migrate_is_pcie(void *opaque
, int version_id
)
628 return pci_is_express((PCIDevice
*)opaque
);
631 static bool migrate_is_not_pcie(void *opaque
, int version_id
)
633 return !pci_is_express((PCIDevice
*)opaque
);
636 const VMStateDescription vmstate_pci_device
= {
639 .minimum_version_id
= 1,
640 .fields
= (VMStateField
[]) {
641 VMSTATE_INT32_POSITIVE_LE(version_id
, PCIDevice
),
642 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
644 0, vmstate_info_pci_config
,
645 PCI_CONFIG_SPACE_SIZE
),
646 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config
, PCIDevice
,
648 0, vmstate_info_pci_config
,
649 PCIE_CONFIG_SPACE_SIZE
),
650 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
651 vmstate_info_pci_irq_state
,
652 PCI_NUM_PINS
* sizeof(int32_t)),
653 VMSTATE_END_OF_LIST()
658 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
660 /* Clear interrupt status bit: it is implicit
661 * in irq_state which we are saving.
662 * This makes us compatible with old devices
663 * which never set or clear this bit. */
664 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
665 vmstate_save_state(f
, &vmstate_pci_device
, s
, NULL
);
666 /* Restore the interrupt status bit. */
667 pci_update_irq_status(s
);
670 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
673 ret
= vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
674 /* Restore the interrupt status bit. */
675 pci_update_irq_status(s
);
679 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
681 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
682 pci_default_sub_vendor_id
);
683 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
684 pci_default_sub_device_id
);
688 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
689 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
691 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
692 unsigned int *slotp
, unsigned int *funcp
)
697 unsigned long dom
= 0, bus
= 0;
698 unsigned int slot
= 0;
699 unsigned int func
= 0;
702 val
= strtoul(p
, &e
, 16);
708 val
= strtoul(p
, &e
, 16);
715 val
= strtoul(p
, &e
, 16);
728 val
= strtoul(p
, &e
, 16);
735 /* if funcp == NULL func is 0 */
736 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
750 static void pci_init_cmask(PCIDevice
*dev
)
752 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
753 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
754 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
755 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
756 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
757 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
758 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
759 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
762 static void pci_init_wmask(PCIDevice
*dev
)
764 int config_size
= pci_config_size(dev
);
766 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
767 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
768 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
769 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
770 PCI_COMMAND_INTX_DISABLE
);
771 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
773 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
774 config_size
- PCI_CONFIG_HEADER_SIZE
);
777 static void pci_init_w1cmask(PCIDevice
*dev
)
780 * Note: It's okay to set w1cmask even for readonly bits as
781 * long as their value is hardwired to 0.
783 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
784 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
785 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
786 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
789 static void pci_init_mask_bridge(PCIDevice
*d
)
791 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
792 PCI_SEC_LETENCY_TIMER */
793 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
796 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
797 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
798 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
799 PCI_MEMORY_RANGE_MASK
& 0xffff);
800 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
801 PCI_MEMORY_RANGE_MASK
& 0xffff);
802 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
803 PCI_PREF_RANGE_MASK
& 0xffff);
804 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
805 PCI_PREF_RANGE_MASK
& 0xffff);
807 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
808 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
810 /* Supported memory and i/o types */
811 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
812 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
813 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
814 PCI_PREF_RANGE_TYPE_64
);
815 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
816 PCI_PREF_RANGE_TYPE_64
);
819 * TODO: Bridges default to 10-bit VGA decoding but we currently only
820 * implement 16-bit decoding (no alias support).
822 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
823 PCI_BRIDGE_CTL_PARITY
|
824 PCI_BRIDGE_CTL_SERR
|
827 PCI_BRIDGE_CTL_VGA_16BIT
|
828 PCI_BRIDGE_CTL_MASTER_ABORT
|
829 PCI_BRIDGE_CTL_BUS_RESET
|
830 PCI_BRIDGE_CTL_FAST_BACK
|
831 PCI_BRIDGE_CTL_DISCARD
|
832 PCI_BRIDGE_CTL_SEC_DISCARD
|
833 PCI_BRIDGE_CTL_DISCARD_SERR
);
834 /* Below does not do anything as we never set this bit, put here for
836 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
837 PCI_BRIDGE_CTL_DISCARD_STATUS
);
838 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
839 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
840 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
841 PCI_PREF_RANGE_TYPE_MASK
);
842 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
843 PCI_PREF_RANGE_TYPE_MASK
);
846 static void pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
, Error
**errp
)
848 uint8_t slot
= PCI_SLOT(dev
->devfn
);
851 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
852 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
856 * multifunction bit is interpreted in two ways as follows.
857 * - all functions must set the bit to 1.
859 * - function 0 must set the bit, but the rest function (> 0)
860 * is allowed to leave the bit to 0.
861 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
863 * So OS (at least Linux) checks the bit of only function 0,
864 * and doesn't see the bit of function > 0.
866 * The below check allows both interpretation.
868 if (PCI_FUNC(dev
->devfn
)) {
869 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
870 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
871 /* function 0 should set multifunction bit */
872 error_setg(errp
, "PCI: single function device can't be populated "
873 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
879 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
882 /* function 0 indicates single function, so function > 0 must be NULL */
883 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
884 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
885 error_setg(errp
, "PCI: %x.0 indicates single function, "
886 "but %x.%x is already populated.",
893 static void pci_config_alloc(PCIDevice
*pci_dev
)
895 int config_size
= pci_config_size(pci_dev
);
897 pci_dev
->config
= g_malloc0(config_size
);
898 pci_dev
->cmask
= g_malloc0(config_size
);
899 pci_dev
->wmask
= g_malloc0(config_size
);
900 pci_dev
->w1cmask
= g_malloc0(config_size
);
901 pci_dev
->used
= g_malloc0(config_size
);
904 static void pci_config_free(PCIDevice
*pci_dev
)
906 g_free(pci_dev
->config
);
907 g_free(pci_dev
->cmask
);
908 g_free(pci_dev
->wmask
);
909 g_free(pci_dev
->w1cmask
);
910 g_free(pci_dev
->used
);
913 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
915 pci_get_bus(pci_dev
)->devices
[pci_dev
->devfn
] = NULL
;
916 pci_config_free(pci_dev
);
918 if (memory_region_is_mapped(&pci_dev
->bus_master_enable_region
)) {
919 memory_region_del_subregion(&pci_dev
->bus_master_container_region
,
920 &pci_dev
->bus_master_enable_region
);
922 address_space_destroy(&pci_dev
->bus_master_as
);
925 /* Extract PCIReqIDCache into BDF format */
926 static uint16_t pci_req_id_cache_extract(PCIReqIDCache
*cache
)
931 switch (cache
->type
) {
933 result
= pci_get_bdf(cache
->dev
);
935 case PCI_REQ_ID_SECONDARY_BUS
:
936 bus_n
= pci_dev_bus_num(cache
->dev
);
937 result
= PCI_BUILD_BDF(bus_n
, 0);
940 error_report("Invalid PCI requester ID cache type: %d",
949 /* Parse bridges up to the root complex and return requester ID
950 * cache for specific device. For full PCIe topology, the cache
951 * result would be exactly the same as getting BDF of the device.
952 * However, several tricks are required when system mixed up with
953 * legacy PCI devices and PCIe-to-PCI bridges.
955 * Here we cache the proxy device (and type) not requester ID since
956 * bus number might change from time to time.
958 static PCIReqIDCache
pci_req_id_cache_get(PCIDevice
*dev
)
961 PCIReqIDCache cache
= {
963 .type
= PCI_REQ_ID_BDF
,
966 while (!pci_bus_is_root(pci_get_bus(dev
))) {
967 /* We are under PCI/PCIe bridges */
968 parent
= pci_get_bus(dev
)->parent_dev
;
969 if (pci_is_express(parent
)) {
970 if (pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
971 /* When we pass through PCIe-to-PCI/PCIX bridges, we
972 * override the requester ID using secondary bus
973 * number of parent bridge with zeroed devfn
974 * (pcie-to-pci bridge spec chap 2.3). */
975 cache
.type
= PCI_REQ_ID_SECONDARY_BUS
;
979 /* Legacy PCI, override requester ID with the bridge's
980 * BDF upstream. When the root complex connects to
981 * legacy PCI devices (including buses), it can only
982 * obtain requester ID info from directly attached
983 * devices. If devices are attached under bridges, only
984 * the requester ID of the bridge that is directly
985 * attached to the root complex can be recognized. */
986 cache
.type
= PCI_REQ_ID_BDF
;
995 uint16_t pci_requester_id(PCIDevice
*dev
)
997 return pci_req_id_cache_extract(&dev
->requester_id_cache
);
1000 static bool pci_bus_devfn_available(PCIBus
*bus
, int devfn
)
1002 return !(bus
->devices
[devfn
]);
1005 static bool pci_bus_devfn_reserved(PCIBus
*bus
, int devfn
)
1007 return bus
->slot_reserved_mask
& (1UL << PCI_SLOT(devfn
));
1010 /* -1 for devfn means auto assign */
1011 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
,
1012 const char *name
, int devfn
,
1015 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1016 PCIConfigReadFunc
*config_read
= pc
->config_read
;
1017 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
1018 Error
*local_err
= NULL
;
1019 DeviceState
*dev
= DEVICE(pci_dev
);
1020 PCIBus
*bus
= pci_get_bus(pci_dev
);
1022 /* Only pci bridges can be attached to extra PCI root buses */
1023 if (pci_bus_is_root(bus
) && bus
->parent_dev
&& !pc
->is_bridge
) {
1025 "PCI: Only PCI/PCIe bridges can be plugged into %s",
1026 bus
->parent_dev
->name
);
1031 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
1032 devfn
+= PCI_FUNC_MAX
) {
1033 if (pci_bus_devfn_available(bus
, devfn
) &&
1034 !pci_bus_devfn_reserved(bus
, devfn
)) {
1038 error_setg(errp
, "PCI: no slot/function available for %s, all in use "
1039 "or reserved", name
);
1042 } else if (pci_bus_devfn_reserved(bus
, devfn
)) {
1043 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1045 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
);
1047 } else if (!pci_bus_devfn_available(bus
, devfn
)) {
1048 error_setg(errp
, "PCI: slot %d function %d not available for %s,"
1050 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
,
1051 bus
->devices
[devfn
]->name
);
1053 } else if (dev
->hotplugged
&&
1054 pci_get_function_0(pci_dev
)) {
1055 error_setg(errp
, "PCI: slot %d function 0 already occupied by %s,"
1056 " new func %s cannot be exposed to guest.",
1057 PCI_SLOT(pci_get_function_0(pci_dev
)->devfn
),
1058 pci_get_function_0(pci_dev
)->name
,
1064 pci_dev
->devfn
= devfn
;
1065 pci_dev
->requester_id_cache
= pci_req_id_cache_get(pci_dev
);
1066 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
1068 memory_region_init(&pci_dev
->bus_master_container_region
, OBJECT(pci_dev
),
1069 "bus master container", UINT64_MAX
);
1070 address_space_init(&pci_dev
->bus_master_as
,
1071 &pci_dev
->bus_master_container_region
, pci_dev
->name
);
1073 if (phase_check(PHASE_MACHINE_READY
)) {
1074 pci_init_bus_master(pci_dev
);
1076 pci_dev
->irq_state
= 0;
1077 pci_config_alloc(pci_dev
);
1079 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
1080 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
1081 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
1082 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
1084 if (!pc
->is_bridge
) {
1085 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
1086 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
1087 pc
->subsystem_vendor_id
);
1088 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
1091 pci_set_default_subsystem_id(pci_dev
);
1094 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1095 assert(!pc
->subsystem_vendor_id
);
1096 assert(!pc
->subsystem_id
);
1098 pci_init_cmask(pci_dev
);
1099 pci_init_wmask(pci_dev
);
1100 pci_init_w1cmask(pci_dev
);
1101 if (pc
->is_bridge
) {
1102 pci_init_mask_bridge(pci_dev
);
1104 pci_init_multifunction(bus
, pci_dev
, &local_err
);
1106 error_propagate(errp
, local_err
);
1107 do_pci_unregister_device(pci_dev
);
1112 config_read
= pci_default_read_config
;
1114 config_write
= pci_default_write_config
;
1115 pci_dev
->config_read
= config_read
;
1116 pci_dev
->config_write
= config_write
;
1117 bus
->devices
[devfn
] = pci_dev
;
1118 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
1122 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
1127 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1128 r
= &pci_dev
->io_regions
[i
];
1129 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
1131 memory_region_del_subregion(r
->address_space
, r
->memory
);
1134 pci_unregister_vga(pci_dev
);
1137 static void pci_qdev_unrealize(DeviceState
*dev
)
1139 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
1140 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1142 pci_unregister_io_regions(pci_dev
);
1143 pci_del_option_rom(pci_dev
);
1149 pci_device_deassert_intx(pci_dev
);
1150 do_pci_unregister_device(pci_dev
);
1153 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
1154 uint8_t type
, MemoryRegion
*memory
)
1157 uint32_t addr
; /* offset in pci config space */
1159 pcibus_t size
= memory_region_size(memory
);
1162 assert(region_num
>= 0);
1163 assert(region_num
< PCI_NUM_REGIONS
);
1164 assert(is_power_of_2(size
));
1166 /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */
1168 pci_dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1169 assert(hdr_type
!= PCI_HEADER_TYPE_BRIDGE
|| region_num
< 2);
1171 r
= &pci_dev
->io_regions
[region_num
];
1172 r
->addr
= PCI_BAR_UNMAPPED
;
1176 r
->address_space
= type
& PCI_BASE_ADDRESS_SPACE_IO
1177 ? pci_get_bus(pci_dev
)->address_space_io
1178 : pci_get_bus(pci_dev
)->address_space_mem
;
1180 wmask
= ~(size
- 1);
1181 if (region_num
== PCI_ROM_SLOT
) {
1182 /* ROM enable bit is writable */
1183 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
1186 addr
= pci_bar(pci_dev
, region_num
);
1187 pci_set_long(pci_dev
->config
+ addr
, type
);
1189 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
1190 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1191 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
1192 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
1194 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
1195 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
1199 static void pci_update_vga(PCIDevice
*pci_dev
)
1203 if (!pci_dev
->has_vga
) {
1207 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1209 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
1210 cmd
& PCI_COMMAND_MEMORY
);
1211 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
1212 cmd
& PCI_COMMAND_IO
);
1213 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
1214 cmd
& PCI_COMMAND_IO
);
1217 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
1218 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
1220 PCIBus
*bus
= pci_get_bus(pci_dev
);
1222 assert(!pci_dev
->has_vga
);
1224 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
1225 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
1226 memory_region_add_subregion_overlap(bus
->address_space_mem
,
1227 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
1229 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
1230 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
1231 memory_region_add_subregion_overlap(bus
->address_space_io
,
1232 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
1234 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
1235 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
1236 memory_region_add_subregion_overlap(bus
->address_space_io
,
1237 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
1238 pci_dev
->has_vga
= true;
1240 pci_update_vga(pci_dev
);
1243 void pci_unregister_vga(PCIDevice
*pci_dev
)
1245 PCIBus
*bus
= pci_get_bus(pci_dev
);
1247 if (!pci_dev
->has_vga
) {
1251 memory_region_del_subregion(bus
->address_space_mem
,
1252 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
1253 memory_region_del_subregion(bus
->address_space_io
,
1254 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
1255 memory_region_del_subregion(bus
->address_space_io
,
1256 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
1257 pci_dev
->has_vga
= false;
1260 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1262 return pci_dev
->io_regions
[region_num
].addr
;
1265 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1266 int reg
, uint8_t type
, pcibus_t size
)
1268 pcibus_t new_addr
, last_addr
;
1269 int bar
= pci_bar(d
, reg
);
1270 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1271 Object
*machine
= qdev_get_machine();
1272 ObjectClass
*oc
= object_get_class(machine
);
1273 MachineClass
*mc
= MACHINE_CLASS(oc
);
1274 bool allow_0_address
= mc
->pci_allow_0_address
;
1276 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1277 if (!(cmd
& PCI_COMMAND_IO
)) {
1278 return PCI_BAR_UNMAPPED
;
1280 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1281 last_addr
= new_addr
+ size
- 1;
1282 /* Check if 32 bit BAR wraps around explicitly.
1283 * TODO: make priorities correct and remove this work around.
1285 if (last_addr
<= new_addr
|| last_addr
>= UINT32_MAX
||
1286 (!allow_0_address
&& new_addr
== 0)) {
1287 return PCI_BAR_UNMAPPED
;
1292 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1293 return PCI_BAR_UNMAPPED
;
1295 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1296 new_addr
= pci_get_quad(d
->config
+ bar
);
1298 new_addr
= pci_get_long(d
->config
+ bar
);
1300 /* the ROM slot has a specific enable bit */
1301 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1302 return PCI_BAR_UNMAPPED
;
1304 new_addr
&= ~(size
- 1);
1305 last_addr
= new_addr
+ size
- 1;
1306 /* NOTE: we do not support wrapping */
1307 /* XXX: as we cannot support really dynamic
1308 mappings, we handle specific values as invalid
1310 if (last_addr
<= new_addr
|| last_addr
== PCI_BAR_UNMAPPED
||
1311 (!allow_0_address
&& new_addr
== 0)) {
1312 return PCI_BAR_UNMAPPED
;
1315 /* Now pcibus_t is 64bit.
1316 * Check if 32 bit BAR wraps around explicitly.
1317 * Without this, PC ide doesn't work well.
1318 * TODO: remove this work around.
1320 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1321 return PCI_BAR_UNMAPPED
;
1325 * OS is allowed to set BAR beyond its addressable
1326 * bits. For example, 32 bit OS can set 64bit bar
1327 * to >4G. Check it. TODO: we might need to support
1328 * it in the future for e.g. PAE.
1330 if (last_addr
>= HWADDR_MAX
) {
1331 return PCI_BAR_UNMAPPED
;
1337 static void pci_update_mappings(PCIDevice
*d
)
1343 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1344 r
= &d
->io_regions
[i
];
1346 /* this region isn't registered */
1350 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1352 /* This bar isn't changed */
1353 if (new_addr
== r
->addr
)
1356 /* now do the real mapping */
1357 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1358 trace_pci_update_mappings_del(d
, pci_dev_bus_num(d
),
1361 i
, r
->addr
, r
->size
);
1362 memory_region_del_subregion(r
->address_space
, r
->memory
);
1365 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1366 trace_pci_update_mappings_add(d
, pci_dev_bus_num(d
),
1369 i
, r
->addr
, r
->size
);
1370 memory_region_add_subregion_overlap(r
->address_space
,
1371 r
->addr
, r
->memory
, 1);
1378 static inline int pci_irq_disabled(PCIDevice
*d
)
1380 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1383 /* Called after interrupt disabled field update in config space,
1384 * assert/deassert interrupts if necessary.
1385 * Gets original interrupt disable bit value (before update). */
1386 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1388 int i
, disabled
= pci_irq_disabled(d
);
1389 if (disabled
== was_irq_disabled
)
1391 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1392 int state
= pci_irq_state(d
, i
);
1393 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1397 uint32_t pci_default_read_config(PCIDevice
*d
,
1398 uint32_t address
, int len
)
1402 assert(address
+ len
<= pci_config_size(d
));
1404 if (pci_is_express_downstream_port(d
) &&
1405 ranges_overlap(address
, len
, d
->exp
.exp_cap
+ PCI_EXP_LNKSTA
, 2)) {
1406 pcie_sync_bridge_lnk(d
);
1408 memcpy(&val
, d
->config
+ address
, len
);
1409 return le32_to_cpu(val
);
1412 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val_in
, int l
)
1414 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1415 uint32_t val
= val_in
;
1417 assert(addr
+ l
<= pci_config_size(d
));
1419 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1420 uint8_t wmask
= d
->wmask
[addr
+ i
];
1421 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1422 assert(!(wmask
& w1cmask
));
1423 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1424 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1426 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1427 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1428 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1429 range_covers_byte(addr
, l
, PCI_COMMAND
))
1430 pci_update_mappings(d
);
1432 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1433 pci_update_irq_disabled(d
, was_irq_disabled
);
1434 memory_region_set_enabled(&d
->bus_master_enable_region
,
1435 pci_get_word(d
->config
+ PCI_COMMAND
)
1436 & PCI_COMMAND_MASTER
);
1439 msi_write_config(d
, addr
, val_in
, l
);
1440 msix_write_config(d
, addr
, val_in
, l
);
1443 /***********************************************************/
1444 /* generic PCI irq support */
1446 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1447 static void pci_irq_handler(void *opaque
, int irq_num
, int level
)
1449 PCIDevice
*pci_dev
= opaque
;
1452 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1456 pci_set_irq_state(pci_dev
, irq_num
, level
);
1457 pci_update_irq_status(pci_dev
);
1458 if (pci_irq_disabled(pci_dev
))
1460 pci_change_irq_level(pci_dev
, irq_num
, change
);
1463 static inline int pci_intx(PCIDevice
*pci_dev
)
1465 return pci_get_byte(pci_dev
->config
+ PCI_INTERRUPT_PIN
) - 1;
1468 qemu_irq
pci_allocate_irq(PCIDevice
*pci_dev
)
1470 int intx
= pci_intx(pci_dev
);
1472 return qemu_allocate_irq(pci_irq_handler
, pci_dev
, intx
);
1475 void pci_set_irq(PCIDevice
*pci_dev
, int level
)
1477 int intx
= pci_intx(pci_dev
);
1478 pci_irq_handler(pci_dev
, intx
, level
);
1481 /* Special hooks used by device assignment */
1482 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1484 assert(pci_bus_is_root(bus
));
1485 bus
->route_intx_to_irq
= route_intx_to_irq
;
1488 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1493 bus
= pci_get_bus(dev
);
1494 pin
= bus
->map_irq(dev
, pin
);
1495 dev
= bus
->parent_dev
;
1498 if (!bus
->route_intx_to_irq
) {
1499 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1500 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1501 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1504 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1507 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1509 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1512 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1518 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1519 dev
= bus
->devices
[i
];
1520 if (dev
&& dev
->intx_routing_notifier
) {
1521 dev
->intx_routing_notifier(dev
);
1525 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1526 pci_bus_fire_intx_routing_notifier(sec
);
1530 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1531 PCIINTxRoutingNotifier notifier
)
1533 dev
->intx_routing_notifier
= notifier
;
1537 * PCI-to-PCI bridge specification
1538 * 9.1: Interrupt routing. Table 9-1
1540 * the PCI Express Base Specification, Revision 2.1
1541 * 2.2.8.1: INTx interrutp signaling - Rules
1542 * the Implementation Note
1546 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1547 * 0-origin unlike PCI interrupt pin register.
1549 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1551 return pci_swizzle(PCI_SLOT(pci_dev
->devfn
), pin
);
1554 /***********************************************************/
1555 /* monitor info on PCI */
1560 const char *fw_name
;
1561 uint16_t fw_ign_bits
;
1564 static const pci_class_desc pci_class_descriptions
[] =
1566 { 0x0001, "VGA controller", "display"},
1567 { 0x0100, "SCSI controller", "scsi"},
1568 { 0x0101, "IDE controller", "ide"},
1569 { 0x0102, "Floppy controller", "fdc"},
1570 { 0x0103, "IPI controller", "ipi"},
1571 { 0x0104, "RAID controller", "raid"},
1572 { 0x0106, "SATA controller"},
1573 { 0x0107, "SAS controller"},
1574 { 0x0180, "Storage controller"},
1575 { 0x0200, "Ethernet controller", "ethernet"},
1576 { 0x0201, "Token Ring controller", "token-ring"},
1577 { 0x0202, "FDDI controller", "fddi"},
1578 { 0x0203, "ATM controller", "atm"},
1579 { 0x0280, "Network controller"},
1580 { 0x0300, "VGA controller", "display", 0x00ff},
1581 { 0x0301, "XGA controller"},
1582 { 0x0302, "3D controller"},
1583 { 0x0380, "Display controller"},
1584 { 0x0400, "Video controller", "video"},
1585 { 0x0401, "Audio controller", "sound"},
1587 { 0x0403, "Audio controller", "sound"},
1588 { 0x0480, "Multimedia controller"},
1589 { 0x0500, "RAM controller", "memory"},
1590 { 0x0501, "Flash controller", "flash"},
1591 { 0x0580, "Memory controller"},
1592 { 0x0600, "Host bridge", "host"},
1593 { 0x0601, "ISA bridge", "isa"},
1594 { 0x0602, "EISA bridge", "eisa"},
1595 { 0x0603, "MC bridge", "mca"},
1596 { 0x0604, "PCI bridge", "pci-bridge"},
1597 { 0x0605, "PCMCIA bridge", "pcmcia"},
1598 { 0x0606, "NUBUS bridge", "nubus"},
1599 { 0x0607, "CARDBUS bridge", "cardbus"},
1600 { 0x0608, "RACEWAY bridge"},
1601 { 0x0680, "Bridge"},
1602 { 0x0700, "Serial port", "serial"},
1603 { 0x0701, "Parallel port", "parallel"},
1604 { 0x0800, "Interrupt controller", "interrupt-controller"},
1605 { 0x0801, "DMA controller", "dma-controller"},
1606 { 0x0802, "Timer", "timer"},
1607 { 0x0803, "RTC", "rtc"},
1608 { 0x0900, "Keyboard", "keyboard"},
1609 { 0x0901, "Pen", "pen"},
1610 { 0x0902, "Mouse", "mouse"},
1611 { 0x0A00, "Dock station", "dock", 0x00ff},
1612 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1613 { 0x0c00, "Fireware contorller", "fireware"},
1614 { 0x0c01, "Access bus controller", "access-bus"},
1615 { 0x0c02, "SSA controller", "ssa"},
1616 { 0x0c03, "USB controller", "usb"},
1617 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1622 static void pci_for_each_device_under_bus_reverse(PCIBus
*bus
,
1623 void (*fn
)(PCIBus
*b
,
1631 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1632 d
= bus
->devices
[ARRAY_SIZE(bus
->devices
) - 1 - devfn
];
1639 void pci_for_each_device_reverse(PCIBus
*bus
, int bus_num
,
1640 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1643 bus
= pci_find_bus_nr(bus
, bus_num
);
1646 pci_for_each_device_under_bus_reverse(bus
, fn
, opaque
);
1650 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1651 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1658 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1659 d
= bus
->devices
[devfn
];
1666 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1667 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1670 bus
= pci_find_bus_nr(bus
, bus_num
);
1673 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1677 static const pci_class_desc
*get_class_desc(int class)
1679 const pci_class_desc
*desc
;
1681 desc
= pci_class_descriptions
;
1682 while (desc
->desc
&& class != desc
->class) {
1689 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1691 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1693 PciMemoryRegionList
*head
= NULL
, **tail
= &head
;
1696 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1697 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1698 PciMemoryRegion
*region
;
1704 region
= g_malloc0(sizeof(*region
));
1706 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1707 region
->type
= g_strdup("io");
1709 region
->type
= g_strdup("memory");
1710 region
->has_prefetch
= true;
1711 region
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1712 region
->has_mem_type_64
= true;
1713 region
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1717 region
->address
= r
->addr
;
1718 region
->size
= r
->size
;
1720 QAPI_LIST_APPEND(tail
, region
);
1726 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1729 PciBridgeInfo
*info
;
1730 PciMemoryRange
*range
;
1732 info
= g_new0(PciBridgeInfo
, 1);
1734 info
->bus
= g_new0(PciBusInfo
, 1);
1735 info
->bus
->number
= dev
->config
[PCI_PRIMARY_BUS
];
1736 info
->bus
->secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1737 info
->bus
->subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1739 range
= info
->bus
->io_range
= g_new0(PciMemoryRange
, 1);
1740 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1741 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1743 range
= info
->bus
->memory_range
= g_new0(PciMemoryRange
, 1);
1744 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1745 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1747 range
= info
->bus
->prefetchable_range
= g_new0(PciMemoryRange
, 1);
1748 range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1749 range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1751 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1752 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1754 info
->has_devices
= true;
1755 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1762 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1765 const pci_class_desc
*desc
;
1766 PciDeviceInfo
*info
;
1770 info
= g_new0(PciDeviceInfo
, 1);
1771 info
->bus
= bus_num
;
1772 info
->slot
= PCI_SLOT(dev
->devfn
);
1773 info
->function
= PCI_FUNC(dev
->devfn
);
1775 info
->class_info
= g_new0(PciDeviceClass
, 1);
1776 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1777 info
->class_info
->q_class
= class;
1778 desc
= get_class_desc(class);
1780 info
->class_info
->has_desc
= true;
1781 info
->class_info
->desc
= g_strdup(desc
->desc
);
1784 info
->id
= g_new0(PciDeviceId
, 1);
1785 info
->id
->vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1786 info
->id
->device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1787 info
->regions
= qmp_query_pci_regions(dev
);
1788 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1790 info
->irq_pin
= dev
->config
[PCI_INTERRUPT_PIN
];
1791 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1792 info
->has_irq
= true;
1793 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1796 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1797 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1798 info
->has_pci_bridge
= true;
1799 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1800 } else if (type
== PCI_HEADER_TYPE_NORMAL
) {
1801 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1802 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_SUBSYSTEM_ID
);
1803 info
->id
->subsystem_vendor
=
1804 pci_get_word(dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
);
1805 } else if (type
== PCI_HEADER_TYPE_CARDBUS
) {
1806 info
->id
->has_subsystem
= info
->id
->has_subsystem_vendor
= true;
1807 info
->id
->subsystem
= pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_ID
);
1808 info
->id
->subsystem_vendor
=
1809 pci_get_word(dev
->config
+ PCI_CB_SUBSYSTEM_VENDOR_ID
);
1815 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1817 PciDeviceInfoList
*head
= NULL
, **tail
= &head
;
1821 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1822 dev
= bus
->devices
[devfn
];
1824 QAPI_LIST_APPEND(tail
, qmp_query_pci_device(dev
, bus
, bus_num
));
1831 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1833 PciInfo
*info
= NULL
;
1835 bus
= pci_find_bus_nr(bus
, bus_num
);
1837 info
= g_malloc0(sizeof(*info
));
1838 info
->bus
= bus_num
;
1839 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1845 PciInfoList
*qmp_query_pci(Error
**errp
)
1847 PciInfoList
*head
= NULL
, **tail
= &head
;
1848 PCIHostState
*host_bridge
;
1850 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
1851 QAPI_LIST_APPEND(tail
,
1852 qmp_query_pci_bus(host_bridge
->bus
,
1853 pci_bus_num(host_bridge
->bus
)));
1859 /* Initialize a PCI NIC. */
1860 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, PCIBus
*rootbus
,
1861 const char *default_model
,
1862 const char *default_devaddr
)
1864 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1866 GPtrArray
*pci_nic_models
;
1875 if (nd
->model
&& !strcmp(nd
->model
, "virtio")) {
1877 nd
->model
= g_strdup("virtio-net-pci");
1880 list
= object_class_get_list_sorted(TYPE_PCI_DEVICE
, false);
1881 pci_nic_models
= g_ptr_array_new();
1883 DeviceClass
*dc
= OBJECT_CLASS_CHECK(DeviceClass
, list
->data
,
1886 if (test_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
) &&
1887 dc
->user_creatable
) {
1888 const char *name
= object_class_get_name(list
->data
);
1890 * A network device might also be something else than a NIC, see
1891 * e.g. the "rocker" device. Thus we have to look for the "netdev"
1892 * property, too. Unfortunately, some devices like virtio-net only
1893 * create this property during instance_init, so we have to create
1894 * a temporary instance here to be able to check it.
1896 Object
*obj
= object_new_with_class(OBJECT_CLASS(dc
));
1897 if (object_property_find(obj
, "netdev")) {
1898 g_ptr_array_add(pci_nic_models
, (gpointer
)name
);
1903 g_slist_free_1(list
);
1906 g_ptr_array_add(pci_nic_models
, NULL
);
1908 if (qemu_show_nic_models(nd
->model
, (const char **)pci_nic_models
->pdata
)) {
1912 i
= qemu_find_nic_model(nd
, (const char **)pci_nic_models
->pdata
,
1919 error_report("No primary PCI bus");
1923 assert(!rootbus
->parent_dev
);
1929 if (pci_parse_devaddr(devaddr
, &dom
, &busnr
, &slot
, NULL
) < 0) {
1930 error_report("Invalid PCI device address %s for device %s",
1931 devaddr
, nd
->model
);
1936 error_report("No support for non-zero PCI domains");
1940 devfn
= PCI_DEVFN(slot
, 0);
1943 bus
= pci_find_bus_nr(rootbus
, busnr
);
1945 error_report("Invalid PCI device address %s for device %s",
1946 devaddr
, nd
->model
);
1950 pci_dev
= pci_new(devfn
, nd
->model
);
1951 dev
= &pci_dev
->qdev
;
1952 qdev_set_nic_properties(dev
, nd
);
1953 pci_realize_and_unref(pci_dev
, bus
, &error_fatal
);
1954 g_ptr_array_free(pci_nic_models
, true);
1958 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1960 switch (vga_interface_type
) {
1962 return pci_create_simple(bus
, -1, "cirrus-vga");
1964 return pci_create_simple(bus
, -1, "qxl-vga");
1966 return pci_create_simple(bus
, -1, "VGA");
1968 return pci_create_simple(bus
, -1, "vmware-svga");
1970 return pci_create_simple(bus
, -1, "virtio-vga");
1972 default: /* Other non-PCI types. Checking for unsupported types is already
1978 /* Whether a given bus number is in range of the secondary
1979 * bus of the given bridge device. */
1980 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1982 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1983 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1984 dev
->config
[PCI_SECONDARY_BUS
] <= bus_num
&&
1985 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1988 /* Whether a given bus number is in a range of a root bus */
1989 static bool pci_root_bus_in_range(PCIBus
*bus
, int bus_num
)
1993 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1994 PCIDevice
*dev
= bus
->devices
[i
];
1996 if (dev
&& PCI_DEVICE_GET_CLASS(dev
)->is_bridge
) {
1997 if (pci_secondary_bus_in_range(dev
, bus_num
)) {
2006 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
2014 if (pci_bus_num(bus
) == bus_num
) {
2018 /* Consider all bus numbers in range for the host pci bridge. */
2019 if (!pci_bus_is_root(bus
) &&
2020 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
2025 for (; bus
; bus
= sec
) {
2026 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2027 if (pci_bus_num(sec
) == bus_num
) {
2030 /* PXB buses assumed to be children of bus 0 */
2031 if (pci_bus_is_root(sec
)) {
2032 if (pci_root_bus_in_range(sec
, bus_num
)) {
2036 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
2046 void pci_for_each_bus_depth_first(PCIBus
*bus
,
2047 void *(*begin
)(PCIBus
*bus
, void *parent_state
),
2048 void (*end
)(PCIBus
*bus
, void *state
),
2059 state
= begin(bus
, parent_state
);
2061 state
= parent_state
;
2064 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
2065 pci_for_each_bus_depth_first(sec
, begin
, end
, state
);
2074 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
2076 bus
= pci_find_bus_nr(bus
, bus_num
);
2081 return bus
->devices
[devfn
];
2084 static void pci_qdev_realize(DeviceState
*qdev
, Error
**errp
)
2086 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
2087 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
2088 ObjectClass
*klass
= OBJECT_CLASS(pc
);
2089 Error
*local_err
= NULL
;
2090 bool is_default_rom
;
2093 if (pci_dev
->romsize
!= -1 && !is_power_of_2(pci_dev
->romsize
)) {
2094 error_setg(errp
, "ROM size %u is not a power of two", pci_dev
->romsize
);
2098 /* initialize cap_present for pci_is_express() and pci_config_size(),
2099 * Note that hybrid PCIs are not set automatically and need to manage
2100 * QEMU_PCI_CAP_EXPRESS manually */
2101 if (object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
) &&
2102 !object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
)) {
2103 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
2106 pci_dev
= do_pci_register_device(pci_dev
,
2107 object_get_typename(OBJECT(qdev
)),
2108 pci_dev
->devfn
, errp
);
2109 if (pci_dev
== NULL
)
2113 pc
->realize(pci_dev
, &local_err
);
2115 error_propagate(errp
, local_err
);
2116 do_pci_unregister_device(pci_dev
);
2121 if (pci_dev
->failover_pair_id
) {
2122 if (!pci_bus_is_express(pci_get_bus(pci_dev
))) {
2123 error_setg(errp
, "failover primary device must be on "
2125 pci_qdev_unrealize(DEVICE(pci_dev
));
2128 class_id
= pci_get_word(pci_dev
->config
+ PCI_CLASS_DEVICE
);
2129 if (class_id
!= PCI_CLASS_NETWORK_ETHERNET
) {
2130 error_setg(errp
, "failover primary device is not an "
2132 pci_qdev_unrealize(DEVICE(pci_dev
));
2135 if ((pci_dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)
2136 || (PCI_FUNC(pci_dev
->devfn
) != 0)) {
2137 error_setg(errp
, "failover: primary device must be in its own "
2139 pci_qdev_unrealize(DEVICE(pci_dev
));
2142 qdev
->allow_unplug_during_migration
= true;
2146 is_default_rom
= false;
2147 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
2148 pci_dev
->romfile
= g_strdup(pc
->romfile
);
2149 is_default_rom
= true;
2152 pci_add_option_rom(pci_dev
, is_default_rom
, &local_err
);
2154 error_propagate(errp
, local_err
);
2155 pci_qdev_unrealize(DEVICE(pci_dev
));
2160 PCIDevice
*pci_new_multifunction(int devfn
, bool multifunction
,
2165 dev
= qdev_new(name
);
2166 qdev_prop_set_int32(dev
, "addr", devfn
);
2167 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
2168 return PCI_DEVICE(dev
);
2171 PCIDevice
*pci_new(int devfn
, const char *name
)
2173 return pci_new_multifunction(devfn
, false, name
);
2176 bool pci_realize_and_unref(PCIDevice
*dev
, PCIBus
*bus
, Error
**errp
)
2178 return qdev_realize_and_unref(&dev
->qdev
, &bus
->qbus
, errp
);
2181 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
2185 PCIDevice
*dev
= pci_new_multifunction(devfn
, multifunction
, name
);
2186 pci_realize_and_unref(dev
, bus
, &error_fatal
);
2190 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
2192 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
2195 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
2197 int offset
= PCI_CONFIG_HEADER_SIZE
;
2199 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
2202 else if (i
- offset
+ 1 == size
)
2208 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
2213 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
2216 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2217 prev
= next
+ PCI_CAP_LIST_NEXT
)
2218 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
2226 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
2228 uint8_t next
, prev
, found
= 0;
2230 if (!(pdev
->used
[offset
])) {
2234 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
2236 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
2237 prev
= next
+ PCI_CAP_LIST_NEXT
) {
2238 if (next
<= offset
&& next
> found
) {
2245 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2246 This is needed for an option rom which is used for more than one device. */
2247 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, uint32_t size
)
2251 uint16_t rom_vendor_id
;
2252 uint16_t rom_device_id
;
2254 uint16_t pcir_offset
;
2257 /* Words in rom data are little endian (like in PCI configuration),
2258 so they can be read / written with pci_get_word / pci_set_word. */
2260 /* Only a valid rom will be patched. */
2261 rom_magic
= pci_get_word(ptr
);
2262 if (rom_magic
!= 0xaa55) {
2263 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
2266 pcir_offset
= pci_get_word(ptr
+ 0x18);
2267 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
2268 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
2272 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2273 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2274 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
2275 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
2277 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
2278 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
2282 if (vendor_id
!= rom_vendor_id
) {
2283 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2284 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
2285 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
2286 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2288 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
2291 if (device_id
!= rom_device_id
) {
2292 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2293 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
2294 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
2295 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
2297 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
2301 /* Add an option rom for the device */
2302 static void pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
,
2309 const VMStateDescription
*vmsd
;
2313 if (strlen(pdev
->romfile
) == 0)
2316 if (!pdev
->rom_bar
) {
2318 * Load rom via fw_cfg instead of creating a rom bar,
2319 * for 0.11 compatibility.
2321 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
2324 * Hot-plugged devices can't use the option ROM
2325 * if the rom bar is disabled.
2327 if (DEVICE(pdev
)->hotplugged
) {
2328 error_setg(errp
, "Hot-plugged device without ROM bar"
2329 " can't have an option ROM");
2333 if (class == 0x0300) {
2334 rom_add_vga(pdev
->romfile
);
2336 rom_add_option(pdev
->romfile
, -1);
2341 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
2343 path
= g_strdup(pdev
->romfile
);
2346 size
= get_image_size(path
);
2348 error_setg(errp
, "failed to find romfile \"%s\"", pdev
->romfile
);
2351 } else if (size
== 0) {
2352 error_setg(errp
, "romfile \"%s\" is empty", pdev
->romfile
);
2355 } else if (size
> 2 * GiB
) {
2356 error_setg(errp
, "romfile \"%s\" too large (size cannot exceed 2 GiB)",
2361 if (pdev
->romsize
!= -1) {
2362 if (size
> pdev
->romsize
) {
2363 error_setg(errp
, "romfile \"%s\" (%u bytes) is too large for ROM size %u",
2364 pdev
->romfile
, (uint32_t)size
, pdev
->romsize
);
2369 pdev
->romsize
= pow2ceil(size
);
2372 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
2375 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
2377 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
2379 pdev
->has_rom
= true;
2380 memory_region_init_rom(&pdev
->rom
, OBJECT(pdev
), name
, pdev
->romsize
, &error_fatal
);
2381 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
2382 if (load_image_size(path
, ptr
, size
) < 0) {
2383 error_setg(errp
, "failed to load romfile \"%s\"", pdev
->romfile
);
2389 if (is_default_rom
) {
2390 /* Only the default rom images will be patched (if needed). */
2391 pci_patch_ids(pdev
, ptr
, size
);
2394 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
2397 static void pci_del_option_rom(PCIDevice
*pdev
)
2402 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
2403 pdev
->has_rom
= false;
2407 * On success, pci_add_capability() returns a positive value
2408 * that the offset of the pci capability.
2409 * On failure, it sets an error and returns a negative error
2412 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
2413 uint8_t offset
, uint8_t size
,
2417 int i
, overlapping_cap
;
2420 offset
= pci_find_space(pdev
, size
);
2421 /* out of PCI config space is programming error */
2424 /* Verify that capabilities don't overlap. Note: device assignment
2425 * depends on this check to verify that the device is not broken.
2426 * Should never trigger for emulated devices, but it's helpful
2427 * for debugging these. */
2428 for (i
= offset
; i
< offset
+ size
; i
++) {
2429 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
2430 if (overlapping_cap
) {
2431 error_setg(errp
, "%s:%02x:%02x.%x "
2432 "Attempt to add PCI capability %x at offset "
2433 "%x overlaps existing capability %x at offset %x",
2434 pci_root_bus_path(pdev
), pci_dev_bus_num(pdev
),
2435 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2436 cap_id
, offset
, overlapping_cap
, i
);
2442 config
= pdev
->config
+ offset
;
2443 config
[PCI_CAP_LIST_ID
] = cap_id
;
2444 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2445 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2446 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2447 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2448 /* Make capability read-only by default */
2449 memset(pdev
->wmask
+ offset
, 0, size
);
2450 /* Check capability by default */
2451 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2455 /* Unlink capability from the pci config space. */
2456 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2458 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2461 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2462 /* Make capability writable again */
2463 memset(pdev
->wmask
+ offset
, 0xff, size
);
2464 memset(pdev
->w1cmask
+ offset
, 0, size
);
2465 /* Clear cmask as device-specific registers can't be checked */
2466 memset(pdev
->cmask
+ offset
, 0, size
);
2467 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2469 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2470 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2473 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2475 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2478 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2480 PCIDevice
*d
= (PCIDevice
*)dev
;
2481 const pci_class_desc
*desc
;
2486 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2487 desc
= pci_class_descriptions
;
2488 while (desc
->desc
&& class != desc
->class)
2491 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2493 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2496 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2497 "pci id %04x:%04x (sub %04x:%04x)\n",
2498 indent
, "", ctxt
, pci_dev_bus_num(d
),
2499 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2500 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2501 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2502 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2503 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2504 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2505 r
= &d
->io_regions
[i
];
2508 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2509 " [0x%"FMT_PCIBUS
"]\n",
2511 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2512 r
->addr
, r
->addr
+ r
->size
- 1);
2516 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2518 PCIDevice
*d
= (PCIDevice
*)dev
;
2519 const char *name
= NULL
;
2520 const pci_class_desc
*desc
= pci_class_descriptions
;
2521 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2523 while (desc
->desc
&&
2524 (class & ~desc
->fw_ign_bits
) !=
2525 (desc
->class & ~desc
->fw_ign_bits
)) {
2530 name
= desc
->fw_name
;
2534 pstrcpy(buf
, len
, name
);
2536 snprintf(buf
, len
, "pci%04x,%04x",
2537 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2538 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2544 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2546 PCIDevice
*d
= (PCIDevice
*)dev
;
2547 char path
[50], name
[33];
2550 off
= snprintf(path
, sizeof(path
), "%s@%x",
2551 pci_dev_fw_name(dev
, name
, sizeof name
),
2552 PCI_SLOT(d
->devfn
));
2553 if (PCI_FUNC(d
->devfn
))
2554 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2555 return g_strdup(path
);
2558 static char *pcibus_get_dev_path(DeviceState
*dev
)
2560 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2563 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2564 * 00 is added here to make this format compatible with
2565 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2566 * Slot.Function list specifies the slot and function numbers for all
2567 * devices on the path from root to the specific device. */
2568 const char *root_bus_path
;
2570 char slot
[] = ":SS.F";
2571 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2576 root_bus_path
= pci_root_bus_path(d
);
2577 root_bus_len
= strlen(root_bus_path
);
2579 /* Calculate # of slots on path between device and root. */;
2581 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2585 path_len
= root_bus_len
+ slot_len
* slot_depth
;
2587 /* Allocate memory, fill in the terminating null byte. */
2588 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2589 path
[path_len
] = '\0';
2591 memcpy(path
, root_bus_path
, root_bus_len
);
2593 /* Fill in slot numbers. We walk up from device to root, so need to print
2594 * them in the reverse order, last to first. */
2595 p
= path
+ path_len
;
2596 for (t
= d
; t
; t
= pci_get_bus(t
)->parent_dev
) {
2598 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2599 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2600 assert(s
== slot_len
);
2601 memcpy(p
, slot
, slot_len
);
2607 static int pci_qdev_find_recursive(PCIBus
*bus
,
2608 const char *id
, PCIDevice
**pdev
)
2610 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2615 /* roughly check if given qdev is pci device */
2616 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2617 *pdev
= PCI_DEVICE(qdev
);
2623 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2625 PCIHostState
*host_bridge
;
2628 QLIST_FOREACH(host_bridge
, &pci_host_bridges
, next
) {
2629 int tmp
= pci_qdev_find_recursive(host_bridge
->bus
, id
, pdev
);
2634 if (tmp
!= -ENODEV
) {
2642 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2644 return pci_get_bus(dev
)->address_space_mem
;
2647 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2649 return pci_get_bus(dev
)->address_space_io
;
2652 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2654 DeviceClass
*k
= DEVICE_CLASS(klass
);
2656 k
->realize
= pci_qdev_realize
;
2657 k
->unrealize
= pci_qdev_unrealize
;
2658 k
->bus_type
= TYPE_PCI_BUS
;
2659 device_class_set_props(k
, pci_props
);
2662 static void pci_device_class_base_init(ObjectClass
*klass
, void *data
)
2664 if (!object_class_is_abstract(klass
)) {
2665 ObjectClass
*conventional
=
2666 object_class_dynamic_cast(klass
, INTERFACE_CONVENTIONAL_PCI_DEVICE
);
2668 object_class_dynamic_cast(klass
, INTERFACE_PCIE_DEVICE
);
2669 assert(conventional
|| pcie
);
2673 AddressSpace
*pci_device_iommu_address_space(PCIDevice
*dev
)
2675 PCIBus
*bus
= pci_get_bus(dev
);
2676 PCIBus
*iommu_bus
= bus
;
2677 uint8_t devfn
= dev
->devfn
;
2679 while (iommu_bus
&& !iommu_bus
->iommu_fn
&& iommu_bus
->parent_dev
) {
2680 PCIBus
*parent_bus
= pci_get_bus(iommu_bus
->parent_dev
);
2683 * The requester ID of the provided device may be aliased, as seen from
2684 * the IOMMU, due to topology limitations. The IOMMU relies on a
2685 * requester ID to provide a unique AddressSpace for devices, but
2686 * conventional PCI buses pre-date such concepts. Instead, the PCIe-
2687 * to-PCI bridge creates and accepts transactions on behalf of down-
2688 * stream devices. When doing so, all downstream devices are masked
2689 * (aliased) behind a single requester ID. The requester ID used
2690 * depends on the format of the bridge devices. Proper PCIe-to-PCI
2691 * bridges, with a PCIe capability indicating such, follow the
2692 * guidelines of chapter 2.3 of the PCIe-to-PCI/X bridge specification,
2693 * where the bridge uses the seconary bus as the bridge portion of the
2694 * requester ID and devfn of 00.0. For other bridges, typically those
2695 * found on the root complex such as the dmi-to-pci-bridge, we follow
2696 * the convention of typical bare-metal hardware, which uses the
2697 * requester ID of the bridge itself. There are device specific
2698 * exceptions to these rules, but these are the defaults that the
2699 * Linux kernel uses when determining DMA aliases itself and believed
2700 * to be true for the bare metal equivalents of the devices emulated
2703 if (!pci_bus_is_express(iommu_bus
)) {
2704 PCIDevice
*parent
= iommu_bus
->parent_dev
;
2706 if (pci_is_express(parent
) &&
2707 pcie_cap_get_type(parent
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2708 devfn
= PCI_DEVFN(0, 0);
2711 devfn
= parent
->devfn
;
2716 iommu_bus
= parent_bus
;
2718 if (iommu_bus
&& iommu_bus
->iommu_fn
) {
2719 return iommu_bus
->iommu_fn(bus
, iommu_bus
->iommu_opaque
, devfn
);
2721 return &address_space_memory
;
2724 void pci_setup_iommu(PCIBus
*bus
, PCIIOMMUFunc fn
, void *opaque
)
2727 bus
->iommu_opaque
= opaque
;
2730 static void pci_dev_get_w64(PCIBus
*b
, PCIDevice
*dev
, void *opaque
)
2732 Range
*range
= opaque
;
2733 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
2734 uint16_t cmd
= pci_get_word(dev
->config
+ PCI_COMMAND
);
2737 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
2741 if (pc
->is_bridge
) {
2742 pcibus_t base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2743 pcibus_t limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
2745 base
= MAX(base
, 0x1ULL
<< 32);
2747 if (limit
>= base
) {
2749 range_set_bounds(&pref_range
, base
, limit
);
2750 range_extend(range
, &pref_range
);
2753 for (i
= 0; i
< PCI_NUM_REGIONS
; ++i
) {
2754 PCIIORegion
*r
= &dev
->io_regions
[i
];
2759 (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) ||
2760 !(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
2764 lob
= pci_bar_address(dev
, i
, r
->type
, r
->size
);
2765 upb
= lob
+ r
->size
- 1;
2766 if (lob
== PCI_BAR_UNMAPPED
) {
2770 lob
= MAX(lob
, 0x1ULL
<< 32);
2773 range_set_bounds(®ion_range
, lob
, upb
);
2774 range_extend(range
, ®ion_range
);
2779 void pci_bus_get_w64_range(PCIBus
*bus
, Range
*range
)
2781 range_make_empty(range
);
2782 pci_for_each_device_under_bus(bus
, pci_dev_get_w64
, range
);
2785 static bool pcie_has_upstream_port(PCIDevice
*dev
)
2787 PCIDevice
*parent_dev
= pci_bridge_get_device(pci_get_bus(dev
));
2789 /* Device associated with an upstream port.
2790 * As there are several types of these, it's easier to check the
2791 * parent device: upstream ports are always connected to
2792 * root or downstream ports.
2794 return parent_dev
&&
2795 pci_is_express(parent_dev
) &&
2796 parent_dev
->exp
.exp_cap
&&
2797 (pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2798 pcie_cap_get_type(parent_dev
) == PCI_EXP_TYPE_DOWNSTREAM
);
2801 PCIDevice
*pci_get_function_0(PCIDevice
*pci_dev
)
2803 PCIBus
*bus
= pci_get_bus(pci_dev
);
2805 if(pcie_has_upstream_port(pci_dev
)) {
2806 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2807 return bus
->devices
[0];
2809 /* Other bus types might support multiple devices at slots 0-31 */
2810 return bus
->devices
[PCI_DEVFN(PCI_SLOT(pci_dev
->devfn
), 0)];
2814 MSIMessage
pci_get_msi_message(PCIDevice
*dev
, int vector
)
2817 if (msix_enabled(dev
)) {
2818 msg
= msix_get_message(dev
, vector
);
2819 } else if (msi_enabled(dev
)) {
2820 msg
= msi_get_message(dev
, vector
);
2822 /* Should never happen */
2823 error_report("%s: unknown interrupt type", __func__
);
2829 static const TypeInfo pci_device_type_info
= {
2830 .name
= TYPE_PCI_DEVICE
,
2831 .parent
= TYPE_DEVICE
,
2832 .instance_size
= sizeof(PCIDevice
),
2834 .class_size
= sizeof(PCIDeviceClass
),
2835 .class_init
= pci_device_class_init
,
2836 .class_base_init
= pci_device_class_base_init
,
2839 static void pci_register_types(void)
2841 type_register_static(&pci_bus_info
);
2842 type_register_static(&pcie_bus_info
);
2843 type_register_static(&conventional_pci_interface_info
);
2844 type_register_static(&pcie_interface_info
);
2845 type_register_static(&pci_device_type_info
);
2848 type_init(pci_register_types
)