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Fix configure test for PBKDF2 in nettle
[qemu.git] / target-ppc / translate_init.c
blobf51572552bc2e334ed577e09fd67de7479198a21
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include <sysemu/kvm.h>
25 #include "kvm_ppc.h"
26 #include "sysemu/arch_init.h"
27 #include "sysemu/cpus.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/visitor.h"
33 #include "hw/qdev-properties.h"
34
35 //#define PPC_DUMP_CPU
36 //#define PPC_DEBUG_SPR
37 //#define PPC_DUMP_SPR_ACCESSES
38 /* #define USE_APPLE_GDB */
39
40 /* For user-mode emulation, we don't emulate any IRQ controller */
41 #if defined(CONFIG_USER_ONLY)
42 #define PPC_IRQ_INIT_FN(name) \
43 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
44 { \
45 }
46 #else
47 #define PPC_IRQ_INIT_FN(name) \
48 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
49 #endif
50
51 PPC_IRQ_INIT_FN(40x);
52 PPC_IRQ_INIT_FN(6xx);
53 PPC_IRQ_INIT_FN(970);
54 PPC_IRQ_INIT_FN(POWER7);
55 PPC_IRQ_INIT_FN(e500);
56
57 /* Generic callbacks:
58 * do nothing but store/retrieve spr value
59 */
60 static void spr_load_dump_spr(int sprn)
61 {
62 #ifdef PPC_DUMP_SPR_ACCESSES
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_load_dump_spr(cpu_env, t0);
65 tcg_temp_free_i32(t0);
66 #endif
67 }
68
69 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
70 {
71 gen_load_spr(cpu_gpr[gprn], sprn);
72 spr_load_dump_spr(sprn);
73 }
74
75 static void spr_store_dump_spr(int sprn)
76 {
77 #ifdef PPC_DUMP_SPR_ACCESSES
78 TCGv_i32 t0 = tcg_const_i32(sprn);
79 gen_helper_store_dump_spr(cpu_env, t0);
80 tcg_temp_free_i32(t0);
81 #endif
82 }
83
84 static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
85 {
86 gen_store_spr(sprn, cpu_gpr[gprn]);
87 spr_store_dump_spr(sprn);
88 }
89
90 #if !defined(CONFIG_USER_ONLY)
91 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
92 {
93 #ifdef TARGET_PPC64
94 TCGv t0 = tcg_temp_new();
95 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
96 gen_store_spr(sprn, t0);
97 tcg_temp_free(t0);
98 spr_store_dump_spr(sprn);
99 #else
100 spr_write_generic(ctx, sprn, gprn);
101 #endif
102 }
103
104 static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
105 {
106 TCGv t0 = tcg_temp_new();
107 TCGv t1 = tcg_temp_new();
108 gen_load_spr(t0, sprn);
109 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
110 tcg_gen_and_tl(t0, t0, t1);
111 gen_store_spr(sprn, t0);
112 tcg_temp_free(t0);
113 tcg_temp_free(t1);
114 }
115
116 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
117 {
118 }
119
120 #endif
121
122 /* SPR common to all PowerPC */
123 /* XER */
124 static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
125 {
126 gen_read_xer(cpu_gpr[gprn]);
127 }
128
129 static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
130 {
131 gen_write_xer(cpu_gpr[gprn]);
132 }
133
134 /* LR */
135 static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
136 {
137 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
138 }
139
140 static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
141 {
142 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
143 }
144
145 /* CFAR */
146 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
147 static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
148 {
149 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
150 }
151
152 static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
153 {
154 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
155 }
156 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
157
158 /* CTR */
159 static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
160 {
161 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
162 }
163
164 static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
165 {
166 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
167 }
168
169 /* User read access to SPR */
170 /* USPRx */
171 /* UMMCRx */
172 /* UPMCx */
173 /* USIA */
174 /* UDECR */
175 static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
176 {
177 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
178 }
179
180 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
181 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
182 {
183 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
184 }
185 #endif
186
187 /* SPR common to all non-embedded PowerPC */
188 /* DECR */
189 #if !defined(CONFIG_USER_ONLY)
190 static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
191 {
192 if (ctx->tb->cflags & CF_USE_ICOUNT) {
193 gen_io_start();
194 }
195 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
196 if (ctx->tb->cflags & CF_USE_ICOUNT) {
197 gen_io_end();
198 gen_stop_exception(ctx);
199 }
200 }
201
202 static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
203 {
204 if (ctx->tb->cflags & CF_USE_ICOUNT) {
205 gen_io_start();
206 }
207 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
208 if (ctx->tb->cflags & CF_USE_ICOUNT) {
209 gen_io_end();
210 gen_stop_exception(ctx);
211 }
212 }
213 #endif
214
215 /* SPR common to all non-embedded PowerPC, except 601 */
216 /* Time base */
217 static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
218 {
219 if (ctx->tb->cflags & CF_USE_ICOUNT) {
220 gen_io_start();
221 }
222 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
223 if (ctx->tb->cflags & CF_USE_ICOUNT) {
224 gen_io_end();
225 gen_stop_exception(ctx);
226 }
227 }
228
229 static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
230 {
231 if (ctx->tb->cflags & CF_USE_ICOUNT) {
232 gen_io_start();
233 }
234 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
235 if (ctx->tb->cflags & CF_USE_ICOUNT) {
236 gen_io_end();
237 gen_stop_exception(ctx);
238 }
239 }
240
241 __attribute__ (( unused ))
242 static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
243 {
244 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
245 }
246
247 __attribute__ (( unused ))
248 static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
249 {
250 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
251 }
252
253 #if !defined(CONFIG_USER_ONLY)
254 static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
255 {
256 if (ctx->tb->cflags & CF_USE_ICOUNT) {
257 gen_io_start();
258 }
259 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
260 if (ctx->tb->cflags & CF_USE_ICOUNT) {
261 gen_io_end();
262 gen_stop_exception(ctx);
263 }
264 }
265
266 static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
267 {
268 if (ctx->tb->cflags & CF_USE_ICOUNT) {
269 gen_io_start();
270 }
271 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
272 if (ctx->tb->cflags & CF_USE_ICOUNT) {
273 gen_io_end();
274 gen_stop_exception(ctx);
275 }
276 }
277
278 __attribute__ (( unused ))
279 static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
280 {
281 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
282 }
283
284 __attribute__ (( unused ))
285 static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
286 {
287 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
288 }
289
290 #if defined(TARGET_PPC64)
291 __attribute__ (( unused ))
292 static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
293 {
294 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
295 }
296 #endif
297 #endif
298
299 #if !defined(CONFIG_USER_ONLY)
300 /* IBAT0U...IBAT0U */
301 /* IBAT0L...IBAT7L */
302 static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
303 {
304 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
305 }
306
307 static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
308 {
309 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
310 }
311
312 static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
313 {
314 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
315 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
316 tcg_temp_free_i32(t0);
317 }
318
319 static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
320 {
321 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
322 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
324 }
325
326 static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
327 {
328 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
329 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
331 }
332
333 static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
334 {
335 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
336 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
338 }
339
340 /* DBAT0U...DBAT7U */
341 /* DBAT0L...DBAT7L */
342 static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
343 {
344 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
345 }
346
347 static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
348 {
349 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
350 }
351
352 static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
353 {
354 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
355 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
356 tcg_temp_free_i32(t0);
357 }
358
359 static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
360 {
361 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
362 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
363 tcg_temp_free_i32(t0);
364 }
365
366 static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
367 {
368 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
369 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
370 tcg_temp_free_i32(t0);
371 }
372
373 static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
374 {
375 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
376 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
377 tcg_temp_free_i32(t0);
378 }
379
380 /* SDR1 */
381 static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
382 {
383 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
384 }
385
386 /* 64 bits PowerPC specific SPRs */
387 #if defined(TARGET_PPC64)
388 static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
389 {
390 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
391 }
392
393 static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
394 {
395 TCGv t0 = tcg_temp_new();
396 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
397 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
398 tcg_temp_free(t0);
399 }
400 #endif
401 #endif
402
403 /* PowerPC 601 specific registers */
404 /* RTC */
405 static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
406 {
407 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
408 }
409
410 static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
411 {
412 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
413 }
414
415 #if !defined(CONFIG_USER_ONLY)
416 static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
417 {
418 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
419 }
420
421 static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
422 {
423 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
424 }
425
426 static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
427 {
428 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
429 /* Must stop the translation as endianness may have changed */
430 gen_stop_exception(ctx);
431 }
432 #endif
433
434 /* Unified bats */
435 #if !defined(CONFIG_USER_ONLY)
436 static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
437 {
438 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
439 }
440
441 static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
442 {
443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
444 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
445 tcg_temp_free_i32(t0);
446 }
447
448 static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
449 {
450 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
451 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
452 tcg_temp_free_i32(t0);
453 }
454 #endif
455
456 /* PowerPC 40x specific registers */
457 #if !defined(CONFIG_USER_ONLY)
458 static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
459 {
460 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
461 }
462
463 static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
464 {
465 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
466 }
467
468 static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
469 {
470 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
471 /* We must stop translation as we may have rebooted */
472 gen_stop_exception(ctx);
473 }
474
475 static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
476 {
477 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
478 }
479
480 static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
481 {
482 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
483 }
484
485 static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
486 {
487 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
488 }
489 #endif
490
491 /* PowerPC 403 specific registers */
492 /* PBL1 / PBU1 / PBL2 / PBU2 */
493 #if !defined(CONFIG_USER_ONLY)
494 static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
495 {
496 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
497 }
498
499 static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
500 {
501 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
502 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
503 tcg_temp_free_i32(t0);
504 }
505
506 static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
507 {
508 TCGv t0 = tcg_temp_new();
509 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
510 gen_store_spr(SPR_PIR, t0);
511 tcg_temp_free(t0);
512 }
513 #endif
514
515 /* SPE specific registers */
516 static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
517 {
518 TCGv_i32 t0 = tcg_temp_new_i32();
519 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
520 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
521 tcg_temp_free_i32(t0);
522 }
523
524 static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
525 {
526 TCGv_i32 t0 = tcg_temp_new_i32();
527 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
528 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
529 tcg_temp_free_i32(t0);
530 }
531
532 #if !defined(CONFIG_USER_ONLY)
533 /* Callback used to write the exception vector base */
534 static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
535 {
536 TCGv t0 = tcg_temp_new();
537 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
538 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
539 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
540 gen_store_spr(sprn, t0);
541 tcg_temp_free(t0);
542 }
543
544 static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
545 {
546 int sprn_offs;
547
548 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
549 sprn_offs = sprn - SPR_BOOKE_IVOR0;
550 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
551 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
552 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
553 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
554 } else {
555 printf("Trying to write an unknown exception vector %d %03x\n",
556 sprn, sprn);
557 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
558 return;
559 }
560
561 TCGv t0 = tcg_temp_new();
562 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
563 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
564 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
565 gen_store_spr(sprn, t0);
566 tcg_temp_free(t0);
567 }
568 #endif
569
570 static inline void vscr_init (CPUPPCState *env, uint32_t val)
571 {
572 env->vscr = val;
573 /* Altivec always uses round-to-nearest */
574 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
575 set_flush_to_zero(vscr_nj, &env->vec_status);
576 }
577
578 #ifdef CONFIG_USER_ONLY
579 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
580 oea_read, oea_write, one_reg_id, initial_value) \
581 _spr_register(env, num, name, uea_read, uea_write, initial_value)
582 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, hea_read, hea_write, \
584 one_reg_id, initial_value) \
585 _spr_register(env, num, name, uea_read, uea_write, initial_value)
586 #else
587 #if !defined(CONFIG_KVM)
588 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
589 oea_read, oea_write, one_reg_id, initial_value) \
590 _spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, oea_read, oea_write, initial_value)
592 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, hea_read, hea_write, \
594 one_reg_id, initial_value) \
595 _spr_register(env, num, name, uea_read, uea_write, \
596 oea_read, oea_write, hea_read, hea_write, initial_value)
597 #else
598 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
599 oea_read, oea_write, one_reg_id, initial_value) \
600 _spr_register(env, num, name, uea_read, uea_write, \
601 oea_read, oea_write, oea_read, oea_write, \
602 one_reg_id, initial_value)
603 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
604 oea_read, oea_write, hea_read, hea_write, \
605 one_reg_id, initial_value) \
606 _spr_register(env, num, name, uea_read, uea_write, \
607 oea_read, oea_write, hea_read, hea_write, \
608 one_reg_id, initial_value)
609 #endif
610 #endif
611
612 #define spr_register(env, num, name, uea_read, uea_write, \
613 oea_read, oea_write, initial_value) \
614 spr_register_kvm(env, num, name, uea_read, uea_write, \
615 oea_read, oea_write, 0, initial_value)
616
617 #define spr_register_hv(env, num, name, uea_read, uea_write, \
618 oea_read, oea_write, hea_read, hea_write, \
619 initial_value) \
620 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
621 oea_read, oea_write, hea_read, hea_write, \
622 0, initial_value)
623
624 static inline void _spr_register(CPUPPCState *env, int num,
625 const char *name,
626 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
627 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
628 #if !defined(CONFIG_USER_ONLY)
629
630 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
631 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
632 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
633 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
634 #endif
635 #if defined(CONFIG_KVM)
636 uint64_t one_reg_id,
637 #endif
638 target_ulong initial_value)
639 {
640 ppc_spr_t *spr;
641
642 spr = &env->spr_cb[num];
643 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
644 #if !defined(CONFIG_USER_ONLY)
645 spr->oea_read != NULL || spr->oea_write != NULL ||
646 #endif
647 spr->uea_read != NULL || spr->uea_write != NULL) {
648 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
649 exit(1);
650 }
651 #if defined(PPC_DEBUG_SPR)
652 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
653 name, initial_value);
654 #endif
655 spr->name = name;
656 spr->uea_read = uea_read;
657 spr->uea_write = uea_write;
658 #if !defined(CONFIG_USER_ONLY)
659 spr->oea_read = oea_read;
660 spr->oea_write = oea_write;
661 spr->hea_read = hea_read;
662 spr->hea_write = hea_write;
663 #endif
664 #if defined(CONFIG_KVM)
665 spr->one_reg_id = one_reg_id,
666 #endif
667 env->spr[num] = spr->default_value = initial_value;
668 }
669
670 /* Generic PowerPC SPRs */
671 static void gen_spr_generic (CPUPPCState *env)
672 {
673 /* Integer processing */
674 spr_register(env, SPR_XER, "XER",
675 &spr_read_xer, &spr_write_xer,
676 &spr_read_xer, &spr_write_xer,
677 0x00000000);
678 /* Branch contol */
679 spr_register(env, SPR_LR, "LR",
680 &spr_read_lr, &spr_write_lr,
681 &spr_read_lr, &spr_write_lr,
682 0x00000000);
683 spr_register(env, SPR_CTR, "CTR",
684 &spr_read_ctr, &spr_write_ctr,
685 &spr_read_ctr, &spr_write_ctr,
686 0x00000000);
687 /* Interrupt processing */
688 spr_register(env, SPR_SRR0, "SRR0",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_generic, &spr_write_generic,
691 0x00000000);
692 spr_register(env, SPR_SRR1, "SRR1",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_generic, &spr_write_generic,
695 0x00000000);
696 /* Processor control */
697 spr_register(env, SPR_SPRG0, "SPRG0",
698 SPR_NOACCESS, SPR_NOACCESS,
699 &spr_read_generic, &spr_write_generic,
700 0x00000000);
701 spr_register(env, SPR_SPRG1, "SPRG1",
702 SPR_NOACCESS, SPR_NOACCESS,
703 &spr_read_generic, &spr_write_generic,
704 0x00000000);
705 spr_register(env, SPR_SPRG2, "SPRG2",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, &spr_write_generic,
708 0x00000000);
709 spr_register(env, SPR_SPRG3, "SPRG3",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713 }
714
715 /* SPR common to all non-embedded PowerPC, including 601 */
716 static void gen_spr_ne_601 (CPUPPCState *env)
717 {
718 /* Exception processing */
719 spr_register_kvm(env, SPR_DSISR, "DSISR",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 KVM_REG_PPC_DSISR, 0x00000000);
723 spr_register_kvm(env, SPR_DAR, "DAR",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_generic, &spr_write_generic,
726 KVM_REG_PPC_DAR, 0x00000000);
727 /* Timer */
728 spr_register(env, SPR_DECR, "DECR",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_decr, &spr_write_decr,
731 0x00000000);
732 /* Memory management */
733 spr_register(env, SPR_SDR1, "SDR1",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_generic, &spr_write_sdr1,
736 0x00000000);
737 }
738
739 /* BATs 0-3 */
740 static void gen_low_BATs (CPUPPCState *env)
741 {
742 #if !defined(CONFIG_USER_ONLY)
743 spr_register(env, SPR_IBAT0U, "IBAT0U",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_ibat, &spr_write_ibatu,
746 0x00000000);
747 spr_register(env, SPR_IBAT0L, "IBAT0L",
748 SPR_NOACCESS, SPR_NOACCESS,
749 &spr_read_ibat, &spr_write_ibatl,
750 0x00000000);
751 spr_register(env, SPR_IBAT1U, "IBAT1U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat, &spr_write_ibatu,
754 0x00000000);
755 spr_register(env, SPR_IBAT1L, "IBAT1L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat, &spr_write_ibatl,
758 0x00000000);
759 spr_register(env, SPR_IBAT2U, "IBAT2U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_ibat, &spr_write_ibatu,
762 0x00000000);
763 spr_register(env, SPR_IBAT2L, "IBAT2L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_ibat, &spr_write_ibatl,
766 0x00000000);
767 spr_register(env, SPR_IBAT3U, "IBAT3U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_ibat, &spr_write_ibatu,
770 0x00000000);
771 spr_register(env, SPR_IBAT3L, "IBAT3L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat, &spr_write_ibatl,
774 0x00000000);
775 spr_register(env, SPR_DBAT0U, "DBAT0U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_dbat, &spr_write_dbatu,
778 0x00000000);
779 spr_register(env, SPR_DBAT0L, "DBAT0L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_dbat, &spr_write_dbatl,
782 0x00000000);
783 spr_register(env, SPR_DBAT1U, "DBAT1U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat, &spr_write_dbatu,
786 0x00000000);
787 spr_register(env, SPR_DBAT1L, "DBAT1L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat, &spr_write_dbatl,
790 0x00000000);
791 spr_register(env, SPR_DBAT2U, "DBAT2U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_dbat, &spr_write_dbatu,
794 0x00000000);
795 spr_register(env, SPR_DBAT2L, "DBAT2L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_dbat, &spr_write_dbatl,
798 0x00000000);
799 spr_register(env, SPR_DBAT3U, "DBAT3U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_dbat, &spr_write_dbatu,
802 0x00000000);
803 spr_register(env, SPR_DBAT3L, "DBAT3L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat, &spr_write_dbatl,
806 0x00000000);
807 env->nb_BATs += 4;
808 #endif
809 }
810
811 /* BATs 4-7 */
812 static void gen_high_BATs (CPUPPCState *env)
813 {
814 #if !defined(CONFIG_USER_ONLY)
815 spr_register(env, SPR_IBAT4U, "IBAT4U",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_ibat_h, &spr_write_ibatu_h,
818 0x00000000);
819 spr_register(env, SPR_IBAT4L, "IBAT4L",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_ibat_h, &spr_write_ibatl_h,
822 0x00000000);
823 spr_register(env, SPR_IBAT5U, "IBAT5U",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_ibat_h, &spr_write_ibatu_h,
826 0x00000000);
827 spr_register(env, SPR_IBAT5L, "IBAT5L",
828 SPR_NOACCESS, SPR_NOACCESS,
829 &spr_read_ibat_h, &spr_write_ibatl_h,
830 0x00000000);
831 spr_register(env, SPR_IBAT6U, "IBAT6U",
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_ibat_h, &spr_write_ibatu_h,
834 0x00000000);
835 spr_register(env, SPR_IBAT6L, "IBAT6L",
836 SPR_NOACCESS, SPR_NOACCESS,
837 &spr_read_ibat_h, &spr_write_ibatl_h,
838 0x00000000);
839 spr_register(env, SPR_IBAT7U, "IBAT7U",
840 SPR_NOACCESS, SPR_NOACCESS,
841 &spr_read_ibat_h, &spr_write_ibatu_h,
842 0x00000000);
843 spr_register(env, SPR_IBAT7L, "IBAT7L",
844 SPR_NOACCESS, SPR_NOACCESS,
845 &spr_read_ibat_h, &spr_write_ibatl_h,
846 0x00000000);
847 spr_register(env, SPR_DBAT4U, "DBAT4U",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_dbat_h, &spr_write_dbatu_h,
850 0x00000000);
851 spr_register(env, SPR_DBAT4L, "DBAT4L",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_dbat_h, &spr_write_dbatl_h,
854 0x00000000);
855 spr_register(env, SPR_DBAT5U, "DBAT5U",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_dbat_h, &spr_write_dbatu_h,
858 0x00000000);
859 spr_register(env, SPR_DBAT5L, "DBAT5L",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_dbat_h, &spr_write_dbatl_h,
862 0x00000000);
863 spr_register(env, SPR_DBAT6U, "DBAT6U",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_dbat_h, &spr_write_dbatu_h,
866 0x00000000);
867 spr_register(env, SPR_DBAT6L, "DBAT6L",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_dbat_h, &spr_write_dbatl_h,
870 0x00000000);
871 spr_register(env, SPR_DBAT7U, "DBAT7U",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_dbat_h, &spr_write_dbatu_h,
874 0x00000000);
875 spr_register(env, SPR_DBAT7L, "DBAT7L",
876 SPR_NOACCESS, SPR_NOACCESS,
877 &spr_read_dbat_h, &spr_write_dbatl_h,
878 0x00000000);
879 env->nb_BATs += 4;
880 #endif
881 }
882
883 /* Generic PowerPC time base */
884 static void gen_tbl (CPUPPCState *env)
885 {
886 spr_register(env, SPR_VTBL, "TBL",
887 &spr_read_tbl, SPR_NOACCESS,
888 &spr_read_tbl, SPR_NOACCESS,
889 0x00000000);
890 spr_register(env, SPR_TBL, "TBL",
891 &spr_read_tbl, SPR_NOACCESS,
892 &spr_read_tbl, &spr_write_tbl,
893 0x00000000);
894 spr_register(env, SPR_VTBU, "TBU",
895 &spr_read_tbu, SPR_NOACCESS,
896 &spr_read_tbu, SPR_NOACCESS,
897 0x00000000);
898 spr_register(env, SPR_TBU, "TBU",
899 &spr_read_tbu, SPR_NOACCESS,
900 &spr_read_tbu, &spr_write_tbu,
901 0x00000000);
902 }
903
904 /* Softare table search registers */
905 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
906 {
907 #if !defined(CONFIG_USER_ONLY)
908 env->nb_tlb = nb_tlbs;
909 env->nb_ways = nb_ways;
910 env->id_tlbs = 1;
911 env->tlb_type = TLB_6XX;
912 spr_register(env, SPR_DMISS, "DMISS",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, SPR_NOACCESS,
915 0x00000000);
916 spr_register(env, SPR_DCMP, "DCMP",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, SPR_NOACCESS,
919 0x00000000);
920 spr_register(env, SPR_HASH1, "HASH1",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, SPR_NOACCESS,
923 0x00000000);
924 spr_register(env, SPR_HASH2, "HASH2",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, SPR_NOACCESS,
927 0x00000000);
928 spr_register(env, SPR_IMISS, "IMISS",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, SPR_NOACCESS,
931 0x00000000);
932 spr_register(env, SPR_ICMP, "ICMP",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, SPR_NOACCESS,
935 0x00000000);
936 spr_register(env, SPR_RPA, "RPA",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_generic, &spr_write_generic,
939 0x00000000);
940 #endif
941 }
942
943 /* SPR common to MPC755 and G2 */
944 static void gen_spr_G2_755 (CPUPPCState *env)
945 {
946 /* SGPRs */
947 spr_register(env, SPR_SPRG4, "SPRG4",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951 spr_register(env, SPR_SPRG5, "SPRG5",
952 SPR_NOACCESS, SPR_NOACCESS,
953 &spr_read_generic, &spr_write_generic,
954 0x00000000);
955 spr_register(env, SPR_SPRG6, "SPRG6",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959 spr_register(env, SPR_SPRG7, "SPRG7",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 }
964
965 /* SPR common to all 7xx PowerPC implementations */
966 static void gen_spr_7xx (CPUPPCState *env)
967 {
968 /* Breakpoints */
969 /* XXX : not implemented */
970 spr_register_kvm(env, SPR_DABR, "DABR",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 KVM_REG_PPC_DABR, 0x00000000);
974 /* XXX : not implemented */
975 spr_register(env, SPR_IABR, "IABR",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, &spr_write_generic,
978 0x00000000);
979 /* Cache management */
980 /* XXX : not implemented */
981 spr_register(env, SPR_ICTC, "ICTC",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985 /* Performance monitors */
986 /* XXX : not implemented */
987 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
988 SPR_NOACCESS, SPR_NOACCESS,
989 &spr_read_generic, &spr_write_generic,
990 0x00000000);
991 /* XXX : not implemented */
992 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
993 SPR_NOACCESS, SPR_NOACCESS,
994 &spr_read_generic, &spr_write_generic,
995 0x00000000);
996 /* XXX : not implemented */
997 spr_register(env, SPR_7XX_PMC1, "PMC1",
998 SPR_NOACCESS, SPR_NOACCESS,
999 &spr_read_generic, &spr_write_generic,
1000 0x00000000);
1001 /* XXX : not implemented */
1002 spr_register(env, SPR_7XX_PMC2, "PMC2",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1005 0x00000000);
1006 /* XXX : not implemented */
1007 spr_register(env, SPR_7XX_PMC3, "PMC3",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011 /* XXX : not implemented */
1012 spr_register(env, SPR_7XX_PMC4, "PMC4",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
1016 /* XXX : not implemented */
1017 spr_register(env, SPR_7XX_SIAR, "SIAR",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, SPR_NOACCESS,
1020 0x00000000);
1021 /* XXX : not implemented */
1022 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1023 &spr_read_ureg, SPR_NOACCESS,
1024 &spr_read_ureg, SPR_NOACCESS,
1025 0x00000000);
1026 /* XXX : not implemented */
1027 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1028 &spr_read_ureg, SPR_NOACCESS,
1029 &spr_read_ureg, SPR_NOACCESS,
1030 0x00000000);
1031 /* XXX : not implemented */
1032 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1033 &spr_read_ureg, SPR_NOACCESS,
1034 &spr_read_ureg, SPR_NOACCESS,
1035 0x00000000);
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1038 &spr_read_ureg, SPR_NOACCESS,
1039 &spr_read_ureg, SPR_NOACCESS,
1040 0x00000000);
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1043 &spr_read_ureg, SPR_NOACCESS,
1044 &spr_read_ureg, SPR_NOACCESS,
1045 0x00000000);
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1048 &spr_read_ureg, SPR_NOACCESS,
1049 &spr_read_ureg, SPR_NOACCESS,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_7XX_USIAR, "USIAR",
1053 &spr_read_ureg, SPR_NOACCESS,
1054 &spr_read_ureg, SPR_NOACCESS,
1055 0x00000000);
1056 /* External access control */
1057 /* XXX : not implemented */
1058 spr_register(env, SPR_EAR, "EAR",
1059 SPR_NOACCESS, SPR_NOACCESS,
1060 &spr_read_generic, &spr_write_generic,
1061 0x00000000);
1062 }
1063
1064 #ifdef TARGET_PPC64
1065 #ifndef CONFIG_USER_ONLY
1066 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1067 {
1068 TCGv t0 = tcg_temp_new();
1069 TCGv t1 = tcg_temp_new();
1070 TCGv t2 = tcg_temp_new();
1071
1072 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1073 * spr_write_generic for HV mode in the SPR table
1074 */
1075
1076 /* Build insertion mask into t1 based on context */
1077 if (ctx->pr) {
1078 gen_load_spr(t1, SPR_UAMOR);
1079 } else {
1080 gen_load_spr(t1, SPR_AMOR);
1081 }
1082
1083 /* Mask new bits into t2 */
1084 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1085
1086 /* Load AMR and clear new bits in t0 */
1087 gen_load_spr(t0, SPR_AMR);
1088 tcg_gen_andc_tl(t0, t0, t1);
1089
1090 /* Or'in new bits and write it out */
1091 tcg_gen_or_tl(t0, t0, t2);
1092 gen_store_spr(SPR_AMR, t0);
1093 spr_store_dump_spr(SPR_AMR);
1094
1095 tcg_temp_free(t0);
1096 tcg_temp_free(t1);
1097 tcg_temp_free(t2);
1098 }
1099
1100 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1101 {
1102 TCGv t0 = tcg_temp_new();
1103 TCGv t1 = tcg_temp_new();
1104 TCGv t2 = tcg_temp_new();
1105
1106 /* Note, the HV=1 case is handled earlier by simply using
1107 * spr_write_generic for HV mode in the SPR table
1108 */
1109
1110 /* Build insertion mask into t1 based on context */
1111 gen_load_spr(t1, SPR_AMOR);
1112
1113 /* Mask new bits into t2 */
1114 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1115
1116 /* Load AMR and clear new bits in t0 */
1117 gen_load_spr(t0, SPR_UAMOR);
1118 tcg_gen_andc_tl(t0, t0, t1);
1119
1120 /* Or'in new bits and write it out */
1121 tcg_gen_or_tl(t0, t0, t2);
1122 gen_store_spr(SPR_UAMOR, t0);
1123 spr_store_dump_spr(SPR_UAMOR);
1124
1125 tcg_temp_free(t0);
1126 tcg_temp_free(t1);
1127 tcg_temp_free(t2);
1128 }
1129
1130 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1131 {
1132 TCGv t0 = tcg_temp_new();
1133 TCGv t1 = tcg_temp_new();
1134 TCGv t2 = tcg_temp_new();
1135
1136 /* Note, the HV=1 case is handled earlier by simply using
1137 * spr_write_generic for HV mode in the SPR table
1138 */
1139
1140 /* Build insertion mask into t1 based on context */
1141 gen_load_spr(t1, SPR_AMOR);
1142
1143 /* Mask new bits into t2 */
1144 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1145
1146 /* Load AMR and clear new bits in t0 */
1147 gen_load_spr(t0, SPR_IAMR);
1148 tcg_gen_andc_tl(t0, t0, t1);
1149
1150 /* Or'in new bits and write it out */
1151 tcg_gen_or_tl(t0, t0, t2);
1152 gen_store_spr(SPR_IAMR, t0);
1153 spr_store_dump_spr(SPR_IAMR);
1154
1155 tcg_temp_free(t0);
1156 tcg_temp_free(t1);
1157 tcg_temp_free(t2);
1158 }
1159 #endif /* CONFIG_USER_ONLY */
1160
1161 static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
1162 {
1163 #ifndef CONFIG_USER_ONLY
1164 /* Virtual Page Class Key protection */
1165 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1166 * userspace accessible, 29 is privileged. So we only need to set
1167 * the kvm ONE_REG id on one of them, we use 29 */
1168 spr_register(env, SPR_UAMR, "UAMR",
1169 &spr_read_generic, &spr_write_amr,
1170 &spr_read_generic, &spr_write_amr,
1171 0);
1172 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_amr,
1175 &spr_read_generic, &spr_write_generic,
1176 KVM_REG_PPC_AMR, 0);
1177 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_uamor,
1180 &spr_read_generic, &spr_write_generic,
1181 KVM_REG_PPC_UAMOR, 0);
1182 spr_register_hv(env, SPR_AMOR, "AMOR",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0);
1187 if (has_iamr) {
1188 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_iamr,
1191 &spr_read_generic, &spr_write_generic,
1192 KVM_REG_PPC_IAMR, 0);
1193 }
1194 #endif /* !CONFIG_USER_ONLY */
1195 }
1196 #endif /* TARGET_PPC64 */
1197
1198 static void gen_spr_thrm (CPUPPCState *env)
1199 {
1200 /* Thermal management */
1201 /* XXX : not implemented */
1202 spr_register(env, SPR_THRM1, "THRM1",
1203 SPR_NOACCESS, SPR_NOACCESS,
1204 &spr_read_generic, &spr_write_generic,
1205 0x00000000);
1206 /* XXX : not implemented */
1207 spr_register(env, SPR_THRM2, "THRM2",
1208 SPR_NOACCESS, SPR_NOACCESS,
1209 &spr_read_generic, &spr_write_generic,
1210 0x00000000);
1211 /* XXX : not implemented */
1212 spr_register(env, SPR_THRM3, "THRM3",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 }
1217
1218 /* SPR specific to PowerPC 604 implementation */
1219 static void gen_spr_604 (CPUPPCState *env)
1220 {
1221 /* Processor identification */
1222 spr_register(env, SPR_PIR, "PIR",
1223 SPR_NOACCESS, SPR_NOACCESS,
1224 &spr_read_generic, &spr_write_pir,
1225 0x00000000);
1226 /* Breakpoints */
1227 /* XXX : not implemented */
1228 spr_register(env, SPR_IABR, "IABR",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_generic, &spr_write_generic,
1231 0x00000000);
1232 /* XXX : not implemented */
1233 spr_register_kvm(env, SPR_DABR, "DABR",
1234 SPR_NOACCESS, SPR_NOACCESS,
1235 &spr_read_generic, &spr_write_generic,
1236 KVM_REG_PPC_DABR, 0x00000000);
1237 /* Performance counters */
1238 /* XXX : not implemented */
1239 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243 /* XXX : not implemented */
1244 spr_register(env, SPR_7XX_PMC1, "PMC1",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_generic, &spr_write_generic,
1247 0x00000000);
1248 /* XXX : not implemented */
1249 spr_register(env, SPR_7XX_PMC2, "PMC2",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 &spr_read_generic, &spr_write_generic,
1252 0x00000000);
1253 /* XXX : not implemented */
1254 spr_register(env, SPR_7XX_SIAR, "SIAR",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, SPR_NOACCESS,
1257 0x00000000);
1258 /* XXX : not implemented */
1259 spr_register(env, SPR_SDA, "SDA",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, SPR_NOACCESS,
1262 0x00000000);
1263 /* External access control */
1264 /* XXX : not implemented */
1265 spr_register(env, SPR_EAR, "EAR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
1269 }
1270
1271 /* SPR specific to PowerPC 603 implementation */
1272 static void gen_spr_603 (CPUPPCState *env)
1273 {
1274 /* External access control */
1275 /* XXX : not implemented */
1276 spr_register(env, SPR_EAR, "EAR",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1279 0x00000000);
1280 /* Breakpoints */
1281 /* XXX : not implemented */
1282 spr_register(env, SPR_IABR, "IABR",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 &spr_read_generic, &spr_write_generic,
1285 0x00000000);
1286
1287 }
1288
1289 /* SPR specific to PowerPC G2 implementation */
1290 static void gen_spr_G2 (CPUPPCState *env)
1291 {
1292 /* Memory base address */
1293 /* MBAR */
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_MBAR, "MBAR",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* Exception processing */
1300 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, &spr_write_generic,
1303 0x00000000);
1304 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* Breakpoints */
1309 /* XXX : not implemented */
1310 spr_register(env, SPR_DABR, "DABR",
1311 SPR_NOACCESS, SPR_NOACCESS,
1312 &spr_read_generic, &spr_write_generic,
1313 0x00000000);
1314 /* XXX : not implemented */
1315 spr_register(env, SPR_DABR2, "DABR2",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_generic, &spr_write_generic,
1318 0x00000000);
1319 /* XXX : not implemented */
1320 spr_register(env, SPR_IABR, "IABR",
1321 SPR_NOACCESS, SPR_NOACCESS,
1322 &spr_read_generic, &spr_write_generic,
1323 0x00000000);
1324 /* XXX : not implemented */
1325 spr_register(env, SPR_IABR2, "IABR2",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 /* XXX : not implemented */
1330 spr_register(env, SPR_IBCR, "IBCR",
1331 SPR_NOACCESS, SPR_NOACCESS,
1332 &spr_read_generic, &spr_write_generic,
1333 0x00000000);
1334 /* XXX : not implemented */
1335 spr_register(env, SPR_DBCR, "DBCR",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_generic, &spr_write_generic,
1338 0x00000000);
1339 }
1340
1341 /* SPR specific to PowerPC 602 implementation */
1342 static void gen_spr_602 (CPUPPCState *env)
1343 {
1344 /* ESA registers */
1345 /* XXX : not implemented */
1346 spr_register(env, SPR_SER, "SER",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 /* XXX : not implemented */
1351 spr_register(env, SPR_SEBR, "SEBR",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_ESASRR, "ESASRR",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 /* Floating point status */
1361 /* XXX : not implemented */
1362 spr_register(env, SPR_SP, "SP",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_generic,
1365 0x00000000);
1366 /* XXX : not implemented */
1367 spr_register(env, SPR_LT, "LT",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 /* Watchdog timer */
1372 /* XXX : not implemented */
1373 spr_register(env, SPR_TCR, "TCR",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 /* Interrupt base */
1378 spr_register(env, SPR_IBR, "IBR",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382 /* XXX : not implemented */
1383 spr_register(env, SPR_IABR, "IABR",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387 }
1388
1389 /* SPR specific to PowerPC 601 implementation */
1390 static void gen_spr_601 (CPUPPCState *env)
1391 {
1392 /* Multiplication/division register */
1393 /* MQ */
1394 spr_register(env, SPR_MQ, "MQ",
1395 &spr_read_generic, &spr_write_generic,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
1398 /* RTC registers */
1399 spr_register(env, SPR_601_RTCU, "RTCU",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 SPR_NOACCESS, &spr_write_601_rtcu,
1402 0x00000000);
1403 spr_register(env, SPR_601_VRTCU, "RTCU",
1404 &spr_read_601_rtcu, SPR_NOACCESS,
1405 &spr_read_601_rtcu, SPR_NOACCESS,
1406 0x00000000);
1407 spr_register(env, SPR_601_RTCL, "RTCL",
1408 SPR_NOACCESS, SPR_NOACCESS,
1409 SPR_NOACCESS, &spr_write_601_rtcl,
1410 0x00000000);
1411 spr_register(env, SPR_601_VRTCL, "RTCL",
1412 &spr_read_601_rtcl, SPR_NOACCESS,
1413 &spr_read_601_rtcl, SPR_NOACCESS,
1414 0x00000000);
1415 /* Timer */
1416 #if 0 /* ? */
1417 spr_register(env, SPR_601_UDECR, "UDECR",
1418 &spr_read_decr, SPR_NOACCESS,
1419 &spr_read_decr, SPR_NOACCESS,
1420 0x00000000);
1421 #endif
1422 /* External access control */
1423 /* XXX : not implemented */
1424 spr_register(env, SPR_EAR, "EAR",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428 /* Memory management */
1429 #if !defined(CONFIG_USER_ONLY)
1430 spr_register(env, SPR_IBAT0U, "IBAT0U",
1431 SPR_NOACCESS, SPR_NOACCESS,
1432 &spr_read_601_ubat, &spr_write_601_ubatu,
1433 0x00000000);
1434 spr_register(env, SPR_IBAT0L, "IBAT0L",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_601_ubat, &spr_write_601_ubatl,
1437 0x00000000);
1438 spr_register(env, SPR_IBAT1U, "IBAT1U",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_601_ubat, &spr_write_601_ubatu,
1441 0x00000000);
1442 spr_register(env, SPR_IBAT1L, "IBAT1L",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_601_ubat, &spr_write_601_ubatl,
1445 0x00000000);
1446 spr_register(env, SPR_IBAT2U, "IBAT2U",
1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_601_ubat, &spr_write_601_ubatu,
1449 0x00000000);
1450 spr_register(env, SPR_IBAT2L, "IBAT2L",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_601_ubat, &spr_write_601_ubatl,
1453 0x00000000);
1454 spr_register(env, SPR_IBAT3U, "IBAT3U",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_601_ubat, &spr_write_601_ubatu,
1457 0x00000000);
1458 spr_register(env, SPR_IBAT3L, "IBAT3L",
1459 SPR_NOACCESS, SPR_NOACCESS,
1460 &spr_read_601_ubat, &spr_write_601_ubatl,
1461 0x00000000);
1462 env->nb_BATs = 4;
1463 #endif
1464 }
1465
1466 static void gen_spr_74xx (CPUPPCState *env)
1467 {
1468 /* Processor identification */
1469 spr_register(env, SPR_PIR, "PIR",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_pir,
1472 0x00000000);
1473 /* XXX : not implemented */
1474 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
1478 /* XXX : not implemented */
1479 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1480 &spr_read_ureg, SPR_NOACCESS,
1481 &spr_read_ureg, SPR_NOACCESS,
1482 0x00000000);
1483 /* XXX: not implemented */
1484 spr_register(env, SPR_BAMR, "BAMR",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* XXX : not implemented */
1489 spr_register(env, SPR_MSSCR0, "MSSCR0",
1490 SPR_NOACCESS, SPR_NOACCESS,
1491 &spr_read_generic, &spr_write_generic,
1492 0x00000000);
1493 /* Hardware implementation registers */
1494 /* XXX : not implemented */
1495 spr_register(env, SPR_HID0, "HID0",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 /* XXX : not implemented */
1500 spr_register(env, SPR_HID1, "HID1",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_generic, &spr_write_generic,
1503 0x00000000);
1504 /* Altivec */
1505 spr_register(env, SPR_VRSAVE, "VRSAVE",
1506 &spr_read_generic, &spr_write_generic,
1507 &spr_read_generic, &spr_write_generic,
1508 0x00000000);
1509 /* XXX : not implemented */
1510 spr_register(env, SPR_L2CR, "L2CR",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_generic, spr_access_nop,
1513 0x00000000);
1514 /* Not strictly an SPR */
1515 vscr_init(env, 0x00010000);
1516 }
1517
1518 static void gen_l3_ctrl (CPUPPCState *env)
1519 {
1520 /* L3CR */
1521 /* XXX : not implemented */
1522 spr_register(env, SPR_L3CR, "L3CR",
1523 SPR_NOACCESS, SPR_NOACCESS,
1524 &spr_read_generic, &spr_write_generic,
1525 0x00000000);
1526 /* L3ITCR0 */
1527 /* XXX : not implemented */
1528 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 /* L3PM */
1533 /* XXX : not implemented */
1534 spr_register(env, SPR_L3PM, "L3PM",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538 }
1539
1540 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1541 {
1542 #if !defined(CONFIG_USER_ONLY)
1543 env->nb_tlb = nb_tlbs;
1544 env->nb_ways = nb_ways;
1545 env->id_tlbs = 1;
1546 env->tlb_type = TLB_6XX;
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_PTEHI, "PTEHI",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_PTELO, "PTELO",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_TLBMISS, "TLBMISS",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 #endif
1563 }
1564
1565 #if !defined(CONFIG_USER_ONLY)
1566 static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
1567 {
1568 TCGv t0 = tcg_temp_new();
1569
1570 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1571 gen_store_spr(sprn, t0);
1572 tcg_temp_free(t0);
1573 }
1574
1575 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1576 {
1577 TCGv t0 = tcg_temp_new();
1578
1579 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1580 gen_store_spr(sprn, t0);
1581 tcg_temp_free(t0);
1582 }
1583
1584 static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
1585 {
1586 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1587 }
1588
1589 static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
1590 {
1591 TCGv_i32 t0 = tcg_const_i32(sprn);
1592 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1593 tcg_temp_free_i32(t0);
1594 }
1595 #endif
1596
1597 static void gen_spr_usprgh (CPUPPCState *env)
1598 {
1599 spr_register(env, SPR_USPRG4, "USPRG4",
1600 &spr_read_ureg, SPR_NOACCESS,
1601 &spr_read_ureg, SPR_NOACCESS,
1602 0x00000000);
1603 spr_register(env, SPR_USPRG5, "USPRG5",
1604 &spr_read_ureg, SPR_NOACCESS,
1605 &spr_read_ureg, SPR_NOACCESS,
1606 0x00000000);
1607 spr_register(env, SPR_USPRG6, "USPRG6",
1608 &spr_read_ureg, SPR_NOACCESS,
1609 &spr_read_ureg, SPR_NOACCESS,
1610 0x00000000);
1611 spr_register(env, SPR_USPRG7, "USPRG7",
1612 &spr_read_ureg, SPR_NOACCESS,
1613 &spr_read_ureg, SPR_NOACCESS,
1614 0x00000000);
1615 }
1616
1617 /* PowerPC BookE SPR */
1618 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1619 {
1620 const char *ivor_names[64] = {
1621 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1622 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1623 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1624 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1625 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1626 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1627 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1628 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1629 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1630 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1631 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1632 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1633 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1634 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1635 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1636 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1637 };
1638 #define SPR_BOOKE_IVORxx (-1)
1639 int ivor_sprn[64] = {
1640 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1641 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1642 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1643 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1644 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1645 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1646 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1647 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1648 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1649 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1650 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1651 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1652 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1653 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1654 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1655 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1656 };
1657 int i;
1658
1659 /* Interrupt processing */
1660 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1661 SPR_NOACCESS, SPR_NOACCESS,
1662 &spr_read_generic, &spr_write_generic,
1663 0x00000000);
1664 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* Debug */
1669 /* XXX : not implemented */
1670 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1671 SPR_NOACCESS, SPR_NOACCESS,
1672 &spr_read_generic, &spr_write_generic,
1673 0x00000000);
1674 /* XXX : not implemented */
1675 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1676 SPR_NOACCESS, SPR_NOACCESS,
1677 &spr_read_generic, &spr_write_generic,
1678 0x00000000);
1679 /* XXX : not implemented */
1680 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1681 SPR_NOACCESS, SPR_NOACCESS,
1682 &spr_read_generic, &spr_write_generic,
1683 0x00000000);
1684 /* XXX : not implemented */
1685 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1686 SPR_NOACCESS, SPR_NOACCESS,
1687 &spr_read_generic, &spr_write_generic,
1688 0x00000000);
1689 /* XXX : not implemented */
1690 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1691 SPR_NOACCESS, SPR_NOACCESS,
1692 &spr_read_generic, &spr_write_40x_dbcr0,
1693 0x00000000);
1694 /* XXX : not implemented */
1695 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1696 SPR_NOACCESS, SPR_NOACCESS,
1697 &spr_read_generic, &spr_write_generic,
1698 0x00000000);
1699 /* XXX : not implemented */
1700 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_generic, &spr_write_generic,
1703 0x00000000);
1704 /* XXX : not implemented */
1705 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, &spr_write_clear,
1708 0x00000000);
1709 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_generic,
1712 0x00000000);
1713 spr_register(env, SPR_BOOKE_ESR, "ESR",
1714 SPR_NOACCESS, SPR_NOACCESS,
1715 &spr_read_generic, &spr_write_generic,
1716 0x00000000);
1717 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1718 SPR_NOACCESS, SPR_NOACCESS,
1719 &spr_read_generic, &spr_write_excp_prefix,
1720 0x00000000);
1721 /* Exception vectors */
1722 for (i = 0; i < 64; i++) {
1723 if (ivor_mask & (1ULL << i)) {
1724 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1725 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1726 exit(1);
1727 }
1728 spr_register(env, ivor_sprn[i], ivor_names[i],
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_excp_vector,
1731 0x00000000);
1732 }
1733 }
1734 spr_register(env, SPR_BOOKE_PID, "PID",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_booke_pid,
1737 0x00000000);
1738 spr_register(env, SPR_BOOKE_TCR, "TCR",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_booke_tcr,
1741 0x00000000);
1742 spr_register(env, SPR_BOOKE_TSR, "TSR",
1743 SPR_NOACCESS, SPR_NOACCESS,
1744 &spr_read_generic, &spr_write_booke_tsr,
1745 0x00000000);
1746 /* Timer */
1747 spr_register(env, SPR_DECR, "DECR",
1748 SPR_NOACCESS, SPR_NOACCESS,
1749 &spr_read_decr, &spr_write_decr,
1750 0x00000000);
1751 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1752 SPR_NOACCESS, SPR_NOACCESS,
1753 SPR_NOACCESS, &spr_write_generic,
1754 0x00000000);
1755 /* SPRGs */
1756 spr_register(env, SPR_USPRG0, "USPRG0",
1757 &spr_read_generic, &spr_write_generic,
1758 &spr_read_generic, &spr_write_generic,
1759 0x00000000);
1760 spr_register(env, SPR_SPRG4, "SPRG4",
1761 SPR_NOACCESS, SPR_NOACCESS,
1762 &spr_read_generic, &spr_write_generic,
1763 0x00000000);
1764 spr_register(env, SPR_SPRG5, "SPRG5",
1765 SPR_NOACCESS, SPR_NOACCESS,
1766 &spr_read_generic, &spr_write_generic,
1767 0x00000000);
1768 spr_register(env, SPR_SPRG6, "SPRG6",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 spr_register(env, SPR_SPRG7, "SPRG7",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 }
1777
1778 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1779 uint32_t maxsize, uint32_t flags,
1780 uint32_t nentries)
1781 {
1782 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1783 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1784 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1785 flags | nentries;
1786 }
1787
1788 /* BookE 2.06 storage control registers */
1789 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1790 uint32_t *tlbncfg)
1791 {
1792 #if !defined(CONFIG_USER_ONLY)
1793 const char *mas_names[8] = {
1794 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1795 };
1796 int mas_sprn[8] = {
1797 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1798 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1799 };
1800 int i;
1801
1802 /* TLB assist registers */
1803 /* XXX : not implemented */
1804 for (i = 0; i < 8; i++) {
1805 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1806 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1807 uea_write = &spr_write_generic;
1808 }
1809 if (mas_mask & (1 << i)) {
1810 spr_register(env, mas_sprn[i], mas_names[i],
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, uea_write,
1813 0x00000000);
1814 }
1815 }
1816 if (env->nb_pids > 1) {
1817 /* XXX : not implemented */
1818 spr_register(env, SPR_BOOKE_PID1, "PID1",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_booke_pid,
1821 0x00000000);
1822 }
1823 if (env->nb_pids > 2) {
1824 /* XXX : not implemented */
1825 spr_register(env, SPR_BOOKE_PID2, "PID2",
1826 SPR_NOACCESS, SPR_NOACCESS,
1827 &spr_read_generic, &spr_write_booke_pid,
1828 0x00000000);
1829 }
1830 /* XXX : not implemented */
1831 spr_register(env, SPR_MMUCFG, "MMUCFG",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, SPR_NOACCESS,
1834 0x00000000); /* TOFIX */
1835 switch (env->nb_ways) {
1836 case 4:
1837 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, SPR_NOACCESS,
1840 tlbncfg[3]);
1841 /* Fallthru */
1842 case 3:
1843 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1844 SPR_NOACCESS, SPR_NOACCESS,
1845 &spr_read_generic, SPR_NOACCESS,
1846 tlbncfg[2]);
1847 /* Fallthru */
1848 case 2:
1849 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, SPR_NOACCESS,
1852 tlbncfg[1]);
1853 /* Fallthru */
1854 case 1:
1855 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1856 SPR_NOACCESS, SPR_NOACCESS,
1857 &spr_read_generic, SPR_NOACCESS,
1858 tlbncfg[0]);
1859 /* Fallthru */
1860 case 0:
1861 default:
1862 break;
1863 }
1864 #endif
1865
1866 gen_spr_usprgh(env);
1867 }
1868
1869 /* SPR specific to PowerPC 440 implementation */
1870 static void gen_spr_440 (CPUPPCState *env)
1871 {
1872 /* Cache control */
1873 /* XXX : not implemented */
1874 spr_register(env, SPR_440_DNV0, "DNV0",
1875 SPR_NOACCESS, SPR_NOACCESS,
1876 &spr_read_generic, &spr_write_generic,
1877 0x00000000);
1878 /* XXX : not implemented */
1879 spr_register(env, SPR_440_DNV1, "DNV1",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_generic,
1882 0x00000000);
1883 /* XXX : not implemented */
1884 spr_register(env, SPR_440_DNV2, "DNV2",
1885 SPR_NOACCESS, SPR_NOACCESS,
1886 &spr_read_generic, &spr_write_generic,
1887 0x00000000);
1888 /* XXX : not implemented */
1889 spr_register(env, SPR_440_DNV3, "DNV3",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_generic,
1892 0x00000000);
1893 /* XXX : not implemented */
1894 spr_register(env, SPR_440_DTV0, "DTV0",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* XXX : not implemented */
1899 spr_register(env, SPR_440_DTV1, "DTV1",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, &spr_write_generic,
1902 0x00000000);
1903 /* XXX : not implemented */
1904 spr_register(env, SPR_440_DTV2, "DTV2",
1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908 /* XXX : not implemented */
1909 spr_register(env, SPR_440_DTV3, "DTV3",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_generic,
1912 0x00000000);
1913 /* XXX : not implemented */
1914 spr_register(env, SPR_440_DVLIM, "DVLIM",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_generic,
1917 0x00000000);
1918 /* XXX : not implemented */
1919 spr_register(env, SPR_440_INV0, "INV0",
1920 SPR_NOACCESS, SPR_NOACCESS,
1921 &spr_read_generic, &spr_write_generic,
1922 0x00000000);
1923 /* XXX : not implemented */
1924 spr_register(env, SPR_440_INV1, "INV1",
1925 SPR_NOACCESS, SPR_NOACCESS,
1926 &spr_read_generic, &spr_write_generic,
1927 0x00000000);
1928 /* XXX : not implemented */
1929 spr_register(env, SPR_440_INV2, "INV2",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 /* XXX : not implemented */
1934 spr_register(env, SPR_440_INV3, "INV3",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 &spr_read_generic, &spr_write_generic,
1937 0x00000000);
1938 /* XXX : not implemented */
1939 spr_register(env, SPR_440_ITV0, "ITV0",
1940 SPR_NOACCESS, SPR_NOACCESS,
1941 &spr_read_generic, &spr_write_generic,
1942 0x00000000);
1943 /* XXX : not implemented */
1944 spr_register(env, SPR_440_ITV1, "ITV1",
1945 SPR_NOACCESS, SPR_NOACCESS,
1946 &spr_read_generic, &spr_write_generic,
1947 0x00000000);
1948 /* XXX : not implemented */
1949 spr_register(env, SPR_440_ITV2, "ITV2",
1950 SPR_NOACCESS, SPR_NOACCESS,
1951 &spr_read_generic, &spr_write_generic,
1952 0x00000000);
1953 /* XXX : not implemented */
1954 spr_register(env, SPR_440_ITV3, "ITV3",
1955 SPR_NOACCESS, SPR_NOACCESS,
1956 &spr_read_generic, &spr_write_generic,
1957 0x00000000);
1958 /* XXX : not implemented */
1959 spr_register(env, SPR_440_IVLIM, "IVLIM",
1960 SPR_NOACCESS, SPR_NOACCESS,
1961 &spr_read_generic, &spr_write_generic,
1962 0x00000000);
1963 /* Cache debug */
1964 /* XXX : not implemented */
1965 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1966 SPR_NOACCESS, SPR_NOACCESS,
1967 &spr_read_generic, SPR_NOACCESS,
1968 0x00000000);
1969 /* XXX : not implemented */
1970 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1971 SPR_NOACCESS, SPR_NOACCESS,
1972 &spr_read_generic, SPR_NOACCESS,
1973 0x00000000);
1974 /* XXX : not implemented */
1975 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, SPR_NOACCESS,
1978 0x00000000);
1979 /* XXX : not implemented */
1980 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1981 SPR_NOACCESS, SPR_NOACCESS,
1982 &spr_read_generic, SPR_NOACCESS,
1983 0x00000000);
1984 /* XXX : not implemented */
1985 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1986 SPR_NOACCESS, SPR_NOACCESS,
1987 &spr_read_generic, SPR_NOACCESS,
1988 0x00000000);
1989 /* XXX : not implemented */
1990 spr_register(env, SPR_440_DBDR, "DBDR",
1991 SPR_NOACCESS, SPR_NOACCESS,
1992 &spr_read_generic, &spr_write_generic,
1993 0x00000000);
1994 /* Processor control */
1995 spr_register(env, SPR_4xx_CCR0, "CCR0",
1996 SPR_NOACCESS, SPR_NOACCESS,
1997 &spr_read_generic, &spr_write_generic,
1998 0x00000000);
1999 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, SPR_NOACCESS,
2002 0x00000000);
2003 /* Storage control */
2004 spr_register(env, SPR_440_MMUCR, "MMUCR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 }
2009
2010 /* SPR shared between PowerPC 40x implementations */
2011 static void gen_spr_40x (CPUPPCState *env)
2012 {
2013 /* Cache */
2014 /* not emulated, as QEMU do not emulate caches */
2015 spr_register(env, SPR_40x_DCCR, "DCCR",
2016 SPR_NOACCESS, SPR_NOACCESS,
2017 &spr_read_generic, &spr_write_generic,
2018 0x00000000);
2019 /* not emulated, as QEMU do not emulate caches */
2020 spr_register(env, SPR_40x_ICCR, "ICCR",
2021 SPR_NOACCESS, SPR_NOACCESS,
2022 &spr_read_generic, &spr_write_generic,
2023 0x00000000);
2024 /* not emulated, as QEMU do not emulate caches */
2025 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2026 SPR_NOACCESS, SPR_NOACCESS,
2027 &spr_read_generic, SPR_NOACCESS,
2028 0x00000000);
2029 /* Exception */
2030 spr_register(env, SPR_40x_DEAR, "DEAR",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 &spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 spr_register(env, SPR_40x_ESR, "ESR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 spr_register(env, SPR_40x_EVPR, "EVPR",
2039 SPR_NOACCESS, SPR_NOACCESS,
2040 &spr_read_generic, &spr_write_excp_prefix,
2041 0x00000000);
2042 spr_register(env, SPR_40x_SRR2, "SRR2",
2043 &spr_read_generic, &spr_write_generic,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
2046 spr_register(env, SPR_40x_SRR3, "SRR3",
2047 &spr_read_generic, &spr_write_generic,
2048 &spr_read_generic, &spr_write_generic,
2049 0x00000000);
2050 /* Timers */
2051 spr_register(env, SPR_40x_PIT, "PIT",
2052 SPR_NOACCESS, SPR_NOACCESS,
2053 &spr_read_40x_pit, &spr_write_40x_pit,
2054 0x00000000);
2055 spr_register(env, SPR_40x_TCR, "TCR",
2056 SPR_NOACCESS, SPR_NOACCESS,
2057 &spr_read_generic, &spr_write_booke_tcr,
2058 0x00000000);
2059 spr_register(env, SPR_40x_TSR, "TSR",
2060 SPR_NOACCESS, SPR_NOACCESS,
2061 &spr_read_generic, &spr_write_booke_tsr,
2062 0x00000000);
2063 }
2064
2065 /* SPR specific to PowerPC 405 implementation */
2066 static void gen_spr_405 (CPUPPCState *env)
2067 {
2068 /* MMU */
2069 spr_register(env, SPR_40x_PID, "PID",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, &spr_write_generic,
2072 0x00000000);
2073 spr_register(env, SPR_4xx_CCR0, "CCR0",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 &spr_read_generic, &spr_write_generic,
2076 0x00700000);
2077 /* Debug interface */
2078 /* XXX : not implemented */
2079 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, &spr_write_40x_dbcr0,
2082 0x00000000);
2083 /* XXX : not implemented */
2084 spr_register(env, SPR_405_DBCR1, "DBCR1",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
2088 /* XXX : not implemented */
2089 spr_register(env, SPR_40x_DBSR, "DBSR",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, &spr_write_clear,
2092 /* Last reset was system reset */
2093 0x00000300);
2094 /* XXX : not implemented */
2095 spr_register(env, SPR_40x_DAC1, "DAC1",
2096 SPR_NOACCESS, SPR_NOACCESS,
2097 &spr_read_generic, &spr_write_generic,
2098 0x00000000);
2099 spr_register(env, SPR_40x_DAC2, "DAC2",
2100 SPR_NOACCESS, SPR_NOACCESS,
2101 &spr_read_generic, &spr_write_generic,
2102 0x00000000);
2103 /* XXX : not implemented */
2104 spr_register(env, SPR_405_DVC1, "DVC1",
2105 SPR_NOACCESS, SPR_NOACCESS,
2106 &spr_read_generic, &spr_write_generic,
2107 0x00000000);
2108 /* XXX : not implemented */
2109 spr_register(env, SPR_405_DVC2, "DVC2",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_generic,
2112 0x00000000);
2113 /* XXX : not implemented */
2114 spr_register(env, SPR_40x_IAC1, "IAC1",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 spr_register(env, SPR_40x_IAC2, "IAC2",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_405_IAC3, "IAC3",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 /* XXX : not implemented */
2128 spr_register(env, SPR_405_IAC4, "IAC4",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 /* Storage control */
2133 /* XXX: TODO: not implemented */
2134 spr_register(env, SPR_405_SLER, "SLER",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_40x_sler,
2137 0x00000000);
2138 spr_register(env, SPR_40x_ZPR, "ZPR",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_405_SU0R, "SU0R",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_generic,
2146 0x00000000);
2147 /* SPRG */
2148 spr_register(env, SPR_USPRG0, "USPRG0",
2149 &spr_read_ureg, SPR_NOACCESS,
2150 &spr_read_ureg, SPR_NOACCESS,
2151 0x00000000);
2152 spr_register(env, SPR_SPRG4, "SPRG4",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, &spr_write_generic,
2155 0x00000000);
2156 spr_register(env, SPR_SPRG5, "SPRG5",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 spr_read_generic, &spr_write_generic,
2159 0x00000000);
2160 spr_register(env, SPR_SPRG6, "SPRG6",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 spr_register(env, SPR_SPRG7, "SPRG7",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 gen_spr_usprgh(env);
2169 }
2170
2171 /* SPR shared between PowerPC 401 & 403 implementations */
2172 static void gen_spr_401_403 (CPUPPCState *env)
2173 {
2174 /* Time base */
2175 spr_register(env, SPR_403_VTBL, "TBL",
2176 &spr_read_tbl, SPR_NOACCESS,
2177 &spr_read_tbl, SPR_NOACCESS,
2178 0x00000000);
2179 spr_register(env, SPR_403_TBL, "TBL",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 SPR_NOACCESS, &spr_write_tbl,
2182 0x00000000);
2183 spr_register(env, SPR_403_VTBU, "TBU",
2184 &spr_read_tbu, SPR_NOACCESS,
2185 &spr_read_tbu, SPR_NOACCESS,
2186 0x00000000);
2187 spr_register(env, SPR_403_TBU, "TBU",
2188 SPR_NOACCESS, SPR_NOACCESS,
2189 SPR_NOACCESS, &spr_write_tbu,
2190 0x00000000);
2191 /* Debug */
2192 /* not emulated, as QEMU do not emulate caches */
2193 spr_register(env, SPR_403_CDBCR, "CDBCR",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 }
2198
2199 /* SPR specific to PowerPC 401 implementation */
2200 static void gen_spr_401 (CPUPPCState *env)
2201 {
2202 /* Debug interface */
2203 /* XXX : not implemented */
2204 spr_register(env, SPR_40x_DBCR0, "DBCR",
2205 SPR_NOACCESS, SPR_NOACCESS,
2206 &spr_read_generic, &spr_write_40x_dbcr0,
2207 0x00000000);
2208 /* XXX : not implemented */
2209 spr_register(env, SPR_40x_DBSR, "DBSR",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_clear,
2212 /* Last reset was system reset */
2213 0x00000300);
2214 /* XXX : not implemented */
2215 spr_register(env, SPR_40x_DAC1, "DAC",
2216 SPR_NOACCESS, SPR_NOACCESS,
2217 &spr_read_generic, &spr_write_generic,
2218 0x00000000);
2219 /* XXX : not implemented */
2220 spr_register(env, SPR_40x_IAC1, "IAC",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 /* Storage control */
2225 /* XXX: TODO: not implemented */
2226 spr_register(env, SPR_405_SLER, "SLER",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_40x_sler,
2229 0x00000000);
2230 /* not emulated, as QEMU never does speculative access */
2231 spr_register(env, SPR_40x_SGR, "SGR",
2232 SPR_NOACCESS, SPR_NOACCESS,
2233 &spr_read_generic, &spr_write_generic,
2234 0xFFFFFFFF);
2235 /* not emulated, as QEMU do not emulate caches */
2236 spr_register(env, SPR_40x_DCWR, "DCWR",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 }
2241
2242 static void gen_spr_401x2 (CPUPPCState *env)
2243 {
2244 gen_spr_401(env);
2245 spr_register(env, SPR_40x_PID, "PID",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 spr_register(env, SPR_40x_ZPR, "ZPR",
2250 SPR_NOACCESS, SPR_NOACCESS,
2251 &spr_read_generic, &spr_write_generic,
2252 0x00000000);
2253 }
2254
2255 /* SPR specific to PowerPC 403 implementation */
2256 static void gen_spr_403 (CPUPPCState *env)
2257 {
2258 /* Debug interface */
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_40x_dbcr0,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_40x_DBSR, "DBSR",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_clear,
2268 /* Last reset was system reset */
2269 0x00000300);
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_40x_DAC1, "DAC1",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_40x_DAC2, "DAC2",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 /* XXX : not implemented */
2281 spr_register(env, SPR_40x_IAC1, "IAC1",
2282 SPR_NOACCESS, SPR_NOACCESS,
2283 &spr_read_generic, &spr_write_generic,
2284 0x00000000);
2285 /* XXX : not implemented */
2286 spr_register(env, SPR_40x_IAC2, "IAC2",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_generic, &spr_write_generic,
2289 0x00000000);
2290 }
2291
2292 static void gen_spr_403_real (CPUPPCState *env)
2293 {
2294 spr_register(env, SPR_403_PBL1, "PBL1",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_403_pbr, &spr_write_403_pbr,
2297 0x00000000);
2298 spr_register(env, SPR_403_PBU1, "PBU1",
2299 SPR_NOACCESS, SPR_NOACCESS,
2300 &spr_read_403_pbr, &spr_write_403_pbr,
2301 0x00000000);
2302 spr_register(env, SPR_403_PBL2, "PBL2",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_403_pbr, &spr_write_403_pbr,
2305 0x00000000);
2306 spr_register(env, SPR_403_PBU2, "PBU2",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_403_pbr, &spr_write_403_pbr,
2309 0x00000000);
2310 }
2311
2312 static void gen_spr_403_mmu (CPUPPCState *env)
2313 {
2314 /* MMU */
2315 spr_register(env, SPR_40x_PID, "PID",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 spr_register(env, SPR_40x_ZPR, "ZPR",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_generic,
2322 0x00000000);
2323 }
2324
2325 /* SPR specific to PowerPC compression coprocessor extension */
2326 static void gen_spr_compress (CPUPPCState *env)
2327 {
2328 /* XXX : not implemented */
2329 spr_register(env, SPR_401_SKR, "SKR",
2330 SPR_NOACCESS, SPR_NOACCESS,
2331 &spr_read_generic, &spr_write_generic,
2332 0x00000000);
2333 }
2334
2335 static void gen_spr_5xx_8xx (CPUPPCState *env)
2336 {
2337 /* Exception processing */
2338 spr_register_kvm(env, SPR_DSISR, "DSISR",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 KVM_REG_PPC_DSISR, 0x00000000);
2342 spr_register_kvm(env, SPR_DAR, "DAR",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 KVM_REG_PPC_DAR, 0x00000000);
2346 /* Timer */
2347 spr_register(env, SPR_DECR, "DECR",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_decr, &spr_write_decr,
2350 0x00000000);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_MPC_EIE, "EIE",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_MPC_EID, "EID",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* XXX : not implemented */
2362 spr_register(env, SPR_MPC_NRI, "NRI",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 /* XXX : not implemented */
2367 spr_register(env, SPR_MPC_CMPA, "CMPA",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_generic, &spr_write_generic,
2370 0x00000000);
2371 /* XXX : not implemented */
2372 spr_register(env, SPR_MPC_CMPB, "CMPB",
2373 SPR_NOACCESS, SPR_NOACCESS,
2374 &spr_read_generic, &spr_write_generic,
2375 0x00000000);
2376 /* XXX : not implemented */
2377 spr_register(env, SPR_MPC_CMPC, "CMPC",
2378 SPR_NOACCESS, SPR_NOACCESS,
2379 &spr_read_generic, &spr_write_generic,
2380 0x00000000);
2381 /* XXX : not implemented */
2382 spr_register(env, SPR_MPC_CMPD, "CMPD",
2383 SPR_NOACCESS, SPR_NOACCESS,
2384 &spr_read_generic, &spr_write_generic,
2385 0x00000000);
2386 /* XXX : not implemented */
2387 spr_register(env, SPR_MPC_ECR, "ECR",
2388 SPR_NOACCESS, SPR_NOACCESS,
2389 &spr_read_generic, &spr_write_generic,
2390 0x00000000);
2391 /* XXX : not implemented */
2392 spr_register(env, SPR_MPC_DER, "DER",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_generic,
2395 0x00000000);
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 /* XXX : not implemented */
2402 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2403 SPR_NOACCESS, SPR_NOACCESS,
2404 &spr_read_generic, &spr_write_generic,
2405 0x00000000);
2406 /* XXX : not implemented */
2407 spr_register(env, SPR_MPC_CMPE, "CMPE",
2408 SPR_NOACCESS, SPR_NOACCESS,
2409 &spr_read_generic, &spr_write_generic,
2410 0x00000000);
2411 /* XXX : not implemented */
2412 spr_register(env, SPR_MPC_CMPF, "CMPF",
2413 SPR_NOACCESS, SPR_NOACCESS,
2414 &spr_read_generic, &spr_write_generic,
2415 0x00000000);
2416 /* XXX : not implemented */
2417 spr_register(env, SPR_MPC_CMPG, "CMPG",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 /* XXX : not implemented */
2422 spr_register(env, SPR_MPC_CMPH, "CMPH",
2423 SPR_NOACCESS, SPR_NOACCESS,
2424 &spr_read_generic, &spr_write_generic,
2425 0x00000000);
2426 /* XXX : not implemented */
2427 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2428 SPR_NOACCESS, SPR_NOACCESS,
2429 &spr_read_generic, &spr_write_generic,
2430 0x00000000);
2431 /* XXX : not implemented */
2432 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2433 SPR_NOACCESS, SPR_NOACCESS,
2434 &spr_read_generic, &spr_write_generic,
2435 0x00000000);
2436 /* XXX : not implemented */
2437 spr_register(env, SPR_MPC_BAR, "BAR",
2438 SPR_NOACCESS, SPR_NOACCESS,
2439 &spr_read_generic, &spr_write_generic,
2440 0x00000000);
2441 /* XXX : not implemented */
2442 spr_register(env, SPR_MPC_DPDR, "DPDR",
2443 SPR_NOACCESS, SPR_NOACCESS,
2444 &spr_read_generic, &spr_write_generic,
2445 0x00000000);
2446 /* XXX : not implemented */
2447 spr_register(env, SPR_MPC_IMMR, "IMMR",
2448 SPR_NOACCESS, SPR_NOACCESS,
2449 &spr_read_generic, &spr_write_generic,
2450 0x00000000);
2451 }
2452
2453 static void gen_spr_5xx (CPUPPCState *env)
2454 {
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 /* XXX : not implemented */
2506 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 0x00000000);
2510 /* XXX : not implemented */
2511 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2512 SPR_NOACCESS, SPR_NOACCESS,
2513 &spr_read_generic, &spr_write_generic,
2514 0x00000000);
2515 /* XXX : not implemented */
2516 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2517 SPR_NOACCESS, SPR_NOACCESS,
2518 &spr_read_generic, &spr_write_generic,
2519 0x00000000);
2520 /* XXX : not implemented */
2521 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2522 SPR_NOACCESS, SPR_NOACCESS,
2523 &spr_read_generic, &spr_write_generic,
2524 0x00000000);
2525 /* XXX : not implemented */
2526 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2527 SPR_NOACCESS, SPR_NOACCESS,
2528 &spr_read_generic, &spr_write_generic,
2529 0x00000000);
2530 /* XXX : not implemented */
2531 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2532 SPR_NOACCESS, SPR_NOACCESS,
2533 &spr_read_generic, &spr_write_generic,
2534 0x00000000);
2535 /* XXX : not implemented */
2536 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2537 SPR_NOACCESS, SPR_NOACCESS,
2538 &spr_read_generic, &spr_write_generic,
2539 0x00000000);
2540 /* XXX : not implemented */
2541 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2542 SPR_NOACCESS, SPR_NOACCESS,
2543 &spr_read_generic, &spr_write_generic,
2544 0x00000000);
2545 /* XXX : not implemented */
2546 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2547 SPR_NOACCESS, SPR_NOACCESS,
2548 &spr_read_generic, &spr_write_generic,
2549 0x00000000);
2550 /* XXX : not implemented */
2551 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2552 SPR_NOACCESS, SPR_NOACCESS,
2553 &spr_read_generic, &spr_write_generic,
2554 0x00000000);
2555 /* XXX : not implemented */
2556 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2557 SPR_NOACCESS, SPR_NOACCESS,
2558 &spr_read_generic, &spr_write_generic,
2559 0x00000000);
2560 }
2561
2562 static void gen_spr_8xx (CPUPPCState *env)
2563 {
2564 /* XXX : not implemented */
2565 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2566 SPR_NOACCESS, SPR_NOACCESS,
2567 &spr_read_generic, &spr_write_generic,
2568 0x00000000);
2569 /* XXX : not implemented */
2570 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2571 SPR_NOACCESS, SPR_NOACCESS,
2572 &spr_read_generic, &spr_write_generic,
2573 0x00000000);
2574 /* XXX : not implemented */
2575 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2576 SPR_NOACCESS, SPR_NOACCESS,
2577 &spr_read_generic, &spr_write_generic,
2578 0x00000000);
2579 /* XXX : not implemented */
2580 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2581 SPR_NOACCESS, SPR_NOACCESS,
2582 &spr_read_generic, &spr_write_generic,
2583 0x00000000);
2584 /* XXX : not implemented */
2585 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2586 SPR_NOACCESS, SPR_NOACCESS,
2587 &spr_read_generic, &spr_write_generic,
2588 0x00000000);
2589 /* XXX : not implemented */
2590 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2591 SPR_NOACCESS, SPR_NOACCESS,
2592 &spr_read_generic, &spr_write_generic,
2593 0x00000000);
2594 /* XXX : not implemented */
2595 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2596 SPR_NOACCESS, SPR_NOACCESS,
2597 &spr_read_generic, &spr_write_generic,
2598 0x00000000);
2599 /* XXX : not implemented */
2600 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2601 SPR_NOACCESS, SPR_NOACCESS,
2602 &spr_read_generic, &spr_write_generic,
2603 0x00000000);
2604 /* XXX : not implemented */
2605 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2606 SPR_NOACCESS, SPR_NOACCESS,
2607 &spr_read_generic, &spr_write_generic,
2608 0x00000000);
2609 /* XXX : not implemented */
2610 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2611 SPR_NOACCESS, SPR_NOACCESS,
2612 &spr_read_generic, &spr_write_generic,
2613 0x00000000);
2614 /* XXX : not implemented */
2615 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2616 SPR_NOACCESS, SPR_NOACCESS,
2617 &spr_read_generic, &spr_write_generic,
2618 0x00000000);
2619 /* XXX : not implemented */
2620 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2621 SPR_NOACCESS, SPR_NOACCESS,
2622 &spr_read_generic, &spr_write_generic,
2623 0x00000000);
2624 /* XXX : not implemented */
2625 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2626 SPR_NOACCESS, SPR_NOACCESS,
2627 &spr_read_generic, &spr_write_generic,
2628 0x00000000);
2629 /* XXX : not implemented */
2630 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2631 SPR_NOACCESS, SPR_NOACCESS,
2632 &spr_read_generic, &spr_write_generic,
2633 0x00000000);
2634 /* XXX : not implemented */
2635 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2636 SPR_NOACCESS, SPR_NOACCESS,
2637 &spr_read_generic, &spr_write_generic,
2638 0x00000000);
2639 /* XXX : not implemented */
2640 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2641 SPR_NOACCESS, SPR_NOACCESS,
2642 &spr_read_generic, &spr_write_generic,
2643 0x00000000);
2644 /* XXX : not implemented */
2645 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2646 SPR_NOACCESS, SPR_NOACCESS,
2647 &spr_read_generic, &spr_write_generic,
2648 0x00000000);
2649 /* XXX : not implemented */
2650 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2651 SPR_NOACCESS, SPR_NOACCESS,
2652 &spr_read_generic, &spr_write_generic,
2653 0x00000000);
2654 /* XXX : not implemented */
2655 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2656 SPR_NOACCESS, SPR_NOACCESS,
2657 &spr_read_generic, &spr_write_generic,
2658 0x00000000);
2659 /* XXX : not implemented */
2660 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2661 SPR_NOACCESS, SPR_NOACCESS,
2662 &spr_read_generic, &spr_write_generic,
2663 0x00000000);
2664 /* XXX : not implemented */
2665 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2666 SPR_NOACCESS, SPR_NOACCESS,
2667 &spr_read_generic, &spr_write_generic,
2668 0x00000000);
2669 /* XXX : not implemented */
2670 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2671 SPR_NOACCESS, SPR_NOACCESS,
2672 &spr_read_generic, &spr_write_generic,
2673 0x00000000);
2674 /* XXX : not implemented */
2675 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2676 SPR_NOACCESS, SPR_NOACCESS,
2677 &spr_read_generic, &spr_write_generic,
2678 0x00000000);
2679 /* XXX : not implemented */
2680 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2681 SPR_NOACCESS, SPR_NOACCESS,
2682 &spr_read_generic, &spr_write_generic,
2683 0x00000000);
2684 /* XXX : not implemented */
2685 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2686 SPR_NOACCESS, SPR_NOACCESS,
2687 &spr_read_generic, &spr_write_generic,
2688 0x00000000);
2689 }
2690
2691 // XXX: TODO
2692 /*
2693 * AMR => SPR 29 (Power 2.04)
2694 * CTRL => SPR 136 (Power 2.04)
2695 * CTRL => SPR 152 (Power 2.04)
2696 * SCOMC => SPR 276 (64 bits ?)
2697 * SCOMD => SPR 277 (64 bits ?)
2698 * TBU40 => SPR 286 (Power 2.04 hypv)
2699 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2700 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2701 * HDSISR => SPR 306 (Power 2.04 hypv)
2702 * HDAR => SPR 307 (Power 2.04 hypv)
2703 * PURR => SPR 309 (Power 2.04 hypv)
2704 * HDEC => SPR 310 (Power 2.04 hypv)
2705 * HIOR => SPR 311 (hypv)
2706 * RMOR => SPR 312 (970)
2707 * HRMOR => SPR 313 (Power 2.04 hypv)
2708 * HSRR0 => SPR 314 (Power 2.04 hypv)
2709 * HSRR1 => SPR 315 (Power 2.04 hypv)
2710 * LPIDR => SPR 317 (970)
2711 * EPR => SPR 702 (Power 2.04 emb)
2712 * perf => 768-783 (Power 2.04)
2713 * perf => 784-799 (Power 2.04)
2714 * PPR => SPR 896 (Power 2.04)
2715 * EPLC => SPR 947 (Power 2.04 emb)
2716 * EPSC => SPR 948 (Power 2.04 emb)
2717 * DABRX => 1015 (Power 2.04 hypv)
2718 * FPECR => SPR 1022 (?)
2719 * ... and more (thermal management, performance counters, ...)
2720 */
2721
2722 /*****************************************************************************/
2723 /* Exception vectors models */
2724 static void init_excp_4xx_real (CPUPPCState *env)
2725 {
2726 #if !defined(CONFIG_USER_ONLY)
2727 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2728 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2729 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2730 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2731 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2732 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2733 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2734 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2735 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2736 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2737 env->ivor_mask = 0x0000FFF0UL;
2738 env->ivpr_mask = 0xFFFF0000UL;
2739 /* Hardware reset vector */
2740 env->hreset_vector = 0xFFFFFFFCUL;
2741 #endif
2742 }
2743
2744 static void init_excp_4xx_softmmu (CPUPPCState *env)
2745 {
2746 #if !defined(CONFIG_USER_ONLY)
2747 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2748 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2749 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2750 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2751 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2752 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2753 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2754 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2755 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2756 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2757 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2758 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2759 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2760 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2761 env->ivor_mask = 0x0000FFF0UL;
2762 env->ivpr_mask = 0xFFFF0000UL;
2763 /* Hardware reset vector */
2764 env->hreset_vector = 0xFFFFFFFCUL;
2765 #endif
2766 }
2767
2768 static void init_excp_MPC5xx (CPUPPCState *env)
2769 {
2770 #if !defined(CONFIG_USER_ONLY)
2771 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2772 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2773 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2774 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2775 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2776 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2777 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2778 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2779 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2780 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2781 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2782 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2783 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2784 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2785 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2786 env->ivor_mask = 0x0000FFF0UL;
2787 env->ivpr_mask = 0xFFFF0000UL;
2788 /* Hardware reset vector */
2789 env->hreset_vector = 0x00000100UL;
2790 #endif
2791 }
2792
2793 static void init_excp_MPC8xx (CPUPPCState *env)
2794 {
2795 #if !defined(CONFIG_USER_ONLY)
2796 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2797 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2798 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2799 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2800 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2801 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2802 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2803 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2804 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2805 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2806 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2807 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2808 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2809 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2810 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2811 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2812 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2813 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2814 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2815 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2816 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2817 env->ivor_mask = 0x0000FFF0UL;
2818 env->ivpr_mask = 0xFFFF0000UL;
2819 /* Hardware reset vector */
2820 env->hreset_vector = 0x00000100UL;
2821 #endif
2822 }
2823
2824 static void init_excp_G2 (CPUPPCState *env)
2825 {
2826 #if !defined(CONFIG_USER_ONLY)
2827 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2828 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2829 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2830 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2831 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2832 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2833 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2834 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2835 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2836 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2837 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2838 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2839 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2840 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2841 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2842 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2843 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2844 /* Hardware reset vector */
2845 env->hreset_vector = 0x00000100UL;
2846 #endif
2847 }
2848
2849 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2850 {
2851 #if !defined(CONFIG_USER_ONLY)
2852 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2853 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2861 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2862 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2863 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2864 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2865 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2866 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2867 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2868 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2869 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2870 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2871 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2872 env->ivor_mask = 0x0000FFF7UL;
2873 env->ivpr_mask = ivpr_mask;
2874 /* Hardware reset vector */
2875 env->hreset_vector = 0xFFFFFFFCUL;
2876 #endif
2877 }
2878
2879 static void init_excp_BookE (CPUPPCState *env)
2880 {
2881 #if !defined(CONFIG_USER_ONLY)
2882 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2883 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2884 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2885 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2886 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2887 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2888 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2889 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2890 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2891 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2892 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2893 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2894 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2895 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2896 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2897 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2898 env->ivor_mask = 0x0000FFF0UL;
2899 env->ivpr_mask = 0xFFFF0000UL;
2900 /* Hardware reset vector */
2901 env->hreset_vector = 0xFFFFFFFCUL;
2902 #endif
2903 }
2904
2905 static void init_excp_601 (CPUPPCState *env)
2906 {
2907 #if !defined(CONFIG_USER_ONLY)
2908 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2909 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2910 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2911 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2912 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2913 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2914 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2915 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2916 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2917 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2918 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2919 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2920 /* Hardware reset vector */
2921 env->hreset_vector = 0x00000100UL;
2922 #endif
2923 }
2924
2925 static void init_excp_602 (CPUPPCState *env)
2926 {
2927 #if !defined(CONFIG_USER_ONLY)
2928 /* XXX: exception prefix has a special behavior on 602 */
2929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2940 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2941 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2942 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2943 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2944 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2945 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2946 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2947 /* Hardware reset vector */
2948 env->hreset_vector = 0x00000100UL;
2949 #endif
2950 }
2951
2952 static void init_excp_603 (CPUPPCState *env)
2953 {
2954 #if !defined(CONFIG_USER_ONLY)
2955 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2956 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2957 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2958 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2959 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2960 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2961 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2962 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2963 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2964 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2965 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2966 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2967 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2968 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2969 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2970 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2971 /* Hardware reset vector */
2972 env->hreset_vector = 0x00000100UL;
2973 #endif
2974 }
2975
2976 static void init_excp_604 (CPUPPCState *env)
2977 {
2978 #if !defined(CONFIG_USER_ONLY)
2979 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2980 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2981 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2982 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2983 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2984 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2985 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2986 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2987 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2988 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2989 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2990 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2991 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2992 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2993 /* Hardware reset vector */
2994 env->hreset_vector = 0x00000100UL;
2995 #endif
2996 }
2997
2998 static void init_excp_7x0 (CPUPPCState *env)
2999 {
3000 #if !defined(CONFIG_USER_ONLY)
3001 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3002 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3003 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3004 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3005 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3006 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3007 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3008 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3009 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3010 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3011 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3012 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3013 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3014 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3015 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3016 /* Hardware reset vector */
3017 env->hreset_vector = 0x00000100UL;
3018 #endif
3019 }
3020
3021 static void init_excp_750cl (CPUPPCState *env)
3022 {
3023 #if !defined(CONFIG_USER_ONLY)
3024 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3025 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3026 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3027 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3028 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3030 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3031 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3032 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3033 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3034 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3035 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3036 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3037 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3038 /* Hardware reset vector */
3039 env->hreset_vector = 0x00000100UL;
3040 #endif
3041 }
3042
3043 static void init_excp_750cx (CPUPPCState *env)
3044 {
3045 #if !defined(CONFIG_USER_ONLY)
3046 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3047 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3048 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3049 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3050 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3051 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3052 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3053 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3054 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3055 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3056 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3057 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3058 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3059 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3060 /* Hardware reset vector */
3061 env->hreset_vector = 0x00000100UL;
3062 #endif
3063 }
3064
3065 /* XXX: Check if this is correct */
3066 static void init_excp_7x5 (CPUPPCState *env)
3067 {
3068 #if !defined(CONFIG_USER_ONLY)
3069 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3070 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3071 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3072 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3073 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3074 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3075 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3076 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3077 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3078 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3079 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3080 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3081 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3082 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3083 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3084 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3085 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3086 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3087 /* Hardware reset vector */
3088 env->hreset_vector = 0x00000100UL;
3089 #endif
3090 }
3091
3092 static void init_excp_7400 (CPUPPCState *env)
3093 {
3094 #if !defined(CONFIG_USER_ONLY)
3095 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3096 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3097 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3098 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3099 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3100 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3101 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3102 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3103 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3104 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3105 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3106 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3107 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3108 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3109 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3110 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3111 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3112 /* Hardware reset vector */
3113 env->hreset_vector = 0x00000100UL;
3114 #endif
3115 }
3116
3117 static void init_excp_7450 (CPUPPCState *env)
3118 {
3119 #if !defined(CONFIG_USER_ONLY)
3120 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3121 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3122 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3123 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3124 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3125 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3126 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3127 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3128 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3129 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3130 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3131 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3132 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3133 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3134 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3135 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3136 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3137 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3138 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3139 /* Hardware reset vector */
3140 env->hreset_vector = 0x00000100UL;
3141 #endif
3142 }
3143
3144 #if defined (TARGET_PPC64)
3145 static void init_excp_970 (CPUPPCState *env)
3146 {
3147 #if !defined(CONFIG_USER_ONLY)
3148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3149 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3150 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3151 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3152 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3153 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3154 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3155 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3156 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3157 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3158 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3159 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3160 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3161 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3162 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3163 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3164 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3165 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3166 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3167 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3168 /* Hardware reset vector */
3169 env->hreset_vector = 0x0000000000000100ULL;
3170 #endif
3171 }
3172
3173 static void init_excp_POWER7 (CPUPPCState *env)
3174 {
3175 #if !defined(CONFIG_USER_ONLY)
3176 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3177 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3178 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3179 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3180 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3181 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3182 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3183 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3184 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3185 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3186 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3187 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3188 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3189 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3190 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3191 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3192 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3193 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
3194 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3195 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3196 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3197 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3198 /* Hardware reset vector */
3199 env->hreset_vector = 0x0000000000000100ULL;
3200 #endif
3201 }
3202 #endif
3203
3204 /*****************************************************************************/
3205 /* Power management enable checks */
3206 static int check_pow_none (CPUPPCState *env)
3207 {
3208 return 0;
3209 }
3210
3211 static int check_pow_nocheck (CPUPPCState *env)
3212 {
3213 return 1;
3214 }
3215
3216 static int check_pow_hid0 (CPUPPCState *env)
3217 {
3218 if (env->spr[SPR_HID0] & 0x00E00000)
3219 return 1;
3220
3221 return 0;
3222 }
3223
3224 static int check_pow_hid0_74xx (CPUPPCState *env)
3225 {
3226 if (env->spr[SPR_HID0] & 0x00600000)
3227 return 1;
3228
3229 return 0;
3230 }
3231
3232 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3233 {
3234 return true;
3235 }
3236
3237 #ifdef TARGET_PPC64
3238 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3239 {
3240 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3241 }
3242 #endif
3243
3244 /*****************************************************************************/
3245 /* PowerPC implementations definitions */
3246
3247 #define POWERPC_FAMILY(_name) \
3248 static void \
3249 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3250 \
3251 static const TypeInfo \
3252 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3253 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3254 .parent = TYPE_POWERPC_CPU, \
3255 .abstract = true, \
3256 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3257 }; \
3258 \
3259 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3260 { \
3261 type_register_static( \
3262 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3263 } \
3264 \
3265 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3266 \
3267 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3268
3269 static void init_proc_401 (CPUPPCState *env)
3270 {
3271 gen_spr_40x(env);
3272 gen_spr_401_403(env);
3273 gen_spr_401(env);
3274 init_excp_4xx_real(env);
3275 env->dcache_line_size = 32;
3276 env->icache_line_size = 32;
3277 /* Allocate hardware IRQ controller */
3278 ppc40x_irq_init(env);
3279
3280 SET_FIT_PERIOD(12, 16, 20, 24);
3281 SET_WDT_PERIOD(16, 20, 24, 28);
3282 }
3283
3284 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3285 {
3286 DeviceClass *dc = DEVICE_CLASS(oc);
3287 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3288
3289 dc->desc = "PowerPC 401";
3290 pcc->init_proc = init_proc_401;
3291 pcc->check_pow = check_pow_nocheck;
3292 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3293 PPC_WRTEE | PPC_DCR |
3294 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3295 PPC_CACHE_DCBZ |
3296 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3297 PPC_4xx_COMMON | PPC_40x_EXCP;
3298 pcc->msr_mask = (1ull << MSR_KEY) |
3299 (1ull << MSR_POW) |
3300 (1ull << MSR_CE) |
3301 (1ull << MSR_ILE) |
3302 (1ull << MSR_EE) |
3303 (1ull << MSR_PR) |
3304 (1ull << MSR_ME) |
3305 (1ull << MSR_DE) |
3306 (1ull << MSR_LE);
3307 pcc->mmu_model = POWERPC_MMU_REAL;
3308 pcc->excp_model = POWERPC_EXCP_40x;
3309 pcc->bus_model = PPC_FLAGS_INPUT_401;
3310 pcc->bfd_mach = bfd_mach_ppc_403;
3311 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3312 POWERPC_FLAG_BUS_CLK;
3313 }
3314
3315 static void init_proc_401x2 (CPUPPCState *env)
3316 {
3317 gen_spr_40x(env);
3318 gen_spr_401_403(env);
3319 gen_spr_401x2(env);
3320 gen_spr_compress(env);
3321 /* Memory management */
3322 #if !defined(CONFIG_USER_ONLY)
3323 env->nb_tlb = 64;
3324 env->nb_ways = 1;
3325 env->id_tlbs = 0;
3326 env->tlb_type = TLB_EMB;
3327 #endif
3328 init_excp_4xx_softmmu(env);
3329 env->dcache_line_size = 32;
3330 env->icache_line_size = 32;
3331 /* Allocate hardware IRQ controller */
3332 ppc40x_irq_init(env);
3333
3334 SET_FIT_PERIOD(12, 16, 20, 24);
3335 SET_WDT_PERIOD(16, 20, 24, 28);
3336 }
3337
3338 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3339 {
3340 DeviceClass *dc = DEVICE_CLASS(oc);
3341 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3342
3343 dc->desc = "PowerPC 401x2";
3344 pcc->init_proc = init_proc_401x2;
3345 pcc->check_pow = check_pow_nocheck;
3346 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3347 PPC_DCR | PPC_WRTEE |
3348 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3349 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3350 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3351 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3352 PPC_4xx_COMMON | PPC_40x_EXCP;
3353 pcc->msr_mask = (1ull << 20) |
3354 (1ull << MSR_KEY) |
3355 (1ull << MSR_POW) |
3356 (1ull << MSR_CE) |
3357 (1ull << MSR_ILE) |
3358 (1ull << MSR_EE) |
3359 (1ull << MSR_PR) |
3360 (1ull << MSR_ME) |
3361 (1ull << MSR_DE) |
3362 (1ull << MSR_IR) |
3363 (1ull << MSR_DR) |
3364 (1ull << MSR_LE);
3365 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3366 pcc->excp_model = POWERPC_EXCP_40x;
3367 pcc->bus_model = PPC_FLAGS_INPUT_401;
3368 pcc->bfd_mach = bfd_mach_ppc_403;
3369 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3370 POWERPC_FLAG_BUS_CLK;
3371 }
3372
3373 static void init_proc_401x3 (CPUPPCState *env)
3374 {
3375 gen_spr_40x(env);
3376 gen_spr_401_403(env);
3377 gen_spr_401(env);
3378 gen_spr_401x2(env);
3379 gen_spr_compress(env);
3380 init_excp_4xx_softmmu(env);
3381 env->dcache_line_size = 32;
3382 env->icache_line_size = 32;
3383 /* Allocate hardware IRQ controller */
3384 ppc40x_irq_init(env);
3385
3386 SET_FIT_PERIOD(12, 16, 20, 24);
3387 SET_WDT_PERIOD(16, 20, 24, 28);
3388 }
3389
3390 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3391 {
3392 DeviceClass *dc = DEVICE_CLASS(oc);
3393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3394
3395 dc->desc = "PowerPC 401x3";
3396 pcc->init_proc = init_proc_401x3;
3397 pcc->check_pow = check_pow_nocheck;
3398 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3399 PPC_DCR | PPC_WRTEE |
3400 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3401 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3402 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3403 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3404 PPC_4xx_COMMON | PPC_40x_EXCP;
3405 pcc->msr_mask = (1ull << 20) |
3406 (1ull << MSR_KEY) |
3407 (1ull << MSR_POW) |
3408 (1ull << MSR_CE) |
3409 (1ull << MSR_ILE) |
3410 (1ull << MSR_EE) |
3411 (1ull << MSR_PR) |
3412 (1ull << MSR_ME) |
3413 (1ull << MSR_DWE) |
3414 (1ull << MSR_DE) |
3415 (1ull << MSR_IR) |
3416 (1ull << MSR_DR) |
3417 (1ull << MSR_LE);
3418 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3419 pcc->excp_model = POWERPC_EXCP_40x;
3420 pcc->bus_model = PPC_FLAGS_INPUT_401;
3421 pcc->bfd_mach = bfd_mach_ppc_403;
3422 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3423 POWERPC_FLAG_BUS_CLK;
3424 }
3425
3426 static void init_proc_IOP480 (CPUPPCState *env)
3427 {
3428 gen_spr_40x(env);
3429 gen_spr_401_403(env);
3430 gen_spr_401x2(env);
3431 gen_spr_compress(env);
3432 /* Memory management */
3433 #if !defined(CONFIG_USER_ONLY)
3434 env->nb_tlb = 64;
3435 env->nb_ways = 1;
3436 env->id_tlbs = 0;
3437 env->tlb_type = TLB_EMB;
3438 #endif
3439 init_excp_4xx_softmmu(env);
3440 env->dcache_line_size = 32;
3441 env->icache_line_size = 32;
3442 /* Allocate hardware IRQ controller */
3443 ppc40x_irq_init(env);
3444
3445 SET_FIT_PERIOD(8, 12, 16, 20);
3446 SET_WDT_PERIOD(16, 20, 24, 28);
3447 }
3448
3449 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3450 {
3451 DeviceClass *dc = DEVICE_CLASS(oc);
3452 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3453
3454 dc->desc = "IOP480";
3455 pcc->init_proc = init_proc_IOP480;
3456 pcc->check_pow = check_pow_nocheck;
3457 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3458 PPC_DCR | PPC_WRTEE |
3459 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3460 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3461 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3462 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3463 PPC_4xx_COMMON | PPC_40x_EXCP;
3464 pcc->msr_mask = (1ull << 20) |
3465 (1ull << MSR_KEY) |
3466 (1ull << MSR_POW) |
3467 (1ull << MSR_CE) |
3468 (1ull << MSR_ILE) |
3469 (1ull << MSR_EE) |
3470 (1ull << MSR_PR) |
3471 (1ull << MSR_ME) |
3472 (1ull << MSR_DE) |
3473 (1ull << MSR_IR) |
3474 (1ull << MSR_DR) |
3475 (1ull << MSR_LE);
3476 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3477 pcc->excp_model = POWERPC_EXCP_40x;
3478 pcc->bus_model = PPC_FLAGS_INPUT_401;
3479 pcc->bfd_mach = bfd_mach_ppc_403;
3480 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3481 POWERPC_FLAG_BUS_CLK;
3482 }
3483
3484 static void init_proc_403 (CPUPPCState *env)
3485 {
3486 gen_spr_40x(env);
3487 gen_spr_401_403(env);
3488 gen_spr_403(env);
3489 gen_spr_403_real(env);
3490 init_excp_4xx_real(env);
3491 env->dcache_line_size = 32;
3492 env->icache_line_size = 32;
3493 /* Allocate hardware IRQ controller */
3494 ppc40x_irq_init(env);
3495
3496 SET_FIT_PERIOD(8, 12, 16, 20);
3497 SET_WDT_PERIOD(16, 20, 24, 28);
3498 }
3499
3500 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3501 {
3502 DeviceClass *dc = DEVICE_CLASS(oc);
3503 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3504
3505 dc->desc = "PowerPC 403";
3506 pcc->init_proc = init_proc_403;
3507 pcc->check_pow = check_pow_nocheck;
3508 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3509 PPC_DCR | PPC_WRTEE |
3510 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3511 PPC_CACHE_DCBZ |
3512 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3513 PPC_4xx_COMMON | PPC_40x_EXCP;
3514 pcc->msr_mask = (1ull << MSR_POW) |
3515 (1ull << MSR_CE) |
3516 (1ull << MSR_ILE) |
3517 (1ull << MSR_EE) |
3518 (1ull << MSR_PR) |
3519 (1ull << MSR_ME) |
3520 (1ull << MSR_PE) |
3521 (1ull << MSR_PX) |
3522 (1ull << MSR_LE);
3523 pcc->mmu_model = POWERPC_MMU_REAL;
3524 pcc->excp_model = POWERPC_EXCP_40x;
3525 pcc->bus_model = PPC_FLAGS_INPUT_401;
3526 pcc->bfd_mach = bfd_mach_ppc_403;
3527 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3528 POWERPC_FLAG_BUS_CLK;
3529 }
3530
3531 static void init_proc_403GCX (CPUPPCState *env)
3532 {
3533 gen_spr_40x(env);
3534 gen_spr_401_403(env);
3535 gen_spr_403(env);
3536 gen_spr_403_real(env);
3537 gen_spr_403_mmu(env);
3538 /* Bus access control */
3539 /* not emulated, as QEMU never does speculative access */
3540 spr_register(env, SPR_40x_SGR, "SGR",
3541 SPR_NOACCESS, SPR_NOACCESS,
3542 &spr_read_generic, &spr_write_generic,
3543 0xFFFFFFFF);
3544 /* not emulated, as QEMU do not emulate caches */
3545 spr_register(env, SPR_40x_DCWR, "DCWR",
3546 SPR_NOACCESS, SPR_NOACCESS,
3547 &spr_read_generic, &spr_write_generic,
3548 0x00000000);
3549 /* Memory management */
3550 #if !defined(CONFIG_USER_ONLY)
3551 env->nb_tlb = 64;
3552 env->nb_ways = 1;
3553 env->id_tlbs = 0;
3554 env->tlb_type = TLB_EMB;
3555 #endif
3556 init_excp_4xx_softmmu(env);
3557 env->dcache_line_size = 32;
3558 env->icache_line_size = 32;
3559 /* Allocate hardware IRQ controller */
3560 ppc40x_irq_init(env);
3561
3562 SET_FIT_PERIOD(8, 12, 16, 20);
3563 SET_WDT_PERIOD(16, 20, 24, 28);
3564 }
3565
3566 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3567 {
3568 DeviceClass *dc = DEVICE_CLASS(oc);
3569 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3570
3571 dc->desc = "PowerPC 403 GCX";
3572 pcc->init_proc = init_proc_403GCX;
3573 pcc->check_pow = check_pow_nocheck;
3574 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3575 PPC_DCR | PPC_WRTEE |
3576 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3577 PPC_CACHE_DCBZ |
3578 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3579 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3580 PPC_4xx_COMMON | PPC_40x_EXCP;
3581 pcc->msr_mask = (1ull << MSR_POW) |
3582 (1ull << MSR_CE) |
3583 (1ull << MSR_ILE) |
3584 (1ull << MSR_EE) |
3585 (1ull << MSR_PR) |
3586 (1ull << MSR_ME) |
3587 (1ull << MSR_PE) |
3588 (1ull << MSR_PX) |
3589 (1ull << MSR_LE);
3590 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3591 pcc->excp_model = POWERPC_EXCP_40x;
3592 pcc->bus_model = PPC_FLAGS_INPUT_401;
3593 pcc->bfd_mach = bfd_mach_ppc_403;
3594 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3595 POWERPC_FLAG_BUS_CLK;
3596 }
3597
3598 static void init_proc_405 (CPUPPCState *env)
3599 {
3600 /* Time base */
3601 gen_tbl(env);
3602 gen_spr_40x(env);
3603 gen_spr_405(env);
3604 /* Bus access control */
3605 /* not emulated, as QEMU never does speculative access */
3606 spr_register(env, SPR_40x_SGR, "SGR",
3607 SPR_NOACCESS, SPR_NOACCESS,
3608 &spr_read_generic, &spr_write_generic,
3609 0xFFFFFFFF);
3610 /* not emulated, as QEMU do not emulate caches */
3611 spr_register(env, SPR_40x_DCWR, "DCWR",
3612 SPR_NOACCESS, SPR_NOACCESS,
3613 &spr_read_generic, &spr_write_generic,
3614 0x00000000);
3615 /* Memory management */
3616 #if !defined(CONFIG_USER_ONLY)
3617 env->nb_tlb = 64;
3618 env->nb_ways = 1;
3619 env->id_tlbs = 0;
3620 env->tlb_type = TLB_EMB;
3621 #endif
3622 init_excp_4xx_softmmu(env);
3623 env->dcache_line_size = 32;
3624 env->icache_line_size = 32;
3625 /* Allocate hardware IRQ controller */
3626 ppc40x_irq_init(env);
3627
3628 SET_FIT_PERIOD(8, 12, 16, 20);
3629 SET_WDT_PERIOD(16, 20, 24, 28);
3630 }
3631
3632 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3633 {
3634 DeviceClass *dc = DEVICE_CLASS(oc);
3635 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3636
3637 dc->desc = "PowerPC 405";
3638 pcc->init_proc = init_proc_405;
3639 pcc->check_pow = check_pow_nocheck;
3640 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3641 PPC_DCR | PPC_WRTEE |
3642 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3643 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3644 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3645 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3646 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3647 pcc->msr_mask = (1ull << MSR_POW) |
3648 (1ull << MSR_CE) |
3649 (1ull << MSR_EE) |
3650 (1ull << MSR_PR) |
3651 (1ull << MSR_FP) |
3652 (1ull << MSR_DWE) |
3653 (1ull << MSR_DE) |
3654 (1ull << MSR_IR) |
3655 (1ull << MSR_DR);
3656 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3657 pcc->excp_model = POWERPC_EXCP_40x;
3658 pcc->bus_model = PPC_FLAGS_INPUT_405;
3659 pcc->bfd_mach = bfd_mach_ppc_403;
3660 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3661 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3662 }
3663
3664 static void init_proc_440EP (CPUPPCState *env)
3665 {
3666 /* Time base */
3667 gen_tbl(env);
3668 gen_spr_BookE(env, 0x000000000000FFFFULL);
3669 gen_spr_440(env);
3670 gen_spr_usprgh(env);
3671 /* Processor identification */
3672 spr_register(env, SPR_BOOKE_PIR, "PIR",
3673 SPR_NOACCESS, SPR_NOACCESS,
3674 &spr_read_generic, &spr_write_pir,
3675 0x00000000);
3676 /* XXX : not implemented */
3677 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3678 SPR_NOACCESS, SPR_NOACCESS,
3679 &spr_read_generic, &spr_write_generic,
3680 0x00000000);
3681 /* XXX : not implemented */
3682 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3683 SPR_NOACCESS, SPR_NOACCESS,
3684 &spr_read_generic, &spr_write_generic,
3685 0x00000000);
3686 /* XXX : not implemented */
3687 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3688 SPR_NOACCESS, SPR_NOACCESS,
3689 &spr_read_generic, &spr_write_generic,
3690 0x00000000);
3691 /* XXX : not implemented */
3692 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3693 SPR_NOACCESS, SPR_NOACCESS,
3694 &spr_read_generic, &spr_write_generic,
3695 0x00000000);
3696 /* XXX : not implemented */
3697 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3698 SPR_NOACCESS, SPR_NOACCESS,
3699 &spr_read_generic, &spr_write_generic,
3700 0x00000000);
3701 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3702 SPR_NOACCESS, SPR_NOACCESS,
3703 &spr_read_generic, &spr_write_generic,
3704 0x00000000);
3705 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3706 SPR_NOACCESS, SPR_NOACCESS,
3707 &spr_read_generic, &spr_write_generic,
3708 0x00000000);
3709 /* XXX : not implemented */
3710 spr_register(env, SPR_440_CCR1, "CCR1",
3711 SPR_NOACCESS, SPR_NOACCESS,
3712 &spr_read_generic, &spr_write_generic,
3713 0x00000000);
3714 /* Memory management */
3715 #if !defined(CONFIG_USER_ONLY)
3716 env->nb_tlb = 64;
3717 env->nb_ways = 1;
3718 env->id_tlbs = 0;
3719 env->tlb_type = TLB_EMB;
3720 #endif
3721 init_excp_BookE(env);
3722 env->dcache_line_size = 32;
3723 env->icache_line_size = 32;
3724 ppc40x_irq_init(env);
3725
3726 SET_FIT_PERIOD(12, 16, 20, 24);
3727 SET_WDT_PERIOD(20, 24, 28, 32);
3728 }
3729
3730 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3731 {
3732 DeviceClass *dc = DEVICE_CLASS(oc);
3733 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3734
3735 dc->desc = "PowerPC 440 EP";
3736 pcc->init_proc = init_proc_440EP;
3737 pcc->check_pow = check_pow_nocheck;
3738 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3739 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3740 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3741 PPC_FLOAT_STFIWX |
3742 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3743 PPC_CACHE | PPC_CACHE_ICBI |
3744 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3745 PPC_MEM_TLBSYNC | PPC_MFTB |
3746 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3747 PPC_440_SPEC;
3748 pcc->msr_mask = (1ull << MSR_POW) |
3749 (1ull << MSR_CE) |
3750 (1ull << MSR_EE) |
3751 (1ull << MSR_PR) |
3752 (1ull << MSR_FP) |
3753 (1ull << MSR_ME) |
3754 (1ull << MSR_FE0) |
3755 (1ull << MSR_DWE) |
3756 (1ull << MSR_DE) |
3757 (1ull << MSR_FE1) |
3758 (1ull << MSR_IR) |
3759 (1ull << MSR_DR);
3760 pcc->mmu_model = POWERPC_MMU_BOOKE;
3761 pcc->excp_model = POWERPC_EXCP_BOOKE;
3762 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3763 pcc->bfd_mach = bfd_mach_ppc_403;
3764 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3765 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3766 }
3767
3768 static void init_proc_440GP (CPUPPCState *env)
3769 {
3770 /* Time base */
3771 gen_tbl(env);
3772 gen_spr_BookE(env, 0x000000000000FFFFULL);
3773 gen_spr_440(env);
3774 gen_spr_usprgh(env);
3775 /* Processor identification */
3776 spr_register(env, SPR_BOOKE_PIR, "PIR",
3777 SPR_NOACCESS, SPR_NOACCESS,
3778 &spr_read_generic, &spr_write_pir,
3779 0x00000000);
3780 /* XXX : not implemented */
3781 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3782 SPR_NOACCESS, SPR_NOACCESS,
3783 &spr_read_generic, &spr_write_generic,
3784 0x00000000);
3785 /* XXX : not implemented */
3786 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3787 SPR_NOACCESS, SPR_NOACCESS,
3788 &spr_read_generic, &spr_write_generic,
3789 0x00000000);
3790 /* XXX : not implemented */
3791 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3792 SPR_NOACCESS, SPR_NOACCESS,
3793 &spr_read_generic, &spr_write_generic,
3794 0x00000000);
3795 /* XXX : not implemented */
3796 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3797 SPR_NOACCESS, SPR_NOACCESS,
3798 &spr_read_generic, &spr_write_generic,
3799 0x00000000);
3800 /* Memory management */
3801 #if !defined(CONFIG_USER_ONLY)
3802 env->nb_tlb = 64;
3803 env->nb_ways = 1;
3804 env->id_tlbs = 0;
3805 env->tlb_type = TLB_EMB;
3806 #endif
3807 init_excp_BookE(env);
3808 env->dcache_line_size = 32;
3809 env->icache_line_size = 32;
3810 /* XXX: TODO: allocate internal IRQ controller */
3811
3812 SET_FIT_PERIOD(12, 16, 20, 24);
3813 SET_WDT_PERIOD(20, 24, 28, 32);
3814 }
3815
3816 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3817 {
3818 DeviceClass *dc = DEVICE_CLASS(oc);
3819 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3820
3821 dc->desc = "PowerPC 440 GP";
3822 pcc->init_proc = init_proc_440GP;
3823 pcc->check_pow = check_pow_nocheck;
3824 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3825 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3826 PPC_CACHE | PPC_CACHE_ICBI |
3827 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3828 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3829 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3830 PPC_440_SPEC;
3831 pcc->msr_mask = (1ull << MSR_POW) |
3832 (1ull << MSR_CE) |
3833 (1ull << MSR_EE) |
3834 (1ull << MSR_PR) |
3835 (1ull << MSR_FP) |
3836 (1ull << MSR_ME) |
3837 (1ull << MSR_FE0) |
3838 (1ull << MSR_DWE) |
3839 (1ull << MSR_DE) |
3840 (1ull << MSR_FE1) |
3841 (1ull << MSR_IR) |
3842 (1ull << MSR_DR);
3843 pcc->mmu_model = POWERPC_MMU_BOOKE;
3844 pcc->excp_model = POWERPC_EXCP_BOOKE;
3845 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3846 pcc->bfd_mach = bfd_mach_ppc_403;
3847 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3848 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3849 }
3850
3851 static void init_proc_440x4 (CPUPPCState *env)
3852 {
3853 /* Time base */
3854 gen_tbl(env);
3855 gen_spr_BookE(env, 0x000000000000FFFFULL);
3856 gen_spr_440(env);
3857 gen_spr_usprgh(env);
3858 /* Processor identification */
3859 spr_register(env, SPR_BOOKE_PIR, "PIR",
3860 SPR_NOACCESS, SPR_NOACCESS,
3861 &spr_read_generic, &spr_write_pir,
3862 0x00000000);
3863 /* XXX : not implemented */
3864 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3865 SPR_NOACCESS, SPR_NOACCESS,
3866 &spr_read_generic, &spr_write_generic,
3867 0x00000000);
3868 /* XXX : not implemented */
3869 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3870 SPR_NOACCESS, SPR_NOACCESS,
3871 &spr_read_generic, &spr_write_generic,
3872 0x00000000);
3873 /* XXX : not implemented */
3874 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3875 SPR_NOACCESS, SPR_NOACCESS,
3876 &spr_read_generic, &spr_write_generic,
3877 0x00000000);
3878 /* XXX : not implemented */
3879 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3880 SPR_NOACCESS, SPR_NOACCESS,
3881 &spr_read_generic, &spr_write_generic,
3882 0x00000000);
3883 /* Memory management */
3884 #if !defined(CONFIG_USER_ONLY)
3885 env->nb_tlb = 64;
3886 env->nb_ways = 1;
3887 env->id_tlbs = 0;
3888 env->tlb_type = TLB_EMB;
3889 #endif
3890 init_excp_BookE(env);
3891 env->dcache_line_size = 32;
3892 env->icache_line_size = 32;
3893 /* XXX: TODO: allocate internal IRQ controller */
3894
3895 SET_FIT_PERIOD(12, 16, 20, 24);
3896 SET_WDT_PERIOD(20, 24, 28, 32);
3897 }
3898
3899 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3900 {
3901 DeviceClass *dc = DEVICE_CLASS(oc);
3902 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3903
3904 dc->desc = "PowerPC 440x4";
3905 pcc->init_proc = init_proc_440x4;
3906 pcc->check_pow = check_pow_nocheck;
3907 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3908 PPC_DCR | PPC_WRTEE |
3909 PPC_CACHE | PPC_CACHE_ICBI |
3910 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3911 PPC_MEM_TLBSYNC | PPC_MFTB |
3912 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3913 PPC_440_SPEC;
3914 pcc->msr_mask = (1ull << MSR_POW) |
3915 (1ull << MSR_CE) |
3916 (1ull << MSR_EE) |
3917 (1ull << MSR_PR) |
3918 (1ull << MSR_FP) |
3919 (1ull << MSR_ME) |
3920 (1ull << MSR_FE0) |
3921 (1ull << MSR_DWE) |
3922 (1ull << MSR_DE) |
3923 (1ull << MSR_FE1) |
3924 (1ull << MSR_IR) |
3925 (1ull << MSR_DR);
3926 pcc->mmu_model = POWERPC_MMU_BOOKE;
3927 pcc->excp_model = POWERPC_EXCP_BOOKE;
3928 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3929 pcc->bfd_mach = bfd_mach_ppc_403;
3930 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3931 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3932 }
3933
3934 static void init_proc_440x5 (CPUPPCState *env)
3935 {
3936 /* Time base */
3937 gen_tbl(env);
3938 gen_spr_BookE(env, 0x000000000000FFFFULL);
3939 gen_spr_440(env);
3940 gen_spr_usprgh(env);
3941 /* Processor identification */
3942 spr_register(env, SPR_BOOKE_PIR, "PIR",
3943 SPR_NOACCESS, SPR_NOACCESS,
3944 &spr_read_generic, &spr_write_pir,
3945 0x00000000);
3946 /* XXX : not implemented */
3947 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3948 SPR_NOACCESS, SPR_NOACCESS,
3949 &spr_read_generic, &spr_write_generic,
3950 0x00000000);
3951 /* XXX : not implemented */
3952 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3953 SPR_NOACCESS, SPR_NOACCESS,
3954 &spr_read_generic, &spr_write_generic,
3955 0x00000000);
3956 /* XXX : not implemented */
3957 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3958 SPR_NOACCESS, SPR_NOACCESS,
3959 &spr_read_generic, &spr_write_generic,
3960 0x00000000);
3961 /* XXX : not implemented */
3962 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3963 SPR_NOACCESS, SPR_NOACCESS,
3964 &spr_read_generic, &spr_write_generic,
3965 0x00000000);
3966 /* XXX : not implemented */
3967 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3968 SPR_NOACCESS, SPR_NOACCESS,
3969 &spr_read_generic, &spr_write_generic,
3970 0x00000000);
3971 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3972 SPR_NOACCESS, SPR_NOACCESS,
3973 &spr_read_generic, &spr_write_generic,
3974 0x00000000);
3975 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* XXX : not implemented */
3980 spr_register(env, SPR_440_CCR1, "CCR1",
3981 SPR_NOACCESS, SPR_NOACCESS,
3982 &spr_read_generic, &spr_write_generic,
3983 0x00000000);
3984 /* Memory management */
3985 #if !defined(CONFIG_USER_ONLY)
3986 env->nb_tlb = 64;
3987 env->nb_ways = 1;
3988 env->id_tlbs = 0;
3989 env->tlb_type = TLB_EMB;
3990 #endif
3991 init_excp_BookE(env);
3992 env->dcache_line_size = 32;
3993 env->icache_line_size = 32;
3994 ppc40x_irq_init(env);
3995
3996 SET_FIT_PERIOD(12, 16, 20, 24);
3997 SET_WDT_PERIOD(20, 24, 28, 32);
3998 }
3999
4000 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4001 {
4002 DeviceClass *dc = DEVICE_CLASS(oc);
4003 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4004
4005 dc->desc = "PowerPC 440x5";
4006 pcc->init_proc = init_proc_440x5;
4007 pcc->check_pow = check_pow_nocheck;
4008 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4009 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4010 PPC_CACHE | PPC_CACHE_ICBI |
4011 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4012 PPC_MEM_TLBSYNC | PPC_MFTB |
4013 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4014 PPC_440_SPEC;
4015 pcc->msr_mask = (1ull << MSR_POW) |
4016 (1ull << MSR_CE) |
4017 (1ull << MSR_EE) |
4018 (1ull << MSR_PR) |
4019 (1ull << MSR_FP) |
4020 (1ull << MSR_ME) |
4021 (1ull << MSR_FE0) |
4022 (1ull << MSR_DWE) |
4023 (1ull << MSR_DE) |
4024 (1ull << MSR_FE1) |
4025 (1ull << MSR_IR) |
4026 (1ull << MSR_DR);
4027 pcc->mmu_model = POWERPC_MMU_BOOKE;
4028 pcc->excp_model = POWERPC_EXCP_BOOKE;
4029 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4030 pcc->bfd_mach = bfd_mach_ppc_403;
4031 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4032 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4033 }
4034
4035 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4036 {
4037 DeviceClass *dc = DEVICE_CLASS(oc);
4038 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4039
4040 dc->desc = "PowerPC 440x5 with double precision FPU";
4041 pcc->init_proc = init_proc_440x5;
4042 pcc->check_pow = check_pow_nocheck;
4043 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4044 PPC_FLOAT | PPC_FLOAT_FSQRT |
4045 PPC_FLOAT_STFIWX |
4046 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4047 PPC_CACHE | PPC_CACHE_ICBI |
4048 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4049 PPC_MEM_TLBSYNC | PPC_MFTB |
4050 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4051 PPC_440_SPEC;
4052 pcc->insns_flags2 = PPC2_FP_CVT_S64;
4053 pcc->msr_mask = (1ull << MSR_POW) |
4054 (1ull << MSR_CE) |
4055 (1ull << MSR_EE) |
4056 (1ull << MSR_PR) |
4057 (1ull << MSR_FP) |
4058 (1ull << MSR_ME) |
4059 (1ull << MSR_FE0) |
4060 (1ull << MSR_DWE) |
4061 (1ull << MSR_DE) |
4062 (1ull << MSR_FE1) |
4063 (1ull << MSR_IR) |
4064 (1ull << MSR_DR);
4065 pcc->mmu_model = POWERPC_MMU_BOOKE;
4066 pcc->excp_model = POWERPC_EXCP_BOOKE;
4067 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4068 pcc->bfd_mach = bfd_mach_ppc_403;
4069 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4070 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4071 }
4072
4073 static void init_proc_460 (CPUPPCState *env)
4074 {
4075 /* Time base */
4076 gen_tbl(env);
4077 gen_spr_BookE(env, 0x000000000000FFFFULL);
4078 gen_spr_440(env);
4079 gen_spr_usprgh(env);
4080 /* Processor identification */
4081 spr_register(env, SPR_BOOKE_PIR, "PIR",
4082 SPR_NOACCESS, SPR_NOACCESS,
4083 &spr_read_generic, &spr_write_pir,
4084 0x00000000);
4085 /* XXX : not implemented */
4086 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4087 SPR_NOACCESS, SPR_NOACCESS,
4088 &spr_read_generic, &spr_write_generic,
4089 0x00000000);
4090 /* XXX : not implemented */
4091 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4092 SPR_NOACCESS, SPR_NOACCESS,
4093 &spr_read_generic, &spr_write_generic,
4094 0x00000000);
4095 /* XXX : not implemented */
4096 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 /* XXX : not implemented */
4101 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4102 SPR_NOACCESS, SPR_NOACCESS,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
4105 /* XXX : not implemented */
4106 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4107 SPR_NOACCESS, SPR_NOACCESS,
4108 &spr_read_generic, &spr_write_generic,
4109 0x00000000);
4110 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4111 SPR_NOACCESS, SPR_NOACCESS,
4112 &spr_read_generic, &spr_write_generic,
4113 0x00000000);
4114 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4115 SPR_NOACCESS, SPR_NOACCESS,
4116 &spr_read_generic, &spr_write_generic,
4117 0x00000000);
4118 /* XXX : not implemented */
4119 spr_register(env, SPR_440_CCR1, "CCR1",
4120 SPR_NOACCESS, SPR_NOACCESS,
4121 &spr_read_generic, &spr_write_generic,
4122 0x00000000);
4123 /* XXX : not implemented */
4124 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4125 &spr_read_generic, &spr_write_generic,
4126 &spr_read_generic, &spr_write_generic,
4127 0x00000000);
4128 /* Memory management */
4129 #if !defined(CONFIG_USER_ONLY)
4130 env->nb_tlb = 64;
4131 env->nb_ways = 1;
4132 env->id_tlbs = 0;
4133 env->tlb_type = TLB_EMB;
4134 #endif
4135 init_excp_BookE(env);
4136 env->dcache_line_size = 32;
4137 env->icache_line_size = 32;
4138 /* XXX: TODO: allocate internal IRQ controller */
4139
4140 SET_FIT_PERIOD(12, 16, 20, 24);
4141 SET_WDT_PERIOD(20, 24, 28, 32);
4142 }
4143
4144 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4145 {
4146 DeviceClass *dc = DEVICE_CLASS(oc);
4147 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4148
4149 dc->desc = "PowerPC 460 (guessed)";
4150 pcc->init_proc = init_proc_460;
4151 pcc->check_pow = check_pow_nocheck;
4152 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4153 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4154 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4155 PPC_CACHE | PPC_CACHE_ICBI |
4156 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4157 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4158 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4159 PPC_440_SPEC;
4160 pcc->msr_mask = (1ull << MSR_POW) |
4161 (1ull << MSR_CE) |
4162 (1ull << MSR_EE) |
4163 (1ull << MSR_PR) |
4164 (1ull << MSR_FP) |
4165 (1ull << MSR_ME) |
4166 (1ull << MSR_FE0) |
4167 (1ull << MSR_DWE) |
4168 (1ull << MSR_DE) |
4169 (1ull << MSR_FE1) |
4170 (1ull << MSR_IR) |
4171 (1ull << MSR_DR);
4172 pcc->mmu_model = POWERPC_MMU_BOOKE;
4173 pcc->excp_model = POWERPC_EXCP_BOOKE;
4174 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4175 pcc->bfd_mach = bfd_mach_ppc_403;
4176 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4177 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4178 }
4179
4180 static void init_proc_460F (CPUPPCState *env)
4181 {
4182 /* Time base */
4183 gen_tbl(env);
4184 gen_spr_BookE(env, 0x000000000000FFFFULL);
4185 gen_spr_440(env);
4186 gen_spr_usprgh(env);
4187 /* Processor identification */
4188 spr_register(env, SPR_BOOKE_PIR, "PIR",
4189 SPR_NOACCESS, SPR_NOACCESS,
4190 &spr_read_generic, &spr_write_pir,
4191 0x00000000);
4192 /* XXX : not implemented */
4193 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4194 SPR_NOACCESS, SPR_NOACCESS,
4195 &spr_read_generic, &spr_write_generic,
4196 0x00000000);
4197 /* XXX : not implemented */
4198 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4199 SPR_NOACCESS, SPR_NOACCESS,
4200 &spr_read_generic, &spr_write_generic,
4201 0x00000000);
4202 /* XXX : not implemented */
4203 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4204 SPR_NOACCESS, SPR_NOACCESS,
4205 &spr_read_generic, &spr_write_generic,
4206 0x00000000);
4207 /* XXX : not implemented */
4208 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4209 SPR_NOACCESS, SPR_NOACCESS,
4210 &spr_read_generic, &spr_write_generic,
4211 0x00000000);
4212 /* XXX : not implemented */
4213 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4214 SPR_NOACCESS, SPR_NOACCESS,
4215 &spr_read_generic, &spr_write_generic,
4216 0x00000000);
4217 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4218 SPR_NOACCESS, SPR_NOACCESS,
4219 &spr_read_generic, &spr_write_generic,
4220 0x00000000);
4221 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4222 SPR_NOACCESS, SPR_NOACCESS,
4223 &spr_read_generic, &spr_write_generic,
4224 0x00000000);
4225 /* XXX : not implemented */
4226 spr_register(env, SPR_440_CCR1, "CCR1",
4227 SPR_NOACCESS, SPR_NOACCESS,
4228 &spr_read_generic, &spr_write_generic,
4229 0x00000000);
4230 /* XXX : not implemented */
4231 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4232 &spr_read_generic, &spr_write_generic,
4233 &spr_read_generic, &spr_write_generic,
4234 0x00000000);
4235 /* Memory management */
4236 #if !defined(CONFIG_USER_ONLY)
4237 env->nb_tlb = 64;
4238 env->nb_ways = 1;
4239 env->id_tlbs = 0;
4240 env->tlb_type = TLB_EMB;
4241 #endif
4242 init_excp_BookE(env);
4243 env->dcache_line_size = 32;
4244 env->icache_line_size = 32;
4245 /* XXX: TODO: allocate internal IRQ controller */
4246
4247 SET_FIT_PERIOD(12, 16, 20, 24);
4248 SET_WDT_PERIOD(20, 24, 28, 32);
4249 }
4250
4251 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4252 {
4253 DeviceClass *dc = DEVICE_CLASS(oc);
4254 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4255
4256 dc->desc = "PowerPC 460F (guessed)";
4257 pcc->init_proc = init_proc_460F;
4258 pcc->check_pow = check_pow_nocheck;
4259 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4260 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4261 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4262 PPC_FLOAT_STFIWX | PPC_MFTB |
4263 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4264 PPC_WRTEE | PPC_MFAPIDI |
4265 PPC_CACHE | PPC_CACHE_ICBI |
4266 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4267 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4268 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4269 PPC_440_SPEC;
4270 pcc->msr_mask = (1ull << MSR_POW) |
4271 (1ull << MSR_CE) |
4272 (1ull << MSR_EE) |
4273 (1ull << MSR_PR) |
4274 (1ull << MSR_FP) |
4275 (1ull << MSR_ME) |
4276 (1ull << MSR_FE0) |
4277 (1ull << MSR_DWE) |
4278 (1ull << MSR_DE) |
4279 (1ull << MSR_FE1) |
4280 (1ull << MSR_IR) |
4281 (1ull << MSR_DR);
4282 pcc->mmu_model = POWERPC_MMU_BOOKE;
4283 pcc->excp_model = POWERPC_EXCP_BOOKE;
4284 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4285 pcc->bfd_mach = bfd_mach_ppc_403;
4286 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4287 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4288 }
4289
4290 static void init_proc_MPC5xx (CPUPPCState *env)
4291 {
4292 /* Time base */
4293 gen_tbl(env);
4294 gen_spr_5xx_8xx(env);
4295 gen_spr_5xx(env);
4296 init_excp_MPC5xx(env);
4297 env->dcache_line_size = 32;
4298 env->icache_line_size = 32;
4299 /* XXX: TODO: allocate internal IRQ controller */
4300 }
4301
4302 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4303 {
4304 DeviceClass *dc = DEVICE_CLASS(oc);
4305 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4306
4307 dc->desc = "Freescale 5xx cores (aka RCPU)";
4308 pcc->init_proc = init_proc_MPC5xx;
4309 pcc->check_pow = check_pow_none;
4310 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4311 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4312 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4313 PPC_MFTB;
4314 pcc->msr_mask = (1ull << MSR_ILE) |
4315 (1ull << MSR_EE) |
4316 (1ull << MSR_PR) |
4317 (1ull << MSR_FP) |
4318 (1ull << MSR_ME) |
4319 (1ull << MSR_FE0) |
4320 (1ull << MSR_SE) |
4321 (1ull << MSR_DE) |
4322 (1ull << MSR_FE1) |
4323 (1ull << MSR_EP) |
4324 (1ull << MSR_RI) |
4325 (1ull << MSR_LE);
4326 pcc->mmu_model = POWERPC_MMU_REAL;
4327 pcc->excp_model = POWERPC_EXCP_603;
4328 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4329 pcc->bfd_mach = bfd_mach_ppc_505;
4330 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4331 POWERPC_FLAG_BUS_CLK;
4332 }
4333
4334 static void init_proc_MPC8xx (CPUPPCState *env)
4335 {
4336 /* Time base */
4337 gen_tbl(env);
4338 gen_spr_5xx_8xx(env);
4339 gen_spr_8xx(env);
4340 init_excp_MPC8xx(env);
4341 env->dcache_line_size = 32;
4342 env->icache_line_size = 32;
4343 /* XXX: TODO: allocate internal IRQ controller */
4344 }
4345
4346 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4347 {
4348 DeviceClass *dc = DEVICE_CLASS(oc);
4349 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4350
4351 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4352 pcc->init_proc = init_proc_MPC8xx;
4353 pcc->check_pow = check_pow_none;
4354 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4355 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4356 PPC_CACHE_ICBI | PPC_MFTB;
4357 pcc->msr_mask = (1ull << MSR_ILE) |
4358 (1ull << MSR_EE) |
4359 (1ull << MSR_PR) |
4360 (1ull << MSR_FP) |
4361 (1ull << MSR_ME) |
4362 (1ull << MSR_SE) |
4363 (1ull << MSR_DE) |
4364 (1ull << MSR_EP) |
4365 (1ull << MSR_IR) |
4366 (1ull << MSR_DR) |
4367 (1ull << MSR_RI) |
4368 (1ull << MSR_LE);
4369 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4370 pcc->excp_model = POWERPC_EXCP_603;
4371 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4372 pcc->bfd_mach = bfd_mach_ppc_860;
4373 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4374 POWERPC_FLAG_BUS_CLK;
4375 }
4376
4377 /* Freescale 82xx cores (aka PowerQUICC-II) */
4378
4379 static void init_proc_G2 (CPUPPCState *env)
4380 {
4381 gen_spr_ne_601(env);
4382 gen_spr_G2_755(env);
4383 gen_spr_G2(env);
4384 /* Time base */
4385 gen_tbl(env);
4386 /* External access control */
4387 /* XXX : not implemented */
4388 spr_register(env, SPR_EAR, "EAR",
4389 SPR_NOACCESS, SPR_NOACCESS,
4390 &spr_read_generic, &spr_write_generic,
4391 0x00000000);
4392 /* Hardware implementation register */
4393 /* XXX : not implemented */
4394 spr_register(env, SPR_HID0, "HID0",
4395 SPR_NOACCESS, SPR_NOACCESS,
4396 &spr_read_generic, &spr_write_generic,
4397 0x00000000);
4398 /* XXX : not implemented */
4399 spr_register(env, SPR_HID1, "HID1",
4400 SPR_NOACCESS, SPR_NOACCESS,
4401 &spr_read_generic, &spr_write_generic,
4402 0x00000000);
4403 /* XXX : not implemented */
4404 spr_register(env, SPR_HID2, "HID2",
4405 SPR_NOACCESS, SPR_NOACCESS,
4406 &spr_read_generic, &spr_write_generic,
4407 0x00000000);
4408 /* Memory management */
4409 gen_low_BATs(env);
4410 gen_high_BATs(env);
4411 gen_6xx_7xx_soft_tlb(env, 64, 2);
4412 init_excp_G2(env);
4413 env->dcache_line_size = 32;
4414 env->icache_line_size = 32;
4415 /* Allocate hardware IRQ controller */
4416 ppc6xx_irq_init(env);
4417 }
4418
4419 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4420 {
4421 DeviceClass *dc = DEVICE_CLASS(oc);
4422 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4423
4424 dc->desc = "PowerPC G2";
4425 pcc->init_proc = init_proc_G2;
4426 pcc->check_pow = check_pow_hid0;
4427 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4428 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4429 PPC_FLOAT_STFIWX |
4430 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4431 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4432 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4433 PPC_SEGMENT | PPC_EXTERN;
4434 pcc->msr_mask = (1ull << MSR_POW) |
4435 (1ull << MSR_TGPR) |
4436 (1ull << MSR_EE) |
4437 (1ull << MSR_PR) |
4438 (1ull << MSR_FP) |
4439 (1ull << MSR_ME) |
4440 (1ull << MSR_FE0) |
4441 (1ull << MSR_SE) |
4442 (1ull << MSR_DE) |
4443 (1ull << MSR_FE1) |
4444 (1ull << MSR_AL) |
4445 (1ull << MSR_EP) |
4446 (1ull << MSR_IR) |
4447 (1ull << MSR_DR) |
4448 (1ull << MSR_RI);
4449 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4450 pcc->excp_model = POWERPC_EXCP_G2;
4451 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4452 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4453 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4454 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4455 }
4456
4457 static void init_proc_G2LE (CPUPPCState *env)
4458 {
4459 gen_spr_ne_601(env);
4460 gen_spr_G2_755(env);
4461 gen_spr_G2(env);
4462 /* Time base */
4463 gen_tbl(env);
4464 /* External access control */
4465 /* XXX : not implemented */
4466 spr_register(env, SPR_EAR, "EAR",
4467 SPR_NOACCESS, SPR_NOACCESS,
4468 &spr_read_generic, &spr_write_generic,
4469 0x00000000);
4470 /* Hardware implementation register */
4471 /* XXX : not implemented */
4472 spr_register(env, SPR_HID0, "HID0",
4473 SPR_NOACCESS, SPR_NOACCESS,
4474 &spr_read_generic, &spr_write_generic,
4475 0x00000000);
4476 /* XXX : not implemented */
4477 spr_register(env, SPR_HID1, "HID1",
4478 SPR_NOACCESS, SPR_NOACCESS,
4479 &spr_read_generic, &spr_write_generic,
4480 0x00000000);
4481 /* XXX : not implemented */
4482 spr_register(env, SPR_HID2, "HID2",
4483 SPR_NOACCESS, SPR_NOACCESS,
4484 &spr_read_generic, &spr_write_generic,
4485 0x00000000);
4486
4487 /* Memory management */
4488 gen_low_BATs(env);
4489 gen_high_BATs(env);
4490 gen_6xx_7xx_soft_tlb(env, 64, 2);
4491 init_excp_G2(env);
4492 env->dcache_line_size = 32;
4493 env->icache_line_size = 32;
4494 /* Allocate hardware IRQ controller */
4495 ppc6xx_irq_init(env);
4496 }
4497
4498 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4499 {
4500 DeviceClass *dc = DEVICE_CLASS(oc);
4501 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4502
4503 dc->desc = "PowerPC G2LE";
4504 pcc->init_proc = init_proc_G2LE;
4505 pcc->check_pow = check_pow_hid0;
4506 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4507 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4508 PPC_FLOAT_STFIWX |
4509 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4510 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4511 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4512 PPC_SEGMENT | PPC_EXTERN;
4513 pcc->msr_mask = (1ull << MSR_POW) |
4514 (1ull << MSR_TGPR) |
4515 (1ull << MSR_ILE) |
4516 (1ull << MSR_EE) |
4517 (1ull << MSR_PR) |
4518 (1ull << MSR_FP) |
4519 (1ull << MSR_ME) |
4520 (1ull << MSR_FE0) |
4521 (1ull << MSR_SE) |
4522 (1ull << MSR_DE) |
4523 (1ull << MSR_FE1) |
4524 (1ull << MSR_AL) |
4525 (1ull << MSR_EP) |
4526 (1ull << MSR_IR) |
4527 (1ull << MSR_DR) |
4528 (1ull << MSR_RI) |
4529 (1ull << MSR_LE);
4530 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4531 pcc->excp_model = POWERPC_EXCP_G2;
4532 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4533 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4534 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4535 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4536 }
4537
4538 static void init_proc_e200 (CPUPPCState *env)
4539 {
4540 /* Time base */
4541 gen_tbl(env);
4542 gen_spr_BookE(env, 0x000000070000FFFFULL);
4543 /* XXX : not implemented */
4544 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4545 &spr_read_spefscr, &spr_write_spefscr,
4546 &spr_read_spefscr, &spr_write_spefscr,
4547 0x00000000);
4548 /* Memory management */
4549 gen_spr_BookE206(env, 0x0000005D, NULL);
4550 /* XXX : not implemented */
4551 spr_register(env, SPR_HID0, "HID0",
4552 SPR_NOACCESS, SPR_NOACCESS,
4553 &spr_read_generic, &spr_write_generic,
4554 0x00000000);
4555 /* XXX : not implemented */
4556 spr_register(env, SPR_HID1, "HID1",
4557 SPR_NOACCESS, SPR_NOACCESS,
4558 &spr_read_generic, &spr_write_generic,
4559 0x00000000);
4560 /* XXX : not implemented */
4561 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4562 SPR_NOACCESS, SPR_NOACCESS,
4563 &spr_read_generic, &spr_write_generic,
4564 0x00000000);
4565 /* XXX : not implemented */
4566 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4567 SPR_NOACCESS, SPR_NOACCESS,
4568 &spr_read_generic, &spr_write_generic,
4569 0x00000000);
4570 /* XXX : not implemented */
4571 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4572 SPR_NOACCESS, SPR_NOACCESS,
4573 &spr_read_generic, &spr_write_generic,
4574 0x00000000);
4575 /* XXX : not implemented */
4576 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4577 SPR_NOACCESS, SPR_NOACCESS,
4578 &spr_read_generic, &spr_write_generic,
4579 0x00000000);
4580 /* XXX : not implemented */
4581 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4582 SPR_NOACCESS, SPR_NOACCESS,
4583 &spr_read_generic, &spr_write_generic,
4584 0x00000000);
4585 /* XXX : not implemented */
4586 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4587 &spr_read_generic, SPR_NOACCESS,
4588 &spr_read_generic, SPR_NOACCESS,
4589 0x00000000);
4590 /* XXX : not implemented */
4591 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4592 SPR_NOACCESS, SPR_NOACCESS,
4593 &spr_read_generic, &spr_write_generic,
4594 0x00000000);
4595 /* XXX : not implemented */
4596 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4597 SPR_NOACCESS, SPR_NOACCESS,
4598 &spr_read_generic, &spr_write_generic,
4599 0x00000000);
4600 /* XXX : not implemented */
4601 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4602 SPR_NOACCESS, SPR_NOACCESS,
4603 &spr_read_generic, &spr_write_generic,
4604 0x00000000);
4605 /* XXX : not implemented */
4606 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4607 SPR_NOACCESS, SPR_NOACCESS,
4608 &spr_read_generic, &spr_write_generic,
4609 0x00000000);
4610 /* XXX : not implemented */
4611 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4612 SPR_NOACCESS, SPR_NOACCESS,
4613 &spr_read_generic, &spr_write_generic,
4614 0x00000000);
4615 /* XXX : not implemented */
4616 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4617 SPR_NOACCESS, SPR_NOACCESS,
4618 &spr_read_generic, &spr_write_generic,
4619 0x00000000);
4620 /* XXX : not implemented */
4621 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000); /* TOFIX */
4625 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4626 SPR_NOACCESS, SPR_NOACCESS,
4627 &spr_read_generic, &spr_write_generic,
4628 0x00000000);
4629 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4630 SPR_NOACCESS, SPR_NOACCESS,
4631 &spr_read_generic, &spr_write_generic,
4632 0x00000000);
4633 #if !defined(CONFIG_USER_ONLY)
4634 env->nb_tlb = 64;
4635 env->nb_ways = 1;
4636 env->id_tlbs = 0;
4637 env->tlb_type = TLB_EMB;
4638 #endif
4639 init_excp_e200(env, 0xFFFF0000UL);
4640 env->dcache_line_size = 32;
4641 env->icache_line_size = 32;
4642 /* XXX: TODO: allocate internal IRQ controller */
4643 }
4644
4645 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4646 {
4647 DeviceClass *dc = DEVICE_CLASS(oc);
4648 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4649
4650 dc->desc = "e200 core";
4651 pcc->init_proc = init_proc_e200;
4652 pcc->check_pow = check_pow_hid0;
4653 /* XXX: unimplemented instructions:
4654 * dcblc
4655 * dcbtlst
4656 * dcbtstls
4657 * icblc
4658 * icbtls
4659 * tlbivax
4660 * all SPE multiply-accumulate instructions
4661 */
4662 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4663 PPC_SPE | PPC_SPE_SINGLE |
4664 PPC_WRTEE | PPC_RFDI |
4665 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4666 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4667 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4668 PPC_BOOKE;
4669 pcc->msr_mask = (1ull << MSR_UCLE) |
4670 (1ull << MSR_SPE) |
4671 (1ull << MSR_POW) |
4672 (1ull << MSR_CE) |
4673 (1ull << MSR_EE) |
4674 (1ull << MSR_PR) |
4675 (1ull << MSR_FP) |
4676 (1ull << MSR_ME) |
4677 (1ull << MSR_FE0) |
4678 (1ull << MSR_DWE) |
4679 (1ull << MSR_DE) |
4680 (1ull << MSR_FE1) |
4681 (1ull << MSR_IR) |
4682 (1ull << MSR_DR);
4683 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4684 pcc->excp_model = POWERPC_EXCP_BOOKE;
4685 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4686 pcc->bfd_mach = bfd_mach_ppc_860;
4687 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4688 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4689 POWERPC_FLAG_BUS_CLK;
4690 }
4691
4692 static void init_proc_e300 (CPUPPCState *env)
4693 {
4694 gen_spr_ne_601(env);
4695 gen_spr_603(env);
4696 /* Time base */
4697 gen_tbl(env);
4698 /* hardware implementation registers */
4699 /* XXX : not implemented */
4700 spr_register(env, SPR_HID0, "HID0",
4701 SPR_NOACCESS, SPR_NOACCESS,
4702 &spr_read_generic, &spr_write_generic,
4703 0x00000000);
4704 /* XXX : not implemented */
4705 spr_register(env, SPR_HID1, "HID1",
4706 SPR_NOACCESS, SPR_NOACCESS,
4707 &spr_read_generic, &spr_write_generic,
4708 0x00000000);
4709 /* XXX : not implemented */
4710 spr_register(env, SPR_HID2, "HID2",
4711 SPR_NOACCESS, SPR_NOACCESS,
4712 &spr_read_generic, &spr_write_generic,
4713 0x00000000);
4714 /* Breakpoints */
4715 /* XXX : not implemented */
4716 spr_register(env, SPR_DABR, "DABR",
4717 SPR_NOACCESS, SPR_NOACCESS,
4718 &spr_read_generic, &spr_write_generic,
4719 0x00000000);
4720 /* XXX : not implemented */
4721 spr_register(env, SPR_DABR2, "DABR2",
4722 SPR_NOACCESS, SPR_NOACCESS,
4723 &spr_read_generic, &spr_write_generic,
4724 0x00000000);
4725 /* XXX : not implemented */
4726 spr_register(env, SPR_IABR2, "IABR2",
4727 SPR_NOACCESS, SPR_NOACCESS,
4728 &spr_read_generic, &spr_write_generic,
4729 0x00000000);
4730 /* XXX : not implemented */
4731 spr_register(env, SPR_IBCR, "IBCR",
4732 SPR_NOACCESS, SPR_NOACCESS,
4733 &spr_read_generic, &spr_write_generic,
4734 0x00000000);
4735 /* XXX : not implemented */
4736 spr_register(env, SPR_DBCR, "DBCR",
4737 SPR_NOACCESS, SPR_NOACCESS,
4738 &spr_read_generic, &spr_write_generic,
4739 0x00000000);
4740 /* Memory management */
4741 gen_low_BATs(env);
4742 gen_high_BATs(env);
4743 gen_6xx_7xx_soft_tlb(env, 64, 2);
4744 init_excp_603(env);
4745 env->dcache_line_size = 32;
4746 env->icache_line_size = 32;
4747 /* Allocate hardware IRQ controller */
4748 ppc6xx_irq_init(env);
4749 }
4750
4751 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4752 {
4753 DeviceClass *dc = DEVICE_CLASS(oc);
4754 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4755
4756 dc->desc = "e300 core";
4757 pcc->init_proc = init_proc_e300;
4758 pcc->check_pow = check_pow_hid0;
4759 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4760 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4761 PPC_FLOAT_STFIWX |
4762 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4763 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4764 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4765 PPC_SEGMENT | PPC_EXTERN;
4766 pcc->msr_mask = (1ull << MSR_POW) |
4767 (1ull << MSR_TGPR) |
4768 (1ull << MSR_ILE) |
4769 (1ull << MSR_EE) |
4770 (1ull << MSR_PR) |
4771 (1ull << MSR_FP) |
4772 (1ull << MSR_ME) |
4773 (1ull << MSR_FE0) |
4774 (1ull << MSR_SE) |
4775 (1ull << MSR_DE) |
4776 (1ull << MSR_FE1) |
4777 (1ull << MSR_AL) |
4778 (1ull << MSR_EP) |
4779 (1ull << MSR_IR) |
4780 (1ull << MSR_DR) |
4781 (1ull << MSR_RI) |
4782 (1ull << MSR_LE);
4783 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4784 pcc->excp_model = POWERPC_EXCP_603;
4785 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4786 pcc->bfd_mach = bfd_mach_ppc_603;
4787 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4788 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4789 }
4790
4791 #if !defined(CONFIG_USER_ONLY)
4792 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4793 {
4794 TCGv val = tcg_temp_new();
4795 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4796 gen_store_spr(SPR_BOOKE_MAS3, val);
4797 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4798 gen_store_spr(SPR_BOOKE_MAS7, val);
4799 tcg_temp_free(val);
4800 }
4801
4802 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4803 {
4804 TCGv mas7 = tcg_temp_new();
4805 TCGv mas3 = tcg_temp_new();
4806 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4807 tcg_gen_shli_tl(mas7, mas7, 32);
4808 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4809 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4810 tcg_temp_free(mas3);
4811 tcg_temp_free(mas7);
4812 }
4813
4814 #endif
4815
4816 enum fsl_e500_version {
4817 fsl_e500v1,
4818 fsl_e500v2,
4819 fsl_e500mc,
4820 fsl_e5500,
4821 };
4822
4823 static void init_proc_e500 (CPUPPCState *env, int version)
4824 {
4825 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4826 uint32_t tlbncfg[2];
4827 uint64_t ivor_mask;
4828 uint64_t ivpr_mask = 0xFFFF0000ULL;
4829 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4830 | 0x0020; /* 32 kb */
4831 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4832 | 0x0020; /* 32 kb */
4833 #if !defined(CONFIG_USER_ONLY)
4834 int i;
4835 #endif
4836
4837 /* Time base */
4838 gen_tbl(env);
4839 /*
4840 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4841 * complain when accessing them.
4842 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4843 */
4844 switch (version) {
4845 case fsl_e500v1:
4846 case fsl_e500v2:
4847 default:
4848 ivor_mask = 0x0000000F0000FFFFULL;
4849 break;
4850 case fsl_e500mc:
4851 case fsl_e5500:
4852 ivor_mask = 0x000003FE0000FFFFULL;
4853 break;
4854 }
4855 gen_spr_BookE(env, ivor_mask);
4856 /* Processor identification */
4857 spr_register(env, SPR_BOOKE_PIR, "PIR",
4858 SPR_NOACCESS, SPR_NOACCESS,
4859 &spr_read_generic, &spr_write_pir,
4860 0x00000000);
4861 /* XXX : not implemented */
4862 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4863 &spr_read_spefscr, &spr_write_spefscr,
4864 &spr_read_spefscr, &spr_write_spefscr,
4865 0x00000000);
4866 #if !defined(CONFIG_USER_ONLY)
4867 /* Memory management */
4868 env->nb_pids = 3;
4869 env->nb_ways = 2;
4870 env->id_tlbs = 0;
4871 switch (version) {
4872 case fsl_e500v1:
4873 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4874 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4875 break;
4876 case fsl_e500v2:
4877 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4878 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4879 break;
4880 case fsl_e500mc:
4881 case fsl_e5500:
4882 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4883 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4884 break;
4885 default:
4886 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4887 }
4888 #endif
4889 /* Cache sizes */
4890 switch (version) {
4891 case fsl_e500v1:
4892 case fsl_e500v2:
4893 env->dcache_line_size = 32;
4894 env->icache_line_size = 32;
4895 break;
4896 case fsl_e500mc:
4897 case fsl_e5500:
4898 env->dcache_line_size = 64;
4899 env->icache_line_size = 64;
4900 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4901 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4902 break;
4903 default:
4904 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4905 }
4906 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4907 /* XXX : not implemented */
4908 spr_register(env, SPR_HID0, "HID0",
4909 SPR_NOACCESS, SPR_NOACCESS,
4910 &spr_read_generic, &spr_write_generic,
4911 0x00000000);
4912 /* XXX : not implemented */
4913 spr_register(env, SPR_HID1, "HID1",
4914 SPR_NOACCESS, SPR_NOACCESS,
4915 &spr_read_generic, &spr_write_generic,
4916 0x00000000);
4917 /* XXX : not implemented */
4918 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4919 SPR_NOACCESS, SPR_NOACCESS,
4920 &spr_read_generic, &spr_write_generic,
4921 0x00000000);
4922 /* XXX : not implemented */
4923 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4924 SPR_NOACCESS, SPR_NOACCESS,
4925 &spr_read_generic, &spr_write_generic,
4926 0x00000000);
4927 /* XXX : not implemented */
4928 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4929 SPR_NOACCESS, SPR_NOACCESS,
4930 &spr_read_generic, &spr_write_generic,
4931 0x00000000);
4932 /* XXX : not implemented */
4933 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4934 SPR_NOACCESS, SPR_NOACCESS,
4935 &spr_read_generic, &spr_write_generic,
4936 0x00000000);
4937 /* XXX : not implemented */
4938 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4939 SPR_NOACCESS, SPR_NOACCESS,
4940 &spr_read_generic, &spr_write_generic,
4941 0x00000000);
4942 /* XXX : not implemented */
4943 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4944 SPR_NOACCESS, SPR_NOACCESS,
4945 &spr_read_generic, &spr_write_generic,
4946 0x00000000);
4947 /* XXX : not implemented */
4948 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4949 &spr_read_generic, SPR_NOACCESS,
4950 &spr_read_generic, SPR_NOACCESS,
4951 l1cfg0);
4952 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4953 &spr_read_generic, SPR_NOACCESS,
4954 &spr_read_generic, SPR_NOACCESS,
4955 l1cfg1);
4956 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4957 SPR_NOACCESS, SPR_NOACCESS,
4958 &spr_read_generic, &spr_write_e500_l1csr0,
4959 0x00000000);
4960 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4961 SPR_NOACCESS, SPR_NOACCESS,
4962 &spr_read_generic, &spr_write_e500_l1csr1,
4963 0x00000000);
4964 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4965 SPR_NOACCESS, SPR_NOACCESS,
4966 &spr_read_generic, &spr_write_generic,
4967 0x00000000);
4968 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4969 SPR_NOACCESS, SPR_NOACCESS,
4970 &spr_read_generic, &spr_write_generic,
4971 0x00000000);
4972 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4973 SPR_NOACCESS, SPR_NOACCESS,
4974 &spr_read_generic, &spr_write_booke206_mmucsr0,
4975 0x00000000);
4976 spr_register(env, SPR_BOOKE_EPR, "EPR",
4977 SPR_NOACCESS, SPR_NOACCESS,
4978 &spr_read_generic, SPR_NOACCESS,
4979 0x00000000);
4980 /* XXX better abstract into Emb.xxx features */
4981 if (version == fsl_e5500) {
4982 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4983 SPR_NOACCESS, SPR_NOACCESS,
4984 &spr_read_generic, &spr_write_generic,
4985 0x00000000);
4986 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4987 SPR_NOACCESS, SPR_NOACCESS,
4988 &spr_read_mas73, &spr_write_mas73,
4989 0x00000000);
4990 ivpr_mask = (target_ulong)~0xFFFFULL;
4991 }
4992
4993 #if !defined(CONFIG_USER_ONLY)
4994 env->nb_tlb = 0;
4995 env->tlb_type = TLB_MAS;
4996 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4997 env->nb_tlb += booke206_tlb_size(env, i);
4998 }
4999 #endif
5000
5001 init_excp_e200(env, ivpr_mask);
5002 /* Allocate hardware IRQ controller */
5003 ppce500_irq_init(env);
5004 }
5005
5006 static void init_proc_e500v1(CPUPPCState *env)
5007 {
5008 init_proc_e500(env, fsl_e500v1);
5009 }
5010
5011 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
5012 {
5013 DeviceClass *dc = DEVICE_CLASS(oc);
5014 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5015
5016 dc->desc = "e500v1 core";
5017 pcc->init_proc = init_proc_e500v1;
5018 pcc->check_pow = check_pow_hid0;
5019 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5020 PPC_SPE | PPC_SPE_SINGLE |
5021 PPC_WRTEE | PPC_RFDI |
5022 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5023 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5024 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5025 pcc->insns_flags2 = PPC2_BOOKE206;
5026 pcc->msr_mask = (1ull << MSR_UCLE) |
5027 (1ull << MSR_SPE) |
5028 (1ull << MSR_POW) |
5029 (1ull << MSR_CE) |
5030 (1ull << MSR_EE) |
5031 (1ull << MSR_PR) |
5032 (1ull << MSR_FP) |
5033 (1ull << MSR_ME) |
5034 (1ull << MSR_FE0) |
5035 (1ull << MSR_DWE) |
5036 (1ull << MSR_DE) |
5037 (1ull << MSR_FE1) |
5038 (1ull << MSR_IR) |
5039 (1ull << MSR_DR);
5040 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5041 pcc->excp_model = POWERPC_EXCP_BOOKE;
5042 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5043 pcc->bfd_mach = bfd_mach_ppc_860;
5044 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5045 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5046 POWERPC_FLAG_BUS_CLK;
5047 }
5048
5049 static void init_proc_e500v2(CPUPPCState *env)
5050 {
5051 init_proc_e500(env, fsl_e500v2);
5052 }
5053
5054 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
5055 {
5056 DeviceClass *dc = DEVICE_CLASS(oc);
5057 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5058
5059 dc->desc = "e500v2 core";
5060 pcc->init_proc = init_proc_e500v2;
5061 pcc->check_pow = check_pow_hid0;
5062 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5063 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
5064 PPC_WRTEE | PPC_RFDI |
5065 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5066 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5067 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5068 pcc->insns_flags2 = PPC2_BOOKE206;
5069 pcc->msr_mask = (1ull << MSR_UCLE) |
5070 (1ull << MSR_SPE) |
5071 (1ull << MSR_POW) |
5072 (1ull << MSR_CE) |
5073 (1ull << MSR_EE) |
5074 (1ull << MSR_PR) |
5075 (1ull << MSR_FP) |
5076 (1ull << MSR_ME) |
5077 (1ull << MSR_FE0) |
5078 (1ull << MSR_DWE) |
5079 (1ull << MSR_DE) |
5080 (1ull << MSR_FE1) |
5081 (1ull << MSR_IR) |
5082 (1ull << MSR_DR);
5083 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5084 pcc->excp_model = POWERPC_EXCP_BOOKE;
5085 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5086 pcc->bfd_mach = bfd_mach_ppc_860;
5087 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
5088 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
5089 POWERPC_FLAG_BUS_CLK;
5090 }
5091
5092 static void init_proc_e500mc(CPUPPCState *env)
5093 {
5094 init_proc_e500(env, fsl_e500mc);
5095 }
5096
5097 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
5098 {
5099 DeviceClass *dc = DEVICE_CLASS(oc);
5100 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5101
5102 dc->desc = "e500mc core";
5103 pcc->init_proc = init_proc_e500mc;
5104 pcc->check_pow = check_pow_none;
5105 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5106 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5107 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5108 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5109 PPC_FLOAT | PPC_FLOAT_FRES |
5110 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5111 PPC_FLOAT_STFIWX | PPC_WAIT |
5112 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
5113 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
5114 pcc->msr_mask = (1ull << MSR_GS) |
5115 (1ull << MSR_UCLE) |
5116 (1ull << MSR_CE) |
5117 (1ull << MSR_EE) |
5118 (1ull << MSR_PR) |
5119 (1ull << MSR_FP) |
5120 (1ull << MSR_ME) |
5121 (1ull << MSR_FE0) |
5122 (1ull << MSR_DE) |
5123 (1ull << MSR_FE1) |
5124 (1ull << MSR_IR) |
5125 (1ull << MSR_DR) |
5126 (1ull << MSR_PX) |
5127 (1ull << MSR_RI);
5128 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5129 pcc->excp_model = POWERPC_EXCP_BOOKE;
5130 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5131 /* FIXME: figure out the correct flag for e500mc */
5132 pcc->bfd_mach = bfd_mach_ppc_e500;
5133 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5134 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5135 }
5136
5137 #ifdef TARGET_PPC64
5138 static void init_proc_e5500(CPUPPCState *env)
5139 {
5140 init_proc_e500(env, fsl_e5500);
5141 }
5142
5143 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
5144 {
5145 DeviceClass *dc = DEVICE_CLASS(oc);
5146 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5147
5148 dc->desc = "e5500 core";
5149 pcc->init_proc = init_proc_e5500;
5150 pcc->check_pow = check_pow_none;
5151 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
5152 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
5153 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
5154 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
5155 PPC_FLOAT | PPC_FLOAT_FRES |
5156 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5157 PPC_FLOAT_STFIWX | PPC_WAIT |
5158 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5159 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5160 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
5161 PPC2_FP_CVT_S64;
5162 pcc->msr_mask = (1ull << MSR_CM) |
5163 (1ull << MSR_GS) |
5164 (1ull << MSR_UCLE) |
5165 (1ull << MSR_CE) |
5166 (1ull << MSR_EE) |
5167 (1ull << MSR_PR) |
5168 (1ull << MSR_FP) |
5169 (1ull << MSR_ME) |
5170 (1ull << MSR_FE0) |
5171 (1ull << MSR_DE) |
5172 (1ull << MSR_FE1) |
5173 (1ull << MSR_IR) |
5174 (1ull << MSR_DR) |
5175 (1ull << MSR_PX) |
5176 (1ull << MSR_RI);
5177 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5178 pcc->excp_model = POWERPC_EXCP_BOOKE;
5179 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5180 /* FIXME: figure out the correct flag for e5500 */
5181 pcc->bfd_mach = bfd_mach_ppc_e500;
5182 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5183 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5184 }
5185 #endif
5186
5187 /* Non-embedded PowerPC */
5188
5189 /* POWER : same as 601, without mfmsr, mfsr */
5190 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
5191 {
5192 DeviceClass *dc = DEVICE_CLASS(oc);
5193 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5194
5195 dc->desc = "POWER";
5196 /* pcc->insns_flags = XXX_TODO; */
5197 /* POWER RSC (from RAD6000) */
5198 pcc->msr_mask = (1ull << MSR_EE) |
5199 (1ull << MSR_PR) |
5200 (1ull << MSR_FP) |
5201 (1ull << MSR_ME) |
5202 (1ull << MSR_FE0) |
5203 (1ull << MSR_SE) |
5204 (1ull << MSR_DE) |
5205 (1ull << MSR_AL) |
5206 (1ull << MSR_EP) |
5207 (1ull << MSR_IR) |
5208 (1ull << MSR_DR);
5209 }
5210
5211 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5212
5213 static void init_proc_601 (CPUPPCState *env)
5214 {
5215 gen_spr_ne_601(env);
5216 gen_spr_601(env);
5217 /* Hardware implementation registers */
5218 /* XXX : not implemented */
5219 spr_register(env, SPR_HID0, "HID0",
5220 SPR_NOACCESS, SPR_NOACCESS,
5221 &spr_read_generic, &spr_write_hid0_601,
5222 0x80010080);
5223 /* XXX : not implemented */
5224 spr_register(env, SPR_HID1, "HID1",
5225 SPR_NOACCESS, SPR_NOACCESS,
5226 &spr_read_generic, &spr_write_generic,
5227 0x00000000);
5228 /* XXX : not implemented */
5229 spr_register(env, SPR_601_HID2, "HID2",
5230 SPR_NOACCESS, SPR_NOACCESS,
5231 &spr_read_generic, &spr_write_generic,
5232 0x00000000);
5233 /* XXX : not implemented */
5234 spr_register(env, SPR_601_HID5, "HID5",
5235 SPR_NOACCESS, SPR_NOACCESS,
5236 &spr_read_generic, &spr_write_generic,
5237 0x00000000);
5238 /* Memory management */
5239 init_excp_601(env);
5240 /* XXX: beware that dcache line size is 64
5241 * but dcbz uses 32 bytes "sectors"
5242 * XXX: this breaks clcs instruction !
5243 */
5244 env->dcache_line_size = 32;
5245 env->icache_line_size = 64;
5246 /* Allocate hardware IRQ controller */
5247 ppc6xx_irq_init(env);
5248 }
5249
5250 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5251 {
5252 DeviceClass *dc = DEVICE_CLASS(oc);
5253 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5254
5255 dc->desc = "PowerPC 601";
5256 pcc->init_proc = init_proc_601;
5257 pcc->check_pow = check_pow_none;
5258 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5259 PPC_FLOAT |
5260 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5261 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5262 PPC_SEGMENT | PPC_EXTERN;
5263 pcc->msr_mask = (1ull << MSR_EE) |
5264 (1ull << MSR_PR) |
5265 (1ull << MSR_FP) |
5266 (1ull << MSR_ME) |
5267 (1ull << MSR_FE0) |
5268 (1ull << MSR_SE) |
5269 (1ull << MSR_FE1) |
5270 (1ull << MSR_EP) |
5271 (1ull << MSR_IR) |
5272 (1ull << MSR_DR);
5273 pcc->mmu_model = POWERPC_MMU_601;
5274 #if defined(CONFIG_SOFTMMU)
5275 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5276 #endif
5277 pcc->excp_model = POWERPC_EXCP_601;
5278 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5279 pcc->bfd_mach = bfd_mach_ppc_601;
5280 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5281 }
5282
5283 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5284
5285 static void init_proc_601v (CPUPPCState *env)
5286 {
5287 init_proc_601(env);
5288 /* XXX : not implemented */
5289 spr_register(env, SPR_601_HID15, "HID15",
5290 SPR_NOACCESS, SPR_NOACCESS,
5291 &spr_read_generic, &spr_write_generic,
5292 0x00000000);
5293 }
5294
5295 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5296 {
5297 DeviceClass *dc = DEVICE_CLASS(oc);
5298 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5299
5300 dc->desc = "PowerPC 601v";
5301 pcc->init_proc = init_proc_601v;
5302 pcc->check_pow = check_pow_none;
5303 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5304 PPC_FLOAT |
5305 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5306 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5307 PPC_SEGMENT | PPC_EXTERN;
5308 pcc->msr_mask = (1ull << MSR_EE) |
5309 (1ull << MSR_PR) |
5310 (1ull << MSR_FP) |
5311 (1ull << MSR_ME) |
5312 (1ull << MSR_FE0) |
5313 (1ull << MSR_SE) |
5314 (1ull << MSR_FE1) |
5315 (1ull << MSR_EP) |
5316 (1ull << MSR_IR) |
5317 (1ull << MSR_DR);
5318 pcc->mmu_model = POWERPC_MMU_601;
5319 #if defined(CONFIG_SOFTMMU)
5320 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5321 #endif
5322 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5323 pcc->bfd_mach = bfd_mach_ppc_601;
5324 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5325 }
5326
5327 static void init_proc_602 (CPUPPCState *env)
5328 {
5329 gen_spr_ne_601(env);
5330 gen_spr_602(env);
5331 /* Time base */
5332 gen_tbl(env);
5333 /* hardware implementation registers */
5334 /* XXX : not implemented */
5335 spr_register(env, SPR_HID0, "HID0",
5336 SPR_NOACCESS, SPR_NOACCESS,
5337 &spr_read_generic, &spr_write_generic,
5338 0x00000000);
5339 /* XXX : not implemented */
5340 spr_register(env, SPR_HID1, "HID1",
5341 SPR_NOACCESS, SPR_NOACCESS,
5342 &spr_read_generic, &spr_write_generic,
5343 0x00000000);
5344 /* Memory management */
5345 gen_low_BATs(env);
5346 gen_6xx_7xx_soft_tlb(env, 64, 2);
5347 init_excp_602(env);
5348 env->dcache_line_size = 32;
5349 env->icache_line_size = 32;
5350 /* Allocate hardware IRQ controller */
5351 ppc6xx_irq_init(env);
5352 }
5353
5354 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5355 {
5356 DeviceClass *dc = DEVICE_CLASS(oc);
5357 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5358
5359 dc->desc = "PowerPC 602";
5360 pcc->init_proc = init_proc_602;
5361 pcc->check_pow = check_pow_hid0;
5362 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5363 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5364 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5365 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5366 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5367 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5368 PPC_SEGMENT | PPC_602_SPEC;
5369 pcc->msr_mask = (1ull << MSR_VSX) |
5370 (1ull << MSR_SA) |
5371 (1ull << MSR_POW) |
5372 (1ull << MSR_TGPR) |
5373 (1ull << MSR_ILE) |
5374 (1ull << MSR_EE) |
5375 (1ull << MSR_PR) |
5376 (1ull << MSR_FP) |
5377 (1ull << MSR_ME) |
5378 (1ull << MSR_FE0) |
5379 (1ull << MSR_SE) |
5380 (1ull << MSR_DE) |
5381 (1ull << MSR_FE1) |
5382 (1ull << MSR_EP) |
5383 (1ull << MSR_IR) |
5384 (1ull << MSR_DR) |
5385 (1ull << MSR_RI) |
5386 (1ull << MSR_LE);
5387 /* XXX: 602 MMU is quite specific. Should add a special case */
5388 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5389 pcc->excp_model = POWERPC_EXCP_602;
5390 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5391 pcc->bfd_mach = bfd_mach_ppc_602;
5392 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5393 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5394 }
5395
5396 static void init_proc_603 (CPUPPCState *env)
5397 {
5398 gen_spr_ne_601(env);
5399 gen_spr_603(env);
5400 /* Time base */
5401 gen_tbl(env);
5402 /* hardware implementation registers */
5403 /* XXX : not implemented */
5404 spr_register(env, SPR_HID0, "HID0",
5405 SPR_NOACCESS, SPR_NOACCESS,
5406 &spr_read_generic, &spr_write_generic,
5407 0x00000000);
5408 /* XXX : not implemented */
5409 spr_register(env, SPR_HID1, "HID1",
5410 SPR_NOACCESS, SPR_NOACCESS,
5411 &spr_read_generic, &spr_write_generic,
5412 0x00000000);
5413 /* Memory management */
5414 gen_low_BATs(env);
5415 gen_6xx_7xx_soft_tlb(env, 64, 2);
5416 init_excp_603(env);
5417 env->dcache_line_size = 32;
5418 env->icache_line_size = 32;
5419 /* Allocate hardware IRQ controller */
5420 ppc6xx_irq_init(env);
5421 }
5422
5423 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5424 {
5425 DeviceClass *dc = DEVICE_CLASS(oc);
5426 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5427
5428 dc->desc = "PowerPC 603";
5429 pcc->init_proc = init_proc_603;
5430 pcc->check_pow = check_pow_hid0;
5431 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5432 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5433 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5434 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5435 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5436 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5437 PPC_SEGMENT | PPC_EXTERN;
5438 pcc->msr_mask = (1ull << MSR_POW) |
5439 (1ull << MSR_TGPR) |
5440 (1ull << MSR_ILE) |
5441 (1ull << MSR_EE) |
5442 (1ull << MSR_PR) |
5443 (1ull << MSR_FP) |
5444 (1ull << MSR_ME) |
5445 (1ull << MSR_FE0) |
5446 (1ull << MSR_SE) |
5447 (1ull << MSR_DE) |
5448 (1ull << MSR_FE1) |
5449 (1ull << MSR_EP) |
5450 (1ull << MSR_IR) |
5451 (1ull << MSR_DR) |
5452 (1ull << MSR_RI) |
5453 (1ull << MSR_LE);
5454 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5455 pcc->excp_model = POWERPC_EXCP_603;
5456 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5457 pcc->bfd_mach = bfd_mach_ppc_603;
5458 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5459 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5460 }
5461
5462 static void init_proc_603E (CPUPPCState *env)
5463 {
5464 gen_spr_ne_601(env);
5465 gen_spr_603(env);
5466 /* Time base */
5467 gen_tbl(env);
5468 /* hardware implementation registers */
5469 /* XXX : not implemented */
5470 spr_register(env, SPR_HID0, "HID0",
5471 SPR_NOACCESS, SPR_NOACCESS,
5472 &spr_read_generic, &spr_write_generic,
5473 0x00000000);
5474 /* XXX : not implemented */
5475 spr_register(env, SPR_HID1, "HID1",
5476 SPR_NOACCESS, SPR_NOACCESS,
5477 &spr_read_generic, &spr_write_generic,
5478 0x00000000);
5479 /* Memory management */
5480 gen_low_BATs(env);
5481 gen_6xx_7xx_soft_tlb(env, 64, 2);
5482 init_excp_603(env);
5483 env->dcache_line_size = 32;
5484 env->icache_line_size = 32;
5485 /* Allocate hardware IRQ controller */
5486 ppc6xx_irq_init(env);
5487 }
5488
5489 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5490 {
5491 DeviceClass *dc = DEVICE_CLASS(oc);
5492 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5493
5494 dc->desc = "PowerPC 603e";
5495 pcc->init_proc = init_proc_603E;
5496 pcc->check_pow = check_pow_hid0;
5497 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5498 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5499 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5500 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5501 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5502 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5503 PPC_SEGMENT | PPC_EXTERN;
5504 pcc->msr_mask = (1ull << MSR_POW) |
5505 (1ull << MSR_TGPR) |
5506 (1ull << MSR_ILE) |
5507 (1ull << MSR_EE) |
5508 (1ull << MSR_PR) |
5509 (1ull << MSR_FP) |
5510 (1ull << MSR_ME) |
5511 (1ull << MSR_FE0) |
5512 (1ull << MSR_SE) |
5513 (1ull << MSR_DE) |
5514 (1ull << MSR_FE1) |
5515 (1ull << MSR_EP) |
5516 (1ull << MSR_IR) |
5517 (1ull << MSR_DR) |
5518 (1ull << MSR_RI) |
5519 (1ull << MSR_LE);
5520 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5521 pcc->excp_model = POWERPC_EXCP_603E;
5522 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5523 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5524 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5525 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5526 }
5527
5528 static void init_proc_604 (CPUPPCState *env)
5529 {
5530 gen_spr_ne_601(env);
5531 gen_spr_604(env);
5532 /* Time base */
5533 gen_tbl(env);
5534 /* Hardware implementation registers */
5535 /* XXX : not implemented */
5536 spr_register(env, SPR_HID0, "HID0",
5537 SPR_NOACCESS, SPR_NOACCESS,
5538 &spr_read_generic, &spr_write_generic,
5539 0x00000000);
5540 /* Memory management */
5541 gen_low_BATs(env);
5542 init_excp_604(env);
5543 env->dcache_line_size = 32;
5544 env->icache_line_size = 32;
5545 /* Allocate hardware IRQ controller */
5546 ppc6xx_irq_init(env);
5547 }
5548
5549 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5550 {
5551 DeviceClass *dc = DEVICE_CLASS(oc);
5552 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5553
5554 dc->desc = "PowerPC 604";
5555 pcc->init_proc = init_proc_604;
5556 pcc->check_pow = check_pow_nocheck;
5557 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5558 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5559 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5560 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5561 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5562 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5563 PPC_SEGMENT | PPC_EXTERN;
5564 pcc->msr_mask = (1ull << MSR_POW) |
5565 (1ull << MSR_ILE) |
5566 (1ull << MSR_EE) |
5567 (1ull << MSR_PR) |
5568 (1ull << MSR_FP) |
5569 (1ull << MSR_ME) |
5570 (1ull << MSR_FE0) |
5571 (1ull << MSR_SE) |
5572 (1ull << MSR_DE) |
5573 (1ull << MSR_FE1) |
5574 (1ull << MSR_EP) |
5575 (1ull << MSR_IR) |
5576 (1ull << MSR_DR) |
5577 (1ull << MSR_PMM) |
5578 (1ull << MSR_RI) |
5579 (1ull << MSR_LE);
5580 pcc->mmu_model = POWERPC_MMU_32B;
5581 #if defined(CONFIG_SOFTMMU)
5582 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5583 #endif
5584 pcc->excp_model = POWERPC_EXCP_604;
5585 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5586 pcc->bfd_mach = bfd_mach_ppc_604;
5587 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5588 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5589 }
5590
5591 static void init_proc_604E (CPUPPCState *env)
5592 {
5593 gen_spr_ne_601(env);
5594 gen_spr_604(env);
5595 /* XXX : not implemented */
5596 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
5597 SPR_NOACCESS, SPR_NOACCESS,
5598 &spr_read_generic, &spr_write_generic,
5599 0x00000000);
5600 /* XXX : not implemented */
5601 spr_register(env, SPR_7XX_PMC3, "PMC3",
5602 SPR_NOACCESS, SPR_NOACCESS,
5603 &spr_read_generic, &spr_write_generic,
5604 0x00000000);
5605 /* XXX : not implemented */
5606 spr_register(env, SPR_7XX_PMC4, "PMC4",
5607 SPR_NOACCESS, SPR_NOACCESS,
5608 &spr_read_generic, &spr_write_generic,
5609 0x00000000);
5610 /* Time base */
5611 gen_tbl(env);
5612 /* Hardware implementation registers */
5613 /* XXX : not implemented */
5614 spr_register(env, SPR_HID0, "HID0",
5615 SPR_NOACCESS, SPR_NOACCESS,
5616 &spr_read_generic, &spr_write_generic,
5617 0x00000000);
5618 /* XXX : not implemented */
5619 spr_register(env, SPR_HID1, "HID1",
5620 SPR_NOACCESS, SPR_NOACCESS,
5621 &spr_read_generic, &spr_write_generic,
5622 0x00000000);
5623 /* Memory management */
5624 gen_low_BATs(env);
5625 init_excp_604(env);
5626 env->dcache_line_size = 32;
5627 env->icache_line_size = 32;
5628 /* Allocate hardware IRQ controller */
5629 ppc6xx_irq_init(env);
5630 }
5631
5632 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5633 {
5634 DeviceClass *dc = DEVICE_CLASS(oc);
5635 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5636
5637 dc->desc = "PowerPC 604E";
5638 pcc->init_proc = init_proc_604E;
5639 pcc->check_pow = check_pow_nocheck;
5640 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5641 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5642 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5643 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5644 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5645 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5646 PPC_SEGMENT | PPC_EXTERN;
5647 pcc->msr_mask = (1ull << MSR_POW) |
5648 (1ull << MSR_ILE) |
5649 (1ull << MSR_EE) |
5650 (1ull << MSR_PR) |
5651 (1ull << MSR_FP) |
5652 (1ull << MSR_ME) |
5653 (1ull << MSR_FE0) |
5654 (1ull << MSR_SE) |
5655 (1ull << MSR_DE) |
5656 (1ull << MSR_FE1) |
5657 (1ull << MSR_EP) |
5658 (1ull << MSR_IR) |
5659 (1ull << MSR_DR) |
5660 (1ull << MSR_PMM) |
5661 (1ull << MSR_RI) |
5662 (1ull << MSR_LE);
5663 pcc->mmu_model = POWERPC_MMU_32B;
5664 #if defined(CONFIG_SOFTMMU)
5665 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5666 #endif
5667 pcc->excp_model = POWERPC_EXCP_604;
5668 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5669 pcc->bfd_mach = bfd_mach_ppc_604;
5670 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5671 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5672 }
5673
5674 static void init_proc_740 (CPUPPCState *env)
5675 {
5676 gen_spr_ne_601(env);
5677 gen_spr_7xx(env);
5678 /* Time base */
5679 gen_tbl(env);
5680 /* Thermal management */
5681 gen_spr_thrm(env);
5682 /* Hardware implementation registers */
5683 /* XXX : not implemented */
5684 spr_register(env, SPR_HID0, "HID0",
5685 SPR_NOACCESS, SPR_NOACCESS,
5686 &spr_read_generic, &spr_write_generic,
5687 0x00000000);
5688 /* XXX : not implemented */
5689 spr_register(env, SPR_HID1, "HID1",
5690 SPR_NOACCESS, SPR_NOACCESS,
5691 &spr_read_generic, &spr_write_generic,
5692 0x00000000);
5693 /* Memory management */
5694 gen_low_BATs(env);
5695 init_excp_7x0(env);
5696 env->dcache_line_size = 32;
5697 env->icache_line_size = 32;
5698 /* Allocate hardware IRQ controller */
5699 ppc6xx_irq_init(env);
5700 }
5701
5702 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5703 {
5704 DeviceClass *dc = DEVICE_CLASS(oc);
5705 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5706
5707 dc->desc = "PowerPC 740";
5708 pcc->init_proc = init_proc_740;
5709 pcc->check_pow = check_pow_hid0;
5710 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5711 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5712 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5713 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5714 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5715 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5716 PPC_SEGMENT | PPC_EXTERN;
5717 pcc->msr_mask = (1ull << MSR_POW) |
5718 (1ull << MSR_ILE) |
5719 (1ull << MSR_EE) |
5720 (1ull << MSR_PR) |
5721 (1ull << MSR_FP) |
5722 (1ull << MSR_ME) |
5723 (1ull << MSR_FE0) |
5724 (1ull << MSR_SE) |
5725 (1ull << MSR_DE) |
5726 (1ull << MSR_FE1) |
5727 (1ull << MSR_EP) |
5728 (1ull << MSR_IR) |
5729 (1ull << MSR_DR) |
5730 (1ull << MSR_PMM) |
5731 (1ull << MSR_RI) |
5732 (1ull << MSR_LE);
5733 pcc->mmu_model = POWERPC_MMU_32B;
5734 #if defined(CONFIG_SOFTMMU)
5735 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5736 #endif
5737 pcc->excp_model = POWERPC_EXCP_7x0;
5738 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5739 pcc->bfd_mach = bfd_mach_ppc_750;
5740 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5741 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5742 }
5743
5744 static void init_proc_750 (CPUPPCState *env)
5745 {
5746 gen_spr_ne_601(env);
5747 gen_spr_7xx(env);
5748 /* XXX : not implemented */
5749 spr_register(env, SPR_L2CR, "L2CR",
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_read_generic, spr_access_nop,
5752 0x00000000);
5753 /* Time base */
5754 gen_tbl(env);
5755 /* Thermal management */
5756 gen_spr_thrm(env);
5757 /* Hardware implementation registers */
5758 /* XXX : not implemented */
5759 spr_register(env, SPR_HID0, "HID0",
5760 SPR_NOACCESS, SPR_NOACCESS,
5761 &spr_read_generic, &spr_write_generic,
5762 0x00000000);
5763 /* XXX : not implemented */
5764 spr_register(env, SPR_HID1, "HID1",
5765 SPR_NOACCESS, SPR_NOACCESS,
5766 &spr_read_generic, &spr_write_generic,
5767 0x00000000);
5768 /* Memory management */
5769 gen_low_BATs(env);
5770 /* XXX: high BATs are also present but are known to be bugged on
5771 * die version 1.x
5772 */
5773 init_excp_7x0(env);
5774 env->dcache_line_size = 32;
5775 env->icache_line_size = 32;
5776 /* Allocate hardware IRQ controller */
5777 ppc6xx_irq_init(env);
5778 }
5779
5780 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5781 {
5782 DeviceClass *dc = DEVICE_CLASS(oc);
5783 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5784
5785 dc->desc = "PowerPC 750";
5786 pcc->init_proc = init_proc_750;
5787 pcc->check_pow = check_pow_hid0;
5788 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5789 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5790 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5791 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5792 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5793 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5794 PPC_SEGMENT | PPC_EXTERN;
5795 pcc->msr_mask = (1ull << MSR_POW) |
5796 (1ull << MSR_ILE) |
5797 (1ull << MSR_EE) |
5798 (1ull << MSR_PR) |
5799 (1ull << MSR_FP) |
5800 (1ull << MSR_ME) |
5801 (1ull << MSR_FE0) |
5802 (1ull << MSR_SE) |
5803 (1ull << MSR_DE) |
5804 (1ull << MSR_FE1) |
5805 (1ull << MSR_EP) |
5806 (1ull << MSR_IR) |
5807 (1ull << MSR_DR) |
5808 (1ull << MSR_PMM) |
5809 (1ull << MSR_RI) |
5810 (1ull << MSR_LE);
5811 pcc->mmu_model = POWERPC_MMU_32B;
5812 #if defined(CONFIG_SOFTMMU)
5813 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5814 #endif
5815 pcc->excp_model = POWERPC_EXCP_7x0;
5816 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5817 pcc->bfd_mach = bfd_mach_ppc_750;
5818 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5819 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5820 }
5821
5822 static void init_proc_750cl (CPUPPCState *env)
5823 {
5824 gen_spr_ne_601(env);
5825 gen_spr_7xx(env);
5826 /* XXX : not implemented */
5827 spr_register(env, SPR_L2CR, "L2CR",
5828 SPR_NOACCESS, SPR_NOACCESS,
5829 &spr_read_generic, spr_access_nop,
5830 0x00000000);
5831 /* Time base */
5832 gen_tbl(env);
5833 /* Thermal management */
5834 /* Those registers are fake on 750CL */
5835 spr_register(env, SPR_THRM1, "THRM1",
5836 SPR_NOACCESS, SPR_NOACCESS,
5837 &spr_read_generic, &spr_write_generic,
5838 0x00000000);
5839 spr_register(env, SPR_THRM2, "THRM2",
5840 SPR_NOACCESS, SPR_NOACCESS,
5841 &spr_read_generic, &spr_write_generic,
5842 0x00000000);
5843 spr_register(env, SPR_THRM3, "THRM3",
5844 SPR_NOACCESS, SPR_NOACCESS,
5845 &spr_read_generic, &spr_write_generic,
5846 0x00000000);
5847 /* XXX: not implemented */
5848 spr_register(env, SPR_750_TDCL, "TDCL",
5849 SPR_NOACCESS, SPR_NOACCESS,
5850 &spr_read_generic, &spr_write_generic,
5851 0x00000000);
5852 spr_register(env, SPR_750_TDCH, "TDCH",
5853 SPR_NOACCESS, SPR_NOACCESS,
5854 &spr_read_generic, &spr_write_generic,
5855 0x00000000);
5856 /* DMA */
5857 /* XXX : not implemented */
5858 spr_register(env, SPR_750_WPAR, "WPAR",
5859 SPR_NOACCESS, SPR_NOACCESS,
5860 &spr_read_generic, &spr_write_generic,
5861 0x00000000);
5862 spr_register(env, SPR_750_DMAL, "DMAL",
5863 SPR_NOACCESS, SPR_NOACCESS,
5864 &spr_read_generic, &spr_write_generic,
5865 0x00000000);
5866 spr_register(env, SPR_750_DMAU, "DMAU",
5867 SPR_NOACCESS, SPR_NOACCESS,
5868 &spr_read_generic, &spr_write_generic,
5869 0x00000000);
5870 /* Hardware implementation registers */
5871 /* XXX : not implemented */
5872 spr_register(env, SPR_HID0, "HID0",
5873 SPR_NOACCESS, SPR_NOACCESS,
5874 &spr_read_generic, &spr_write_generic,
5875 0x00000000);
5876 /* XXX : not implemented */
5877 spr_register(env, SPR_HID1, "HID1",
5878 SPR_NOACCESS, SPR_NOACCESS,
5879 &spr_read_generic, &spr_write_generic,
5880 0x00000000);
5881 /* XXX : not implemented */
5882 spr_register(env, SPR_750CL_HID2, "HID2",
5883 SPR_NOACCESS, SPR_NOACCESS,
5884 &spr_read_generic, &spr_write_generic,
5885 0x00000000);
5886 /* XXX : not implemented */
5887 spr_register(env, SPR_750CL_HID4, "HID4",
5888 SPR_NOACCESS, SPR_NOACCESS,
5889 &spr_read_generic, &spr_write_generic,
5890 0x00000000);
5891 /* Quantization registers */
5892 /* XXX : not implemented */
5893 spr_register(env, SPR_750_GQR0, "GQR0",
5894 SPR_NOACCESS, SPR_NOACCESS,
5895 &spr_read_generic, &spr_write_generic,
5896 0x00000000);
5897 /* XXX : not implemented */
5898 spr_register(env, SPR_750_GQR1, "GQR1",
5899 SPR_NOACCESS, SPR_NOACCESS,
5900 &spr_read_generic, &spr_write_generic,
5901 0x00000000);
5902 /* XXX : not implemented */
5903 spr_register(env, SPR_750_GQR2, "GQR2",
5904 SPR_NOACCESS, SPR_NOACCESS,
5905 &spr_read_generic, &spr_write_generic,
5906 0x00000000);
5907 /* XXX : not implemented */
5908 spr_register(env, SPR_750_GQR3, "GQR3",
5909 SPR_NOACCESS, SPR_NOACCESS,
5910 &spr_read_generic, &spr_write_generic,
5911 0x00000000);
5912 /* XXX : not implemented */
5913 spr_register(env, SPR_750_GQR4, "GQR4",
5914 SPR_NOACCESS, SPR_NOACCESS,
5915 &spr_read_generic, &spr_write_generic,
5916 0x00000000);
5917 /* XXX : not implemented */
5918 spr_register(env, SPR_750_GQR5, "GQR5",
5919 SPR_NOACCESS, SPR_NOACCESS,
5920 &spr_read_generic, &spr_write_generic,
5921 0x00000000);
5922 /* XXX : not implemented */
5923 spr_register(env, SPR_750_GQR6, "GQR6",
5924 SPR_NOACCESS, SPR_NOACCESS,
5925 &spr_read_generic, &spr_write_generic,
5926 0x00000000);
5927 /* XXX : not implemented */
5928 spr_register(env, SPR_750_GQR7, "GQR7",
5929 SPR_NOACCESS, SPR_NOACCESS,
5930 &spr_read_generic, &spr_write_generic,
5931 0x00000000);
5932 /* Memory management */
5933 gen_low_BATs(env);
5934 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5935 gen_high_BATs(env);
5936 init_excp_750cl(env);
5937 env->dcache_line_size = 32;
5938 env->icache_line_size = 32;
5939 /* Allocate hardware IRQ controller */
5940 ppc6xx_irq_init(env);
5941 }
5942
5943 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5944 {
5945 DeviceClass *dc = DEVICE_CLASS(oc);
5946 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5947
5948 dc->desc = "PowerPC 750 CL";
5949 pcc->init_proc = init_proc_750cl;
5950 pcc->check_pow = check_pow_hid0;
5951 /* XXX: not implemented:
5952 * cache lock instructions:
5953 * dcbz_l
5954 * floating point paired instructions
5955 * psq_lux
5956 * psq_lx
5957 * psq_stux
5958 * psq_stx
5959 * ps_abs
5960 * ps_add
5961 * ps_cmpo0
5962 * ps_cmpo1
5963 * ps_cmpu0
5964 * ps_cmpu1
5965 * ps_div
5966 * ps_madd
5967 * ps_madds0
5968 * ps_madds1
5969 * ps_merge00
5970 * ps_merge01
5971 * ps_merge10
5972 * ps_merge11
5973 * ps_mr
5974 * ps_msub
5975 * ps_mul
5976 * ps_muls0
5977 * ps_muls1
5978 * ps_nabs
5979 * ps_neg
5980 * ps_nmadd
5981 * ps_nmsub
5982 * ps_res
5983 * ps_rsqrte
5984 * ps_sel
5985 * ps_sub
5986 * ps_sum0
5987 * ps_sum1
5988 */
5989 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5990 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5991 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5992 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5993 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5995 PPC_SEGMENT | PPC_EXTERN;
5996 pcc->msr_mask = (1ull << MSR_POW) |
5997 (1ull << MSR_ILE) |
5998 (1ull << MSR_EE) |
5999 (1ull << MSR_PR) |
6000 (1ull << MSR_FP) |
6001 (1ull << MSR_ME) |
6002 (1ull << MSR_FE0) |
6003 (1ull << MSR_SE) |
6004 (1ull << MSR_DE) |
6005 (1ull << MSR_FE1) |
6006 (1ull << MSR_EP) |
6007 (1ull << MSR_IR) |
6008 (1ull << MSR_DR) |
6009 (1ull << MSR_PMM) |
6010 (1ull << MSR_RI) |
6011 (1ull << MSR_LE);
6012 pcc->mmu_model = POWERPC_MMU_32B;
6013 #if defined(CONFIG_SOFTMMU)
6014 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6015 #endif
6016 pcc->excp_model = POWERPC_EXCP_7x0;
6017 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6018 pcc->bfd_mach = bfd_mach_ppc_750;
6019 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6020 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6021 }
6022
6023 static void init_proc_750cx (CPUPPCState *env)
6024 {
6025 gen_spr_ne_601(env);
6026 gen_spr_7xx(env);
6027 /* XXX : not implemented */
6028 spr_register(env, SPR_L2CR, "L2CR",
6029 SPR_NOACCESS, SPR_NOACCESS,
6030 &spr_read_generic, spr_access_nop,
6031 0x00000000);
6032 /* Time base */
6033 gen_tbl(env);
6034 /* Thermal management */
6035 gen_spr_thrm(env);
6036 /* This register is not implemented but is present for compatibility */
6037 spr_register(env, SPR_SDA, "SDA",
6038 SPR_NOACCESS, SPR_NOACCESS,
6039 &spr_read_generic, &spr_write_generic,
6040 0x00000000);
6041 /* Hardware implementation registers */
6042 /* XXX : not implemented */
6043 spr_register(env, SPR_HID0, "HID0",
6044 SPR_NOACCESS, SPR_NOACCESS,
6045 &spr_read_generic, &spr_write_generic,
6046 0x00000000);
6047 /* XXX : not implemented */
6048 spr_register(env, SPR_HID1, "HID1",
6049 SPR_NOACCESS, SPR_NOACCESS,
6050 &spr_read_generic, &spr_write_generic,
6051 0x00000000);
6052 /* Memory management */
6053 gen_low_BATs(env);
6054 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
6055 gen_high_BATs(env);
6056 init_excp_750cx(env);
6057 env->dcache_line_size = 32;
6058 env->icache_line_size = 32;
6059 /* Allocate hardware IRQ controller */
6060 ppc6xx_irq_init(env);
6061 }
6062
6063 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
6064 {
6065 DeviceClass *dc = DEVICE_CLASS(oc);
6066 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6067
6068 dc->desc = "PowerPC 750CX";
6069 pcc->init_proc = init_proc_750cx;
6070 pcc->check_pow = check_pow_hid0;
6071 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6072 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6073 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6074 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6075 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6076 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6077 PPC_SEGMENT | PPC_EXTERN;
6078 pcc->msr_mask = (1ull << MSR_POW) |
6079 (1ull << MSR_ILE) |
6080 (1ull << MSR_EE) |
6081 (1ull << MSR_PR) |
6082 (1ull << MSR_FP) |
6083 (1ull << MSR_ME) |
6084 (1ull << MSR_FE0) |
6085 (1ull << MSR_SE) |
6086 (1ull << MSR_DE) |
6087 (1ull << MSR_FE1) |
6088 (1ull << MSR_EP) |
6089 (1ull << MSR_IR) |
6090 (1ull << MSR_DR) |
6091 (1ull << MSR_PMM) |
6092 (1ull << MSR_RI) |
6093 (1ull << MSR_LE);
6094 pcc->mmu_model = POWERPC_MMU_32B;
6095 #if defined(CONFIG_SOFTMMU)
6096 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6097 #endif
6098 pcc->excp_model = POWERPC_EXCP_7x0;
6099 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6100 pcc->bfd_mach = bfd_mach_ppc_750;
6101 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6102 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6103 }
6104
6105 static void init_proc_750fx (CPUPPCState *env)
6106 {
6107 gen_spr_ne_601(env);
6108 gen_spr_7xx(env);
6109 /* XXX : not implemented */
6110 spr_register(env, SPR_L2CR, "L2CR",
6111 SPR_NOACCESS, SPR_NOACCESS,
6112 &spr_read_generic, spr_access_nop,
6113 0x00000000);
6114 /* Time base */
6115 gen_tbl(env);
6116 /* Thermal management */
6117 gen_spr_thrm(env);
6118 /* XXX : not implemented */
6119 spr_register(env, SPR_750_THRM4, "THRM4",
6120 SPR_NOACCESS, SPR_NOACCESS,
6121 &spr_read_generic, &spr_write_generic,
6122 0x00000000);
6123 /* Hardware implementation registers */
6124 /* XXX : not implemented */
6125 spr_register(env, SPR_HID0, "HID0",
6126 SPR_NOACCESS, SPR_NOACCESS,
6127 &spr_read_generic, &spr_write_generic,
6128 0x00000000);
6129 /* XXX : not implemented */
6130 spr_register(env, SPR_HID1, "HID1",
6131 SPR_NOACCESS, SPR_NOACCESS,
6132 &spr_read_generic, &spr_write_generic,
6133 0x00000000);
6134 /* XXX : not implemented */
6135 spr_register(env, SPR_750FX_HID2, "HID2",
6136 SPR_NOACCESS, SPR_NOACCESS,
6137 &spr_read_generic, &spr_write_generic,
6138 0x00000000);
6139 /* Memory management */
6140 gen_low_BATs(env);
6141 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6142 gen_high_BATs(env);
6143 init_excp_7x0(env);
6144 env->dcache_line_size = 32;
6145 env->icache_line_size = 32;
6146 /* Allocate hardware IRQ controller */
6147 ppc6xx_irq_init(env);
6148 }
6149
6150 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
6151 {
6152 DeviceClass *dc = DEVICE_CLASS(oc);
6153 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6154
6155 dc->desc = "PowerPC 750FX";
6156 pcc->init_proc = init_proc_750fx;
6157 pcc->check_pow = check_pow_hid0;
6158 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6159 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6160 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6161 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6162 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6163 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6164 PPC_SEGMENT | PPC_EXTERN;
6165 pcc->msr_mask = (1ull << MSR_POW) |
6166 (1ull << MSR_ILE) |
6167 (1ull << MSR_EE) |
6168 (1ull << MSR_PR) |
6169 (1ull << MSR_FP) |
6170 (1ull << MSR_ME) |
6171 (1ull << MSR_FE0) |
6172 (1ull << MSR_SE) |
6173 (1ull << MSR_DE) |
6174 (1ull << MSR_FE1) |
6175 (1ull << MSR_EP) |
6176 (1ull << MSR_IR) |
6177 (1ull << MSR_DR) |
6178 (1ull << MSR_PMM) |
6179 (1ull << MSR_RI) |
6180 (1ull << MSR_LE);
6181 pcc->mmu_model = POWERPC_MMU_32B;
6182 #if defined(CONFIG_SOFTMMU)
6183 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6184 #endif
6185 pcc->excp_model = POWERPC_EXCP_7x0;
6186 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6187 pcc->bfd_mach = bfd_mach_ppc_750;
6188 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6189 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6190 }
6191
6192 static void init_proc_750gx (CPUPPCState *env)
6193 {
6194 gen_spr_ne_601(env);
6195 gen_spr_7xx(env);
6196 /* XXX : not implemented (XXX: different from 750fx) */
6197 spr_register(env, SPR_L2CR, "L2CR",
6198 SPR_NOACCESS, SPR_NOACCESS,
6199 &spr_read_generic, spr_access_nop,
6200 0x00000000);
6201 /* Time base */
6202 gen_tbl(env);
6203 /* Thermal management */
6204 gen_spr_thrm(env);
6205 /* XXX : not implemented */
6206 spr_register(env, SPR_750_THRM4, "THRM4",
6207 SPR_NOACCESS, SPR_NOACCESS,
6208 &spr_read_generic, &spr_write_generic,
6209 0x00000000);
6210 /* Hardware implementation registers */
6211 /* XXX : not implemented (XXX: different from 750fx) */
6212 spr_register(env, SPR_HID0, "HID0",
6213 SPR_NOACCESS, SPR_NOACCESS,
6214 &spr_read_generic, &spr_write_generic,
6215 0x00000000);
6216 /* XXX : not implemented */
6217 spr_register(env, SPR_HID1, "HID1",
6218 SPR_NOACCESS, SPR_NOACCESS,
6219 &spr_read_generic, &spr_write_generic,
6220 0x00000000);
6221 /* XXX : not implemented (XXX: different from 750fx) */
6222 spr_register(env, SPR_750FX_HID2, "HID2",
6223 SPR_NOACCESS, SPR_NOACCESS,
6224 &spr_read_generic, &spr_write_generic,
6225 0x00000000);
6226 /* Memory management */
6227 gen_low_BATs(env);
6228 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6229 gen_high_BATs(env);
6230 init_excp_7x0(env);
6231 env->dcache_line_size = 32;
6232 env->icache_line_size = 32;
6233 /* Allocate hardware IRQ controller */
6234 ppc6xx_irq_init(env);
6235 }
6236
6237 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6238 {
6239 DeviceClass *dc = DEVICE_CLASS(oc);
6240 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6241
6242 dc->desc = "PowerPC 750GX";
6243 pcc->init_proc = init_proc_750gx;
6244 pcc->check_pow = check_pow_hid0;
6245 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6246 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6247 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6248 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6249 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6250 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6251 PPC_SEGMENT | PPC_EXTERN;
6252 pcc->msr_mask = (1ull << MSR_POW) |
6253 (1ull << MSR_ILE) |
6254 (1ull << MSR_EE) |
6255 (1ull << MSR_PR) |
6256 (1ull << MSR_FP) |
6257 (1ull << MSR_ME) |
6258 (1ull << MSR_FE0) |
6259 (1ull << MSR_SE) |
6260 (1ull << MSR_DE) |
6261 (1ull << MSR_FE1) |
6262 (1ull << MSR_EP) |
6263 (1ull << MSR_IR) |
6264 (1ull << MSR_DR) |
6265 (1ull << MSR_PMM) |
6266 (1ull << MSR_RI) |
6267 (1ull << MSR_LE);
6268 pcc->mmu_model = POWERPC_MMU_32B;
6269 #if defined(CONFIG_SOFTMMU)
6270 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6271 #endif
6272 pcc->excp_model = POWERPC_EXCP_7x0;
6273 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6274 pcc->bfd_mach = bfd_mach_ppc_750;
6275 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6276 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6277 }
6278
6279 static void init_proc_745 (CPUPPCState *env)
6280 {
6281 gen_spr_ne_601(env);
6282 gen_spr_7xx(env);
6283 gen_spr_G2_755(env);
6284 /* Time base */
6285 gen_tbl(env);
6286 /* Thermal management */
6287 gen_spr_thrm(env);
6288 /* Hardware implementation registers */
6289 /* XXX : not implemented */
6290 spr_register(env, SPR_HID0, "HID0",
6291 SPR_NOACCESS, SPR_NOACCESS,
6292 &spr_read_generic, &spr_write_generic,
6293 0x00000000);
6294 /* XXX : not implemented */
6295 spr_register(env, SPR_HID1, "HID1",
6296 SPR_NOACCESS, SPR_NOACCESS,
6297 &spr_read_generic, &spr_write_generic,
6298 0x00000000);
6299 /* XXX : not implemented */
6300 spr_register(env, SPR_HID2, "HID2",
6301 SPR_NOACCESS, SPR_NOACCESS,
6302 &spr_read_generic, &spr_write_generic,
6303 0x00000000);
6304 /* Memory management */
6305 gen_low_BATs(env);
6306 gen_high_BATs(env);
6307 gen_6xx_7xx_soft_tlb(env, 64, 2);
6308 init_excp_7x5(env);
6309 env->dcache_line_size = 32;
6310 env->icache_line_size = 32;
6311 /* Allocate hardware IRQ controller */
6312 ppc6xx_irq_init(env);
6313 }
6314
6315 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6316 {
6317 DeviceClass *dc = DEVICE_CLASS(oc);
6318 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6319
6320 dc->desc = "PowerPC 745";
6321 pcc->init_proc = init_proc_745;
6322 pcc->check_pow = check_pow_hid0;
6323 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6324 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6325 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6326 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6327 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6328 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6329 PPC_SEGMENT | PPC_EXTERN;
6330 pcc->msr_mask = (1ull << MSR_POW) |
6331 (1ull << MSR_ILE) |
6332 (1ull << MSR_EE) |
6333 (1ull << MSR_PR) |
6334 (1ull << MSR_FP) |
6335 (1ull << MSR_ME) |
6336 (1ull << MSR_FE0) |
6337 (1ull << MSR_SE) |
6338 (1ull << MSR_DE) |
6339 (1ull << MSR_FE1) |
6340 (1ull << MSR_EP) |
6341 (1ull << MSR_IR) |
6342 (1ull << MSR_DR) |
6343 (1ull << MSR_PMM) |
6344 (1ull << MSR_RI) |
6345 (1ull << MSR_LE);
6346 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6347 pcc->excp_model = POWERPC_EXCP_7x5;
6348 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6349 pcc->bfd_mach = bfd_mach_ppc_750;
6350 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6351 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6352 }
6353
6354 static void init_proc_755 (CPUPPCState *env)
6355 {
6356 gen_spr_ne_601(env);
6357 gen_spr_7xx(env);
6358 gen_spr_G2_755(env);
6359 /* Time base */
6360 gen_tbl(env);
6361 /* L2 cache control */
6362 /* XXX : not implemented */
6363 spr_register(env, SPR_L2CR, "L2CR",
6364 SPR_NOACCESS, SPR_NOACCESS,
6365 &spr_read_generic, spr_access_nop,
6366 0x00000000);
6367 /* XXX : not implemented */
6368 spr_register(env, SPR_L2PMCR, "L2PMCR",
6369 SPR_NOACCESS, SPR_NOACCESS,
6370 &spr_read_generic, &spr_write_generic,
6371 0x00000000);
6372 /* Thermal management */
6373 gen_spr_thrm(env);
6374 /* Hardware implementation registers */
6375 /* XXX : not implemented */
6376 spr_register(env, SPR_HID0, "HID0",
6377 SPR_NOACCESS, SPR_NOACCESS,
6378 &spr_read_generic, &spr_write_generic,
6379 0x00000000);
6380 /* XXX : not implemented */
6381 spr_register(env, SPR_HID1, "HID1",
6382 SPR_NOACCESS, SPR_NOACCESS,
6383 &spr_read_generic, &spr_write_generic,
6384 0x00000000);
6385 /* XXX : not implemented */
6386 spr_register(env, SPR_HID2, "HID2",
6387 SPR_NOACCESS, SPR_NOACCESS,
6388 &spr_read_generic, &spr_write_generic,
6389 0x00000000);
6390 /* Memory management */
6391 gen_low_BATs(env);
6392 gen_high_BATs(env);
6393 gen_6xx_7xx_soft_tlb(env, 64, 2);
6394 init_excp_7x5(env);
6395 env->dcache_line_size = 32;
6396 env->icache_line_size = 32;
6397 /* Allocate hardware IRQ controller */
6398 ppc6xx_irq_init(env);
6399 }
6400
6401 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6402 {
6403 DeviceClass *dc = DEVICE_CLASS(oc);
6404 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6405
6406 dc->desc = "PowerPC 755";
6407 pcc->init_proc = init_proc_755;
6408 pcc->check_pow = check_pow_hid0;
6409 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6410 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6411 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6412 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6413 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6414 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6415 PPC_SEGMENT | PPC_EXTERN;
6416 pcc->msr_mask = (1ull << MSR_POW) |
6417 (1ull << MSR_ILE) |
6418 (1ull << MSR_EE) |
6419 (1ull << MSR_PR) |
6420 (1ull << MSR_FP) |
6421 (1ull << MSR_ME) |
6422 (1ull << MSR_FE0) |
6423 (1ull << MSR_SE) |
6424 (1ull << MSR_DE) |
6425 (1ull << MSR_FE1) |
6426 (1ull << MSR_EP) |
6427 (1ull << MSR_IR) |
6428 (1ull << MSR_DR) |
6429 (1ull << MSR_PMM) |
6430 (1ull << MSR_RI) |
6431 (1ull << MSR_LE);
6432 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6433 pcc->excp_model = POWERPC_EXCP_7x5;
6434 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6435 pcc->bfd_mach = bfd_mach_ppc_750;
6436 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6437 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6438 }
6439
6440 static void init_proc_7400 (CPUPPCState *env)
6441 {
6442 gen_spr_ne_601(env);
6443 gen_spr_7xx(env);
6444 /* Time base */
6445 gen_tbl(env);
6446 /* 74xx specific SPR */
6447 gen_spr_74xx(env);
6448 /* XXX : not implemented */
6449 spr_register(env, SPR_UBAMR, "UBAMR",
6450 &spr_read_ureg, SPR_NOACCESS,
6451 &spr_read_ureg, SPR_NOACCESS,
6452 0x00000000);
6453 /* XXX: this seems not implemented on all revisions. */
6454 /* XXX : not implemented */
6455 spr_register(env, SPR_MSSCR1, "MSSCR1",
6456 SPR_NOACCESS, SPR_NOACCESS,
6457 &spr_read_generic, &spr_write_generic,
6458 0x00000000);
6459 /* Thermal management */
6460 gen_spr_thrm(env);
6461 /* Memory management */
6462 gen_low_BATs(env);
6463 init_excp_7400(env);
6464 env->dcache_line_size = 32;
6465 env->icache_line_size = 32;
6466 /* Allocate hardware IRQ controller */
6467 ppc6xx_irq_init(env);
6468 }
6469
6470 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6471 {
6472 DeviceClass *dc = DEVICE_CLASS(oc);
6473 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6474
6475 dc->desc = "PowerPC 7400 (aka G4)";
6476 pcc->init_proc = init_proc_7400;
6477 pcc->check_pow = check_pow_hid0;
6478 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6479 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6480 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6481 PPC_FLOAT_STFIWX |
6482 PPC_CACHE | PPC_CACHE_ICBI |
6483 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6484 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6485 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6486 PPC_MEM_TLBIA |
6487 PPC_SEGMENT | PPC_EXTERN |
6488 PPC_ALTIVEC;
6489 pcc->msr_mask = (1ull << MSR_VR) |
6490 (1ull << MSR_POW) |
6491 (1ull << MSR_ILE) |
6492 (1ull << MSR_EE) |
6493 (1ull << MSR_PR) |
6494 (1ull << MSR_FP) |
6495 (1ull << MSR_ME) |
6496 (1ull << MSR_FE0) |
6497 (1ull << MSR_SE) |
6498 (1ull << MSR_DE) |
6499 (1ull << MSR_FE1) |
6500 (1ull << MSR_EP) |
6501 (1ull << MSR_IR) |
6502 (1ull << MSR_DR) |
6503 (1ull << MSR_PMM) |
6504 (1ull << MSR_RI) |
6505 (1ull << MSR_LE);
6506 pcc->mmu_model = POWERPC_MMU_32B;
6507 #if defined(CONFIG_SOFTMMU)
6508 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6509 #endif
6510 pcc->excp_model = POWERPC_EXCP_74xx;
6511 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6512 pcc->bfd_mach = bfd_mach_ppc_7400;
6513 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6514 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6515 POWERPC_FLAG_BUS_CLK;
6516 }
6517
6518 static void init_proc_7410 (CPUPPCState *env)
6519 {
6520 gen_spr_ne_601(env);
6521 gen_spr_7xx(env);
6522 /* Time base */
6523 gen_tbl(env);
6524 /* 74xx specific SPR */
6525 gen_spr_74xx(env);
6526 /* XXX : not implemented */
6527 spr_register(env, SPR_UBAMR, "UBAMR",
6528 &spr_read_ureg, SPR_NOACCESS,
6529 &spr_read_ureg, SPR_NOACCESS,
6530 0x00000000);
6531 /* Thermal management */
6532 gen_spr_thrm(env);
6533 /* L2PMCR */
6534 /* XXX : not implemented */
6535 spr_register(env, SPR_L2PMCR, "L2PMCR",
6536 SPR_NOACCESS, SPR_NOACCESS,
6537 &spr_read_generic, &spr_write_generic,
6538 0x00000000);
6539 /* LDSTDB */
6540 /* XXX : not implemented */
6541 spr_register(env, SPR_LDSTDB, "LDSTDB",
6542 SPR_NOACCESS, SPR_NOACCESS,
6543 &spr_read_generic, &spr_write_generic,
6544 0x00000000);
6545 /* Memory management */
6546 gen_low_BATs(env);
6547 init_excp_7400(env);
6548 env->dcache_line_size = 32;
6549 env->icache_line_size = 32;
6550 /* Allocate hardware IRQ controller */
6551 ppc6xx_irq_init(env);
6552 }
6553
6554 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6555 {
6556 DeviceClass *dc = DEVICE_CLASS(oc);
6557 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6558
6559 dc->desc = "PowerPC 7410 (aka G4)";
6560 pcc->init_proc = init_proc_7410;
6561 pcc->check_pow = check_pow_hid0;
6562 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6563 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6564 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6565 PPC_FLOAT_STFIWX |
6566 PPC_CACHE | PPC_CACHE_ICBI |
6567 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6568 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6569 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6570 PPC_MEM_TLBIA |
6571 PPC_SEGMENT | PPC_EXTERN |
6572 PPC_ALTIVEC;
6573 pcc->msr_mask = (1ull << MSR_VR) |
6574 (1ull << MSR_POW) |
6575 (1ull << MSR_ILE) |
6576 (1ull << MSR_EE) |
6577 (1ull << MSR_PR) |
6578 (1ull << MSR_FP) |
6579 (1ull << MSR_ME) |
6580 (1ull << MSR_FE0) |
6581 (1ull << MSR_SE) |
6582 (1ull << MSR_DE) |
6583 (1ull << MSR_FE1) |
6584 (1ull << MSR_EP) |
6585 (1ull << MSR_IR) |
6586 (1ull << MSR_DR) |
6587 (1ull << MSR_PMM) |
6588 (1ull << MSR_RI) |
6589 (1ull << MSR_LE);
6590 pcc->mmu_model = POWERPC_MMU_32B;
6591 #if defined(CONFIG_SOFTMMU)
6592 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6593 #endif
6594 pcc->excp_model = POWERPC_EXCP_74xx;
6595 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6596 pcc->bfd_mach = bfd_mach_ppc_7400;
6597 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6598 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6599 POWERPC_FLAG_BUS_CLK;
6600 }
6601
6602 static void init_proc_7440 (CPUPPCState *env)
6603 {
6604 gen_spr_ne_601(env);
6605 gen_spr_7xx(env);
6606 /* Time base */
6607 gen_tbl(env);
6608 /* 74xx specific SPR */
6609 gen_spr_74xx(env);
6610 /* XXX : not implemented */
6611 spr_register(env, SPR_UBAMR, "UBAMR",
6612 &spr_read_ureg, SPR_NOACCESS,
6613 &spr_read_ureg, SPR_NOACCESS,
6614 0x00000000);
6615 /* LDSTCR */
6616 /* XXX : not implemented */
6617 spr_register(env, SPR_LDSTCR, "LDSTCR",
6618 SPR_NOACCESS, SPR_NOACCESS,
6619 &spr_read_generic, &spr_write_generic,
6620 0x00000000);
6621 /* ICTRL */
6622 /* XXX : not implemented */
6623 spr_register(env, SPR_ICTRL, "ICTRL",
6624 SPR_NOACCESS, SPR_NOACCESS,
6625 &spr_read_generic, &spr_write_generic,
6626 0x00000000);
6627 /* MSSSR0 */
6628 /* XXX : not implemented */
6629 spr_register(env, SPR_MSSSR0, "MSSSR0",
6630 SPR_NOACCESS, SPR_NOACCESS,
6631 &spr_read_generic, &spr_write_generic,
6632 0x00000000);
6633 /* PMC */
6634 /* XXX : not implemented */
6635 spr_register(env, SPR_7XX_PMC5, "PMC5",
6636 SPR_NOACCESS, SPR_NOACCESS,
6637 &spr_read_generic, &spr_write_generic,
6638 0x00000000);
6639 /* XXX : not implemented */
6640 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6641 &spr_read_ureg, SPR_NOACCESS,
6642 &spr_read_ureg, SPR_NOACCESS,
6643 0x00000000);
6644 /* XXX : not implemented */
6645 spr_register(env, SPR_7XX_PMC6, "PMC6",
6646 SPR_NOACCESS, SPR_NOACCESS,
6647 &spr_read_generic, &spr_write_generic,
6648 0x00000000);
6649 /* XXX : not implemented */
6650 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6651 &spr_read_ureg, SPR_NOACCESS,
6652 &spr_read_ureg, SPR_NOACCESS,
6653 0x00000000);
6654 /* Memory management */
6655 gen_low_BATs(env);
6656 gen_74xx_soft_tlb(env, 128, 2);
6657 init_excp_7450(env);
6658 env->dcache_line_size = 32;
6659 env->icache_line_size = 32;
6660 /* Allocate hardware IRQ controller */
6661 ppc6xx_irq_init(env);
6662 }
6663
6664 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6665 {
6666 DeviceClass *dc = DEVICE_CLASS(oc);
6667 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6668
6669 dc->desc = "PowerPC 7440 (aka G4)";
6670 pcc->init_proc = init_proc_7440;
6671 pcc->check_pow = check_pow_hid0_74xx;
6672 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6673 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6674 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6675 PPC_FLOAT_STFIWX |
6676 PPC_CACHE | PPC_CACHE_ICBI |
6677 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6678 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6679 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6680 PPC_MEM_TLBIA | PPC_74xx_TLB |
6681 PPC_SEGMENT | PPC_EXTERN |
6682 PPC_ALTIVEC;
6683 pcc->msr_mask = (1ull << MSR_VR) |
6684 (1ull << MSR_POW) |
6685 (1ull << MSR_ILE) |
6686 (1ull << MSR_EE) |
6687 (1ull << MSR_PR) |
6688 (1ull << MSR_FP) |
6689 (1ull << MSR_ME) |
6690 (1ull << MSR_FE0) |
6691 (1ull << MSR_SE) |
6692 (1ull << MSR_DE) |
6693 (1ull << MSR_FE1) |
6694 (1ull << MSR_EP) |
6695 (1ull << MSR_IR) |
6696 (1ull << MSR_DR) |
6697 (1ull << MSR_PMM) |
6698 (1ull << MSR_RI) |
6699 (1ull << MSR_LE);
6700 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6701 pcc->excp_model = POWERPC_EXCP_74xx;
6702 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6703 pcc->bfd_mach = bfd_mach_ppc_7400;
6704 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6705 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6706 POWERPC_FLAG_BUS_CLK;
6707 }
6708
6709 static void init_proc_7450 (CPUPPCState *env)
6710 {
6711 gen_spr_ne_601(env);
6712 gen_spr_7xx(env);
6713 /* Time base */
6714 gen_tbl(env);
6715 /* 74xx specific SPR */
6716 gen_spr_74xx(env);
6717 /* Level 3 cache control */
6718 gen_l3_ctrl(env);
6719 /* L3ITCR1 */
6720 /* XXX : not implemented */
6721 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6722 SPR_NOACCESS, SPR_NOACCESS,
6723 &spr_read_generic, &spr_write_generic,
6724 0x00000000);
6725 /* L3ITCR2 */
6726 /* XXX : not implemented */
6727 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6728 SPR_NOACCESS, SPR_NOACCESS,
6729 &spr_read_generic, &spr_write_generic,
6730 0x00000000);
6731 /* L3ITCR3 */
6732 /* XXX : not implemented */
6733 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6734 SPR_NOACCESS, SPR_NOACCESS,
6735 &spr_read_generic, &spr_write_generic,
6736 0x00000000);
6737 /* L3OHCR */
6738 /* XXX : not implemented */
6739 spr_register(env, SPR_L3OHCR, "L3OHCR",
6740 SPR_NOACCESS, SPR_NOACCESS,
6741 &spr_read_generic, &spr_write_generic,
6742 0x00000000);
6743 /* XXX : not implemented */
6744 spr_register(env, SPR_UBAMR, "UBAMR",
6745 &spr_read_ureg, SPR_NOACCESS,
6746 &spr_read_ureg, SPR_NOACCESS,
6747 0x00000000);
6748 /* LDSTCR */
6749 /* XXX : not implemented */
6750 spr_register(env, SPR_LDSTCR, "LDSTCR",
6751 SPR_NOACCESS, SPR_NOACCESS,
6752 &spr_read_generic, &spr_write_generic,
6753 0x00000000);
6754 /* ICTRL */
6755 /* XXX : not implemented */
6756 spr_register(env, SPR_ICTRL, "ICTRL",
6757 SPR_NOACCESS, SPR_NOACCESS,
6758 &spr_read_generic, &spr_write_generic,
6759 0x00000000);
6760 /* MSSSR0 */
6761 /* XXX : not implemented */
6762 spr_register(env, SPR_MSSSR0, "MSSSR0",
6763 SPR_NOACCESS, SPR_NOACCESS,
6764 &spr_read_generic, &spr_write_generic,
6765 0x00000000);
6766 /* PMC */
6767 /* XXX : not implemented */
6768 spr_register(env, SPR_7XX_PMC5, "PMC5",
6769 SPR_NOACCESS, SPR_NOACCESS,
6770 &spr_read_generic, &spr_write_generic,
6771 0x00000000);
6772 /* XXX : not implemented */
6773 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6774 &spr_read_ureg, SPR_NOACCESS,
6775 &spr_read_ureg, SPR_NOACCESS,
6776 0x00000000);
6777 /* XXX : not implemented */
6778 spr_register(env, SPR_7XX_PMC6, "PMC6",
6779 SPR_NOACCESS, SPR_NOACCESS,
6780 &spr_read_generic, &spr_write_generic,
6781 0x00000000);
6782 /* XXX : not implemented */
6783 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6784 &spr_read_ureg, SPR_NOACCESS,
6785 &spr_read_ureg, SPR_NOACCESS,
6786 0x00000000);
6787 /* Memory management */
6788 gen_low_BATs(env);
6789 gen_74xx_soft_tlb(env, 128, 2);
6790 init_excp_7450(env);
6791 env->dcache_line_size = 32;
6792 env->icache_line_size = 32;
6793 /* Allocate hardware IRQ controller */
6794 ppc6xx_irq_init(env);
6795 }
6796
6797 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6798 {
6799 DeviceClass *dc = DEVICE_CLASS(oc);
6800 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6801
6802 dc->desc = "PowerPC 7450 (aka G4)";
6803 pcc->init_proc = init_proc_7450;
6804 pcc->check_pow = check_pow_hid0_74xx;
6805 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6806 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6807 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6808 PPC_FLOAT_STFIWX |
6809 PPC_CACHE | PPC_CACHE_ICBI |
6810 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6811 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6812 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6813 PPC_MEM_TLBIA | PPC_74xx_TLB |
6814 PPC_SEGMENT | PPC_EXTERN |
6815 PPC_ALTIVEC;
6816 pcc->msr_mask = (1ull << MSR_VR) |
6817 (1ull << MSR_POW) |
6818 (1ull << MSR_ILE) |
6819 (1ull << MSR_EE) |
6820 (1ull << MSR_PR) |
6821 (1ull << MSR_FP) |
6822 (1ull << MSR_ME) |
6823 (1ull << MSR_FE0) |
6824 (1ull << MSR_SE) |
6825 (1ull << MSR_DE) |
6826 (1ull << MSR_FE1) |
6827 (1ull << MSR_EP) |
6828 (1ull << MSR_IR) |
6829 (1ull << MSR_DR) |
6830 (1ull << MSR_PMM) |
6831 (1ull << MSR_RI) |
6832 (1ull << MSR_LE);
6833 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6834 pcc->excp_model = POWERPC_EXCP_74xx;
6835 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6836 pcc->bfd_mach = bfd_mach_ppc_7400;
6837 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6838 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6839 POWERPC_FLAG_BUS_CLK;
6840 }
6841
6842 static void init_proc_7445 (CPUPPCState *env)
6843 {
6844 gen_spr_ne_601(env);
6845 gen_spr_7xx(env);
6846 /* Time base */
6847 gen_tbl(env);
6848 /* 74xx specific SPR */
6849 gen_spr_74xx(env);
6850 /* LDSTCR */
6851 /* XXX : not implemented */
6852 spr_register(env, SPR_LDSTCR, "LDSTCR",
6853 SPR_NOACCESS, SPR_NOACCESS,
6854 &spr_read_generic, &spr_write_generic,
6855 0x00000000);
6856 /* ICTRL */
6857 /* XXX : not implemented */
6858 spr_register(env, SPR_ICTRL, "ICTRL",
6859 SPR_NOACCESS, SPR_NOACCESS,
6860 &spr_read_generic, &spr_write_generic,
6861 0x00000000);
6862 /* MSSSR0 */
6863 /* XXX : not implemented */
6864 spr_register(env, SPR_MSSSR0, "MSSSR0",
6865 SPR_NOACCESS, SPR_NOACCESS,
6866 &spr_read_generic, &spr_write_generic,
6867 0x00000000);
6868 /* PMC */
6869 /* XXX : not implemented */
6870 spr_register(env, SPR_7XX_PMC5, "PMC5",
6871 SPR_NOACCESS, SPR_NOACCESS,
6872 &spr_read_generic, &spr_write_generic,
6873 0x00000000);
6874 /* XXX : not implemented */
6875 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
6876 &spr_read_ureg, SPR_NOACCESS,
6877 &spr_read_ureg, SPR_NOACCESS,
6878 0x00000000);
6879 /* XXX : not implemented */
6880 spr_register(env, SPR_7XX_PMC6, "PMC6",
6881 SPR_NOACCESS, SPR_NOACCESS,
6882 &spr_read_generic, &spr_write_generic,
6883 0x00000000);
6884 /* XXX : not implemented */
6885 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
6886 &spr_read_ureg, SPR_NOACCESS,
6887 &spr_read_ureg, SPR_NOACCESS,
6888 0x00000000);
6889 /* SPRGs */
6890 spr_register(env, SPR_SPRG4, "SPRG4",
6891 SPR_NOACCESS, SPR_NOACCESS,
6892 &spr_read_generic, &spr_write_generic,
6893 0x00000000);
6894 spr_register(env, SPR_USPRG4, "USPRG4",
6895 &spr_read_ureg, SPR_NOACCESS,
6896 &spr_read_ureg, SPR_NOACCESS,
6897 0x00000000);
6898 spr_register(env, SPR_SPRG5, "SPRG5",
6899 SPR_NOACCESS, SPR_NOACCESS,
6900 &spr_read_generic, &spr_write_generic,
6901 0x00000000);
6902 spr_register(env, SPR_USPRG5, "USPRG5",
6903 &spr_read_ureg, SPR_NOACCESS,
6904 &spr_read_ureg, SPR_NOACCESS,
6905 0x00000000);
6906 spr_register(env, SPR_SPRG6, "SPRG6",
6907 SPR_NOACCESS, SPR_NOACCESS,
6908 &spr_read_generic, &spr_write_generic,
6909 0x00000000);
6910 spr_register(env, SPR_USPRG6, "USPRG6",
6911 &spr_read_ureg, SPR_NOACCESS,
6912 &spr_read_ureg, SPR_NOACCESS,
6913 0x00000000);
6914 spr_register(env, SPR_SPRG7, "SPRG7",
6915 SPR_NOACCESS, SPR_NOACCESS,
6916 &spr_read_generic, &spr_write_generic,
6917 0x00000000);
6918 spr_register(env, SPR_USPRG7, "USPRG7",
6919 &spr_read_ureg, SPR_NOACCESS,
6920 &spr_read_ureg, SPR_NOACCESS,
6921 0x00000000);
6922 /* Memory management */
6923 gen_low_BATs(env);
6924 gen_high_BATs(env);
6925 gen_74xx_soft_tlb(env, 128, 2);
6926 init_excp_7450(env);
6927 env->dcache_line_size = 32;
6928 env->icache_line_size = 32;
6929 /* Allocate hardware IRQ controller */
6930 ppc6xx_irq_init(env);
6931 }
6932
6933 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6934 {
6935 DeviceClass *dc = DEVICE_CLASS(oc);
6936 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6937
6938 dc->desc = "PowerPC 7445 (aka G4)";
6939 pcc->init_proc = init_proc_7445;
6940 pcc->check_pow = check_pow_hid0_74xx;
6941 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6942 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6943 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6944 PPC_FLOAT_STFIWX |
6945 PPC_CACHE | PPC_CACHE_ICBI |
6946 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6947 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6948 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6949 PPC_MEM_TLBIA | PPC_74xx_TLB |
6950 PPC_SEGMENT | PPC_EXTERN |
6951 PPC_ALTIVEC;
6952 pcc->msr_mask = (1ull << MSR_VR) |
6953 (1ull << MSR_POW) |
6954 (1ull << MSR_ILE) |
6955 (1ull << MSR_EE) |
6956 (1ull << MSR_PR) |
6957 (1ull << MSR_FP) |
6958 (1ull << MSR_ME) |
6959 (1ull << MSR_FE0) |
6960 (1ull << MSR_SE) |
6961 (1ull << MSR_DE) |
6962 (1ull << MSR_FE1) |
6963 (1ull << MSR_EP) |
6964 (1ull << MSR_IR) |
6965 (1ull << MSR_DR) |
6966 (1ull << MSR_PMM) |
6967 (1ull << MSR_RI) |
6968 (1ull << MSR_LE);
6969 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6970 pcc->excp_model = POWERPC_EXCP_74xx;
6971 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6972 pcc->bfd_mach = bfd_mach_ppc_7400;
6973 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6974 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6975 POWERPC_FLAG_BUS_CLK;
6976 }
6977
6978 static void init_proc_7455 (CPUPPCState *env)
6979 {
6980 gen_spr_ne_601(env);
6981 gen_spr_7xx(env);
6982 /* Time base */
6983 gen_tbl(env);
6984 /* 74xx specific SPR */
6985 gen_spr_74xx(env);
6986 /* Level 3 cache control */
6987 gen_l3_ctrl(env);
6988 /* LDSTCR */
6989 /* XXX : not implemented */
6990 spr_register(env, SPR_LDSTCR, "LDSTCR",
6991 SPR_NOACCESS, SPR_NOACCESS,
6992 &spr_read_generic, &spr_write_generic,
6993 0x00000000);
6994 /* ICTRL */
6995 /* XXX : not implemented */
6996 spr_register(env, SPR_ICTRL, "ICTRL",
6997 SPR_NOACCESS, SPR_NOACCESS,
6998 &spr_read_generic, &spr_write_generic,
6999 0x00000000);
7000 /* MSSSR0 */
7001 /* XXX : not implemented */
7002 spr_register(env, SPR_MSSSR0, "MSSSR0",
7003 SPR_NOACCESS, SPR_NOACCESS,
7004 &spr_read_generic, &spr_write_generic,
7005 0x00000000);
7006 /* PMC */
7007 /* XXX : not implemented */
7008 spr_register(env, SPR_7XX_PMC5, "PMC5",
7009 SPR_NOACCESS, SPR_NOACCESS,
7010 &spr_read_generic, &spr_write_generic,
7011 0x00000000);
7012 /* XXX : not implemented */
7013 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7014 &spr_read_ureg, SPR_NOACCESS,
7015 &spr_read_ureg, SPR_NOACCESS,
7016 0x00000000);
7017 /* XXX : not implemented */
7018 spr_register(env, SPR_7XX_PMC6, "PMC6",
7019 SPR_NOACCESS, SPR_NOACCESS,
7020 &spr_read_generic, &spr_write_generic,
7021 0x00000000);
7022 /* XXX : not implemented */
7023 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7024 &spr_read_ureg, SPR_NOACCESS,
7025 &spr_read_ureg, SPR_NOACCESS,
7026 0x00000000);
7027 /* SPRGs */
7028 spr_register(env, SPR_SPRG4, "SPRG4",
7029 SPR_NOACCESS, SPR_NOACCESS,
7030 &spr_read_generic, &spr_write_generic,
7031 0x00000000);
7032 spr_register(env, SPR_USPRG4, "USPRG4",
7033 &spr_read_ureg, SPR_NOACCESS,
7034 &spr_read_ureg, SPR_NOACCESS,
7035 0x00000000);
7036 spr_register(env, SPR_SPRG5, "SPRG5",
7037 SPR_NOACCESS, SPR_NOACCESS,
7038 &spr_read_generic, &spr_write_generic,
7039 0x00000000);
7040 spr_register(env, SPR_USPRG5, "USPRG5",
7041 &spr_read_ureg, SPR_NOACCESS,
7042 &spr_read_ureg, SPR_NOACCESS,
7043 0x00000000);
7044 spr_register(env, SPR_SPRG6, "SPRG6",
7045 SPR_NOACCESS, SPR_NOACCESS,
7046 &spr_read_generic, &spr_write_generic,
7047 0x00000000);
7048 spr_register(env, SPR_USPRG6, "USPRG6",
7049 &spr_read_ureg, SPR_NOACCESS,
7050 &spr_read_ureg, SPR_NOACCESS,
7051 0x00000000);
7052 spr_register(env, SPR_SPRG7, "SPRG7",
7053 SPR_NOACCESS, SPR_NOACCESS,
7054 &spr_read_generic, &spr_write_generic,
7055 0x00000000);
7056 spr_register(env, SPR_USPRG7, "USPRG7",
7057 &spr_read_ureg, SPR_NOACCESS,
7058 &spr_read_ureg, SPR_NOACCESS,
7059 0x00000000);
7060 /* Memory management */
7061 gen_low_BATs(env);
7062 gen_high_BATs(env);
7063 gen_74xx_soft_tlb(env, 128, 2);
7064 init_excp_7450(env);
7065 env->dcache_line_size = 32;
7066 env->icache_line_size = 32;
7067 /* Allocate hardware IRQ controller */
7068 ppc6xx_irq_init(env);
7069 }
7070
7071 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
7072 {
7073 DeviceClass *dc = DEVICE_CLASS(oc);
7074 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7075
7076 dc->desc = "PowerPC 7455 (aka G4)";
7077 pcc->init_proc = init_proc_7455;
7078 pcc->check_pow = check_pow_hid0_74xx;
7079 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7080 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7081 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7082 PPC_FLOAT_STFIWX |
7083 PPC_CACHE | PPC_CACHE_ICBI |
7084 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7085 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7086 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7087 PPC_MEM_TLBIA | PPC_74xx_TLB |
7088 PPC_SEGMENT | PPC_EXTERN |
7089 PPC_ALTIVEC;
7090 pcc->msr_mask = (1ull << MSR_VR) |
7091 (1ull << MSR_POW) |
7092 (1ull << MSR_ILE) |
7093 (1ull << MSR_EE) |
7094 (1ull << MSR_PR) |
7095 (1ull << MSR_FP) |
7096 (1ull << MSR_ME) |
7097 (1ull << MSR_FE0) |
7098 (1ull << MSR_SE) |
7099 (1ull << MSR_DE) |
7100 (1ull << MSR_FE1) |
7101 (1ull << MSR_EP) |
7102 (1ull << MSR_IR) |
7103 (1ull << MSR_DR) |
7104 (1ull << MSR_PMM) |
7105 (1ull << MSR_RI) |
7106 (1ull << MSR_LE);
7107 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7108 pcc->excp_model = POWERPC_EXCP_74xx;
7109 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7110 pcc->bfd_mach = bfd_mach_ppc_7400;
7111 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7112 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7113 POWERPC_FLAG_BUS_CLK;
7114 }
7115
7116 static void init_proc_7457 (CPUPPCState *env)
7117 {
7118 gen_spr_ne_601(env);
7119 gen_spr_7xx(env);
7120 /* Time base */
7121 gen_tbl(env);
7122 /* 74xx specific SPR */
7123 gen_spr_74xx(env);
7124 /* Level 3 cache control */
7125 gen_l3_ctrl(env);
7126 /* L3ITCR1 */
7127 /* XXX : not implemented */
7128 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
7129 SPR_NOACCESS, SPR_NOACCESS,
7130 &spr_read_generic, &spr_write_generic,
7131 0x00000000);
7132 /* L3ITCR2 */
7133 /* XXX : not implemented */
7134 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
7135 SPR_NOACCESS, SPR_NOACCESS,
7136 &spr_read_generic, &spr_write_generic,
7137 0x00000000);
7138 /* L3ITCR3 */
7139 /* XXX : not implemented */
7140 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
7141 SPR_NOACCESS, SPR_NOACCESS,
7142 &spr_read_generic, &spr_write_generic,
7143 0x00000000);
7144 /* L3OHCR */
7145 /* XXX : not implemented */
7146 spr_register(env, SPR_L3OHCR, "L3OHCR",
7147 SPR_NOACCESS, SPR_NOACCESS,
7148 &spr_read_generic, &spr_write_generic,
7149 0x00000000);
7150 /* LDSTCR */
7151 /* XXX : not implemented */
7152 spr_register(env, SPR_LDSTCR, "LDSTCR",
7153 SPR_NOACCESS, SPR_NOACCESS,
7154 &spr_read_generic, &spr_write_generic,
7155 0x00000000);
7156 /* ICTRL */
7157 /* XXX : not implemented */
7158 spr_register(env, SPR_ICTRL, "ICTRL",
7159 SPR_NOACCESS, SPR_NOACCESS,
7160 &spr_read_generic, &spr_write_generic,
7161 0x00000000);
7162 /* MSSSR0 */
7163 /* XXX : not implemented */
7164 spr_register(env, SPR_MSSSR0, "MSSSR0",
7165 SPR_NOACCESS, SPR_NOACCESS,
7166 &spr_read_generic, &spr_write_generic,
7167 0x00000000);
7168 /* PMC */
7169 /* XXX : not implemented */
7170 spr_register(env, SPR_7XX_PMC5, "PMC5",
7171 SPR_NOACCESS, SPR_NOACCESS,
7172 &spr_read_generic, &spr_write_generic,
7173 0x00000000);
7174 /* XXX : not implemented */
7175 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7176 &spr_read_ureg, SPR_NOACCESS,
7177 &spr_read_ureg, SPR_NOACCESS,
7178 0x00000000);
7179 /* XXX : not implemented */
7180 spr_register(env, SPR_7XX_PMC6, "PMC6",
7181 SPR_NOACCESS, SPR_NOACCESS,
7182 &spr_read_generic, &spr_write_generic,
7183 0x00000000);
7184 /* XXX : not implemented */
7185 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7186 &spr_read_ureg, SPR_NOACCESS,
7187 &spr_read_ureg, SPR_NOACCESS,
7188 0x00000000);
7189 /* SPRGs */
7190 spr_register(env, SPR_SPRG4, "SPRG4",
7191 SPR_NOACCESS, SPR_NOACCESS,
7192 &spr_read_generic, &spr_write_generic,
7193 0x00000000);
7194 spr_register(env, SPR_USPRG4, "USPRG4",
7195 &spr_read_ureg, SPR_NOACCESS,
7196 &spr_read_ureg, SPR_NOACCESS,
7197 0x00000000);
7198 spr_register(env, SPR_SPRG5, "SPRG5",
7199 SPR_NOACCESS, SPR_NOACCESS,
7200 &spr_read_generic, &spr_write_generic,
7201 0x00000000);
7202 spr_register(env, SPR_USPRG5, "USPRG5",
7203 &spr_read_ureg, SPR_NOACCESS,
7204 &spr_read_ureg, SPR_NOACCESS,
7205 0x00000000);
7206 spr_register(env, SPR_SPRG6, "SPRG6",
7207 SPR_NOACCESS, SPR_NOACCESS,
7208 &spr_read_generic, &spr_write_generic,
7209 0x00000000);
7210 spr_register(env, SPR_USPRG6, "USPRG6",
7211 &spr_read_ureg, SPR_NOACCESS,
7212 &spr_read_ureg, SPR_NOACCESS,
7213 0x00000000);
7214 spr_register(env, SPR_SPRG7, "SPRG7",
7215 SPR_NOACCESS, SPR_NOACCESS,
7216 &spr_read_generic, &spr_write_generic,
7217 0x00000000);
7218 spr_register(env, SPR_USPRG7, "USPRG7",
7219 &spr_read_ureg, SPR_NOACCESS,
7220 &spr_read_ureg, SPR_NOACCESS,
7221 0x00000000);
7222 /* Memory management */
7223 gen_low_BATs(env);
7224 gen_high_BATs(env);
7225 gen_74xx_soft_tlb(env, 128, 2);
7226 init_excp_7450(env);
7227 env->dcache_line_size = 32;
7228 env->icache_line_size = 32;
7229 /* Allocate hardware IRQ controller */
7230 ppc6xx_irq_init(env);
7231 }
7232
7233 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7234 {
7235 DeviceClass *dc = DEVICE_CLASS(oc);
7236 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7237
7238 dc->desc = "PowerPC 7457 (aka G4)";
7239 pcc->init_proc = init_proc_7457;
7240 pcc->check_pow = check_pow_hid0_74xx;
7241 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7242 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7243 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7244 PPC_FLOAT_STFIWX |
7245 PPC_CACHE | PPC_CACHE_ICBI |
7246 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7247 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7248 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7249 PPC_MEM_TLBIA | PPC_74xx_TLB |
7250 PPC_SEGMENT | PPC_EXTERN |
7251 PPC_ALTIVEC;
7252 pcc->msr_mask = (1ull << MSR_VR) |
7253 (1ull << MSR_POW) |
7254 (1ull << MSR_ILE) |
7255 (1ull << MSR_EE) |
7256 (1ull << MSR_PR) |
7257 (1ull << MSR_FP) |
7258 (1ull << MSR_ME) |
7259 (1ull << MSR_FE0) |
7260 (1ull << MSR_SE) |
7261 (1ull << MSR_DE) |
7262 (1ull << MSR_FE1) |
7263 (1ull << MSR_EP) |
7264 (1ull << MSR_IR) |
7265 (1ull << MSR_DR) |
7266 (1ull << MSR_PMM) |
7267 (1ull << MSR_RI) |
7268 (1ull << MSR_LE);
7269 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7270 pcc->excp_model = POWERPC_EXCP_74xx;
7271 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7272 pcc->bfd_mach = bfd_mach_ppc_7400;
7273 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7274 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7275 POWERPC_FLAG_BUS_CLK;
7276 }
7277
7278 static void init_proc_e600 (CPUPPCState *env)
7279 {
7280 gen_spr_ne_601(env);
7281 gen_spr_7xx(env);
7282 /* Time base */
7283 gen_tbl(env);
7284 /* 74xx specific SPR */
7285 gen_spr_74xx(env);
7286 /* XXX : not implemented */
7287 spr_register(env, SPR_UBAMR, "UBAMR",
7288 &spr_read_ureg, SPR_NOACCESS,
7289 &spr_read_ureg, SPR_NOACCESS,
7290 0x00000000);
7291 /* XXX : not implemented */
7292 spr_register(env, SPR_LDSTCR, "LDSTCR",
7293 SPR_NOACCESS, SPR_NOACCESS,
7294 &spr_read_generic, &spr_write_generic,
7295 0x00000000);
7296 /* XXX : not implemented */
7297 spr_register(env, SPR_ICTRL, "ICTRL",
7298 SPR_NOACCESS, SPR_NOACCESS,
7299 &spr_read_generic, &spr_write_generic,
7300 0x00000000);
7301 /* XXX : not implemented */
7302 spr_register(env, SPR_MSSSR0, "MSSSR0",
7303 SPR_NOACCESS, SPR_NOACCESS,
7304 &spr_read_generic, &spr_write_generic,
7305 0x00000000);
7306 /* XXX : not implemented */
7307 spr_register(env, SPR_7XX_PMC5, "PMC5",
7308 SPR_NOACCESS, SPR_NOACCESS,
7309 &spr_read_generic, &spr_write_generic,
7310 0x00000000);
7311 /* XXX : not implemented */
7312 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7313 &spr_read_ureg, SPR_NOACCESS,
7314 &spr_read_ureg, SPR_NOACCESS,
7315 0x00000000);
7316 /* XXX : not implemented */
7317 spr_register(env, SPR_7XX_PMC6, "PMC6",
7318 SPR_NOACCESS, SPR_NOACCESS,
7319 &spr_read_generic, &spr_write_generic,
7320 0x00000000);
7321 /* XXX : not implemented */
7322 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7323 &spr_read_ureg, SPR_NOACCESS,
7324 &spr_read_ureg, SPR_NOACCESS,
7325 0x00000000);
7326 /* SPRGs */
7327 spr_register(env, SPR_SPRG4, "SPRG4",
7328 SPR_NOACCESS, SPR_NOACCESS,
7329 &spr_read_generic, &spr_write_generic,
7330 0x00000000);
7331 spr_register(env, SPR_USPRG4, "USPRG4",
7332 &spr_read_ureg, SPR_NOACCESS,
7333 &spr_read_ureg, SPR_NOACCESS,
7334 0x00000000);
7335 spr_register(env, SPR_SPRG5, "SPRG5",
7336 SPR_NOACCESS, SPR_NOACCESS,
7337 &spr_read_generic, &spr_write_generic,
7338 0x00000000);
7339 spr_register(env, SPR_USPRG5, "USPRG5",
7340 &spr_read_ureg, SPR_NOACCESS,
7341 &spr_read_ureg, SPR_NOACCESS,
7342 0x00000000);
7343 spr_register(env, SPR_SPRG6, "SPRG6",
7344 SPR_NOACCESS, SPR_NOACCESS,
7345 &spr_read_generic, &spr_write_generic,
7346 0x00000000);
7347 spr_register(env, SPR_USPRG6, "USPRG6",
7348 &spr_read_ureg, SPR_NOACCESS,
7349 &spr_read_ureg, SPR_NOACCESS,
7350 0x00000000);
7351 spr_register(env, SPR_SPRG7, "SPRG7",
7352 SPR_NOACCESS, SPR_NOACCESS,
7353 &spr_read_generic, &spr_write_generic,
7354 0x00000000);
7355 spr_register(env, SPR_USPRG7, "USPRG7",
7356 &spr_read_ureg, SPR_NOACCESS,
7357 &spr_read_ureg, SPR_NOACCESS,
7358 0x00000000);
7359 /* Memory management */
7360 gen_low_BATs(env);
7361 gen_high_BATs(env);
7362 gen_74xx_soft_tlb(env, 128, 2);
7363 init_excp_7450(env);
7364 env->dcache_line_size = 32;
7365 env->icache_line_size = 32;
7366 /* Allocate hardware IRQ controller */
7367 ppc6xx_irq_init(env);
7368 }
7369
7370 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7371 {
7372 DeviceClass *dc = DEVICE_CLASS(oc);
7373 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7374
7375 dc->desc = "PowerPC e600";
7376 pcc->init_proc = init_proc_e600;
7377 pcc->check_pow = check_pow_hid0_74xx;
7378 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7379 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7380 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7381 PPC_FLOAT_STFIWX |
7382 PPC_CACHE | PPC_CACHE_ICBI |
7383 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7384 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7385 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7386 PPC_MEM_TLBIA | PPC_74xx_TLB |
7387 PPC_SEGMENT | PPC_EXTERN |
7388 PPC_ALTIVEC;
7389 pcc->insns_flags2 = PPC_NONE;
7390 pcc->msr_mask = (1ull << MSR_VR) |
7391 (1ull << MSR_POW) |
7392 (1ull << MSR_ILE) |
7393 (1ull << MSR_EE) |
7394 (1ull << MSR_PR) |
7395 (1ull << MSR_FP) |
7396 (1ull << MSR_ME) |
7397 (1ull << MSR_FE0) |
7398 (1ull << MSR_SE) |
7399 (1ull << MSR_DE) |
7400 (1ull << MSR_FE1) |
7401 (1ull << MSR_EP) |
7402 (1ull << MSR_IR) |
7403 (1ull << MSR_DR) |
7404 (1ull << MSR_PMM) |
7405 (1ull << MSR_RI) |
7406 (1ull << MSR_LE);
7407 pcc->mmu_model = POWERPC_MMU_32B;
7408 #if defined(CONFIG_SOFTMMU)
7409 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7410 #endif
7411 pcc->excp_model = POWERPC_EXCP_74xx;
7412 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7413 pcc->bfd_mach = bfd_mach_ppc_7400;
7414 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7415 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7416 POWERPC_FLAG_BUS_CLK;
7417 }
7418
7419 #if defined (TARGET_PPC64)
7420 #if defined(CONFIG_USER_ONLY)
7421 #define POWERPC970_HID5_INIT 0x00000080
7422 #else
7423 #define POWERPC970_HID5_INIT 0x00000000
7424 #endif
7425
7426 enum BOOK3S_CPU_TYPE {
7427 BOOK3S_CPU_970,
7428 BOOK3S_CPU_POWER5PLUS,
7429 BOOK3S_CPU_POWER6,
7430 BOOK3S_CPU_POWER7,
7431 BOOK3S_CPU_POWER8
7432 };
7433
7434 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
7435 int bit, int sprn, int cause)
7436 {
7437 TCGv_i32 t1 = tcg_const_i32(bit);
7438 TCGv_i32 t2 = tcg_const_i32(sprn);
7439 TCGv_i32 t3 = tcg_const_i32(cause);
7440
7441 gen_update_current_nip(ctx);
7442 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
7443
7444 tcg_temp_free_i32(t3);
7445 tcg_temp_free_i32(t2);
7446 tcg_temp_free_i32(t1);
7447 }
7448
7449 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
7450 int bit, int sprn, int cause)
7451 {
7452 TCGv_i32 t1 = tcg_const_i32(bit);
7453 TCGv_i32 t2 = tcg_const_i32(sprn);
7454 TCGv_i32 t3 = tcg_const_i32(cause);
7455
7456 gen_update_current_nip(ctx);
7457 gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
7458
7459 tcg_temp_free_i32(t3);
7460 tcg_temp_free_i32(t2);
7461 tcg_temp_free_i32(t1);
7462 }
7463
7464 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn)
7465 {
7466 TCGv spr_up = tcg_temp_new();
7467 TCGv spr = tcg_temp_new();
7468
7469 gen_load_spr(spr, sprn - 1);
7470 tcg_gen_shri_tl(spr_up, spr, 32);
7471 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up);
7472
7473 tcg_temp_free(spr);
7474 tcg_temp_free(spr_up);
7475 }
7476
7477 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn)
7478 {
7479 TCGv spr = tcg_temp_new();
7480
7481 gen_load_spr(spr, sprn - 1);
7482 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32);
7483 gen_store_spr(sprn - 1, spr);
7484
7485 tcg_temp_free(spr);
7486 }
7487
7488 static int check_pow_970 (CPUPPCState *env)
7489 {
7490 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
7491 return 1;
7492 }
7493
7494 return 0;
7495 }
7496
7497 static void gen_spr_970_hid(CPUPPCState *env)
7498 {
7499 /* Hardware implementation registers */
7500 /* XXX : not implemented */
7501 spr_register(env, SPR_HID0, "HID0",
7502 SPR_NOACCESS, SPR_NOACCESS,
7503 &spr_read_generic, &spr_write_clear,
7504 0x60000000);
7505 spr_register(env, SPR_HID1, "HID1",
7506 SPR_NOACCESS, SPR_NOACCESS,
7507 &spr_read_generic, &spr_write_generic,
7508 0x00000000);
7509 spr_register(env, SPR_970_HID5, "HID5",
7510 SPR_NOACCESS, SPR_NOACCESS,
7511 &spr_read_generic, &spr_write_generic,
7512 POWERPC970_HID5_INIT);
7513 }
7514
7515 static void gen_spr_970_hior(CPUPPCState *env)
7516 {
7517 spr_register(env, SPR_HIOR, "SPR_HIOR",
7518 SPR_NOACCESS, SPR_NOACCESS,
7519 &spr_read_hior, &spr_write_hior,
7520 0x00000000);
7521 }
7522
7523 static void gen_spr_970_lpar(CPUPPCState *env)
7524 {
7525 /* Logical partitionning */
7526 /* PPC970: HID4 is effectively the LPCR */
7527 spr_register(env, SPR_970_HID4, "HID4",
7528 SPR_NOACCESS, SPR_NOACCESS,
7529 &spr_read_generic, &spr_write_generic,
7530 0x00000000);
7531 }
7532
7533 static void gen_spr_book3s_common(CPUPPCState *env)
7534 {
7535 spr_register(env, SPR_CTRL, "SPR_CTRL",
7536 SPR_NOACCESS, SPR_NOACCESS,
7537 SPR_NOACCESS, &spr_write_generic,
7538 0x00000000);
7539 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7540 &spr_read_ureg, SPR_NOACCESS,
7541 &spr_read_ureg, SPR_NOACCESS,
7542 0x00000000);
7543 }
7544
7545 static void gen_spr_book3s_altivec(CPUPPCState *env)
7546 {
7547 if (!(env->insns_flags & PPC_ALTIVEC)) {
7548 return;
7549 }
7550
7551 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
7552 &spr_read_generic, &spr_write_generic,
7553 &spr_read_generic, &spr_write_generic,
7554 KVM_REG_PPC_VRSAVE, 0x00000000);
7555
7556 /* Can't find information on what this should be on reset. This
7557 * value is the one used by 74xx processors. */
7558 vscr_init(env, 0x00010000);
7559 }
7560
7561 static void gen_spr_book3s_dbg(CPUPPCState *env)
7562 {
7563 /*
7564 * TODO: different specs define different scopes for these,
7565 * will have to address this:
7566 * 970: super/write and super/read
7567 * powerisa 2.03..2.04: hypv/write and super/read.
7568 * powerisa 2.05 and newer: hypv/write and hypv/read.
7569 */
7570 spr_register_kvm(env, SPR_DABR, "DABR",
7571 SPR_NOACCESS, SPR_NOACCESS,
7572 &spr_read_generic, &spr_write_generic,
7573 KVM_REG_PPC_DABR, 0x00000000);
7574 spr_register_kvm(env, SPR_DABRX, "DABRX",
7575 SPR_NOACCESS, SPR_NOACCESS,
7576 &spr_read_generic, &spr_write_generic,
7577 KVM_REG_PPC_DABRX, 0x00000000);
7578 }
7579
7580 static void gen_spr_book3s_207_dbg(CPUPPCState *env)
7581 {
7582 spr_register_kvm_hv(env, SPR_DAWR, "DAWR",
7583 SPR_NOACCESS, SPR_NOACCESS,
7584 SPR_NOACCESS, SPR_NOACCESS,
7585 &spr_read_generic, &spr_write_generic,
7586 KVM_REG_PPC_DAWR, 0x00000000);
7587 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX",
7588 SPR_NOACCESS, SPR_NOACCESS,
7589 SPR_NOACCESS, SPR_NOACCESS,
7590 &spr_read_generic, &spr_write_generic,
7591 KVM_REG_PPC_DAWRX, 0x00000000);
7592 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
7593 SPR_NOACCESS, SPR_NOACCESS,
7594 SPR_NOACCESS, SPR_NOACCESS,
7595 &spr_read_generic, &spr_write_generic,
7596 KVM_REG_PPC_CIABR, 0x00000000);
7597 }
7598
7599 static void gen_spr_970_dbg(CPUPPCState *env)
7600 {
7601 /* Breakpoints */
7602 spr_register(env, SPR_IABR, "IABR",
7603 SPR_NOACCESS, SPR_NOACCESS,
7604 &spr_read_generic, &spr_write_generic,
7605 0x00000000);
7606 }
7607
7608 static void gen_spr_book3s_pmu_sup(CPUPPCState *env)
7609 {
7610 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
7611 SPR_NOACCESS, SPR_NOACCESS,
7612 &spr_read_generic, &spr_write_generic,
7613 KVM_REG_PPC_MMCR0, 0x00000000);
7614 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
7615 SPR_NOACCESS, SPR_NOACCESS,
7616 &spr_read_generic, &spr_write_generic,
7617 KVM_REG_PPC_MMCR1, 0x00000000);
7618 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
7619 SPR_NOACCESS, SPR_NOACCESS,
7620 &spr_read_generic, &spr_write_generic,
7621 KVM_REG_PPC_MMCRA, 0x00000000);
7622 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
7623 SPR_NOACCESS, SPR_NOACCESS,
7624 &spr_read_generic, &spr_write_generic,
7625 KVM_REG_PPC_PMC1, 0x00000000);
7626 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
7627 SPR_NOACCESS, SPR_NOACCESS,
7628 &spr_read_generic, &spr_write_generic,
7629 KVM_REG_PPC_PMC2, 0x00000000);
7630 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
7631 SPR_NOACCESS, SPR_NOACCESS,
7632 &spr_read_generic, &spr_write_generic,
7633 KVM_REG_PPC_PMC3, 0x00000000);
7634 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
7635 SPR_NOACCESS, SPR_NOACCESS,
7636 &spr_read_generic, &spr_write_generic,
7637 KVM_REG_PPC_PMC4, 0x00000000);
7638 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
7639 SPR_NOACCESS, SPR_NOACCESS,
7640 &spr_read_generic, &spr_write_generic,
7641 KVM_REG_PPC_PMC5, 0x00000000);
7642 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
7643 SPR_NOACCESS, SPR_NOACCESS,
7644 &spr_read_generic, &spr_write_generic,
7645 KVM_REG_PPC_PMC6, 0x00000000);
7646 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
7647 SPR_NOACCESS, SPR_NOACCESS,
7648 &spr_read_generic, &spr_write_generic,
7649 KVM_REG_PPC_SIAR, 0x00000000);
7650 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
7651 SPR_NOACCESS, SPR_NOACCESS,
7652 &spr_read_generic, &spr_write_generic,
7653 KVM_REG_PPC_SDAR, 0x00000000);
7654 }
7655
7656 static void gen_spr_book3s_pmu_user(CPUPPCState *env)
7657 {
7658 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
7659 &spr_read_ureg, SPR_NOACCESS,
7660 &spr_read_ureg, &spr_write_ureg,
7661 0x00000000);
7662 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
7663 &spr_read_ureg, SPR_NOACCESS,
7664 &spr_read_ureg, &spr_write_ureg,
7665 0x00000000);
7666 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
7667 &spr_read_ureg, SPR_NOACCESS,
7668 &spr_read_ureg, &spr_write_ureg,
7669 0x00000000);
7670 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
7671 &spr_read_ureg, SPR_NOACCESS,
7672 &spr_read_ureg, &spr_write_ureg,
7673 0x00000000);
7674 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
7675 &spr_read_ureg, SPR_NOACCESS,
7676 &spr_read_ureg, &spr_write_ureg,
7677 0x00000000);
7678 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
7679 &spr_read_ureg, SPR_NOACCESS,
7680 &spr_read_ureg, &spr_write_ureg,
7681 0x00000000);
7682 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
7683 &spr_read_ureg, SPR_NOACCESS,
7684 &spr_read_ureg, &spr_write_ureg,
7685 0x00000000);
7686 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
7687 &spr_read_ureg, SPR_NOACCESS,
7688 &spr_read_ureg, &spr_write_ureg,
7689 0x00000000);
7690 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
7691 &spr_read_ureg, SPR_NOACCESS,
7692 &spr_read_ureg, &spr_write_ureg,
7693 0x00000000);
7694 spr_register(env, SPR_POWER_USIAR, "USIAR",
7695 &spr_read_ureg, SPR_NOACCESS,
7696 &spr_read_ureg, &spr_write_ureg,
7697 0x00000000);
7698 spr_register(env, SPR_POWER_USDAR, "USDAR",
7699 &spr_read_ureg, SPR_NOACCESS,
7700 &spr_read_ureg, &spr_write_ureg,
7701 0x00000000);
7702 }
7703
7704 static void gen_spr_970_pmu_sup(CPUPPCState *env)
7705 {
7706 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
7707 SPR_NOACCESS, SPR_NOACCESS,
7708 &spr_read_generic, &spr_write_generic,
7709 KVM_REG_PPC_PMC7, 0x00000000);
7710 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
7711 SPR_NOACCESS, SPR_NOACCESS,
7712 &spr_read_generic, &spr_write_generic,
7713 KVM_REG_PPC_PMC8, 0x00000000);
7714 }
7715
7716 static void gen_spr_970_pmu_user(CPUPPCState *env)
7717 {
7718 spr_register(env, SPR_970_UPMC7, "UPMC7",
7719 &spr_read_ureg, SPR_NOACCESS,
7720 &spr_read_ureg, &spr_write_ureg,
7721 0x00000000);
7722 spr_register(env, SPR_970_UPMC8, "UPMC8",
7723 &spr_read_ureg, SPR_NOACCESS,
7724 &spr_read_ureg, &spr_write_ureg,
7725 0x00000000);
7726 }
7727
7728 static void gen_spr_power8_pmu_sup(CPUPPCState *env)
7729 {
7730 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
7731 SPR_NOACCESS, SPR_NOACCESS,
7732 &spr_read_generic, &spr_write_generic,
7733 KVM_REG_PPC_MMCR2, 0x00000000);
7734 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
7735 SPR_NOACCESS, SPR_NOACCESS,
7736 &spr_read_generic, &spr_write_generic,
7737 KVM_REG_PPC_MMCRS, 0x00000000);
7738 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
7739 SPR_NOACCESS, SPR_NOACCESS,
7740 &spr_read_generic, &spr_write_generic,
7741 KVM_REG_PPC_SIER, 0x00000000);
7742 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
7743 SPR_NOACCESS, SPR_NOACCESS,
7744 &spr_read_generic, &spr_write_generic,
7745 KVM_REG_PPC_SPMC1, 0x00000000);
7746 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
7747 SPR_NOACCESS, SPR_NOACCESS,
7748 &spr_read_generic, &spr_write_generic,
7749 KVM_REG_PPC_SPMC2, 0x00000000);
7750 spr_register_kvm(env, SPR_TACR, "TACR",
7751 SPR_NOACCESS, SPR_NOACCESS,
7752 &spr_read_generic, &spr_write_generic,
7753 KVM_REG_PPC_TACR, 0x00000000);
7754 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
7755 SPR_NOACCESS, SPR_NOACCESS,
7756 &spr_read_generic, &spr_write_generic,
7757 KVM_REG_PPC_TCSCR, 0x00000000);
7758 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
7759 SPR_NOACCESS, SPR_NOACCESS,
7760 &spr_read_generic, &spr_write_generic,
7761 KVM_REG_PPC_CSIGR, 0x00000000);
7762 }
7763
7764 static void gen_spr_power8_pmu_user(CPUPPCState *env)
7765 {
7766 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7767 &spr_read_ureg, SPR_NOACCESS,
7768 &spr_read_ureg, &spr_write_ureg,
7769 0x00000000);
7770 spr_register(env, SPR_POWER_USIER, "USIER",
7771 &spr_read_generic, SPR_NOACCESS,
7772 &spr_read_generic, &spr_write_generic,
7773 0x00000000);
7774 }
7775
7776 static void gen_spr_power5p_ear(CPUPPCState *env)
7777 {
7778 /* External access control */
7779 spr_register(env, SPR_EAR, "EAR",
7780 SPR_NOACCESS, SPR_NOACCESS,
7781 &spr_read_generic, &spr_write_generic,
7782 0x00000000);
7783 }
7784
7785 static void gen_spr_power5p_lpar(CPUPPCState *env)
7786 {
7787 /* Logical partitionning */
7788 spr_register_kvm(env, SPR_LPCR, "LPCR",
7789 SPR_NOACCESS, SPR_NOACCESS,
7790 &spr_read_generic, &spr_write_generic,
7791 KVM_REG_PPC_LPCR, 0x00000000);
7792 }
7793
7794 static void gen_spr_book3s_ids(CPUPPCState *env)
7795 {
7796 /* Processor identification */
7797 spr_register(env, SPR_PIR, "PIR",
7798 SPR_NOACCESS, SPR_NOACCESS,
7799 &spr_read_generic, &spr_write_pir,
7800 0x00000000);
7801 }
7802
7803 static void gen_spr_power8_ids(CPUPPCState *env)
7804 {
7805 /* Thread identification */
7806 spr_register(env, SPR_TIR, "TIR",
7807 SPR_NOACCESS, SPR_NOACCESS,
7808 &spr_read_generic, SPR_NOACCESS,
7809 0x00000000);
7810 }
7811
7812 static void gen_spr_book3s_purr(CPUPPCState *env)
7813 {
7814 #if !defined(CONFIG_USER_ONLY)
7815 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7816 spr_register_kvm(env, SPR_PURR, "PURR",
7817 &spr_read_purr, SPR_NOACCESS,
7818 &spr_read_purr, SPR_NOACCESS,
7819 KVM_REG_PPC_PURR, 0x00000000);
7820 spr_register_kvm(env, SPR_SPURR, "SPURR",
7821 &spr_read_purr, SPR_NOACCESS,
7822 &spr_read_purr, SPR_NOACCESS,
7823 KVM_REG_PPC_SPURR, 0x00000000);
7824 #endif
7825 }
7826
7827 static void gen_spr_power6_dbg(CPUPPCState *env)
7828 {
7829 #if !defined(CONFIG_USER_ONLY)
7830 spr_register(env, SPR_CFAR, "SPR_CFAR",
7831 SPR_NOACCESS, SPR_NOACCESS,
7832 &spr_read_cfar, &spr_write_cfar,
7833 0x00000000);
7834 #endif
7835 }
7836
7837 static void gen_spr_power5p_common(CPUPPCState *env)
7838 {
7839 spr_register_kvm(env, SPR_PPR, "PPR",
7840 &spr_read_generic, &spr_write_generic,
7841 &spr_read_generic, &spr_write_generic,
7842 KVM_REG_PPC_PPR, 0x00000000);
7843 }
7844
7845 static void gen_spr_power6_common(CPUPPCState *env)
7846 {
7847 #if !defined(CONFIG_USER_ONLY)
7848 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7849 SPR_NOACCESS, SPR_NOACCESS,
7850 &spr_read_generic, &spr_write_generic,
7851 KVM_REG_PPC_DSCR, 0x00000000);
7852 #endif
7853 /*
7854 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7855 * POWERPC_EXCP_INVAL_SPR.
7856 */
7857 spr_register(env, SPR_PCR, "PCR",
7858 SPR_NOACCESS, SPR_NOACCESS,
7859 SPR_NOACCESS, SPR_NOACCESS,
7860 0x00000000);
7861 }
7862
7863 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn)
7864 {
7865 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7866 spr_read_generic(ctx, gprn, sprn);
7867 }
7868
7869 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn)
7870 {
7871 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR);
7872 spr_write_generic(ctx, sprn, gprn);
7873 }
7874
7875 static void gen_spr_power8_tce_address_control(CPUPPCState *env)
7876 {
7877 spr_register_kvm(env, SPR_TAR, "TAR",
7878 &spr_read_tar, &spr_write_tar,
7879 &spr_read_generic, &spr_write_generic,
7880 KVM_REG_PPC_TAR, 0x00000000);
7881 }
7882
7883 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn)
7884 {
7885 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7886 spr_read_generic(ctx, gprn, sprn);
7887 }
7888
7889 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn)
7890 {
7891 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7892 spr_write_generic(ctx, sprn, gprn);
7893 }
7894
7895 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn)
7896 {
7897 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7898 spr_read_prev_upper32(ctx, gprn, sprn);
7899 }
7900
7901 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn)
7902 {
7903 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM);
7904 spr_write_prev_upper32(ctx, sprn, gprn);
7905 }
7906
7907 static void gen_spr_power8_tm(CPUPPCState *env)
7908 {
7909 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
7910 &spr_read_tm, &spr_write_tm,
7911 &spr_read_tm, &spr_write_tm,
7912 KVM_REG_PPC_TFHAR, 0x00000000);
7913 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
7914 &spr_read_tm, &spr_write_tm,
7915 &spr_read_tm, &spr_write_tm,
7916 KVM_REG_PPC_TFIAR, 0x00000000);
7917 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
7918 &spr_read_tm, &spr_write_tm,
7919 &spr_read_tm, &spr_write_tm,
7920 KVM_REG_PPC_TEXASR, 0x00000000);
7921 spr_register(env, SPR_TEXASRU, "TEXASRU",
7922 &spr_read_tm_upper32, &spr_write_tm_upper32,
7923 &spr_read_tm_upper32, &spr_write_tm_upper32,
7924 0x00000000);
7925 }
7926
7927 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn)
7928 {
7929 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7930 spr_read_generic(ctx, gprn, sprn);
7931 }
7932
7933 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn)
7934 {
7935 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7936 spr_write_generic(ctx, sprn, gprn);
7937 }
7938
7939 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn)
7940 {
7941 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7942 spr_read_prev_upper32(ctx, gprn, sprn);
7943 }
7944
7945 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn)
7946 {
7947 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB);
7948 spr_write_prev_upper32(ctx, sprn, gprn);
7949 }
7950
7951 static void gen_spr_power8_ebb(CPUPPCState *env)
7952 {
7953 spr_register(env, SPR_BESCRS, "BESCRS",
7954 &spr_read_ebb, &spr_write_ebb,
7955 &spr_read_generic, &spr_write_generic,
7956 0x00000000);
7957 spr_register(env, SPR_BESCRSU, "BESCRSU",
7958 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7959 &spr_read_prev_upper32, &spr_write_prev_upper32,
7960 0x00000000);
7961 spr_register(env, SPR_BESCRR, "BESCRR",
7962 &spr_read_ebb, &spr_write_ebb,
7963 &spr_read_generic, &spr_write_generic,
7964 0x00000000);
7965 spr_register(env, SPR_BESCRRU, "BESCRRU",
7966 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
7967 &spr_read_prev_upper32, &spr_write_prev_upper32,
7968 0x00000000);
7969 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
7970 &spr_read_ebb, &spr_write_ebb,
7971 &spr_read_generic, &spr_write_generic,
7972 KVM_REG_PPC_EBBHR, 0x00000000);
7973 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
7974 &spr_read_ebb, &spr_write_ebb,
7975 &spr_read_generic, &spr_write_generic,
7976 KVM_REG_PPC_EBBRR, 0x00000000);
7977 spr_register_kvm(env, SPR_BESCR, "BESCR",
7978 &spr_read_ebb, &spr_write_ebb,
7979 &spr_read_generic, &spr_write_generic,
7980 KVM_REG_PPC_BESCR, 0x00000000);
7981 }
7982
7983 /* Virtual Time Base */
7984 static void gen_spr_vtb(CPUPPCState *env)
7985 {
7986 spr_register(env, SPR_VTB, "VTB",
7987 SPR_NOACCESS, SPR_NOACCESS,
7988 &spr_read_tbl, SPR_NOACCESS,
7989 0x00000000);
7990 }
7991
7992 static void gen_spr_power8_fscr(CPUPPCState *env)
7993 {
7994 #if defined(CONFIG_USER_ONLY)
7995 target_ulong initval = 1ULL << FSCR_TAR;
7996 #else
7997 target_ulong initval = 0;
7998 #endif
7999 spr_register_kvm(env, SPR_FSCR, "FSCR",
8000 SPR_NOACCESS, SPR_NOACCESS,
8001 &spr_read_generic, &spr_write_generic,
8002 KVM_REG_PPC_FSCR, initval);
8003 }
8004
8005 static void gen_spr_power8_pspb(CPUPPCState *env)
8006 {
8007 spr_register_kvm(env, SPR_PSPB, "PSPB",
8008 SPR_NOACCESS, SPR_NOACCESS,
8009 &spr_read_generic, &spr_write_generic32,
8010 KVM_REG_PPC_PSPB, 0);
8011 }
8012
8013 static void gen_spr_power8_ic(CPUPPCState *env)
8014 {
8015 #if !defined(CONFIG_USER_ONLY)
8016 spr_register_hv(env, SPR_IC, "IC",
8017 SPR_NOACCESS, SPR_NOACCESS,
8018 &spr_read_generic, SPR_NOACCESS,
8019 &spr_read_generic, &spr_write_generic,
8020 0);
8021 #endif
8022 }
8023
8024 static void gen_spr_power8_book4(CPUPPCState *env)
8025 {
8026 /* Add a number of P8 book4 registers */
8027 #if !defined(CONFIG_USER_ONLY)
8028 spr_register_kvm(env, SPR_ACOP, "ACOP",
8029 SPR_NOACCESS, SPR_NOACCESS,
8030 &spr_read_generic, &spr_write_generic,
8031 KVM_REG_PPC_ACOP, 0);
8032 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
8033 SPR_NOACCESS, SPR_NOACCESS,
8034 &spr_read_generic, &spr_write_generic,
8035 KVM_REG_PPC_PID, 0);
8036 spr_register_kvm(env, SPR_WORT, "WORT",
8037 SPR_NOACCESS, SPR_NOACCESS,
8038 &spr_read_generic, &spr_write_generic,
8039 KVM_REG_PPC_WORT, 0);
8040 #endif
8041 }
8042
8043 static void init_proc_book3s_64(CPUPPCState *env, int version)
8044 {
8045 gen_spr_ne_601(env);
8046 gen_tbl(env);
8047 gen_spr_book3s_altivec(env);
8048 gen_spr_book3s_pmu_sup(env);
8049 gen_spr_book3s_pmu_user(env);
8050 gen_spr_book3s_common(env);
8051
8052 switch (version) {
8053 case BOOK3S_CPU_970:
8054 case BOOK3S_CPU_POWER5PLUS:
8055 gen_spr_970_hid(env);
8056 gen_spr_970_hior(env);
8057 gen_low_BATs(env);
8058 gen_spr_970_pmu_sup(env);
8059 gen_spr_970_pmu_user(env);
8060 break;
8061 case BOOK3S_CPU_POWER7:
8062 case BOOK3S_CPU_POWER8:
8063 gen_spr_book3s_ids(env);
8064 gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
8065 gen_spr_book3s_purr(env);
8066 env->ci_large_pages = true;
8067 break;
8068 default:
8069 g_assert_not_reached();
8070 }
8071 if (version >= BOOK3S_CPU_POWER5PLUS) {
8072 gen_spr_power5p_common(env);
8073 gen_spr_power5p_lpar(env);
8074 gen_spr_power5p_ear(env);
8075 } else {
8076 gen_spr_970_lpar(env);
8077 }
8078 if (version == BOOK3S_CPU_970) {
8079 gen_spr_970_dbg(env);
8080 }
8081 if (version >= BOOK3S_CPU_POWER6) {
8082 gen_spr_power6_common(env);
8083 gen_spr_power6_dbg(env);
8084 }
8085 if (version >= BOOK3S_CPU_POWER8) {
8086 gen_spr_power8_tce_address_control(env);
8087 gen_spr_power8_ids(env);
8088 gen_spr_power8_ebb(env);
8089 gen_spr_power8_fscr(env);
8090 gen_spr_power8_pmu_sup(env);
8091 gen_spr_power8_pmu_user(env);
8092 gen_spr_power8_tm(env);
8093 gen_spr_power8_pspb(env);
8094 gen_spr_vtb(env);
8095 gen_spr_power8_ic(env);
8096 gen_spr_power8_book4(env);
8097 }
8098 if (version < BOOK3S_CPU_POWER8) {
8099 gen_spr_book3s_dbg(env);
8100 } else {
8101 gen_spr_book3s_207_dbg(env);
8102 }
8103 #if !defined(CONFIG_USER_ONLY)
8104 switch (version) {
8105 case BOOK3S_CPU_970:
8106 case BOOK3S_CPU_POWER5PLUS:
8107 env->slb_nr = 64;
8108 break;
8109 case BOOK3S_CPU_POWER7:
8110 case BOOK3S_CPU_POWER8:
8111 default:
8112 env->slb_nr = 32;
8113 break;
8114 }
8115 #endif
8116 /* Allocate hardware IRQ controller */
8117 switch (version) {
8118 case BOOK3S_CPU_970:
8119 case BOOK3S_CPU_POWER5PLUS:
8120 init_excp_970(env);
8121 ppc970_irq_init(env);
8122 break;
8123 case BOOK3S_CPU_POWER7:
8124 case BOOK3S_CPU_POWER8:
8125 init_excp_POWER7(env);
8126 ppcPOWER7_irq_init(env);
8127 break;
8128 default:
8129 g_assert_not_reached();
8130 }
8131
8132 env->dcache_line_size = 128;
8133 env->icache_line_size = 128;
8134 }
8135
8136 static void init_proc_970(CPUPPCState *env)
8137 {
8138 init_proc_book3s_64(env, BOOK3S_CPU_970);
8139 }
8140
8141 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
8142 {
8143 DeviceClass *dc = DEVICE_CLASS(oc);
8144 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8145
8146 dc->desc = "PowerPC 970";
8147 pcc->init_proc = init_proc_970;
8148 pcc->check_pow = check_pow_970;
8149 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8150 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8151 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8152 PPC_FLOAT_STFIWX |
8153 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8154 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8155 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8156 PPC_64B | PPC_ALTIVEC |
8157 PPC_SEGMENT_64B | PPC_SLBI;
8158 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8159 pcc->msr_mask = (1ull << MSR_SF) |
8160 (1ull << MSR_VR) |
8161 (1ull << MSR_POW) |
8162 (1ull << MSR_EE) |
8163 (1ull << MSR_PR) |
8164 (1ull << MSR_FP) |
8165 (1ull << MSR_ME) |
8166 (1ull << MSR_FE0) |
8167 (1ull << MSR_SE) |
8168 (1ull << MSR_DE) |
8169 (1ull << MSR_FE1) |
8170 (1ull << MSR_IR) |
8171 (1ull << MSR_DR) |
8172 (1ull << MSR_PMM) |
8173 (1ull << MSR_RI);
8174 pcc->mmu_model = POWERPC_MMU_64B;
8175 #if defined(CONFIG_SOFTMMU)
8176 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8177 #endif
8178 pcc->excp_model = POWERPC_EXCP_970;
8179 pcc->bus_model = PPC_FLAGS_INPUT_970;
8180 pcc->bfd_mach = bfd_mach_ppc64;
8181 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8182 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8183 POWERPC_FLAG_BUS_CLK;
8184 pcc->l1_dcache_size = 0x8000;
8185 pcc->l1_icache_size = 0x10000;
8186 }
8187
8188 static void init_proc_power5plus(CPUPPCState *env)
8189 {
8190 init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
8191 }
8192
8193 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
8194 {
8195 DeviceClass *dc = DEVICE_CLASS(oc);
8196 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8197
8198 dc->fw_name = "PowerPC,POWER5";
8199 dc->desc = "POWER5+";
8200 pcc->init_proc = init_proc_power5plus;
8201 pcc->check_pow = check_pow_970;
8202 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
8203 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8204 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8205 PPC_FLOAT_STFIWX |
8206 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8207 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8208 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8209 PPC_64B |
8210 PPC_SEGMENT_64B | PPC_SLBI;
8211 pcc->insns_flags2 = PPC2_FP_CVT_S64;
8212 pcc->msr_mask = (1ull << MSR_SF) |
8213 (1ull << MSR_VR) |
8214 (1ull << MSR_POW) |
8215 (1ull << MSR_EE) |
8216 (1ull << MSR_PR) |
8217 (1ull << MSR_FP) |
8218 (1ull << MSR_ME) |
8219 (1ull << MSR_FE0) |
8220 (1ull << MSR_SE) |
8221 (1ull << MSR_DE) |
8222 (1ull << MSR_FE1) |
8223 (1ull << MSR_IR) |
8224 (1ull << MSR_DR) |
8225 (1ull << MSR_PMM) |
8226 (1ull << MSR_RI);
8227 pcc->mmu_model = POWERPC_MMU_2_03;
8228 #if defined(CONFIG_SOFTMMU)
8229 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8230 #endif
8231 pcc->excp_model = POWERPC_EXCP_970;
8232 pcc->bus_model = PPC_FLAGS_INPUT_970;
8233 pcc->bfd_mach = bfd_mach_ppc64;
8234 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8235 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8236 POWERPC_FLAG_BUS_CLK;
8237 pcc->l1_dcache_size = 0x8000;
8238 pcc->l1_icache_size = 0x10000;
8239 }
8240
8241 static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
8242 void *opaque, Error **errp)
8243 {
8244 char *value = (char *)"";
8245 Property *prop = opaque;
8246 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8247
8248 switch (*max_compat) {
8249 case CPU_POWERPC_LOGICAL_2_05:
8250 value = (char *)"power6";
8251 break;
8252 case CPU_POWERPC_LOGICAL_2_06:
8253 value = (char *)"power7";
8254 break;
8255 case CPU_POWERPC_LOGICAL_2_07:
8256 value = (char *)"power8";
8257 break;
8258 case 0:
8259 break;
8260 default:
8261 error_setg(errp, "Internal error: compat is set to %x",
8262 max_compat ? *max_compat : -1);
8263 break;
8264 }
8265
8266 visit_type_str(v, name, &value, errp);
8267 }
8268
8269 static void powerpc_set_compat(Object *obj, Visitor *v, const char *name,
8270 void *opaque, Error **errp)
8271 {
8272 Error *error = NULL;
8273 char *value = NULL;
8274 Property *prop = opaque;
8275 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
8276
8277 visit_type_str(v, name, &value, &error);
8278 if (error) {
8279 error_propagate(errp, error);
8280 return;
8281 }
8282
8283 if (strcmp(value, "power6") == 0) {
8284 *max_compat = CPU_POWERPC_LOGICAL_2_05;
8285 } else if (strcmp(value, "power7") == 0) {
8286 *max_compat = CPU_POWERPC_LOGICAL_2_06;
8287 } else if (strcmp(value, "power8") == 0) {
8288 *max_compat = CPU_POWERPC_LOGICAL_2_07;
8289 } else {
8290 error_setg(errp, "Invalid compatibility mode \"%s\"", value);
8291 }
8292
8293 g_free(value);
8294 }
8295
8296 static PropertyInfo powerpc_compat_propinfo = {
8297 .name = "str",
8298 .description = "compatibility mode, power6/power7/power8",
8299 .get = powerpc_get_compat,
8300 .set = powerpc_set_compat,
8301 };
8302
8303 #define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
8304 DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
8305
8306 static Property powerpc_servercpu_properties[] = {
8307 DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat),
8308 DEFINE_PROP_END_OF_LIST(),
8309 };
8310
8311 #ifdef CONFIG_SOFTMMU
8312 static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
8313 .sps = {
8314 {
8315 .page_shift = 12, /* 4K */
8316 .slb_enc = 0,
8317 .enc = { { .page_shift = 12, .pte_enc = 0 },
8318 { .page_shift = 16, .pte_enc = 0x7 },
8319 { .page_shift = 24, .pte_enc = 0x38 }, },
8320 },
8321 {
8322 .page_shift = 16, /* 64K */
8323 .slb_enc = SLB_VSID_64K,
8324 .enc = { { .page_shift = 16, .pte_enc = 0x1 },
8325 { .page_shift = 24, .pte_enc = 0x8 }, },
8326 },
8327 {
8328 .page_shift = 24, /* 16M */
8329 .slb_enc = SLB_VSID_16M,
8330 .enc = { { .page_shift = 24, .pte_enc = 0 }, },
8331 },
8332 {
8333 .page_shift = 34, /* 16G */
8334 .slb_enc = SLB_VSID_16G,
8335 .enc = { { .page_shift = 34, .pte_enc = 0x3 }, },
8336 },
8337 }
8338 };
8339 #endif /* CONFIG_SOFTMMU */
8340
8341 static void init_proc_POWER7 (CPUPPCState *env)
8342 {
8343 init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
8344 }
8345
8346 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
8347 {
8348 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) {
8349 return true;
8350 }
8351 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) {
8352 return true;
8353 }
8354 return false;
8355 }
8356
8357 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
8358 {
8359 DeviceClass *dc = DEVICE_CLASS(oc);
8360 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8361
8362 dc->fw_name = "PowerPC,POWER7";
8363 dc->desc = "POWER7";
8364 dc->props = powerpc_servercpu_properties;
8365 pcc->pvr_match = ppc_pvr_match_power7;
8366 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
8367 pcc->init_proc = init_proc_POWER7;
8368 pcc->check_pow = check_pow_nocheck;
8369 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8370 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8371 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8372 PPC_FLOAT_FRSQRTES |
8373 PPC_FLOAT_STFIWX |
8374 PPC_FLOAT_EXT |
8375 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8376 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8377 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8378 PPC_64B | PPC_ALTIVEC |
8379 PPC_SEGMENT_64B | PPC_SLBI |
8380 PPC_POPCNTB | PPC_POPCNTWD;
8381 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
8382 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8383 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8384 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64;
8385 pcc->msr_mask = (1ull << MSR_SF) |
8386 (1ull << MSR_VR) |
8387 (1ull << MSR_VSX) |
8388 (1ull << MSR_EE) |
8389 (1ull << MSR_PR) |
8390 (1ull << MSR_FP) |
8391 (1ull << MSR_ME) |
8392 (1ull << MSR_FE0) |
8393 (1ull << MSR_SE) |
8394 (1ull << MSR_DE) |
8395 (1ull << MSR_FE1) |
8396 (1ull << MSR_IR) |
8397 (1ull << MSR_DR) |
8398 (1ull << MSR_PMM) |
8399 (1ull << MSR_RI) |
8400 (1ull << MSR_LE);
8401 pcc->mmu_model = POWERPC_MMU_2_06;
8402 #if defined(CONFIG_SOFTMMU)
8403 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8404 pcc->sps = &POWER7_POWER8_sps;
8405 #endif
8406 pcc->excp_model = POWERPC_EXCP_POWER7;
8407 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8408 pcc->bfd_mach = bfd_mach_ppc64;
8409 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8410 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8411 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8412 POWERPC_FLAG_VSX;
8413 pcc->l1_dcache_size = 0x8000;
8414 pcc->l1_icache_size = 0x8000;
8415 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8416 }
8417
8418 static void init_proc_POWER8(CPUPPCState *env)
8419 {
8420 init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
8421 }
8422
8423 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
8424 {
8425 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) {
8426 return true;
8427 }
8428 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) {
8429 return true;
8430 }
8431 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) {
8432 return true;
8433 }
8434 return false;
8435 }
8436
8437 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8438 {
8439 DeviceClass *dc = DEVICE_CLASS(oc);
8440 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8441
8442 dc->fw_name = "PowerPC,POWER8";
8443 dc->desc = "POWER8";
8444 dc->props = powerpc_servercpu_properties;
8445 pcc->pvr_match = ppc_pvr_match_power8;
8446 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
8447 pcc->init_proc = init_proc_POWER8;
8448 pcc->check_pow = check_pow_nocheck;
8449 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8450 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
8451 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
8452 PPC_FLOAT_FRSQRTES |
8453 PPC_FLOAT_STFIWX |
8454 PPC_FLOAT_EXT |
8455 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
8456 PPC_MEM_SYNC | PPC_MEM_EIEIO |
8457 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
8458 PPC_64B | PPC_64BX | PPC_ALTIVEC |
8459 PPC_SEGMENT_64B | PPC_SLBI |
8460 PPC_POPCNTB | PPC_POPCNTWD;
8461 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8462 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8463 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8464 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8465 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8466 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
8467 PPC2_TM;
8468 pcc->msr_mask = (1ull << MSR_SF) |
8469 (1ull << MSR_TM) |
8470 (1ull << MSR_VR) |
8471 (1ull << MSR_VSX) |
8472 (1ull << MSR_EE) |
8473 (1ull << MSR_PR) |
8474 (1ull << MSR_FP) |
8475 (1ull << MSR_ME) |
8476 (1ull << MSR_FE0) |
8477 (1ull << MSR_SE) |
8478 (1ull << MSR_DE) |
8479 (1ull << MSR_FE1) |
8480 (1ull << MSR_IR) |
8481 (1ull << MSR_DR) |
8482 (1ull << MSR_PMM) |
8483 (1ull << MSR_RI) |
8484 (1ull << MSR_LE);
8485 pcc->mmu_model = POWERPC_MMU_2_07;
8486 #if defined(CONFIG_SOFTMMU)
8487 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8488 pcc->sps = &POWER7_POWER8_sps;
8489 #endif
8490 pcc->excp_model = POWERPC_EXCP_POWER8;
8491 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8492 pcc->bfd_mach = bfd_mach_ppc64;
8493 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8494 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8495 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8496 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
8497 pcc->l1_dcache_size = 0x8000;
8498 pcc->l1_icache_size = 0x8000;
8499 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8500 }
8501
8502 #if !defined(CONFIG_USER_ONLY)
8503
8504 void cpu_ppc_set_papr(PowerPCCPU *cpu)
8505 {
8506 CPUPPCState *env = &cpu->env;
8507 ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
8508
8509 /* PAPR always has exception vectors in RAM not ROM. To ensure this,
8510 * MSR[IP] should never be set.
8511 *
8512 * We also disallow setting of MSR_HV
8513 */
8514 env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
8515
8516 /* Set a full AMOR so guest can use the AMR as it sees fit */
8517 env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
8518
8519 /* Tell KVM that we're in PAPR mode */
8520 if (kvm_enabled()) {
8521 kvmppc_set_papr(cpu);
8522 }
8523 }
8524
8525 #endif /* !defined(CONFIG_USER_ONLY) */
8526
8527 #endif /* defined (TARGET_PPC64) */
8528
8529 /*****************************************************************************/
8530 /* Generic CPU instantiation routine */
8531 static void init_ppc_proc(PowerPCCPU *cpu)
8532 {
8533 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8534 CPUPPCState *env = &cpu->env;
8535 #if !defined(CONFIG_USER_ONLY)
8536 int i;
8537
8538 env->irq_inputs = NULL;
8539 /* Set all exception vectors to an invalid address */
8540 for (i = 0; i < POWERPC_EXCP_NB; i++)
8541 env->excp_vectors[i] = (target_ulong)(-1ULL);
8542 env->ivor_mask = 0x00000000;
8543 env->ivpr_mask = 0x00000000;
8544 /* Default MMU definitions */
8545 env->nb_BATs = 0;
8546 env->nb_tlb = 0;
8547 env->nb_ways = 0;
8548 env->tlb_type = TLB_NONE;
8549 #endif
8550 /* Register SPR common to all PowerPC implementations */
8551 gen_spr_generic(env);
8552 spr_register(env, SPR_PVR, "PVR",
8553 /* Linux permits userspace to read PVR */
8554 #if defined(CONFIG_LINUX_USER)
8555 &spr_read_generic,
8556 #else
8557 SPR_NOACCESS,
8558 #endif
8559 SPR_NOACCESS,
8560 &spr_read_generic, SPR_NOACCESS,
8561 pcc->pvr);
8562 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8563 if (pcc->svr != POWERPC_SVR_NONE) {
8564 if (pcc->svr & POWERPC_SVR_E500) {
8565 spr_register(env, SPR_E500_SVR, "SVR",
8566 SPR_NOACCESS, SPR_NOACCESS,
8567 &spr_read_generic, SPR_NOACCESS,
8568 pcc->svr & ~POWERPC_SVR_E500);
8569 } else {
8570 spr_register(env, SPR_SVR, "SVR",
8571 SPR_NOACCESS, SPR_NOACCESS,
8572 &spr_read_generic, SPR_NOACCESS,
8573 pcc->svr);
8574 }
8575 }
8576 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8577 (*pcc->init_proc)(env);
8578
8579 /* MSR bits & flags consistency checks */
8580 if (env->msr_mask & (1 << 25)) {
8581 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8582 case POWERPC_FLAG_SPE:
8583 case POWERPC_FLAG_VRE:
8584 break;
8585 default:
8586 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8587 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8588 exit(1);
8589 }
8590 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8591 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8592 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8593 exit(1);
8594 }
8595 if (env->msr_mask & (1 << 17)) {
8596 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8597 case POWERPC_FLAG_TGPR:
8598 case POWERPC_FLAG_CE:
8599 break;
8600 default:
8601 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8602 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8603 exit(1);
8604 }
8605 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8606 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8607 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8608 exit(1);
8609 }
8610 if (env->msr_mask & (1 << 10)) {
8611 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8612 POWERPC_FLAG_UBLE)) {
8613 case POWERPC_FLAG_SE:
8614 case POWERPC_FLAG_DWE:
8615 case POWERPC_FLAG_UBLE:
8616 break;
8617 default:
8618 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8619 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8620 "POWERPC_FLAG_UBLE\n");
8621 exit(1);
8622 }
8623 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8624 POWERPC_FLAG_UBLE)) {
8625 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8626 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8627 "POWERPC_FLAG_UBLE\n");
8628 exit(1);
8629 }
8630 if (env->msr_mask & (1 << 9)) {
8631 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8632 case POWERPC_FLAG_BE:
8633 case POWERPC_FLAG_DE:
8634 break;
8635 default:
8636 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8637 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8638 exit(1);
8639 }
8640 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8641 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8642 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8643 exit(1);
8644 }
8645 if (env->msr_mask & (1 << 2)) {
8646 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8647 case POWERPC_FLAG_PX:
8648 case POWERPC_FLAG_PMM:
8649 break;
8650 default:
8651 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8652 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8653 exit(1);
8654 }
8655 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8656 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8657 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8658 exit(1);
8659 }
8660 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8661 fprintf(stderr, "PowerPC flags inconsistency\n"
8662 "Should define the time-base and decrementer clock source\n");
8663 exit(1);
8664 }
8665 /* Allocate TLBs buffer when needed */
8666 #if !defined(CONFIG_USER_ONLY)
8667 if (env->nb_tlb != 0) {
8668 int nb_tlb = env->nb_tlb;
8669 if (env->id_tlbs != 0)
8670 nb_tlb *= 2;
8671 switch (env->tlb_type) {
8672 case TLB_6XX:
8673 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
8674 break;
8675 case TLB_EMB:
8676 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
8677 break;
8678 case TLB_MAS:
8679 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
8680 break;
8681 }
8682 /* Pre-compute some useful values */
8683 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8684 }
8685 if (env->irq_inputs == NULL) {
8686 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8687 " Attempt QEMU to crash very soon !\n");
8688 }
8689 #endif
8690 if (env->check_pow == NULL) {
8691 fprintf(stderr, "WARNING: no power management check handler "
8692 "registered.\n"
8693 " Attempt QEMU to crash very soon !\n");
8694 }
8695 }
8696
8697 #if defined(PPC_DUMP_CPU)
8698 static void dump_ppc_sprs (CPUPPCState *env)
8699 {
8700 ppc_spr_t *spr;
8701 #if !defined(CONFIG_USER_ONLY)
8702 uint32_t sr, sw;
8703 #endif
8704 uint32_t ur, uw;
8705 int i, j, n;
8706
8707 printf("Special purpose registers:\n");
8708 for (i = 0; i < 32; i++) {
8709 for (j = 0; j < 32; j++) {
8710 n = (i << 5) | j;
8711 spr = &env->spr_cb[n];
8712 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8713 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8714 #if !defined(CONFIG_USER_ONLY)
8715 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8716 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8717 if (sw || sr || uw || ur) {
8718 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8719 (i << 5) | j, (i << 5) | j, spr->name,
8720 sw ? 'w' : '-', sr ? 'r' : '-',
8721 uw ? 'w' : '-', ur ? 'r' : '-');
8722 }
8723 #else
8724 if (uw || ur) {
8725 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8726 (i << 5) | j, (i << 5) | j, spr->name,
8727 uw ? 'w' : '-', ur ? 'r' : '-');
8728 }
8729 #endif
8730 }
8731 }
8732 fflush(stdout);
8733 fflush(stderr);
8734 }
8735 #endif
8736
8737 /*****************************************************************************/
8738
8739 /* Opcode types */
8740 enum {
8741 PPC_DIRECT = 0, /* Opcode routine */
8742 PPC_INDIRECT = 1, /* Indirect opcode table */
8743 };
8744
8745 #define PPC_OPCODE_MASK 0x3
8746
8747 static inline int is_indirect_opcode (void *handler)
8748 {
8749 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT;
8750 }
8751
8752 static inline opc_handler_t **ind_table(void *handler)
8753 {
8754 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK);
8755 }
8756
8757 /* Instruction table creation */
8758 /* Opcodes tables creation */
8759 static void fill_new_table (opc_handler_t **table, int len)
8760 {
8761 int i;
8762
8763 for (i = 0; i < len; i++)
8764 table[i] = &invalid_handler;
8765 }
8766
8767 static int create_new_table (opc_handler_t **table, unsigned char idx)
8768 {
8769 opc_handler_t **tmp;
8770
8771 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN);
8772 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN);
8773 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8774
8775 return 0;
8776 }
8777
8778 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8779 opc_handler_t *handler)
8780 {
8781 if (table[idx] != &invalid_handler)
8782 return -1;
8783 table[idx] = handler;
8784
8785 return 0;
8786 }
8787
8788 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8789 unsigned char idx, opc_handler_t *handler)
8790 {
8791 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8792 printf("*** ERROR: opcode %02x already assigned in main "
8793 "opcode table\n", idx);
8794 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8795 printf(" Registered handler '%s' - new handler '%s'\n",
8796 ppc_opcodes[idx]->oname, handler->oname);
8797 #endif
8798 return -1;
8799 }
8800
8801 return 0;
8802 }
8803
8804 static int register_ind_in_table (opc_handler_t **table,
8805 unsigned char idx1, unsigned char idx2,
8806 opc_handler_t *handler)
8807 {
8808 if (table[idx1] == &invalid_handler) {
8809 if (create_new_table(table, idx1) < 0) {
8810 printf("*** ERROR: unable to create indirect table "
8811 "idx=%02x\n", idx1);
8812 return -1;
8813 }
8814 } else {
8815 if (!is_indirect_opcode(table[idx1])) {
8816 printf("*** ERROR: idx %02x already assigned to a direct "
8817 "opcode\n", idx1);
8818 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8819 printf(" Registered handler '%s' - new handler '%s'\n",
8820 ind_table(table[idx1])[idx2]->oname, handler->oname);
8821 #endif
8822 return -1;
8823 }
8824 }
8825 if (handler != NULL &&
8826 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8827 printf("*** ERROR: opcode %02x already assigned in "
8828 "opcode table %02x\n", idx2, idx1);
8829 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8830 printf(" Registered handler '%s' - new handler '%s'\n",
8831 ind_table(table[idx1])[idx2]->oname, handler->oname);
8832 #endif
8833 return -1;
8834 }
8835
8836 return 0;
8837 }
8838
8839 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8840 unsigned char idx1, unsigned char idx2,
8841 opc_handler_t *handler)
8842 {
8843 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8844 }
8845
8846 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8847 unsigned char idx1, unsigned char idx2,
8848 unsigned char idx3, opc_handler_t *handler)
8849 {
8850 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8851 printf("*** ERROR: unable to join indirect table idx "
8852 "[%02x-%02x]\n", idx1, idx2);
8853 return -1;
8854 }
8855 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8856 handler) < 0) {
8857 printf("*** ERROR: unable to insert opcode "
8858 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8859 return -1;
8860 }
8861
8862 return 0;
8863 }
8864
8865 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8866 {
8867 if (insn->opc2 != 0xFF) {
8868 if (insn->opc3 != 0xFF) {
8869 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8870 insn->opc3, &insn->handler) < 0)
8871 return -1;
8872 } else {
8873 if (register_ind_insn(ppc_opcodes, insn->opc1,
8874 insn->opc2, &insn->handler) < 0)
8875 return -1;
8876 }
8877 } else {
8878 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8879 return -1;
8880 }
8881
8882 return 0;
8883 }
8884
8885 static int test_opcode_table (opc_handler_t **table, int len)
8886 {
8887 int i, count, tmp;
8888
8889 for (i = 0, count = 0; i < len; i++) {
8890 /* Consistency fixup */
8891 if (table[i] == NULL)
8892 table[i] = &invalid_handler;
8893 if (table[i] != &invalid_handler) {
8894 if (is_indirect_opcode(table[i])) {
8895 tmp = test_opcode_table(ind_table(table[i]),
8896 PPC_CPU_INDIRECT_OPCODES_LEN);
8897 if (tmp == 0) {
8898 free(table[i]);
8899 table[i] = &invalid_handler;
8900 } else {
8901 count++;
8902 }
8903 } else {
8904 count++;
8905 }
8906 }
8907 }
8908
8909 return count;
8910 }
8911
8912 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8913 {
8914 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0)
8915 printf("*** WARNING: no opcode defined !\n");
8916 }
8917
8918 /*****************************************************************************/
8919 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8920 {
8921 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8922 CPUPPCState *env = &cpu->env;
8923 opcode_t *opc;
8924
8925 fill_new_table(env->opcodes, PPC_CPU_OPCODES_LEN);
8926 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8927 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8928 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8929 if (register_insn(env->opcodes, opc) < 0) {
8930 error_setg(errp, "ERROR initializing PowerPC instruction "
8931 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8932 opc->opc3);
8933 return;
8934 }
8935 }
8936 }
8937 fix_opcode_tables(env->opcodes);
8938 fflush(stdout);
8939 fflush(stderr);
8940 }
8941
8942 #if defined(PPC_DUMP_CPU)
8943 static void dump_ppc_insns (CPUPPCState *env)
8944 {
8945 opc_handler_t **table, *handler;
8946 const char *p, *q;
8947 uint8_t opc1, opc2, opc3;
8948
8949 printf("Instructions set:\n");
8950 /* opc1 is 6 bits long */
8951 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) {
8952 table = env->opcodes;
8953 handler = table[opc1];
8954 if (is_indirect_opcode(handler)) {
8955 /* opc2 is 5 bits long */
8956 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) {
8957 table = env->opcodes;
8958 handler = env->opcodes[opc1];
8959 table = ind_table(handler);
8960 handler = table[opc2];
8961 if (is_indirect_opcode(handler)) {
8962 table = ind_table(handler);
8963 /* opc3 is 5 bits long */
8964 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN;
8965 opc3++) {
8966 handler = table[opc3];
8967 if (handler->handler != &gen_invalid) {
8968 /* Special hack to properly dump SPE insns */
8969 p = strchr(handler->oname, '_');
8970 if (p == NULL) {
8971 printf("INSN: %02x %02x %02x (%02d %04d) : "
8972 "%s\n",
8973 opc1, opc2, opc3, opc1,
8974 (opc3 << 5) | opc2,
8975 handler->oname);
8976 } else {
8977 q = "speundef";
8978 if ((p - handler->oname) != strlen(q) ||
8979 memcmp(handler->oname, q, strlen(q)) != 0) {
8980 /* First instruction */
8981 printf("INSN: %02x %02x %02x (%02d %04d) : "
8982 "%.*s\n",
8983 opc1, opc2 << 1, opc3, opc1,
8984 (opc3 << 6) | (opc2 << 1),
8985 (int)(p - handler->oname),
8986 handler->oname);
8987 }
8988 if (strcmp(p + 1, q) != 0) {
8989 /* Second instruction */
8990 printf("INSN: %02x %02x %02x (%02d %04d) : "
8991 "%s\n",
8992 opc1, (opc2 << 1) | 1, opc3, opc1,
8993 (opc3 << 6) | (opc2 << 1) | 1,
8994 p + 1);
8995 }
8996 }
8997 }
8998 }
8999 } else {
9000 if (handler->handler != &gen_invalid) {
9001 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9002 opc1, opc2, opc1, opc2, handler->oname);
9003 }
9004 }
9005 }
9006 } else {
9007 if (handler->handler != &gen_invalid) {
9008 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9009 opc1, opc1, handler->oname);
9010 }
9011 }
9012 }
9013 }
9014 #endif
9015
9016 static bool avr_need_swap(CPUPPCState *env)
9017 {
9018 #ifdef HOST_WORDS_BIGENDIAN
9019 return msr_le;
9020 #else
9021 return !msr_le;
9022 #endif
9023 }
9024
9025 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9026 {
9027 if (n < 32) {
9028 stfq_p(mem_buf, env->fpr[n]);
9029 ppc_maybe_bswap_register(env, mem_buf, 8);
9030 return 8;
9031 }
9032 if (n == 32) {
9033 stl_p(mem_buf, env->fpscr);
9034 ppc_maybe_bswap_register(env, mem_buf, 4);
9035 return 4;
9036 }
9037 return 0;
9038 }
9039
9040 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9041 {
9042 if (n < 32) {
9043 ppc_maybe_bswap_register(env, mem_buf, 8);
9044 env->fpr[n] = ldfq_p(mem_buf);
9045 return 8;
9046 }
9047 if (n == 32) {
9048 ppc_maybe_bswap_register(env, mem_buf, 4);
9049 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
9050 return 4;
9051 }
9052 return 0;
9053 }
9054
9055 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9056 {
9057 if (n < 32) {
9058 if (!avr_need_swap(env)) {
9059 stq_p(mem_buf, env->avr[n].u64[0]);
9060 stq_p(mem_buf+8, env->avr[n].u64[1]);
9061 } else {
9062 stq_p(mem_buf, env->avr[n].u64[1]);
9063 stq_p(mem_buf+8, env->avr[n].u64[0]);
9064 }
9065 ppc_maybe_bswap_register(env, mem_buf, 8);
9066 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9067 return 16;
9068 }
9069 if (n == 32) {
9070 stl_p(mem_buf, env->vscr);
9071 ppc_maybe_bswap_register(env, mem_buf, 4);
9072 return 4;
9073 }
9074 if (n == 33) {
9075 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9076 ppc_maybe_bswap_register(env, mem_buf, 4);
9077 return 4;
9078 }
9079 return 0;
9080 }
9081
9082 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9083 {
9084 if (n < 32) {
9085 ppc_maybe_bswap_register(env, mem_buf, 8);
9086 ppc_maybe_bswap_register(env, mem_buf + 8, 8);
9087 if (!avr_need_swap(env)) {
9088 env->avr[n].u64[0] = ldq_p(mem_buf);
9089 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9090 } else {
9091 env->avr[n].u64[1] = ldq_p(mem_buf);
9092 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9093 }
9094 return 16;
9095 }
9096 if (n == 32) {
9097 ppc_maybe_bswap_register(env, mem_buf, 4);
9098 env->vscr = ldl_p(mem_buf);
9099 return 4;
9100 }
9101 if (n == 33) {
9102 ppc_maybe_bswap_register(env, mem_buf, 4);
9103 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9104 return 4;
9105 }
9106 return 0;
9107 }
9108
9109 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9110 {
9111 if (n < 32) {
9112 #if defined(TARGET_PPC64)
9113 stl_p(mem_buf, env->gpr[n] >> 32);
9114 ppc_maybe_bswap_register(env, mem_buf, 4);
9115 #else
9116 stl_p(mem_buf, env->gprh[n]);
9117 #endif
9118 return 4;
9119 }
9120 if (n == 32) {
9121 stq_p(mem_buf, env->spe_acc);
9122 ppc_maybe_bswap_register(env, mem_buf, 8);
9123 return 8;
9124 }
9125 if (n == 33) {
9126 stl_p(mem_buf, env->spe_fscr);
9127 ppc_maybe_bswap_register(env, mem_buf, 4);
9128 return 4;
9129 }
9130 return 0;
9131 }
9132
9133 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9134 {
9135 if (n < 32) {
9136 #if defined(TARGET_PPC64)
9137 target_ulong lo = (uint32_t)env->gpr[n];
9138 target_ulong hi;
9139
9140 ppc_maybe_bswap_register(env, mem_buf, 4);
9141
9142 hi = (target_ulong)ldl_p(mem_buf) << 32;
9143 env->gpr[n] = lo | hi;
9144 #else
9145 env->gprh[n] = ldl_p(mem_buf);
9146 #endif
9147 return 4;
9148 }
9149 if (n == 32) {
9150 ppc_maybe_bswap_register(env, mem_buf, 8);
9151 env->spe_acc = ldq_p(mem_buf);
9152 return 8;
9153 }
9154 if (n == 33) {
9155 ppc_maybe_bswap_register(env, mem_buf, 4);
9156 env->spe_fscr = ldl_p(mem_buf);
9157 return 4;
9158 }
9159 return 0;
9160 }
9161
9162 static int gdb_get_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9163 {
9164 if (n < 32) {
9165 stq_p(mem_buf, env->vsr[n]);
9166 ppc_maybe_bswap_register(env, mem_buf, 8);
9167 return 8;
9168 }
9169 return 0;
9170 }
9171
9172 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
9173 {
9174 if (n < 32) {
9175 ppc_maybe_bswap_register(env, mem_buf, 8);
9176 env->vsr[n] = ldq_p(mem_buf);
9177 return 8;
9178 }
9179 return 0;
9180 }
9181
9182 static int ppc_fixup_cpu(PowerPCCPU *cpu)
9183 {
9184 CPUPPCState *env = &cpu->env;
9185
9186 /* TCG doesn't (yet) emulate some groups of instructions that
9187 * are implemented on some otherwise supported CPUs (e.g. VSX
9188 * and decimal floating point instructions on POWER7). We
9189 * remove unsupported instruction groups from the cpu state's
9190 * instruction masks and hope the guest can cope. For at
9191 * least the pseries machine, the unavailability of these
9192 * instructions can be advertised to the guest via the device
9193 * tree. */
9194 if ((env->insns_flags & ~PPC_TCG_INSNS)
9195 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
9196 fprintf(stderr, "Warning: Disabling some instructions which are not "
9197 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
9198 env->insns_flags & ~PPC_TCG_INSNS,
9199 env->insns_flags2 & ~PPC_TCG_INSNS2);
9200 }
9201 env->insns_flags &= PPC_TCG_INSNS;
9202 env->insns_flags2 &= PPC_TCG_INSNS2;
9203 return 0;
9204 }
9205
9206 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
9207 {
9208 #ifdef TARGET_PPCEMB
9209 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
9210 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
9211 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
9212 #else
9213 return true;
9214 #endif
9215 }
9216
9217 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
9218 {
9219 CPUState *cs = CPU(dev);
9220 PowerPCCPU *cpu = POWERPC_CPU(dev);
9221 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9222 Error *local_err = NULL;
9223 #if !defined(CONFIG_USER_ONLY)
9224 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
9225 #endif
9226
9227 #if !defined(CONFIG_USER_ONLY)
9228 if (smp_threads > max_smt) {
9229 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
9230 max_smt, kvm_enabled() ? "KVM" : "TCG");
9231 return;
9232 }
9233 if (!is_power_of_2(smp_threads)) {
9234 error_setg(errp, "Cannot support %d threads on PPC with %s, "
9235 "threads count must be a power of 2.",
9236 smp_threads, kvm_enabled() ? "KVM" : "TCG");
9237 return;
9238 }
9239 #endif
9240
9241 cpu_exec_init(cs, &local_err);
9242 if (local_err != NULL) {
9243 error_propagate(errp, local_err);
9244 return;
9245 }
9246
9247 #if !defined(CONFIG_USER_ONLY)
9248 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
9249 + (cs->cpu_index % smp_threads);
9250 #endif
9251
9252 if (tcg_enabled()) {
9253 if (ppc_fixup_cpu(cpu) != 0) {
9254 error_setg(errp, "Unable to emulate selected CPU with TCG");
9255 return;
9256 }
9257 }
9258
9259 #if defined(TARGET_PPCEMB)
9260 if (!ppc_cpu_is_valid(pcc)) {
9261 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
9262 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
9263 "or choose another CPU model.");
9264 return;
9265 }
9266 #endif
9267
9268 create_ppc_opcodes(cpu, &local_err);
9269 if (local_err != NULL) {
9270 error_propagate(errp, local_err);
9271 return;
9272 }
9273 init_ppc_proc(cpu);
9274
9275 if (pcc->insns_flags & PPC_FLOAT) {
9276 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
9277 33, "power-fpu.xml", 0);
9278 }
9279 if (pcc->insns_flags & PPC_ALTIVEC) {
9280 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
9281 34, "power-altivec.xml", 0);
9282 }
9283 if (pcc->insns_flags & PPC_SPE) {
9284 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
9285 34, "power-spe.xml", 0);
9286 }
9287 if (pcc->insns_flags2 & PPC2_VSX) {
9288 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,
9289 32, "power-vsx.xml", 0);
9290 }
9291
9292 qemu_init_vcpu(cs);
9293
9294 pcc->parent_realize(dev, errp);
9295
9296 #if defined(PPC_DUMP_CPU)
9297 {
9298 CPUPPCState *env = &cpu->env;
9299 const char *mmu_model, *excp_model, *bus_model;
9300 switch (env->mmu_model) {
9301 case POWERPC_MMU_32B:
9302 mmu_model = "PowerPC 32";
9303 break;
9304 case POWERPC_MMU_SOFT_6xx:
9305 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9306 break;
9307 case POWERPC_MMU_SOFT_74xx:
9308 mmu_model = "PowerPC 74xx with software driven TLBs";
9309 break;
9310 case POWERPC_MMU_SOFT_4xx:
9311 mmu_model = "PowerPC 4xx with software driven TLBs";
9312 break;
9313 case POWERPC_MMU_SOFT_4xx_Z:
9314 mmu_model = "PowerPC 4xx with software driven TLBs "
9315 "and zones protections";
9316 break;
9317 case POWERPC_MMU_REAL:
9318 mmu_model = "PowerPC real mode only";
9319 break;
9320 case POWERPC_MMU_MPC8xx:
9321 mmu_model = "PowerPC MPC8xx";
9322 break;
9323 case POWERPC_MMU_BOOKE:
9324 mmu_model = "PowerPC BookE";
9325 break;
9326 case POWERPC_MMU_BOOKE206:
9327 mmu_model = "PowerPC BookE 2.06";
9328 break;
9329 case POWERPC_MMU_601:
9330 mmu_model = "PowerPC 601";
9331 break;
9332 #if defined (TARGET_PPC64)
9333 case POWERPC_MMU_64B:
9334 mmu_model = "PowerPC 64";
9335 break;
9336 #endif
9337 default:
9338 mmu_model = "Unknown or invalid";
9339 break;
9340 }
9341 switch (env->excp_model) {
9342 case POWERPC_EXCP_STD:
9343 excp_model = "PowerPC";
9344 break;
9345 case POWERPC_EXCP_40x:
9346 excp_model = "PowerPC 40x";
9347 break;
9348 case POWERPC_EXCP_601:
9349 excp_model = "PowerPC 601";
9350 break;
9351 case POWERPC_EXCP_602:
9352 excp_model = "PowerPC 602";
9353 break;
9354 case POWERPC_EXCP_603:
9355 excp_model = "PowerPC 603";
9356 break;
9357 case POWERPC_EXCP_603E:
9358 excp_model = "PowerPC 603e";
9359 break;
9360 case POWERPC_EXCP_604:
9361 excp_model = "PowerPC 604";
9362 break;
9363 case POWERPC_EXCP_7x0:
9364 excp_model = "PowerPC 740/750";
9365 break;
9366 case POWERPC_EXCP_7x5:
9367 excp_model = "PowerPC 745/755";
9368 break;
9369 case POWERPC_EXCP_74xx:
9370 excp_model = "PowerPC 74xx";
9371 break;
9372 case POWERPC_EXCP_BOOKE:
9373 excp_model = "PowerPC BookE";
9374 break;
9375 #if defined (TARGET_PPC64)
9376 case POWERPC_EXCP_970:
9377 excp_model = "PowerPC 970";
9378 break;
9379 #endif
9380 default:
9381 excp_model = "Unknown or invalid";
9382 break;
9383 }
9384 switch (env->bus_model) {
9385 case PPC_FLAGS_INPUT_6xx:
9386 bus_model = "PowerPC 6xx";
9387 break;
9388 case PPC_FLAGS_INPUT_BookE:
9389 bus_model = "PowerPC BookE";
9390 break;
9391 case PPC_FLAGS_INPUT_405:
9392 bus_model = "PowerPC 405";
9393 break;
9394 case PPC_FLAGS_INPUT_401:
9395 bus_model = "PowerPC 401/403";
9396 break;
9397 case PPC_FLAGS_INPUT_RCPU:
9398 bus_model = "RCPU / MPC8xx";
9399 break;
9400 #if defined (TARGET_PPC64)
9401 case PPC_FLAGS_INPUT_970:
9402 bus_model = "PowerPC 970";
9403 break;
9404 #endif
9405 default:
9406 bus_model = "Unknown or invalid";
9407 break;
9408 }
9409 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9410 " MMU model : %s\n",
9411 object_class_get_name(OBJECT_CLASS(pcc)),
9412 pcc->pvr, pcc->msr_mask, mmu_model);
9413 #if !defined(CONFIG_USER_ONLY)
9414 if (env->tlb.tlb6) {
9415 printf(" %d %s TLB in %d ways\n",
9416 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9417 env->nb_ways);
9418 }
9419 #endif
9420 printf(" Exceptions model : %s\n"
9421 " Bus model : %s\n",
9422 excp_model, bus_model);
9423 printf(" MSR features :\n");
9424 if (env->flags & POWERPC_FLAG_SPE)
9425 printf(" signal processing engine enable"
9426 "\n");
9427 else if (env->flags & POWERPC_FLAG_VRE)
9428 printf(" vector processor enable\n");
9429 if (env->flags & POWERPC_FLAG_TGPR)
9430 printf(" temporary GPRs\n");
9431 else if (env->flags & POWERPC_FLAG_CE)
9432 printf(" critical input enable\n");
9433 if (env->flags & POWERPC_FLAG_SE)
9434 printf(" single-step trace mode\n");
9435 else if (env->flags & POWERPC_FLAG_DWE)
9436 printf(" debug wait enable\n");
9437 else if (env->flags & POWERPC_FLAG_UBLE)
9438 printf(" user BTB lock enable\n");
9439 if (env->flags & POWERPC_FLAG_BE)
9440 printf(" branch-step trace mode\n");
9441 else if (env->flags & POWERPC_FLAG_DE)
9442 printf(" debug interrupt enable\n");
9443 if (env->flags & POWERPC_FLAG_PX)
9444 printf(" inclusive protection\n");
9445 else if (env->flags & POWERPC_FLAG_PMM)
9446 printf(" performance monitor mark\n");
9447 if (env->flags == POWERPC_FLAG_NONE)
9448 printf(" none\n");
9449 printf(" Time-base/decrementer clock source: %s\n",
9450 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9451 dump_ppc_insns(env);
9452 dump_ppc_sprs(env);
9453 fflush(stdout);
9454 }
9455 #endif
9456 }
9457
9458 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
9459 {
9460 PowerPCCPU *cpu = POWERPC_CPU(dev);
9461 CPUPPCState *env = &cpu->env;
9462 opc_handler_t **table;
9463 int i, j;
9464
9465 cpu_exec_exit(CPU(dev));
9466
9467 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
9468 if (env->opcodes[i] == &invalid_handler) {
9469 continue;
9470 }
9471 if (is_indirect_opcode(env->opcodes[i])) {
9472 table = ind_table(env->opcodes[i]);
9473 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) {
9474 if (table[j] != &invalid_handler &&
9475 is_indirect_opcode(table[j])) {
9476 g_free((opc_handler_t *)((uintptr_t)table[j] &
9477 ~PPC_INDIRECT));
9478 }
9479 }
9480 g_free((opc_handler_t *)((uintptr_t)env->opcodes[i] &
9481 ~PPC_INDIRECT));
9482 }
9483 }
9484 }
9485
9486 int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
9487 {
9488 int ret = MIN(smp_threads, kvmppc_smt_threads());
9489
9490 switch (cpu->cpu_version) {
9491 case CPU_POWERPC_LOGICAL_2_05:
9492 ret = MIN(ret, 2);
9493 break;
9494 case CPU_POWERPC_LOGICAL_2_06:
9495 ret = MIN(ret, 4);
9496 break;
9497 case CPU_POWERPC_LOGICAL_2_07:
9498 ret = MIN(ret, 8);
9499 break;
9500 }
9501
9502 return ret;
9503 }
9504
9505 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp)
9506 {
9507 int ret = 0;
9508 CPUPPCState *env = &cpu->env;
9509
9510 cpu->cpu_version = cpu_version;
9511
9512 switch (cpu_version) {
9513 case CPU_POWERPC_LOGICAL_2_05:
9514 env->spr[SPR_PCR] = PCR_COMPAT_2_05;
9515 break;
9516 case CPU_POWERPC_LOGICAL_2_06:
9517 env->spr[SPR_PCR] = PCR_COMPAT_2_06;
9518 break;
9519 case CPU_POWERPC_LOGICAL_2_06_PLUS:
9520 env->spr[SPR_PCR] = PCR_COMPAT_2_06;
9521 break;
9522 default:
9523 env->spr[SPR_PCR] = 0;
9524 break;
9525 }
9526
9527 if (kvm_enabled()) {
9528 ret = kvmppc_set_compat(cpu, cpu->cpu_version);
9529 if (ret < 0) {
9530 error_setg_errno(errp, -ret,
9531 "Unable to set CPU compatibility mode in KVM");
9532 }
9533 }
9534 }
9535
9536 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
9537 {
9538 ObjectClass *oc = (ObjectClass *)a;
9539 uint32_t pvr = *(uint32_t *)b;
9540 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9541
9542 /* -cpu host does a PVR lookup during construction */
9543 if (unlikely(strcmp(object_class_get_name(oc),
9544 TYPE_HOST_POWERPC_CPU) == 0)) {
9545 return -1;
9546 }
9547
9548 if (!ppc_cpu_is_valid(pcc)) {
9549 return -1;
9550 }
9551
9552 return pcc->pvr == pvr ? 0 : -1;
9553 }
9554
9555 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
9556 {
9557 GSList *list, *item;
9558 PowerPCCPUClass *pcc = NULL;
9559
9560 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9561 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
9562 if (item != NULL) {
9563 pcc = POWERPC_CPU_CLASS(item->data);
9564 }
9565 g_slist_free(list);
9566
9567 return pcc;
9568 }
9569
9570 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
9571 {
9572 ObjectClass *oc = (ObjectClass *)a;
9573 uint32_t pvr = *(uint32_t *)b;
9574 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9575
9576 /* -cpu host does a PVR lookup during construction */
9577 if (unlikely(strcmp(object_class_get_name(oc),
9578 TYPE_HOST_POWERPC_CPU) == 0)) {
9579 return -1;
9580 }
9581
9582 if (!ppc_cpu_is_valid(pcc)) {
9583 return -1;
9584 }
9585
9586 if (pcc->pvr_match(pcc, pvr)) {
9587 return 0;
9588 }
9589
9590 return -1;
9591 }
9592
9593 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
9594 {
9595 GSList *list, *item;
9596 PowerPCCPUClass *pcc = NULL;
9597
9598 list = object_class_get_list(TYPE_POWERPC_CPU, true);
9599 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
9600 if (item != NULL) {
9601 pcc = POWERPC_CPU_CLASS(item->data);
9602 }
9603 g_slist_free(list);
9604
9605 return pcc;
9606 }
9607
9608 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
9609 {
9610 ObjectClass *oc = (ObjectClass *)a;
9611 const char *name = b;
9612 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9613
9614 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
9615 ppc_cpu_is_valid(pcc) &&
9616 strcmp(object_class_get_name(oc) + strlen(name),
9617 "-" TYPE_POWERPC_CPU) == 0) {
9618 return 0;
9619 }
9620 return -1;
9621 }
9622
9623
9624 static ObjectClass *ppc_cpu_class_by_name(const char *name);
9625
9626 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
9627 {
9628 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
9629
9630 /* Cache target class lookups in the alias table */
9631 if (!alias->oc) {
9632 alias->oc = ppc_cpu_class_by_name(alias->model);
9633 if (!alias->oc) {
9634 /* Fast check for non-existing aliases */
9635 alias->oc = invalid_class;
9636 }
9637 }
9638
9639 if (alias->oc == invalid_class) {
9640 return NULL;
9641 } else {
9642 return alias->oc;
9643 }
9644 }
9645
9646 static ObjectClass *ppc_cpu_class_by_name(const char *name)
9647 {
9648 GSList *list, *item;
9649 ObjectClass *ret = NULL;
9650 const char *p;
9651 int i, len;
9652
9653 /* Check if the given name is a PVR */
9654 len = strlen(name);
9655 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9656 p = name + 2;
9657 goto check_pvr;
9658 } else if (len == 8) {
9659 p = name;
9660 check_pvr:
9661 for (i = 0; i < 8; i++) {
9662 if (!qemu_isxdigit(*p++))
9663 break;
9664 }
9665 if (i == 8) {
9666 return OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
9667 }
9668 }
9669
9670 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9671 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
9672 if (item != NULL) {
9673 ret = OBJECT_CLASS(item->data);
9674 }
9675 g_slist_free(list);
9676
9677 if (ret) {
9678 return ret;
9679 }
9680
9681 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9682 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
9683 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
9684 }
9685 }
9686
9687 return NULL;
9688 }
9689
9690 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
9691 {
9692 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
9693 }
9694
9695 /* Sort by PVR, ordering special case "host" last. */
9696 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
9697 {
9698 ObjectClass *oc_a = (ObjectClass *)a;
9699 ObjectClass *oc_b = (ObjectClass *)b;
9700 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
9701 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
9702 const char *name_a = object_class_get_name(oc_a);
9703 const char *name_b = object_class_get_name(oc_b);
9704
9705 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
9706 return 1;
9707 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
9708 return -1;
9709 } else {
9710 /* Avoid an integer overflow during subtraction */
9711 if (pcc_a->pvr < pcc_b->pvr) {
9712 return -1;
9713 } else if (pcc_a->pvr > pcc_b->pvr) {
9714 return 1;
9715 } else {
9716 return 0;
9717 }
9718 }
9719 }
9720
9721 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
9722 {
9723 ObjectClass *oc = data;
9724 CPUListState *s = user_data;
9725 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9726 const char *typename = object_class_get_name(oc);
9727 char *name;
9728 int i;
9729
9730 if (!ppc_cpu_is_valid(pcc)) {
9731 return;
9732 }
9733 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
9734 return;
9735 }
9736
9737 name = g_strndup(typename,
9738 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9739 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
9740 name, pcc->pvr);
9741 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9742 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9743 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
9744
9745 if (alias_oc != oc) {
9746 continue;
9747 }
9748 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
9749 alias->alias, name);
9750 }
9751 g_free(name);
9752 }
9753
9754 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
9755 {
9756 CPUListState s = {
9757 .file = f,
9758 .cpu_fprintf = cpu_fprintf,
9759 };
9760 GSList *list;
9761
9762 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9763 list = g_slist_sort(list, ppc_cpu_list_compare);
9764 g_slist_foreach(list, ppc_cpu_list_entry, &s);
9765 g_slist_free(list);
9766
9767 #ifdef CONFIG_KVM
9768 cpu_fprintf(f, "\n");
9769 cpu_fprintf(f, "PowerPC %-16s\n", "host");
9770 #endif
9771 }
9772
9773 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9774 {
9775 ObjectClass *oc = data;
9776 CpuDefinitionInfoList **first = user_data;
9777 const char *typename;
9778 CpuDefinitionInfoList *entry;
9779 CpuDefinitionInfo *info;
9780 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9781
9782 if (!ppc_cpu_is_valid(pcc)) {
9783 return;
9784 }
9785
9786 typename = object_class_get_name(oc);
9787 info = g_malloc0(sizeof(*info));
9788 info->name = g_strndup(typename,
9789 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9790
9791 entry = g_malloc0(sizeof(*entry));
9792 entry->value = info;
9793 entry->next = *first;
9794 *first = entry;
9795 }
9796
9797 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
9798 {
9799 CpuDefinitionInfoList *cpu_list = NULL;
9800 GSList *list;
9801 int i;
9802
9803 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9804 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9805 g_slist_free(list);
9806
9807 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9808 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9809 ObjectClass *oc;
9810 CpuDefinitionInfoList *entry;
9811 CpuDefinitionInfo *info;
9812
9813 oc = ppc_cpu_class_by_alias(alias);
9814 if (oc == NULL) {
9815 continue;
9816 }
9817
9818 info = g_malloc0(sizeof(*info));
9819 info->name = g_strdup(alias->alias);
9820
9821 entry = g_malloc0(sizeof(*entry));
9822 entry->value = info;
9823 entry->next = cpu_list;
9824 cpu_list = entry;
9825 }
9826
9827 return cpu_list;
9828 }
9829
9830 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9831 {
9832 PowerPCCPU *cpu = POWERPC_CPU(cs);
9833
9834 cpu->env.nip = value;
9835 }
9836
9837 static bool ppc_cpu_has_work(CPUState *cs)
9838 {
9839 PowerPCCPU *cpu = POWERPC_CPU(cs);
9840 CPUPPCState *env = &cpu->env;
9841
9842 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9843 }
9844
9845 static void ppc_cpu_exec_enter(CPUState *cs)
9846 {
9847 PowerPCCPU *cpu = POWERPC_CPU(cs);
9848 CPUPPCState *env = &cpu->env;
9849
9850 env->reserve_addr = -1;
9851 }
9852
9853 /* CPUClass::reset() */
9854 static void ppc_cpu_reset(CPUState *s)
9855 {
9856 PowerPCCPU *cpu = POWERPC_CPU(s);
9857 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9858 CPUPPCState *env = &cpu->env;
9859 target_ulong msr;
9860 int i;
9861
9862 pcc->parent_reset(s);
9863
9864 msr = (target_ulong)0;
9865 if (0) {
9866 /* XXX: find a suitable condition to enable the hypervisor mode */
9867 msr |= (target_ulong)MSR_HVB;
9868 }
9869 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9870 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9871 msr |= (target_ulong)1 << MSR_EP;
9872 #if defined(DO_SINGLE_STEP) && 0
9873 /* Single step trace mode */
9874 msr |= (target_ulong)1 << MSR_SE;
9875 msr |= (target_ulong)1 << MSR_BE;
9876 #endif
9877 #if defined(CONFIG_USER_ONLY)
9878 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9879 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9880 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
9881 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9882 msr |= (target_ulong)1 << MSR_PR;
9883 #if defined(TARGET_PPC64)
9884 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
9885 #endif
9886 #if !defined(TARGET_WORDS_BIGENDIAN)
9887 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
9888 if (!((env->msr_mask >> MSR_LE) & 1)) {
9889 fprintf(stderr, "Selected CPU does not support little-endian.\n");
9890 exit(1);
9891 }
9892 #endif
9893 #endif
9894
9895 #if defined(TARGET_PPC64)
9896 if (env->mmu_model & POWERPC_MMU_64) {
9897 msr |= (1ULL << MSR_SF);
9898 }
9899 #endif
9900
9901 hreg_store_msr(env, msr, 1);
9902
9903 #if !defined(CONFIG_USER_ONLY)
9904 env->nip = env->hreset_vector | env->excp_prefix;
9905 if (env->mmu_model != POWERPC_MMU_REAL) {
9906 ppc_tlb_invalidate_all(env);
9907 }
9908 #endif
9909
9910 hreg_compute_hflags(env);
9911 env->reserve_addr = (target_ulong)-1ULL;
9912 /* Be sure no exception or interrupt is pending */
9913 env->pending_interrupts = 0;
9914 s->exception_index = POWERPC_EXCP_NONE;
9915 env->error_code = 0;
9916
9917 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9918 env->vpa_addr = 0;
9919 env->slb_shadow_addr = 0;
9920 env->slb_shadow_size = 0;
9921 env->dtl_addr = 0;
9922 env->dtl_size = 0;
9923 #endif /* TARGET_PPC64 */
9924
9925 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9926 ppc_spr_t *spr = &env->spr_cb[i];
9927
9928 if (!spr->name) {
9929 continue;
9930 }
9931 env->spr[i] = spr->default_value;
9932 }
9933
9934 /* Flush all TLBs */
9935 tlb_flush(s, 1);
9936 }
9937
9938 #ifndef CONFIG_USER_ONLY
9939 static bool ppc_cpu_is_big_endian(CPUState *cs)
9940 {
9941 PowerPCCPU *cpu = POWERPC_CPU(cs);
9942 CPUPPCState *env = &cpu->env;
9943
9944 cpu_synchronize_state(cs);
9945
9946 return !msr_le;
9947 }
9948 #endif
9949
9950 static void ppc_cpu_initfn(Object *obj)
9951 {
9952 CPUState *cs = CPU(obj);
9953 PowerPCCPU *cpu = POWERPC_CPU(obj);
9954 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9955 CPUPPCState *env = &cpu->env;
9956
9957 cs->env_ptr = env;
9958
9959 env->msr_mask = pcc->msr_mask;
9960 env->mmu_model = pcc->mmu_model;
9961 env->excp_model = pcc->excp_model;
9962 env->bus_model = pcc->bus_model;
9963 env->insns_flags = pcc->insns_flags;
9964 env->insns_flags2 = pcc->insns_flags2;
9965 env->flags = pcc->flags;
9966 env->bfd_mach = pcc->bfd_mach;
9967 env->check_pow = pcc->check_pow;
9968
9969 #if defined(TARGET_PPC64)
9970 if (pcc->sps) {
9971 env->sps = *pcc->sps;
9972 } else if (env->mmu_model & POWERPC_MMU_64) {
9973 /* Use default sets of page sizes */
9974 static const struct ppc_segment_page_sizes defsps = {
9975 .sps = {
9976 { .page_shift = 12, /* 4K */
9977 .slb_enc = 0,
9978 .enc = { { .page_shift = 12, .pte_enc = 0 } }
9979 },
9980 { .page_shift = 24, /* 16M */
9981 .slb_enc = 0x100,
9982 .enc = { { .page_shift = 24, .pte_enc = 0 } }
9983 },
9984 },
9985 };
9986 env->sps = defsps;
9987 }
9988 #endif /* defined(TARGET_PPC64) */
9989
9990 if (tcg_enabled()) {
9991 ppc_translate_init();
9992 }
9993 }
9994
9995 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr)
9996 {
9997 return pcc->pvr == pvr;
9998 }
9999
10000 static gchar *ppc_gdb_arch_name(CPUState *cs)
10001 {
10002 #if defined(TARGET_PPC64)
10003 return g_strdup("powerpc:common64");
10004 #else
10005 return g_strdup("powerpc:common");
10006 #endif
10007 }
10008
10009 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
10010 {
10011 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
10012 CPUClass *cc = CPU_CLASS(oc);
10013 DeviceClass *dc = DEVICE_CLASS(oc);
10014
10015 pcc->parent_realize = dc->realize;
10016 pcc->pvr_match = ppc_pvr_match_default;
10017 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
10018 dc->realize = ppc_cpu_realizefn;
10019 dc->unrealize = ppc_cpu_unrealizefn;
10020
10021 pcc->parent_reset = cc->reset;
10022 cc->reset = ppc_cpu_reset;
10023
10024 cc->class_by_name = ppc_cpu_class_by_name;
10025 cc->has_work = ppc_cpu_has_work;
10026 cc->do_interrupt = ppc_cpu_do_interrupt;
10027 cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt;
10028 cc->dump_state = ppc_cpu_dump_state;
10029 cc->dump_statistics = ppc_cpu_dump_statistics;
10030 cc->set_pc = ppc_cpu_set_pc;
10031 cc->gdb_read_register = ppc_cpu_gdb_read_register;
10032 cc->gdb_write_register = ppc_cpu_gdb_write_register;
10033 #ifdef CONFIG_USER_ONLY
10034 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
10035 #else
10036 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
10037 cc->vmsd = &vmstate_ppc_cpu;
10038 #if defined(TARGET_PPC64)
10039 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
10040 #endif
10041 #endif
10042 cc->cpu_exec_enter = ppc_cpu_exec_enter;
10043
10044 cc->gdb_num_core_regs = 71;
10045
10046 #ifdef USE_APPLE_GDB
10047 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
10048 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
10049 cc->gdb_num_core_regs = 71 + 32;
10050 #endif
10051
10052 cc->gdb_arch_name = ppc_gdb_arch_name;
10053 #if defined(TARGET_PPC64)
10054 cc->gdb_core_xml_file = "power64-core.xml";
10055 #else
10056 cc->gdb_core_xml_file = "power-core.xml";
10057 #endif
10058 #ifndef CONFIG_USER_ONLY
10059 cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
10060 #endif
10061
10062 dc->fw_name = "PowerPC,UNKNOWN";
10063 }
10064
10065 static const TypeInfo ppc_cpu_type_info = {
10066 .name = TYPE_POWERPC_CPU,
10067 .parent = TYPE_CPU,
10068 .instance_size = sizeof(PowerPCCPU),
10069 .instance_init = ppc_cpu_initfn,
10070 .abstract = true,
10071 .class_size = sizeof(PowerPCCPUClass),
10072 .class_init = ppc_cpu_class_init,
10073 };
10074
10075 static void ppc_cpu_register_types(void)
10076 {
10077 type_register_static(&ppc_cpu_type_info);
10078 }
10079
10080 type_init(ppc_cpu_register_types)
QEmu