hw/isa/lpc_ich9.c

   1 /*
   2  * QEMU ICH9 Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009, 2010, 2011
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on piix.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "qemu-common.h"
  31 #include "hw/hw.h"
  32 #include "qapi/visitor.h"
  33 #include "qemu/range.h"
  34 #include "hw/isa/isa.h"
  35 #include "hw/sysbus.h"
  36 #include "hw/i386/pc.h"
  37 #include "hw/isa/apm.h"
  38 #include "hw/i386/ioapic.h"
  39 #include "hw/pci/pci.h"
  40 #include "hw/pci/pcie_host.h"
  41 #include "hw/pci/pci_bridge.h"
  42 #include "hw/i386/ich9.h"
  43 #include "hw/acpi/acpi.h"
  44 #include "hw/acpi/ich9.h"
  45 #include "hw/pci/pci_bus.h"
  46 #include "exec/address-spaces.h"
  47 #include "sysemu/sysemu.h"
  48
  49 static int ich9_lpc_sci_irq(ICH9LPCState *lpc);
  50
  51 /*****************************************************************************/
  52 /* ICH9 LPC PCI to ISA bridge */
  53
  54 static void ich9_lpc_reset(DeviceState *qdev);
  55
  56 /* chipset configuration register
  57  * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
  58  * are used.
  59  * Although it's not pci configuration space, it's little endian as Intel.
  60  */
  61
  62 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
  63 {
  64     int intx;
  65     for (intx = 0; intx < PCI_NUM_PINS; intx++) {
  66         irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
  67     }
  68 }
  69
  70 static void ich9_cc_update(ICH9LPCState *lpc)
  71 {
  72     int slot;
  73     int pci_intx;
  74
  75     const int reg_offsets[] = {
  76         ICH9_CC_D25IR,
  77         ICH9_CC_D26IR,
  78         ICH9_CC_D27IR,
  79         ICH9_CC_D28IR,
  80         ICH9_CC_D29IR,
  81         ICH9_CC_D30IR,
  82         ICH9_CC_D31IR,
  83     };
  84     const int *offset;
  85
  86     /* D{25 - 31}IR, but D30IR is read only to 0. */
  87     for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
  88         if (slot == 30) {
  89             continue;
  90         }
  91         ich9_cc_update_ir(lpc->irr[slot],
  92                           pci_get_word(lpc->chip_config + *offset));
  93     }
  94
  95     /*
  96      * D30: DMI2PCI bridge
  97      * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge
  98      * are connected to pirq lines. Our choice is PIRQ[E-H].
  99      * INT[A-D] are connected to PIRQ[E-H]
 100      */
 101     for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
 102         lpc->irr[30][pci_intx] = pci_intx + 4;
 103     }
 104 }
 105
 106 static void ich9_cc_init(ICH9LPCState *lpc)
 107 {
 108     int slot;
 109     int intx;
 110
 111     /* the default irq routing is arbitrary as long as it matches with
 112      * acpi irq routing table.
 113      * The one that is incompatible with piix_pci(= bochs) one is
 114      * intentionally chosen to let the users know that the different
 115      * board is used.
 116      *
 117      * int[A-D] -> pirq[E-F]
 118      * avoid pirq A-D because they are used for pci express port
 119      */
 120     for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
 121         for (intx = 0; intx < PCI_NUM_PINS; intx++) {
 122             lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
 123         }
 124     }
 125     ich9_cc_update(lpc);
 126 }
 127
 128 static void ich9_cc_reset(ICH9LPCState *lpc)
 129 {
 130     uint8_t *c = lpc->chip_config;
 131
 132     memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
 133
 134     pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
 135     pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
 136     pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
 137     pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
 138     pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
 139     pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
 140     pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
 141     pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
 142
 143     ich9_cc_update(lpc);
 144 }
 145
 146 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
 147 {
 148     *addr &= ICH9_CC_ADDR_MASK;
 149     if (*addr + *len >= ICH9_CC_SIZE) {
 150         *len = ICH9_CC_SIZE - *addr;
 151     }
 152 }
 153
 154 /* val: little endian */
 155 static void ich9_cc_write(void *opaque, hwaddr addr,
 156                           uint64_t val, unsigned len)
 157 {
 158     ICH9LPCState *lpc = (ICH9LPCState *)opaque;
 159
 160     ich9_cc_addr_len(&addr, &len);
 161     memcpy(lpc->chip_config + addr, &val, len);
 162     pci_bus_fire_intx_routing_notifier(lpc->d.bus);
 163     ich9_cc_update(lpc);
 164 }
 165
 166 /* return value: little endian */
 167 static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
 168                               unsigned len)
 169 {
 170     ICH9LPCState *lpc = (ICH9LPCState *)opaque;
 171
 172     uint32_t val = 0;
 173     ich9_cc_addr_len(&addr, &len);
 174     memcpy(&val, lpc->chip_config + addr, len);
 175     return val;
 176 }
 177
 178 /* IRQ routing */
 179 /* */
 180 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
 181 {
 182     *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
 183     *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
 184 }
 185
 186 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num,
 187                              int *pic_irq, int *pic_dis)
 188 {
 189     switch (pirq_num) {
 190     case 0 ... 3: /* A-D */
 191         ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num],
 192                       pic_irq, pic_dis);
 193         return;
 194     case 4 ... 7: /* E-H */
 195         ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)],
 196                       pic_irq, pic_dis);
 197         return;
 198     default:
 199         break;
 200     }
 201     abort();
 202 }
 203
 204 /* pic_irq: i8254 irq 0-15 */
 205 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int pic_irq)
 206 {
 207     int i, pic_level;
 208
 209     /* The pic level is the logical OR of all the PCI irqs mapped to it */
 210     pic_level = 0;
 211     for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
 212         int tmp_irq;
 213         int tmp_dis;
 214         ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
 215         if (!tmp_dis && pic_irq == tmp_irq) {
 216             pic_level |= pci_bus_get_irq_level(lpc->d.bus, i);
 217         }
 218     }
 219     if (pic_irq == ich9_lpc_sci_irq(lpc)) {
 220         pic_level |= lpc->sci_level;
 221     }
 222
 223     qemu_set_irq(lpc->pic[pic_irq], pic_level);
 224 }
 225
 226 /* pirq: pirq[A-H] 0-7*/
 227 static void ich9_lpc_update_by_pirq(ICH9LPCState *lpc, int pirq)
 228 {
 229     int pic_irq;
 230     int pic_dis;
 231
 232     ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
 233     assert(pic_irq < ICH9_LPC_PIC_NUM_PINS);
 234     if (pic_dis) {
 235         return;
 236     }
 237
 238     ich9_lpc_update_pic(lpc, pic_irq);
 239 }
 240
 241 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
 242 static int ich9_pirq_to_gsi(int pirq)
 243 {
 244     return pirq + ICH9_LPC_PIC_NUM_PINS;
 245 }
 246
 247 static int ich9_gsi_to_pirq(int gsi)
 248 {
 249     return gsi - ICH9_LPC_PIC_NUM_PINS;
 250 }
 251
 252 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
 253 {
 254     int level = 0;
 255
 256     if (gsi >= ICH9_LPC_PIC_NUM_PINS) {
 257         level |= pci_bus_get_irq_level(lpc->d.bus, ich9_gsi_to_pirq(gsi));
 258     }
 259     if (gsi == ich9_lpc_sci_irq(lpc)) {
 260         level |= lpc->sci_level;
 261     }
 262
 263     qemu_set_irq(lpc->ioapic[gsi], level);
 264 }
 265
 266 void ich9_lpc_set_irq(void *opaque, int pirq, int level)
 267 {
 268     ICH9LPCState *lpc = opaque;
 269
 270     assert(0 <= pirq);
 271     assert(pirq < ICH9_LPC_NB_PIRQS);
 272
 273     ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq));
 274     ich9_lpc_update_by_pirq(lpc, pirq);
 275 }
 276
 277 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to
 278  * a given device irq pin.
 279  */
 280 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
 281 {
 282     BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
 283     PCIBus *pci_bus = PCI_BUS(bus);
 284     PCIDevice *lpc_pdev =
 285             pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)];
 286     ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev);
 287
 288     return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
 289 }
 290
 291 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
 292 {
 293     ICH9LPCState *lpc = opaque;
 294     PCIINTxRoute route;
 295     int pic_irq;
 296     int pic_dis;
 297
 298     assert(0 <= pirq_pin);
 299     assert(pirq_pin < ICH9_LPC_NB_PIRQS);
 300
 301     route.mode = PCI_INTX_ENABLED;
 302     ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
 303     if (!pic_dis) {
 304         if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
 305             route.irq = pic_irq;
 306         } else {
 307             route.mode = PCI_INTX_DISABLED;
 308             route.irq = -1;
 309         }
 310     } else {
 311         route.irq = ich9_pirq_to_gsi(pirq_pin);
 312     }
 313
 314     return route;
 315 }
 316
 317 void ich9_generate_smi(void)
 318 {
 319     cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 320 }
 321
 322 void ich9_generate_nmi(void)
 323 {
 324     cpu_interrupt(first_cpu, CPU_INTERRUPT_NMI);
 325 }
 326
 327 static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
 328 {
 329     switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
 330             ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
 331     case ICH9_LPC_ACPI_CTRL_9:
 332         return 9;
 333     case ICH9_LPC_ACPI_CTRL_10:
 334         return 10;
 335     case ICH9_LPC_ACPI_CTRL_11:
 336         return 11;
 337     case ICH9_LPC_ACPI_CTRL_20:
 338         return 20;
 339     case ICH9_LPC_ACPI_CTRL_21:
 340         return 21;
 341     default:
 342         /* reserved */
 343         break;
 344     }
 345     return -1;
 346 }
 347
 348 static void ich9_set_sci(void *opaque, int irq_num, int level)
 349 {
 350     ICH9LPCState *lpc = opaque;
 351     int irq;
 352
 353     assert(irq_num == 0);
 354     level = !!level;
 355     if (level == lpc->sci_level) {
 356         return;
 357     }
 358     lpc->sci_level = level;
 359
 360     irq = ich9_lpc_sci_irq(lpc);
 361     if (irq < 0) {
 362         return;
 363     }
 364
 365     ich9_lpc_update_apic(lpc, irq);
 366     if (irq < ICH9_LPC_PIC_NUM_PINS) {
 367         ich9_lpc_update_pic(lpc, irq);
 368     }
 369 }
 370
 371 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled, bool enable_tco)
 372 {
 373     ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
 374     qemu_irq sci_irq;
 375
 376     sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
 377     ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, enable_tco, sci_irq);
 378     ich9_lpc_reset(&lpc->d.qdev);
 379 }
 380
 381 /* APM */
 382
 383 static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
 384 {
 385     ICH9LPCState *lpc = arg;
 386
 387     /* ACPI specs 3.0, 4.7.2.5 */
 388     acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
 389                         val == ICH9_APM_ACPI_ENABLE,
 390                         val == ICH9_APM_ACPI_DISABLE);
 391     if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
 392         return;
 393     }
 394
 395     /* SMI_EN = PMBASE + 30. SMI control and enable register */
 396     if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
 397         cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 398     }
 399 }
 400
 401 /* config:PMBASE */
 402 static void
 403 ich9_lpc_pmbase_update(ICH9LPCState *lpc)
 404 {
 405     uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
 406     pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
 407
 408     ich9_pm_iospace_update(&lpc->pm, pm_io_base);
 409 }
 410
 411 /* config:RBCA */
 412 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rbca_old)
 413 {
 414     uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
 415
 416     if (rbca_old & ICH9_LPC_RCBA_EN) {
 417             memory_region_del_subregion(get_system_memory(), &lpc->rbca_mem);
 418     }
 419     if (rbca & ICH9_LPC_RCBA_EN) {
 420             memory_region_add_subregion_overlap(get_system_memory(),
 421                                                 rbca & ICH9_LPC_RCBA_BA_MASK,
 422                                                 &lpc->rbca_mem, 1);
 423     }
 424 }
 425
 426 /* config:GEN_PMCON* */
 427 static void
 428 ich9_lpc_pmcon_update(ICH9LPCState *lpc)
 429 {
 430     uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
 431     uint16_t wmask;
 432
 433     if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
 434         wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
 435         wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
 436         pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
 437         lpc->pm.smi_en_wmask &= ~1;
 438     }
 439 }
 440
 441 static int ich9_lpc_post_load(void *opaque, int version_id)
 442 {
 443     ICH9LPCState *lpc = opaque;
 444
 445     ich9_lpc_pmbase_update(lpc);
 446     ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */);
 447     ich9_lpc_pmcon_update(lpc);
 448     return 0;
 449 }
 450
 451 static void ich9_lpc_config_write(PCIDevice *d,
 452                                   uint32_t addr, uint32_t val, int len)
 453 {
 454     ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
 455     uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
 456
 457     pci_default_write_config(d, addr, val, len);
 458     if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) {
 459         ich9_lpc_pmbase_update(lpc);
 460     }
 461     if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
 462         ich9_lpc_rcba_update(lpc, rbca_old);
 463     }
 464     if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
 465         pci_bus_fire_intx_routing_notifier(lpc->d.bus);
 466     }
 467     if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
 468         pci_bus_fire_intx_routing_notifier(lpc->d.bus);
 469     }
 470     if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
 471         ich9_lpc_pmcon_update(lpc);
 472     }
 473 }
 474
 475 static void ich9_lpc_reset(DeviceState *qdev)
 476 {
 477     PCIDevice *d = PCI_DEVICE(qdev);
 478     ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
 479     uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
 480     int i;
 481
 482     for (i = 0; i < 4; i++) {
 483         pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
 484                      ICH9_LPC_PIRQ_ROUT_DEFAULT);
 485     }
 486     for (i = 0; i < 4; i++) {
 487         pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
 488                      ICH9_LPC_PIRQ_ROUT_DEFAULT);
 489     }
 490     pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
 491
 492     pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
 493     pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
 494
 495     ich9_cc_reset(lpc);
 496
 497     ich9_lpc_pmbase_update(lpc);
 498     ich9_lpc_rcba_update(lpc, rbca_old);
 499
 500     lpc->sci_level = 0;
 501     lpc->rst_cnt = 0;
 502 }
 503
 504 static const MemoryRegionOps rbca_mmio_ops = {
 505     .read = ich9_cc_read,
 506     .write = ich9_cc_write,
 507     .endianness = DEVICE_LITTLE_ENDIAN,
 508 };
 509
 510 static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
 511 {
 512     ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
 513     MemoryRegion *io_as = pci_address_space_io(&s->d);
 514     uint8_t *pci_conf;
 515
 516     pci_conf = s->d.config;
 517     if (memory_region_present(io_as, 0x3f8)) {
 518         /* com1 */
 519         pci_conf[0x82] |= 0x01;
 520     }
 521     if (memory_region_present(io_as, 0x2f8)) {
 522         /* com2 */
 523         pci_conf[0x82] |= 0x02;
 524     }
 525     if (memory_region_present(io_as, 0x378)) {
 526         /* lpt */
 527         pci_conf[0x82] |= 0x04;
 528     }
 529     if (memory_region_present(io_as, 0x3f2)) {
 530         /* floppy */
 531         pci_conf[0x82] |= 0x08;
 532     }
 533 }
 534
 535 /* reset control */
 536 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
 537                                unsigned len)
 538 {
 539     ICH9LPCState *lpc = opaque;
 540
 541     if (val & 4) {
 542         qemu_system_reset_request();
 543         return;
 544     }
 545     lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
 546 }
 547
 548 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len)
 549 {
 550     ICH9LPCState *lpc = opaque;
 551
 552     return lpc->rst_cnt;
 553 }
 554
 555 static const MemoryRegionOps ich9_rst_cnt_ops = {
 556     .read = ich9_rst_cnt_read,
 557     .write = ich9_rst_cnt_write,
 558     .endianness = DEVICE_LITTLE_ENDIAN
 559 };
 560
 561 Object *ich9_lpc_find(void)
 562 {
 563     bool ambig;
 564     Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig);
 565
 566     if (ambig) {
 567         return NULL;
 568     }
 569     return o;
 570 }
 571
 572 static void ich9_lpc_get_sci_int(Object *obj, Visitor *v,
 573                                  void *opaque, const char *name,
 574                                  Error **errp)
 575 {
 576     ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
 577     uint32_t value = ich9_lpc_sci_irq(lpc);
 578
 579     visit_type_uint32(v, &value, name, errp);
 580 }
 581
 582 static void ich9_lpc_add_properties(ICH9LPCState *lpc)
 583 {
 584     static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
 585     static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
 586
 587     object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32",
 588                         ich9_lpc_get_sci_int,
 589                         NULL, NULL, NULL, NULL);
 590     object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 591                                   &acpi_enable_cmd, NULL);
 592     object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 593                                   &acpi_disable_cmd, NULL);
 594
 595     ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL);
 596 }
 597
 598 static void ich9_lpc_initfn(Object *obj)
 599 {
 600     ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
 601
 602     ich9_lpc_add_properties(lpc);
 603 }
 604
 605 static int ich9_lpc_init(PCIDevice *d)
 606 {
 607     ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
 608     ISABus *isa_bus;
 609
 610     isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io());
 611
 612     pci_set_long(d->wmask + ICH9_LPC_PMBASE,
 613                  ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
 614
 615     memory_region_init_io(&lpc->rbca_mem, OBJECT(d), &rbca_mmio_ops, lpc,
 616                             "lpc-rbca-mmio", ICH9_CC_SIZE);
 617
 618     lpc->isa_bus = isa_bus;
 619
 620     ich9_cc_init(lpc);
 621     apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
 622
 623     lpc->machine_ready.notify = ich9_lpc_machine_ready;
 624     qemu_add_machine_init_done_notifier(&lpc->machine_ready);
 625
 626     memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
 627                           "lpc-reset-control", 1);
 628     memory_region_add_subregion_overlap(pci_address_space_io(d),
 629                                         ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
 630                                         1);
 631     return 0;
 632 }
 633
 634 static void ich9_device_plug_cb(HotplugHandler *hotplug_dev,
 635                                 DeviceState *dev, Error **errp)
 636 {
 637     ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
 638
 639     ich9_pm_device_plug_cb(&lpc->pm, dev, errp);
 640 }
 641
 642 static void ich9_device_unplug_request_cb(HotplugHandler *hotplug_dev,
 643                                           DeviceState *dev, Error **errp)
 644 {
 645     ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
 646
 647     ich9_pm_device_unplug_request_cb(&lpc->pm, dev, errp);
 648 }
 649
 650 static void ich9_device_unplug_cb(HotplugHandler *hotplug_dev,
 651                                   DeviceState *dev, Error **errp)
 652 {
 653     ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev);
 654
 655     ich9_pm_device_unplug_cb(&lpc->pm, dev, errp);
 656 }
 657
 658 static bool ich9_rst_cnt_needed(void *opaque)
 659 {
 660     ICH9LPCState *lpc = opaque;
 661
 662     return (lpc->rst_cnt != 0);
 663 }
 664
 665 static const VMStateDescription vmstate_ich9_rst_cnt = {
 666     .name = "ICH9LPC/rst_cnt",
 667     .version_id = 1,
 668     .minimum_version_id = 1,
 669     .needed = ich9_rst_cnt_needed,
 670     .fields = (VMStateField[]) {
 671         VMSTATE_UINT8(rst_cnt, ICH9LPCState),
 672         VMSTATE_END_OF_LIST()
 673     }
 674 };
 675
 676 static const VMStateDescription vmstate_ich9_lpc = {
 677     .name = "ICH9LPC",
 678     .version_id = 1,
 679     .minimum_version_id = 1,
 680     .post_load = ich9_lpc_post_load,
 681     .fields = (VMStateField[]) {
 682         VMSTATE_PCI_DEVICE(d, ICH9LPCState),
 683         VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
 684         VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
 685         VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
 686         VMSTATE_UINT32(sci_level, ICH9LPCState),
 687         VMSTATE_END_OF_LIST()
 688     },
 689     .subsections = (const VMStateDescription*[]) {
 690         &vmstate_ich9_rst_cnt,
 691         NULL
 692     }
 693 };
 694
 695 static Property ich9_lpc_properties[] = {
 696     DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true),
 697     DEFINE_PROP_END_OF_LIST(),
 698 };
 699
 700 static void ich9_lpc_class_init(ObjectClass *klass, void *data)
 701 {
 702     DeviceClass *dc = DEVICE_CLASS(klass);
 703     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 704     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 705     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
 706
 707     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 708     dc->reset = ich9_lpc_reset;
 709     k->init = ich9_lpc_init;
 710     dc->vmsd = &vmstate_ich9_lpc;
 711     dc->props = ich9_lpc_properties;
 712     k->config_write = ich9_lpc_config_write;
 713     dc->desc = "ICH9 LPC bridge";
 714     k->vendor_id = PCI_VENDOR_ID_INTEL;
 715     k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
 716     k->revision = ICH9_A2_LPC_REVISION;
 717     k->class_id = PCI_CLASS_BRIDGE_ISA;
 718     /*
 719      * Reason: part of ICH9 southbridge, needs to be wired up by
 720      * pc_q35_init()
 721      */
 722     dc->cannot_instantiate_with_device_add_yet = true;
 723     hc->plug = ich9_device_plug_cb;
 724     hc->unplug_request = ich9_device_unplug_request_cb;
 725     hc->unplug = ich9_device_unplug_cb;
 726     adevc->ospm_status = ich9_pm_ospm_status;
 727 }
 728
 729 static const TypeInfo ich9_lpc_info = {
 730     .name       = TYPE_ICH9_LPC_DEVICE,
 731     .parent     = TYPE_PCI_DEVICE,
 732     .instance_size = sizeof(struct ICH9LPCState),
 733     .instance_init = ich9_lpc_initfn,
 734     .class_init  = ich9_lpc_class_init,
 735     .interfaces = (InterfaceInfo[]) {
 736         { TYPE_HOTPLUG_HANDLER },
 737         { TYPE_ACPI_DEVICE_IF },
 738         { }
 739     }
 740 };
 741
 742 static void ich9_lpc_register(void)
 743 {
 744     type_register_static(&ich9_lpc_info);
 745 }
 746
 747 type_init(ich9_lpc_register);