target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_S390X_H
  20 #define CPU_S390X_H
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 #define TARGET_LONG_BITS 64
  26
  27 #define ELF_MACHINE     EM_S390
  28
  29 #define CPUArchState struct CPUS390XState
  30
  31 #include "cpu-defs.h"
  32 #define TARGET_PAGE_BITS 12
  33
  34 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  35 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  36
  37 #include "cpu-all.h"
  38
  39 #include "softfloat.h"
  40
  41 #define NB_MMU_MODES 3
  42
  43 #define MMU_MODE0_SUFFIX _primary
  44 #define MMU_MODE1_SUFFIX _secondary
  45 #define MMU_MODE2_SUFFIX _home
  46
  47 #define MMU_USER_IDX 1
  48
  49 #define MAX_EXT_QUEUE 16
  50
  51 typedef struct PSW {
  52     uint64_t mask;
  53     uint64_t addr;
  54 } PSW;
  55
  56 typedef struct ExtQueue {
  57     uint32_t code;
  58     uint32_t param;
  59     uint32_t param64;
  60 } ExtQueue;
  61
  62 typedef struct CPUS390XState {
  63     uint64_t regs[16];  /* GP registers */
  64
  65     uint32_t aregs[16]; /* access registers */
  66
  67     uint32_t fpc;       /* floating-point control register */
  68     CPU_DoubleU fregs[16]; /* FP registers */
  69     float_status fpu_status; /* passed to softfloat lib */
  70
  71     PSW psw;
  72
  73     uint32_t cc_op;
  74     uint64_t cc_src;
  75     uint64_t cc_dst;
  76     uint64_t cc_vr;
  77
  78     uint64_t __excp_addr;
  79     uint64_t psa;
  80
  81     uint32_t int_pgm_code;
  82     uint32_t int_pgm_ilc;
  83
  84     uint32_t int_svc_code;
  85     uint32_t int_svc_ilc;
  86
  87     uint64_t cregs[16]; /* control registers */
  88
  89     int pending_int;
  90     ExtQueue ext_queue[MAX_EXT_QUEUE];
  91
  92     int ext_index;
  93
  94     CPU_COMMON
  95
  96     /* reset does memset(0) up to here */
  97
  98     int cpu_num;
  99     uint8_t *storage_keys;
 100
 101     uint64_t tod_offset;
 102     uint64_t tod_basetime;
 103     QEMUTimer *tod_timer;
 104
 105     QEMUTimer *cpu_timer;
 106 } CPUS390XState;
 107
 108 #if defined(CONFIG_USER_ONLY)
 109 static inline void cpu_clone_regs(CPUS390XState *env, target_ulong newsp)
 110 {
 111     if (newsp) {
 112         env->regs[15] = newsp;
 113     }
 114     env->regs[0] = 0;
 115 }
 116 #endif
 117
 118 /* Interrupt Codes */
 119 /* Program Interrupts */
 120 #define PGM_OPERATION                   0x0001
 121 #define PGM_PRIVILEGED                  0x0002
 122 #define PGM_EXECUTE                     0x0003
 123 #define PGM_PROTECTION                  0x0004
 124 #define PGM_ADDRESSING                  0x0005
 125 #define PGM_SPECIFICATION               0x0006
 126 #define PGM_DATA                        0x0007
 127 #define PGM_FIXPT_OVERFLOW              0x0008
 128 #define PGM_FIXPT_DIVIDE                0x0009
 129 #define PGM_DEC_OVERFLOW                0x000a
 130 #define PGM_DEC_DIVIDE                  0x000b
 131 #define PGM_HFP_EXP_OVERFLOW            0x000c
 132 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 133 #define PGM_HFP_SIGNIFICANCE            0x000e
 134 #define PGM_HFP_DIVIDE                  0x000f
 135 #define PGM_SEGMENT_TRANS               0x0010
 136 #define PGM_PAGE_TRANS                  0x0011
 137 #define PGM_TRANS_SPEC                  0x0012
 138 #define PGM_SPECIAL_OP                  0x0013
 139 #define PGM_OPERAND                     0x0015
 140 #define PGM_TRACE_TABLE                 0x0016
 141 #define PGM_SPACE_SWITCH                0x001c
 142 #define PGM_HFP_SQRT                    0x001d
 143 #define PGM_PC_TRANS_SPEC               0x001f
 144 #define PGM_AFX_TRANS                   0x0020
 145 #define PGM_ASX_TRANS                   0x0021
 146 #define PGM_LX_TRANS                    0x0022
 147 #define PGM_EX_TRANS                    0x0023
 148 #define PGM_PRIM_AUTH                   0x0024
 149 #define PGM_SEC_AUTH                    0x0025
 150 #define PGM_ALET_SPEC                   0x0028
 151 #define PGM_ALEN_SPEC                   0x0029
 152 #define PGM_ALE_SEQ                     0x002a
 153 #define PGM_ASTE_VALID                  0x002b
 154 #define PGM_ASTE_SEQ                    0x002c
 155 #define PGM_EXT_AUTH                    0x002d
 156 #define PGM_STACK_FULL                  0x0030
 157 #define PGM_STACK_EMPTY                 0x0031
 158 #define PGM_STACK_SPEC                  0x0032
 159 #define PGM_STACK_TYPE                  0x0033
 160 #define PGM_STACK_OP                    0x0034
 161 #define PGM_ASCE_TYPE                   0x0038
 162 #define PGM_REG_FIRST_TRANS             0x0039
 163 #define PGM_REG_SEC_TRANS               0x003a
 164 #define PGM_REG_THIRD_TRANS             0x003b
 165 #define PGM_MONITOR                     0x0040
 166 #define PGM_PER                         0x0080
 167 #define PGM_CRYPTO                      0x0119
 168
 169 /* External Interrupts */
 170 #define EXT_INTERRUPT_KEY               0x0040
 171 #define EXT_CLOCK_COMP                  0x1004
 172 #define EXT_CPU_TIMER                   0x1005
 173 #define EXT_MALFUNCTION                 0x1200
 174 #define EXT_EMERGENCY                   0x1201
 175 #define EXT_EXTERNAL_CALL               0x1202
 176 #define EXT_ETR                         0x1406
 177 #define EXT_SERVICE                     0x2401
 178 #define EXT_VIRTIO                      0x2603
 179
 180 /* PSW defines */
 181 #undef PSW_MASK_PER
 182 #undef PSW_MASK_DAT
 183 #undef PSW_MASK_IO
 184 #undef PSW_MASK_EXT
 185 #undef PSW_MASK_KEY
 186 #undef PSW_SHIFT_KEY
 187 #undef PSW_MASK_MCHECK
 188 #undef PSW_MASK_WAIT
 189 #undef PSW_MASK_PSTATE
 190 #undef PSW_MASK_ASC
 191 #undef PSW_MASK_CC
 192 #undef PSW_MASK_PM
 193 #undef PSW_MASK_64
 194
 195 #define PSW_MASK_PER            0x4000000000000000ULL
 196 #define PSW_MASK_DAT            0x0400000000000000ULL
 197 #define PSW_MASK_IO             0x0200000000000000ULL
 198 #define PSW_MASK_EXT            0x0100000000000000ULL
 199 #define PSW_MASK_KEY            0x00F0000000000000ULL
 200 #define PSW_SHIFT_KEY           56
 201 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 202 #define PSW_MASK_WAIT           0x0002000000000000ULL
 203 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 204 #define PSW_MASK_ASC            0x0000C00000000000ULL
 205 #define PSW_MASK_CC             0x0000300000000000ULL
 206 #define PSW_MASK_PM             0x00000F0000000000ULL
 207 #define PSW_MASK_64             0x0000000100000000ULL
 208 #define PSW_MASK_32             0x0000000080000000ULL
 209
 210 #undef PSW_ASC_PRIMARY
 211 #undef PSW_ASC_ACCREG
 212 #undef PSW_ASC_SECONDARY
 213 #undef PSW_ASC_HOME
 214
 215 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 216 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 217 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 218 #define PSW_ASC_HOME            0x0000C00000000000ULL
 219
 220 /* tb flags */
 221
 222 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 223 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 224 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 225 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 226 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 227 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 228 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 229 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 230 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 231 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 232 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 233 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 234 #define FLAG_MASK_32            0x00001000
 235
 236 static inline int cpu_mmu_index (CPUS390XState *env)
 237 {
 238     if (env->psw.mask & PSW_MASK_PSTATE) {
 239         return 1;
 240     }
 241
 242     return 0;
 243 }
 244
 245 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 246                                         target_ulong *cs_base, int *flags)
 247 {
 248     *pc = env->psw.addr;
 249     *cs_base = 0;
 250     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 251              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 252 }
 253
 254 static inline int get_ilc(uint8_t opc)
 255 {
 256     switch (opc >> 6) {
 257     case 0:
 258         return 1;
 259     case 1:
 260     case 2:
 261         return 2;
 262     case 3:
 263         return 3;
 264     }
 265
 266     return 0;
 267 }
 268
 269 #define ILC_LATER       0x20
 270 #define ILC_LATER_INC   0x21
 271 #define ILC_LATER_INC_2 0x22
 272
 273
 274 CPUS390XState *cpu_s390x_init(const char *cpu_model);
 275 void s390x_translate_init(void);
 276 int cpu_s390x_exec(CPUS390XState *s);
 277 void cpu_s390x_close(CPUS390XState *s);
 278 void do_interrupt (CPUS390XState *env);
 279
 280 /* you can call this signal handler from your SIGBUS and SIGSEGV
 281    signal handlers to inform the virtual CPU of exceptions. non zero
 282    is returned if the signal was handled by the virtual CPU.  */
 283 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 284                            void *puc);
 285 int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
 286                                 int mmu_idx);
 287 #define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
 288
 289
 290 #ifndef CONFIG_USER_ONLY
 291 void s390x_tod_timer(void *opaque);
 292 void s390x_cpu_timer(void *opaque);
 293
 294 int s390_virtio_hypercall(CPUS390XState *env, uint64_t mem, uint64_t hypercall);
 295
 296 #ifdef CONFIG_KVM
 297 void kvm_s390_interrupt(CPUS390XState *env, int type, uint32_t code);
 298 void kvm_s390_virtio_irq(CPUS390XState *env, int config_change, uint64_t token);
 299 void kvm_s390_interrupt_internal(CPUS390XState *env, int type, uint32_t parm,
 300                                  uint64_t parm64, int vm);
 301 #else
 302 static inline void kvm_s390_interrupt(CPUS390XState *env, int type, uint32_t code)
 303 {
 304 }
 305
 306 static inline void kvm_s390_virtio_irq(CPUS390XState *env, int config_change,
 307                                        uint64_t token)
 308 {
 309 }
 310
 311 static inline void kvm_s390_interrupt_internal(CPUS390XState *env, int type,
 312                                                uint32_t parm, uint64_t parm64,
 313                                                int vm)
 314 {
 315 }
 316 #endif
 317 CPUS390XState *s390_cpu_addr2state(uint16_t cpu_addr);
 318 void s390_add_running_cpu(CPUS390XState *env);
 319 unsigned s390_del_running_cpu(CPUS390XState *env);
 320
 321 /* from s390-virtio-bus */
 322 extern const target_phys_addr_t virtio_size;
 323
 324 #else
 325 static inline void s390_add_running_cpu(CPUS390XState *env)
 326 {
 327 }
 328
 329 static inline unsigned s390_del_running_cpu(CPUS390XState *env)
 330 {
 331     return 0;
 332 }
 333 #endif
 334 void cpu_lock(void);
 335 void cpu_unlock(void);
 336
 337 static inline void cpu_set_tls(CPUS390XState *env, target_ulong newtls)
 338 {
 339     env->aregs[0] = newtls >> 32;
 340     env->aregs[1] = newtls & 0xffffffffULL;
 341 }
 342
 343 #define cpu_init cpu_s390x_init
 344 #define cpu_exec cpu_s390x_exec
 345 #define cpu_gen_code cpu_s390x_gen_code
 346 #define cpu_signal_handler cpu_s390x_signal_handler
 347
 348 #include "exec-all.h"
 349
 350 #ifdef CONFIG_USER_ONLY
 351
 352 #define EXCP_OPEX 1 /* operation exception (sigill) */
 353 #define EXCP_SVC 2 /* supervisor call (syscall) */
 354 #define EXCP_ADDR 5 /* addressing exception */
 355 #define EXCP_SPEC 6 /* specification exception */
 356
 357 #else
 358
 359 #define EXCP_EXT 1 /* external interrupt */
 360 #define EXCP_SVC 2 /* supervisor call (syscall) */
 361 #define EXCP_PGM 3 /* program interruption */
 362
 363 #endif /* CONFIG_USER_ONLY */
 364
 365 #define INTERRUPT_EXT        (1 << 0)
 366 #define INTERRUPT_TOD        (1 << 1)
 367 #define INTERRUPT_CPUTIMER   (1 << 2)
 368
 369 /* Program Status Word.  */
 370 #define S390_PSWM_REGNUM 0
 371 #define S390_PSWA_REGNUM 1
 372 /* General Purpose Registers.  */
 373 #define S390_R0_REGNUM 2
 374 #define S390_R1_REGNUM 3
 375 #define S390_R2_REGNUM 4
 376 #define S390_R3_REGNUM 5
 377 #define S390_R4_REGNUM 6
 378 #define S390_R5_REGNUM 7
 379 #define S390_R6_REGNUM 8
 380 #define S390_R7_REGNUM 9
 381 #define S390_R8_REGNUM 10
 382 #define S390_R9_REGNUM 11
 383 #define S390_R10_REGNUM 12
 384 #define S390_R11_REGNUM 13
 385 #define S390_R12_REGNUM 14
 386 #define S390_R13_REGNUM 15
 387 #define S390_R14_REGNUM 16
 388 #define S390_R15_REGNUM 17
 389 /* Access Registers.  */
 390 #define S390_A0_REGNUM 18
 391 #define S390_A1_REGNUM 19
 392 #define S390_A2_REGNUM 20
 393 #define S390_A3_REGNUM 21
 394 #define S390_A4_REGNUM 22
 395 #define S390_A5_REGNUM 23
 396 #define S390_A6_REGNUM 24
 397 #define S390_A7_REGNUM 25
 398 #define S390_A8_REGNUM 26
 399 #define S390_A9_REGNUM 27
 400 #define S390_A10_REGNUM 28
 401 #define S390_A11_REGNUM 29
 402 #define S390_A12_REGNUM 30
 403 #define S390_A13_REGNUM 31
 404 #define S390_A14_REGNUM 32
 405 #define S390_A15_REGNUM 33
 406 /* Floating Point Control Word.  */
 407 #define S390_FPC_REGNUM 34
 408 /* Floating Point Registers.  */
 409 #define S390_F0_REGNUM 35
 410 #define S390_F1_REGNUM 36
 411 #define S390_F2_REGNUM 37
 412 #define S390_F3_REGNUM 38
 413 #define S390_F4_REGNUM 39
 414 #define S390_F5_REGNUM 40
 415 #define S390_F6_REGNUM 41
 416 #define S390_F7_REGNUM 42
 417 #define S390_F8_REGNUM 43
 418 #define S390_F9_REGNUM 44
 419 #define S390_F10_REGNUM 45
 420 #define S390_F11_REGNUM 46
 421 #define S390_F12_REGNUM 47
 422 #define S390_F13_REGNUM 48
 423 #define S390_F14_REGNUM 49
 424 #define S390_F15_REGNUM 50
 425 /* Total.  */
 426 #define S390_NUM_REGS 51
 427
 428 /* Pseudo registers -- PC and condition code.  */
 429 #define S390_PC_REGNUM S390_NUM_REGS
 430 #define S390_CC_REGNUM (S390_NUM_REGS+1)
 431 #define S390_NUM_PSEUDO_REGS 2
 432 #define S390_NUM_TOTAL_REGS (S390_NUM_REGS+2)
 433
 434
 435
 436 /* Program Status Word.  */
 437 #define S390_PSWM_REGNUM 0
 438 #define S390_PSWA_REGNUM 1
 439 /* General Purpose Registers.  */
 440 #define S390_R0_REGNUM 2
 441 #define S390_R1_REGNUM 3
 442 #define S390_R2_REGNUM 4
 443 #define S390_R3_REGNUM 5
 444 #define S390_R4_REGNUM 6
 445 #define S390_R5_REGNUM 7
 446 #define S390_R6_REGNUM 8
 447 #define S390_R7_REGNUM 9
 448 #define S390_R8_REGNUM 10
 449 #define S390_R9_REGNUM 11
 450 #define S390_R10_REGNUM 12
 451 #define S390_R11_REGNUM 13
 452 #define S390_R12_REGNUM 14
 453 #define S390_R13_REGNUM 15
 454 #define S390_R14_REGNUM 16
 455 #define S390_R15_REGNUM 17
 456 /* Access Registers.  */
 457 #define S390_A0_REGNUM 18
 458 #define S390_A1_REGNUM 19
 459 #define S390_A2_REGNUM 20
 460 #define S390_A3_REGNUM 21
 461 #define S390_A4_REGNUM 22
 462 #define S390_A5_REGNUM 23
 463 #define S390_A6_REGNUM 24
 464 #define S390_A7_REGNUM 25
 465 #define S390_A8_REGNUM 26
 466 #define S390_A9_REGNUM 27
 467 #define S390_A10_REGNUM 28
 468 #define S390_A11_REGNUM 29
 469 #define S390_A12_REGNUM 30
 470 #define S390_A13_REGNUM 31
 471 #define S390_A14_REGNUM 32
 472 #define S390_A15_REGNUM 33
 473 /* Floating Point Control Word.  */
 474 #define S390_FPC_REGNUM 34
 475 /* Floating Point Registers.  */
 476 #define S390_F0_REGNUM 35
 477 #define S390_F1_REGNUM 36
 478 #define S390_F2_REGNUM 37
 479 #define S390_F3_REGNUM 38
 480 #define S390_F4_REGNUM 39
 481 #define S390_F5_REGNUM 40
 482 #define S390_F6_REGNUM 41
 483 #define S390_F7_REGNUM 42
 484 #define S390_F8_REGNUM 43
 485 #define S390_F9_REGNUM 44
 486 #define S390_F10_REGNUM 45
 487 #define S390_F11_REGNUM 46
 488 #define S390_F12_REGNUM 47
 489 #define S390_F13_REGNUM 48
 490 #define S390_F14_REGNUM 49
 491 #define S390_F15_REGNUM 50
 492 /* Total.  */
 493 #define S390_NUM_REGS 51
 494
 495 /* Pseudo registers -- PC and condition code.  */
 496 #define S390_PC_REGNUM S390_NUM_REGS
 497 #define S390_CC_REGNUM (S390_NUM_REGS+1)
 498 #define S390_NUM_PSEUDO_REGS 2
 499 #define S390_NUM_TOTAL_REGS (S390_NUM_REGS+2)
 500
 501 /* CC optimization */
 502
 503 enum cc_op {
 504     CC_OP_CONST0 = 0,           /* CC is 0 */
 505     CC_OP_CONST1,               /* CC is 1 */
 506     CC_OP_CONST2,               /* CC is 2 */
 507     CC_OP_CONST3,               /* CC is 3 */
 508
 509     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 510     CC_OP_STATIC,               /* CC value is env->cc_op */
 511
 512     CC_OP_NZ,                   /* env->cc_dst != 0 */
 513     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 514     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 515     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 516     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 517     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 518     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 519
 520     CC_OP_ADD_64,               /* overflow on add (64bit) */
 521     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 522     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 523     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 524     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 525     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 526
 527     CC_OP_ADD_32,               /* overflow on add (32bit) */
 528     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 529     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 530     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 531     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 532     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 533
 534     CC_OP_COMP_32,              /* complement */
 535     CC_OP_COMP_64,              /* complement */
 536
 537     CC_OP_TM_32,                /* test under mask (32bit) */
 538     CC_OP_TM_64,                /* test under mask (64bit) */
 539
 540     CC_OP_LTGT_F32,             /* FP compare (32bit) */
 541     CC_OP_LTGT_F64,             /* FP compare (64bit) */
 542
 543     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 544     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 545
 546     CC_OP_ICM,                  /* insert characters under mask */
 547     CC_OP_SLAG,                 /* Calculate shift left signed */
 548     CC_OP_MAX
 549 };
 550
 551 static const char *cc_names[] = {
 552     [CC_OP_CONST0]    = "CC_OP_CONST0",
 553     [CC_OP_CONST1]    = "CC_OP_CONST1",
 554     [CC_OP_CONST2]    = "CC_OP_CONST2",
 555     [CC_OP_CONST3]    = "CC_OP_CONST3",
 556     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 557     [CC_OP_STATIC]    = "CC_OP_STATIC",
 558     [CC_OP_NZ]        = "CC_OP_NZ",
 559     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 560     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 561     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 562     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 563     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 564     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 565     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 566     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 567     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 568     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 569     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 570     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 571     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 572     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 573     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 574     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 575     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 576     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 577     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 578     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 579     [CC_OP_TM_32]     = "CC_OP_TM_32",
 580     [CC_OP_TM_64]     = "CC_OP_TM_64",
 581     [CC_OP_LTGT_F32]  = "CC_OP_LTGT_F32",
 582     [CC_OP_LTGT_F64]  = "CC_OP_LTGT_F64",
 583     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 584     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 585     [CC_OP_ICM]       = "CC_OP_ICM",
 586     [CC_OP_SLAG]      = "CC_OP_SLAG",
 587 };
 588
 589 static inline const char *cc_name(int cc_op)
 590 {
 591     return cc_names[cc_op];
 592 }
 593
 594 /* SCLP PV interface defines */
 595 #define SCLP_CMDW_READ_SCP_INFO         0x00020001
 596 #define SCLP_CMDW_READ_SCP_INFO_FORCED  0x00120001
 597
 598 #define SCP_LENGTH                      0x00
 599 #define SCP_FUNCTION_CODE               0x02
 600 #define SCP_CONTROL_MASK                0x03
 601 #define SCP_RESPONSE_CODE               0x06
 602 #define SCP_MEM_CODE                    0x08
 603 #define SCP_INCREMENT                   0x0a
 604
 605 typedef struct LowCore
 606 {
 607     /* prefix area: defined by architecture */
 608     uint32_t        ccw1[2];                  /* 0x000 */
 609     uint32_t        ccw2[4];                  /* 0x008 */
 610     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 611     uint32_t        ext_params;               /* 0x080 */
 612     uint16_t        cpu_addr;                 /* 0x084 */
 613     uint16_t        ext_int_code;             /* 0x086 */
 614     uint16_t        svc_ilc;                  /* 0x088 */
 615     uint16_t        svc_code;                 /* 0x08a */
 616     uint16_t        pgm_ilc;                  /* 0x08c */
 617     uint16_t        pgm_code;                 /* 0x08e */
 618     uint32_t        data_exc_code;            /* 0x090 */
 619     uint16_t        mon_class_num;            /* 0x094 */
 620     uint16_t        per_perc_atmid;           /* 0x096 */
 621     uint64_t        per_address;              /* 0x098 */
 622     uint8_t         exc_access_id;            /* 0x0a0 */
 623     uint8_t         per_access_id;            /* 0x0a1 */
 624     uint8_t         op_access_id;             /* 0x0a2 */
 625     uint8_t         ar_access_id;             /* 0x0a3 */
 626     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 627     uint64_t        trans_exc_code;           /* 0x0a8 */
 628     uint64_t        monitor_code;             /* 0x0b0 */
 629     uint16_t        subchannel_id;            /* 0x0b8 */
 630     uint16_t        subchannel_nr;            /* 0x0ba */
 631     uint32_t        io_int_parm;              /* 0x0bc */
 632     uint32_t        io_int_word;              /* 0x0c0 */
 633     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 634     uint32_t        stfl_fac_list;            /* 0x0c8 */
 635     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 636     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 637     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 638     uint32_t        external_damage_code;     /* 0x0f4 */
 639     uint64_t        failing_storage_address;  /* 0x0f8 */
 640     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 641     PSW             restart_old_psw;          /* 0x120 */
 642     PSW             external_old_psw;         /* 0x130 */
 643     PSW             svc_old_psw;              /* 0x140 */
 644     PSW             program_old_psw;          /* 0x150 */
 645     PSW             mcck_old_psw;             /* 0x160 */
 646     PSW             io_old_psw;               /* 0x170 */
 647     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 648     PSW             restart_psw;              /* 0x1a0 */
 649     PSW             external_new_psw;         /* 0x1b0 */
 650     PSW             svc_new_psw;              /* 0x1c0 */
 651     PSW             program_new_psw;          /* 0x1d0 */
 652     PSW             mcck_new_psw;             /* 0x1e0 */
 653     PSW             io_new_psw;               /* 0x1f0 */
 654     PSW             return_psw;               /* 0x200 */
 655     uint8_t         irb[64];                  /* 0x210 */
 656     uint64_t        sync_enter_timer;         /* 0x250 */
 657     uint64_t        async_enter_timer;        /* 0x258 */
 658     uint64_t        exit_timer;               /* 0x260 */
 659     uint64_t        last_update_timer;        /* 0x268 */
 660     uint64_t        user_timer;               /* 0x270 */
 661     uint64_t        system_timer;             /* 0x278 */
 662     uint64_t        last_update_clock;        /* 0x280 */
 663     uint64_t        steal_clock;              /* 0x288 */
 664     PSW             return_mcck_psw;          /* 0x290 */
 665     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 666     /* System info area */
 667     uint64_t        save_area[16];            /* 0xc00 */
 668     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 669     uint64_t        kernel_stack;             /* 0xd40 */
 670     uint64_t        thread_info;              /* 0xd48 */
 671     uint64_t        async_stack;              /* 0xd50 */
 672     uint64_t        kernel_asce;              /* 0xd58 */
 673     uint64_t        user_asce;                /* 0xd60 */
 674     uint64_t        panic_stack;              /* 0xd68 */
 675     uint64_t        user_exec_asce;           /* 0xd70 */
 676     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 677
 678     /* SMP info area: defined by DJB */
 679     uint64_t        clock_comparator;         /* 0xdc0 */
 680     uint64_t        ext_call_fast;            /* 0xdc8 */
 681     uint64_t        percpu_offset;            /* 0xdd0 */
 682     uint64_t        current_task;             /* 0xdd8 */
 683     uint32_t        softirq_pending;          /* 0xde0 */
 684     uint32_t        pad_0x0de4;               /* 0xde4 */
 685     uint64_t        int_clock;                /* 0xde8 */
 686     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 687
 688     /* 0xe00 is used as indicator for dump tools */
 689     /* whether the kernel died with panic() or not */
 690     uint32_t        panic_magic;              /* 0xe00 */
 691
 692     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 693
 694     /* 64 bit extparam used for pfault, diag 250 etc  */
 695     uint64_t        ext_params2;               /* 0x11B8 */
 696
 697     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 698
 699     /* System info area */
 700
 701     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 702     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 703     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 704     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 705     uint32_t        prefixreg_save_area;       /* 0x1318 */
 706     uint32_t        fpt_creg_save_area;        /* 0x131c */
 707     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 708     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 709     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 710     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 711     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 712     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 713     uint64_t        cregs_save_area[16];       /* 0x1380 */
 714
 715     /* align to the top of the prefix area */
 716
 717     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 718 } QEMU_PACKED LowCore;
 719
 720 /* STSI */
 721 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 722 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 723 #define STSI_LEVEL_1            0x0000000010000000ULL
 724 #define STSI_LEVEL_2            0x0000000020000000ULL
 725 #define STSI_LEVEL_3            0x0000000030000000ULL
 726 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 727 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 728 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 729 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 730
 731 /* Basic Machine Configuration */
 732 struct sysib_111 {
 733     uint32_t res1[8];
 734     uint8_t  manuf[16];
 735     uint8_t  type[4];
 736     uint8_t  res2[12];
 737     uint8_t  model[16];
 738     uint8_t  sequence[16];
 739     uint8_t  plant[4];
 740     uint8_t  res3[156];
 741 };
 742
 743 /* Basic Machine CPU */
 744 struct sysib_121 {
 745     uint32_t res1[80];
 746     uint8_t  sequence[16];
 747     uint8_t  plant[4];
 748     uint8_t  res2[2];
 749     uint16_t cpu_addr;
 750     uint8_t  res3[152];
 751 };
 752
 753 /* Basic Machine CPUs */
 754 struct sysib_122 {
 755     uint8_t res1[32];
 756     uint32_t capability;
 757     uint16_t total_cpus;
 758     uint16_t active_cpus;
 759     uint16_t standby_cpus;
 760     uint16_t reserved_cpus;
 761     uint16_t adjustments[2026];
 762 };
 763
 764 /* LPAR CPU */
 765 struct sysib_221 {
 766     uint32_t res1[80];
 767     uint8_t  sequence[16];
 768     uint8_t  plant[4];
 769     uint16_t cpu_id;
 770     uint16_t cpu_addr;
 771     uint8_t  res3[152];
 772 };
 773
 774 /* LPAR CPUs */
 775 struct sysib_222 {
 776     uint32_t res1[32];
 777     uint16_t lpar_num;
 778     uint8_t  res2;
 779     uint8_t  lcpuc;
 780     uint16_t total_cpus;
 781     uint16_t conf_cpus;
 782     uint16_t standby_cpus;
 783     uint16_t reserved_cpus;
 784     uint8_t  name[8];
 785     uint32_t caf;
 786     uint8_t  res3[16];
 787     uint16_t dedicated_cpus;
 788     uint16_t shared_cpus;
 789     uint8_t  res4[180];
 790 };
 791
 792 /* VM CPUs */
 793 struct sysib_322 {
 794     uint8_t  res1[31];
 795     uint8_t  count;
 796     struct {
 797         uint8_t  res2[4];
 798         uint16_t total_cpus;
 799         uint16_t conf_cpus;
 800         uint16_t standby_cpus;
 801         uint16_t reserved_cpus;
 802         uint8_t  name[8];
 803         uint32_t caf;
 804         uint8_t  cpi[16];
 805         uint8_t  res3[24];
 806     } vm[8];
 807     uint8_t res4[3552];
 808 };
 809
 810 /* MMU defines */
 811 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 812 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 813 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 814 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 815 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 816 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 817 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 818 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 819 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 820 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 821 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 822 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 823
 824 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 825 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 826 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 827 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 828 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 829 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 830 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 831
 832 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 833 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 834 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 835
 836 #define _PAGE_RO        0x200            /* HW read-only bit  */
 837 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 838
 839 #define SK_C                    (0x1 << 1)
 840 #define SK_R                    (0x1 << 2)
 841 #define SK_F                    (0x1 << 3)
 842 #define SK_ACC_MASK             (0xf << 4)
 843
 844
 845 /* EBCDIC handling */
 846 static const uint8_t ebcdic2ascii[] = {
 847     0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F,
 848     0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 849     0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07,
 850     0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
 851     0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B,
 852     0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07,
 853     0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04,
 854     0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A,
 855     0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86,
 856     0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21,
 857     0x26, 0x82, 0x88, 0x89, 0x8A, 0xA1, 0x8C, 0x07,
 858     0x8D, 0xE1, 0x5D, 0x24, 0x2A, 0x29, 0x3B, 0x5E,
 859     0x2D, 0x2F, 0x07, 0x8E, 0x07, 0x07, 0x07, 0x8F,
 860     0x80, 0xA5, 0x07, 0x2C, 0x25, 0x5F, 0x3E, 0x3F,
 861     0x07, 0x90, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
 862     0x70, 0x60, 0x3A, 0x23, 0x40, 0x27, 0x3D, 0x22,
 863     0x07, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
 864     0x68, 0x69, 0xAE, 0xAF, 0x07, 0x07, 0x07, 0xF1,
 865     0xF8, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70,
 866     0x71, 0x72, 0xA6, 0xA7, 0x91, 0x07, 0x92, 0x07,
 867     0xE6, 0x7E, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
 868     0x79, 0x7A, 0xAD, 0xAB, 0x07, 0x07, 0x07, 0x07,
 869     0x9B, 0x9C, 0x9D, 0xFA, 0x07, 0x07, 0x07, 0xAC,
 870     0xAB, 0x07, 0xAA, 0x7C, 0x07, 0x07, 0x07, 0x07,
 871     0x7B, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
 872     0x48, 0x49, 0x07, 0x93, 0x94, 0x95, 0xA2, 0x07,
 873     0x7D, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50,
 874     0x51, 0x52, 0x07, 0x96, 0x81, 0x97, 0xA3, 0x98,
 875     0x5C, 0xF6, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
 876     0x59, 0x5A, 0xFD, 0x07, 0x99, 0x07, 0x07, 0x07,
 877     0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
 878     0x38, 0x39, 0x07, 0x07, 0x9A, 0x07, 0x07, 0x07,
 879 };
 880
 881 static const uint8_t ascii2ebcdic [] = {
 882     0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F,
 883     0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 884     0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26,
 885     0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F,
 886     0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D,
 887     0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61,
 888     0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
 889     0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F,
 890     0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
 891     0xC8, 0xC9, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6,
 892     0xD7, 0xD8, 0xD9, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6,
 893     0xE7, 0xE8, 0xE9, 0xBA, 0xE0, 0xBB, 0xB0, 0x6D,
 894     0x79, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
 895     0x88, 0x89, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96,
 896     0x97, 0x98, 0x99, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6,
 897     0xA7, 0xA8, 0xA9, 0xC0, 0x4F, 0xD0, 0xA1, 0x07,
 898     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 899     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 900     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 901     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 902     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 903     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 904     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 905     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 906     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 907     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 908     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 909     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 910     0x3F, 0x59, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 911     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 912     0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
 913     0x90, 0x3F, 0x3F, 0x3F, 0x3F, 0xEA, 0x3F, 0xFF
 914 };
 915
 916 static inline void ebcdic_put(uint8_t *p, const char *ascii, int len)
 917 {
 918     int i;
 919
 920     for (i = 0; i < len; i++) {
 921         p[i] = ascii2ebcdic[(int)ascii[i]];
 922     }
 923 }
 924
 925 #define SIGP_SENSE             0x01
 926 #define SIGP_EXTERNAL_CALL     0x02
 927 #define SIGP_EMERGENCY         0x03
 928 #define SIGP_START             0x04
 929 #define SIGP_STOP              0x05
 930 #define SIGP_RESTART           0x06
 931 #define SIGP_STOP_STORE_STATUS 0x09
 932 #define SIGP_INITIAL_CPU_RESET 0x0b
 933 #define SIGP_CPU_RESET         0x0c
 934 #define SIGP_SET_PREFIX        0x0d
 935 #define SIGP_STORE_STATUS_ADDR 0x0e
 936 #define SIGP_SET_ARCH          0x12
 937
 938 /* cpu status bits */
 939 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 940 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 941 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 942 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 943 #define SIGP_STAT_STOPPED           0x00000040UL
 944 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 945 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 946 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 947 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 948 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 949
 950 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 951 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 952                   target_ulong *raddr, int *flags);
 953 int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code);
 954 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 955                  uint64_t vr);
 956
 957 #define TARGET_HAS_ICE 1
 958
 959 /* The value of the TOD clock for 1.1.1970. */
 960 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 961
 962 /* Converts ns to s390's clock format */
 963 static inline uint64_t time2tod(uint64_t ns) {
 964     return (ns << 9) / 125;
 965 }
 966
 967 static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t param,
 968                                   uint64_t param64)
 969 {
 970     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 971         /* ugh - can't queue anymore. Let's drop. */
 972         return;
 973     }
 974
 975     env->ext_index++;
 976     assert(env->ext_index < MAX_EXT_QUEUE);
 977
 978     env->ext_queue[env->ext_index].code = code;
 979     env->ext_queue[env->ext_index].param = param;
 980     env->ext_queue[env->ext_index].param64 = param64;
 981
 982     env->pending_int |= INTERRUPT_EXT;
 983     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 984 }
 985
 986 static inline bool cpu_has_work(CPUS390XState *env)
 987 {
 988     return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 989         (env->psw.mask & PSW_MASK_EXT);
 990 }
 991
 992 static inline void cpu_pc_from_tb(CPUS390XState *env, TranslationBlock* tb)
 993 {
 994     env->psw.addr = tb->pc;
 995 }
 996
 997 #include "cpu-qom.h"
 998
 999 #endif