hw/ide/ich.c

   1 /*
   2  * QEMU ICH Emulation
   3  *
   4  * Copyright (c) 2010 Sebastian Herbszt <herbszt@gmx.de>
   5  * Copyright (c) 2010 Alexander Graf <agraf@suse.de>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *
  21  * lspci dump of a ICH-9 real device
  22  *
  23  * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
  24  *         Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
  25  *         Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
  26  *         Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
  27  *         Latency: 0
  28  *         Interrupt: pin B routed to IRQ 222
  29  *         Region 0: I/O ports at d000 [size=8]
  30  *         Region 1: I/O ports at cc00 [size=4]
  31  *         Region 2: I/O ports at c880 [size=8]
  32  *         Region 3: I/O ports at c800 [size=4]
  33  *         Region 4: I/O ports at c480 [size=32]
  34  *         Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
  35  *         Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
  36  *                 Address: fee0f00c  Data: 41d9
  37  *         Capabilities: [70] Power Management version 3
  38  *                 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
  39  *                 Status: D0 PME-Enable- DSel=0 DScale=0 PME-
  40  *         Capabilities: [a8] SATA HBA <?>
  41  *         Capabilities: [b0] Vendor Specific Information <?>
  42  *         Kernel driver in use: ahci
  43  *         Kernel modules: ahci
  44  * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
  45  * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
  46  * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
  47  * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
  48  * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
  49  * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  50  * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  51  * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
  52  * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
  53  * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
  54  * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
  55  * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
  56  * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  57  * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  58  * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
  59  * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
  60  *
  61  */
  62
  63 #include <hw/hw.h>
  64 #include <hw/msi.h>
  65 #include <hw/pc.h>
  66 #include <hw/pci.h>
  67 #include <hw/isa.h>
  68 #include "block.h"
  69 #include "block_int.h"
  70 #include "dma.h"
  71
  72 #include <hw/ide/pci.h>
  73 #include <hw/ide/ahci.h>
  74
  75 static int pci_ich9_ahci_init(PCIDevice *dev)
  76 {
  77     struct AHCIPCIState *d;
  78     d = DO_UPCAST(struct AHCIPCIState, card, dev);
  79
  80     pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL);
  81     pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR);
  82
  83     pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA);
  84     pci_config_set_revision(d->card.config, 0x02);
  85     pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
  86
  87     d->card.config[PCI_CACHE_LINE_SIZE] = 0x08;  /* Cache line size */
  88     d->card.config[PCI_LATENCY_TIMER]   = 0x00;  /* Latency timer */
  89     pci_config_set_interrupt_pin(d->card.config, 1);
  90
  91     /* XXX Software should program this register */
  92     d->card.config[0x90]   = 1 << 6; /* Address Map Register - AHCI mode */
  93
  94     qemu_register_reset(ahci_reset, d);
  95
  96     /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
  97     pci_register_bar_simple(&d->card, 5, 0x1000, 0, d->ahci.mem);
  98
  99     msi_init(dev, 0x50, 1, true, false);
 100
 101     ahci_init(&d->ahci, &dev->qdev, 6);
 102     d->ahci.irq = d->card.irq[0];
 103
 104     return 0;
 105 }
 106
 107 static int pci_ich9_uninit(PCIDevice *dev)
 108 {
 109     struct AHCIPCIState *d;
 110     d = DO_UPCAST(struct AHCIPCIState, card, dev);
 111
 112     msi_uninit(dev);
 113     qemu_unregister_reset(ahci_reset, d);
 114     ahci_uninit(&d->ahci);
 115
 116     return 0;
 117 }
 118
 119 static void pci_ich9_write_config(PCIDevice *pci, uint32_t addr,
 120                                   uint32_t val, int len)
 121 {
 122     pci_default_write_config(pci, addr, val, len);
 123     msi_write_config(pci, addr, val, len);
 124 }
 125
 126 static PCIDeviceInfo ich_ahci_info[] = {
 127     {
 128         .qdev.name    = "ich9-ahci",
 129         .qdev.alias   = "ahci",
 130         .qdev.size    = sizeof(AHCIPCIState),
 131         .init         = pci_ich9_ahci_init,
 132         .exit         = pci_ich9_uninit,
 133         .config_write = pci_ich9_write_config,
 134     },{
 135         /* end of list */
 136     }
 137 };
 138
 139 static void ich_ahci_register(void)
 140 {
 141     pci_qdev_register_many(ich_ahci_info);
 142 }
 143 device_init(ich_ahci_register);