target/s390x/helper.c

   1 /*
   2  *  S/390 helpers
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *  Copyright (c) 2011 Alexander Graf
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "internal.h"
  25 #include "exec/gdbstub.h"
  26 #include "qemu/timer.h"
  27 #include "exec/exec-all.h"
  28 #include "hw/s390x/ioinst.h"
  29 #ifndef CONFIG_USER_ONLY
  30 #include "sysemu/sysemu.h"
  31 #endif
  32
  33 //#define DEBUG_S390
  34 //#define DEBUG_S390_STDOUT
  35
  36 #ifdef DEBUG_S390
  37 #ifdef DEBUG_S390_STDOUT
  38 #define DPRINTF(fmt, ...) \
  39     do { fprintf(stderr, fmt, ## __VA_ARGS__); \
  40          if (qemu_log_separate()) qemu_log(fmt, ##__VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
  44 #endif
  45 #else
  46 #define DPRINTF(fmt, ...) \
  47     do { } while (0)
  48 #endif
  49
  50
  51 #ifndef CONFIG_USER_ONLY
  52 void s390x_tod_timer(void *opaque)
  53 {
  54     S390CPU *cpu = opaque;
  55     CPUS390XState *env = &cpu->env;
  56
  57     env->pending_int |= INTERRUPT_TOD;
  58     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
  59 }
  60
  61 void s390x_cpu_timer(void *opaque)
  62 {
  63     S390CPU *cpu = opaque;
  64     CPUS390XState *env = &cpu->env;
  65
  66     env->pending_int |= INTERRUPT_CPUTIMER;
  67     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
  68 }
  69 #endif
  70
  71 S390CPU *s390x_new_cpu(const char *typename, uint32_t core_id, Error **errp)
  72 {
  73     S390CPU *cpu = S390_CPU(object_new(typename));
  74     Error *err = NULL;
  75
  76     object_property_set_int(OBJECT(cpu), core_id, "core-id", &err);
  77     if (err != NULL) {
  78         goto out;
  79     }
  80     object_property_set_bool(OBJECT(cpu), true, "realized", &err);
  81
  82 out:
  83     if (err) {
  84         error_propagate(errp, err);
  85         object_unref(OBJECT(cpu));
  86         cpu = NULL;
  87     }
  88     return cpu;
  89 }
  90
  91 #ifndef CONFIG_USER_ONLY
  92
  93 hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
  94 {
  95     S390CPU *cpu = S390_CPU(cs);
  96     CPUS390XState *env = &cpu->env;
  97     target_ulong raddr;
  98     int prot;
  99     uint64_t asc = env->psw.mask & PSW_MASK_ASC;
 100
 101     /* 31-Bit mode */
 102     if (!(env->psw.mask & PSW_MASK_64)) {
 103         vaddr &= 0x7fffffff;
 104     }
 105
 106     if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) {
 107         return -1;
 108     }
 109     return raddr;
 110 }
 111
 112 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
 113 {
 114     hwaddr phys_addr;
 115     target_ulong page;
 116
 117     page = vaddr & TARGET_PAGE_MASK;
 118     phys_addr = cpu_get_phys_page_debug(cs, page);
 119     phys_addr += (vaddr & ~TARGET_PAGE_MASK);
 120
 121     return phys_addr;
 122 }
 123
 124 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
 125 {
 126     uint64_t old_mask = env->psw.mask;
 127
 128     env->psw.addr = addr;
 129     env->psw.mask = mask;
 130     if (tcg_enabled()) {
 131         env->cc_op = (mask >> 44) & 3;
 132     }
 133
 134     if ((old_mask ^ mask) & PSW_MASK_PER) {
 135         s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env)));
 136     }
 137
 138     if (mask & PSW_MASK_WAIT) {
 139         S390CPU *cpu = s390_env_get_cpu(env);
 140         if (s390_cpu_halt(cpu) == 0) {
 141 #ifndef CONFIG_USER_ONLY
 142             qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
 143 #endif
 144         }
 145     }
 146 }
 147
 148 uint64_t get_psw_mask(CPUS390XState *env)
 149 {
 150     uint64_t r = env->psw.mask;
 151
 152     if (tcg_enabled()) {
 153         env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
 154                              env->cc_vr);
 155
 156         r &= ~PSW_MASK_CC;
 157         assert(!(env->cc_op & ~3));
 158         r |= (uint64_t)env->cc_op << 44;
 159     }
 160
 161     return r;
 162 }
 163
 164 LowCore *cpu_map_lowcore(CPUS390XState *env)
 165 {
 166     S390CPU *cpu = s390_env_get_cpu(env);
 167     LowCore *lowcore;
 168     hwaddr len = sizeof(LowCore);
 169
 170     lowcore = cpu_physical_memory_map(env->psa, &len, 1);
 171
 172     if (len < sizeof(LowCore)) {
 173         cpu_abort(CPU(cpu), "Could not map lowcore\n");
 174     }
 175
 176     return lowcore;
 177 }
 178
 179 void cpu_unmap_lowcore(LowCore *lowcore)
 180 {
 181     cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
 182 }
 183
 184 void do_restart_interrupt(CPUS390XState *env)
 185 {
 186     uint64_t mask, addr;
 187     LowCore *lowcore;
 188
 189     lowcore = cpu_map_lowcore(env);
 190
 191     lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env));
 192     lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr);
 193     mask = be64_to_cpu(lowcore->restart_new_psw.mask);
 194     addr = be64_to_cpu(lowcore->restart_new_psw.addr);
 195
 196     cpu_unmap_lowcore(lowcore);
 197
 198     load_psw(env, mask, addr);
 199 }
 200
 201 void s390_cpu_recompute_watchpoints(CPUState *cs)
 202 {
 203     const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS;
 204     S390CPU *cpu = S390_CPU(cs);
 205     CPUS390XState *env = &cpu->env;
 206
 207     /* We are called when the watchpoints have changed. First
 208        remove them all.  */
 209     cpu_watchpoint_remove_all(cs, BP_CPU);
 210
 211     /* Return if PER is not enabled */
 212     if (!(env->psw.mask & PSW_MASK_PER)) {
 213         return;
 214     }
 215
 216     /* Return if storage-alteration event is not enabled.  */
 217     if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) {
 218         return;
 219     }
 220
 221     if (env->cregs[10] == 0 && env->cregs[11] == -1LL) {
 222         /* We can't create a watchoint spanning the whole memory range, so
 223            split it in two parts.   */
 224         cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL);
 225         cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL);
 226     } else if (env->cregs[10] > env->cregs[11]) {
 227         /* The address range loops, create two watchpoints.  */
 228         cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10],
 229                               wp_flags, NULL);
 230         cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL);
 231
 232     } else {
 233         /* Default case, create a single watchpoint.  */
 234         cpu_watchpoint_insert(cs, env->cregs[10],
 235                               env->cregs[11] - env->cregs[10] + 1,
 236                               wp_flags, NULL);
 237     }
 238 }
 239
 240 #endif /* CONFIG_USER_ONLY */
 241
 242 void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
 243                          int flags)
 244 {
 245     S390CPU *cpu = S390_CPU(cs);
 246     CPUS390XState *env = &cpu->env;
 247     int i;
 248
 249     if (env->cc_op > 3) {
 250         cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
 251                     env->psw.mask, env->psw.addr, cc_name(env->cc_op));
 252     } else {
 253         cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
 254                     env->psw.mask, env->psw.addr, env->cc_op);
 255     }
 256
 257     for (i = 0; i < 16; i++) {
 258         cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
 259         if ((i % 4) == 3) {
 260             cpu_fprintf(f, "\n");
 261         } else {
 262             cpu_fprintf(f, " ");
 263         }
 264     }
 265
 266     for (i = 0; i < 16; i++) {
 267         cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll);
 268         if ((i % 4) == 3) {
 269             cpu_fprintf(f, "\n");
 270         } else {
 271             cpu_fprintf(f, " ");
 272         }
 273     }
 274
 275     for (i = 0; i < 32; i++) {
 276         cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i,
 277                     env->vregs[i][0].ll, env->vregs[i][1].ll);
 278         cpu_fprintf(f, (i % 2) ? "\n" : " ");
 279     }
 280
 281 #ifndef CONFIG_USER_ONLY
 282     for (i = 0; i < 16; i++) {
 283         cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
 284         if ((i % 4) == 3) {
 285             cpu_fprintf(f, "\n");
 286         } else {
 287             cpu_fprintf(f, " ");
 288         }
 289     }
 290 #endif
 291
 292 #ifdef DEBUG_INLINE_BRANCHES
 293     for (i = 0; i < CC_OP_MAX; i++) {
 294         cpu_fprintf(f, "  %15s = %10ld\t%10ld\n", cc_name(i),
 295                     inline_branch_miss[i], inline_branch_hit[i]);
 296     }
 297 #endif
 298
 299     cpu_fprintf(f, "\n");
 300 }
 301
 302 const char *cc_name(enum cc_op cc_op)
 303 {
 304     static const char * const cc_names[] = {
 305         [CC_OP_CONST0]    = "CC_OP_CONST0",
 306         [CC_OP_CONST1]    = "CC_OP_CONST1",
 307         [CC_OP_CONST2]    = "CC_OP_CONST2",
 308         [CC_OP_CONST3]    = "CC_OP_CONST3",
 309         [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 310         [CC_OP_STATIC]    = "CC_OP_STATIC",
 311         [CC_OP_NZ]        = "CC_OP_NZ",
 312         [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 313         [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 314         [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 315         [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 316         [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 317         [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 318         [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 319         [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 320         [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 321         [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 322         [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 323         [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 324         [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 325         [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 326         [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 327         [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 328         [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 329         [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 330         [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 331         [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 332         [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 333         [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 334         [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 335         [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 336         [CC_OP_TM_32]     = "CC_OP_TM_32",
 337         [CC_OP_TM_64]     = "CC_OP_TM_64",
 338         [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 339         [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 340         [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 341         [CC_OP_ICM]       = "CC_OP_ICM",
 342         [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 343         [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 344         [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 345     };
 346
 347     return cc_names[cc_op];
 348 }