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ide: replace blk_drain_all by blk_drain
[qemu.git] / hw / ide / core.c
blob40b6cc8c62e45e215e91a3ed6d192d74698b2b83
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include <hw/hw.h>
27 #include <hw/i386/pc.h>
28 #include <hw/pci/pci.h>
29 #include <hw/isa/isa.h>
30 #include "qemu/error-report.h"
31 #include "qemu/timer.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/dma.h"
34 #include "hw/block/block.h"
35 #include "sysemu/block-backend.h"
36
37 #include <hw/ide/internal.h>
38
39 /* These values were based on a Seagate ST3500418AS but have been modified
40 to make more sense in QEMU */
41 static const int smart_attributes[][12] = {
42 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
43 /* raw read error rate*/
44 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
45 /* spin up */
46 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
47 /* start stop count */
48 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
49 /* remapped sectors */
50 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
51 /* power on hours */
52 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
53 /* power cycle count */
54 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
55 /* airflow-temperature-celsius */
56 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
57 };
58
59 static int ide_handle_rw_error(IDEState *s, int error, int op);
60 static void ide_dummy_transfer_stop(IDEState *s);
61
62 static void padstr(char *str, const char *src, int len)
63 {
64 int i, v;
65 for(i = 0; i < len; i++) {
66 if (*src)
67 v = *src++;
68 else
69 v = ' ';
70 str[i^1] = v;
71 }
72 }
73
74 static void put_le16(uint16_t *p, unsigned int v)
75 {
76 *p = cpu_to_le16(v);
77 }
78
79 static void ide_identify_size(IDEState *s)
80 {
81 uint16_t *p = (uint16_t *)s->identify_data;
82 put_le16(p + 60, s->nb_sectors);
83 put_le16(p + 61, s->nb_sectors >> 16);
84 put_le16(p + 100, s->nb_sectors);
85 put_le16(p + 101, s->nb_sectors >> 16);
86 put_le16(p + 102, s->nb_sectors >> 32);
87 put_le16(p + 103, s->nb_sectors >> 48);
88 }
89
90 static void ide_identify(IDEState *s)
91 {
92 uint16_t *p;
93 unsigned int oldsize;
94 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
95
96 p = (uint16_t *)s->identify_data;
97 if (s->identify_set) {
98 goto fill_buffer;
99 }
100 memset(p, 0, sizeof(s->identify_data));
101
102 put_le16(p + 0, 0x0040);
103 put_le16(p + 1, s->cylinders);
104 put_le16(p + 3, s->heads);
105 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
106 put_le16(p + 5, 512); /* XXX: retired, remove ? */
107 put_le16(p + 6, s->sectors);
108 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
109 put_le16(p + 20, 3); /* XXX: retired, remove ? */
110 put_le16(p + 21, 512); /* cache size in sectors */
111 put_le16(p + 22, 4); /* ecc bytes */
112 padstr((char *)(p + 23), s->version, 8); /* firmware version */
113 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
114 #if MAX_MULT_SECTORS > 1
115 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
116 #endif
117 put_le16(p + 48, 1); /* dword I/O */
118 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
119 put_le16(p + 51, 0x200); /* PIO transfer cycle */
120 put_le16(p + 52, 0x200); /* DMA transfer cycle */
121 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
122 put_le16(p + 54, s->cylinders);
123 put_le16(p + 55, s->heads);
124 put_le16(p + 56, s->sectors);
125 oldsize = s->cylinders * s->heads * s->sectors;
126 put_le16(p + 57, oldsize);
127 put_le16(p + 58, oldsize >> 16);
128 if (s->mult_sectors)
129 put_le16(p + 59, 0x100 | s->mult_sectors);
130 /* *(p + 60) := nb_sectors -- see ide_identify_size */
131 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
132 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
133 put_le16(p + 63, 0x07); /* mdma0-2 supported */
134 put_le16(p + 64, 0x03); /* pio3-4 supported */
135 put_le16(p + 65, 120);
136 put_le16(p + 66, 120);
137 put_le16(p + 67, 120);
138 put_le16(p + 68, 120);
139 if (dev && dev->conf.discard_granularity) {
140 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
141 }
142
143 if (s->ncq_queues) {
144 put_le16(p + 75, s->ncq_queues - 1);
145 /* NCQ supported */
146 put_le16(p + 76, (1 << 8));
147 }
148
149 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
150 put_le16(p + 81, 0x16); /* conforms to ata5 */
151 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
152 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
153 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
154 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
155 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
156 if (s->wwn) {
157 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
158 } else {
159 put_le16(p + 84, (1 << 14) | 0);
160 }
161 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
162 if (blk_enable_write_cache(s->blk)) {
163 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
164 } else {
165 put_le16(p + 85, (1 << 14) | 1);
166 }
167 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
168 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
169 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
170 if (s->wwn) {
171 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
172 } else {
173 put_le16(p + 87, (1 << 14) | 0);
174 }
175 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
176 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
177 /* *(p + 100) := nb_sectors -- see ide_identify_size */
178 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
179 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
180 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
181
182 if (dev && dev->conf.physical_block_size)
183 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
184 if (s->wwn) {
185 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
186 put_le16(p + 108, s->wwn >> 48);
187 put_le16(p + 109, s->wwn >> 32);
188 put_le16(p + 110, s->wwn >> 16);
189 put_le16(p + 111, s->wwn);
190 }
191 if (dev && dev->conf.discard_granularity) {
192 put_le16(p + 169, 1); /* TRIM support */
193 }
194
195 ide_identify_size(s);
196 s->identify_set = 1;
197
198 fill_buffer:
199 memcpy(s->io_buffer, p, sizeof(s->identify_data));
200 }
201
202 static void ide_atapi_identify(IDEState *s)
203 {
204 uint16_t *p;
205
206 p = (uint16_t *)s->identify_data;
207 if (s->identify_set) {
208 goto fill_buffer;
209 }
210 memset(p, 0, sizeof(s->identify_data));
211
212 /* Removable CDROM, 50us response, 12 byte packets */
213 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
214 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
215 put_le16(p + 20, 3); /* buffer type */
216 put_le16(p + 21, 512); /* cache size in sectors */
217 put_le16(p + 22, 4); /* ecc bytes */
218 padstr((char *)(p + 23), s->version, 8); /* firmware version */
219 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
220 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
221 #ifdef USE_DMA_CDROM
222 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
223 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
224 put_le16(p + 62, 7); /* single word dma0-2 supported */
225 put_le16(p + 63, 7); /* mdma0-2 supported */
226 #else
227 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
228 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
229 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
230 #endif
231 put_le16(p + 64, 3); /* pio3-4 supported */
232 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
233 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
234 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
235 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
236
237 put_le16(p + 71, 30); /* in ns */
238 put_le16(p + 72, 30); /* in ns */
239
240 if (s->ncq_queues) {
241 put_le16(p + 75, s->ncq_queues - 1);
242 /* NCQ supported */
243 put_le16(p + 76, (1 << 8));
244 }
245
246 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
247 if (s->wwn) {
248 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
249 put_le16(p + 87, (1 << 8)); /* WWN enabled */
250 }
251
252 #ifdef USE_DMA_CDROM
253 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
254 #endif
255
256 if (s->wwn) {
257 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
258 put_le16(p + 108, s->wwn >> 48);
259 put_le16(p + 109, s->wwn >> 32);
260 put_le16(p + 110, s->wwn >> 16);
261 put_le16(p + 111, s->wwn);
262 }
263
264 s->identify_set = 1;
265
266 fill_buffer:
267 memcpy(s->io_buffer, p, sizeof(s->identify_data));
268 }
269
270 static void ide_cfata_identify_size(IDEState *s)
271 {
272 uint16_t *p = (uint16_t *)s->identify_data;
273 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
274 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
275 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
276 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
277 }
278
279 static void ide_cfata_identify(IDEState *s)
280 {
281 uint16_t *p;
282 uint32_t cur_sec;
283
284 p = (uint16_t *)s->identify_data;
285 if (s->identify_set) {
286 goto fill_buffer;
287 }
288 memset(p, 0, sizeof(s->identify_data));
289
290 cur_sec = s->cylinders * s->heads * s->sectors;
291
292 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
293 put_le16(p + 1, s->cylinders); /* Default cylinders */
294 put_le16(p + 3, s->heads); /* Default heads */
295 put_le16(p + 6, s->sectors); /* Default sectors per track */
296 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
297 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
298 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
299 put_le16(p + 22, 0x0004); /* ECC bytes */
300 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
301 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
302 #if MAX_MULT_SECTORS > 1
303 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
304 #else
305 put_le16(p + 47, 0x0000);
306 #endif
307 put_le16(p + 49, 0x0f00); /* Capabilities */
308 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
309 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
310 put_le16(p + 53, 0x0003); /* Translation params valid */
311 put_le16(p + 54, s->cylinders); /* Current cylinders */
312 put_le16(p + 55, s->heads); /* Current heads */
313 put_le16(p + 56, s->sectors); /* Current sectors */
314 put_le16(p + 57, cur_sec); /* Current capacity */
315 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
316 if (s->mult_sectors) /* Multiple sector setting */
317 put_le16(p + 59, 0x100 | s->mult_sectors);
318 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
319 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
320 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
321 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
322 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
323 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
324 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
325 put_le16(p + 82, 0x400c); /* Command Set supported */
326 put_le16(p + 83, 0x7068); /* Command Set supported */
327 put_le16(p + 84, 0x4000); /* Features supported */
328 put_le16(p + 85, 0x000c); /* Command Set enabled */
329 put_le16(p + 86, 0x7044); /* Command Set enabled */
330 put_le16(p + 87, 0x4000); /* Features enabled */
331 put_le16(p + 91, 0x4060); /* Current APM level */
332 put_le16(p + 129, 0x0002); /* Current features option */
333 put_le16(p + 130, 0x0005); /* Reassigned sectors */
334 put_le16(p + 131, 0x0001); /* Initial power mode */
335 put_le16(p + 132, 0x0000); /* User signature */
336 put_le16(p + 160, 0x8100); /* Power requirement */
337 put_le16(p + 161, 0x8001); /* CF command set */
338
339 ide_cfata_identify_size(s);
340 s->identify_set = 1;
341
342 fill_buffer:
343 memcpy(s->io_buffer, p, sizeof(s->identify_data));
344 }
345
346 static void ide_set_signature(IDEState *s)
347 {
348 s->select &= 0xf0; /* clear head */
349 /* put signature */
350 s->nsector = 1;
351 s->sector = 1;
352 if (s->drive_kind == IDE_CD) {
353 s->lcyl = 0x14;
354 s->hcyl = 0xeb;
355 } else if (s->blk) {
356 s->lcyl = 0;
357 s->hcyl = 0;
358 } else {
359 s->lcyl = 0xff;
360 s->hcyl = 0xff;
361 }
362 }
363
364 typedef struct TrimAIOCB {
365 BlockAIOCB common;
366 BlockBackend *blk;
367 QEMUBH *bh;
368 int ret;
369 QEMUIOVector *qiov;
370 BlockAIOCB *aiocb;
371 int i, j;
372 } TrimAIOCB;
373
374 static void trim_aio_cancel(BlockAIOCB *acb)
375 {
376 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
377
378 /* Exit the loop so ide_issue_trim_cb will not continue */
379 iocb->j = iocb->qiov->niov - 1;
380 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
381
382 iocb->ret = -ECANCELED;
383
384 if (iocb->aiocb) {
385 blk_aio_cancel_async(iocb->aiocb);
386 iocb->aiocb = NULL;
387 }
388 }
389
390 static const AIOCBInfo trim_aiocb_info = {
391 .aiocb_size = sizeof(TrimAIOCB),
392 .cancel_async = trim_aio_cancel,
393 };
394
395 static void ide_trim_bh_cb(void *opaque)
396 {
397 TrimAIOCB *iocb = opaque;
398
399 iocb->common.cb(iocb->common.opaque, iocb->ret);
400
401 qemu_bh_delete(iocb->bh);
402 iocb->bh = NULL;
403 qemu_aio_unref(iocb);
404 }
405
406 static void ide_issue_trim_cb(void *opaque, int ret)
407 {
408 TrimAIOCB *iocb = opaque;
409 if (ret >= 0) {
410 while (iocb->j < iocb->qiov->niov) {
411 int j = iocb->j;
412 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
413 int i = iocb->i;
414 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
415
416 /* 6-byte LBA + 2-byte range per entry */
417 uint64_t entry = le64_to_cpu(buffer[i]);
418 uint64_t sector = entry & 0x0000ffffffffffffULL;
419 uint16_t count = entry >> 48;
420
421 if (count == 0) {
422 continue;
423 }
424
425 /* Got an entry! Submit and exit. */
426 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
427 ide_issue_trim_cb, opaque);
428 return;
429 }
430
431 iocb->j++;
432 iocb->i = -1;
433 }
434 } else {
435 iocb->ret = ret;
436 }
437
438 iocb->aiocb = NULL;
439 if (iocb->bh) {
440 qemu_bh_schedule(iocb->bh);
441 }
442 }
443
444 BlockAIOCB *ide_issue_trim(BlockBackend *blk,
445 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
446 BlockCompletionFunc *cb, void *opaque)
447 {
448 TrimAIOCB *iocb;
449
450 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
451 iocb->blk = blk;
452 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
453 iocb->ret = 0;
454 iocb->qiov = qiov;
455 iocb->i = -1;
456 iocb->j = 0;
457 ide_issue_trim_cb(iocb, 0);
458 return &iocb->common;
459 }
460
461 void ide_abort_command(IDEState *s)
462 {
463 ide_transfer_stop(s);
464 s->status = READY_STAT | ERR_STAT;
465 s->error = ABRT_ERR;
466 }
467
468 /* prepare data transfer and tell what to do after */
469 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
470 EndTransferFunc *end_transfer_func)
471 {
472 s->end_transfer_func = end_transfer_func;
473 s->data_ptr = buf;
474 s->data_end = buf + size;
475 if (!(s->status & ERR_STAT)) {
476 s->status |= DRQ_STAT;
477 }
478 if (s->bus->dma->ops->start_transfer) {
479 s->bus->dma->ops->start_transfer(s->bus->dma);
480 }
481 }
482
483 static void ide_cmd_done(IDEState *s)
484 {
485 if (s->bus->dma->ops->cmd_done) {
486 s->bus->dma->ops->cmd_done(s->bus->dma);
487 }
488 }
489
490 void ide_transfer_stop(IDEState *s)
491 {
492 s->end_transfer_func = ide_transfer_stop;
493 s->data_ptr = s->io_buffer;
494 s->data_end = s->io_buffer;
495 s->status &= ~DRQ_STAT;
496 ide_cmd_done(s);
497 }
498
499 int64_t ide_get_sector(IDEState *s)
500 {
501 int64_t sector_num;
502 if (s->select & 0x40) {
503 /* lba */
504 if (!s->lba48) {
505 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
506 (s->lcyl << 8) | s->sector;
507 } else {
508 sector_num = ((int64_t)s->hob_hcyl << 40) |
509 ((int64_t) s->hob_lcyl << 32) |
510 ((int64_t) s->hob_sector << 24) |
511 ((int64_t) s->hcyl << 16) |
512 ((int64_t) s->lcyl << 8) | s->sector;
513 }
514 } else {
515 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
516 (s->select & 0x0f) * s->sectors + (s->sector - 1);
517 }
518 return sector_num;
519 }
520
521 void ide_set_sector(IDEState *s, int64_t sector_num)
522 {
523 unsigned int cyl, r;
524 if (s->select & 0x40) {
525 if (!s->lba48) {
526 s->select = (s->select & 0xf0) | (sector_num >> 24);
527 s->hcyl = (sector_num >> 16);
528 s->lcyl = (sector_num >> 8);
529 s->sector = (sector_num);
530 } else {
531 s->sector = sector_num;
532 s->lcyl = sector_num >> 8;
533 s->hcyl = sector_num >> 16;
534 s->hob_sector = sector_num >> 24;
535 s->hob_lcyl = sector_num >> 32;
536 s->hob_hcyl = sector_num >> 40;
537 }
538 } else {
539 cyl = sector_num / (s->heads * s->sectors);
540 r = sector_num % (s->heads * s->sectors);
541 s->hcyl = cyl >> 8;
542 s->lcyl = cyl;
543 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
544 s->sector = (r % s->sectors) + 1;
545 }
546 }
547
548 static void ide_rw_error(IDEState *s) {
549 ide_abort_command(s);
550 ide_set_irq(s->bus);
551 }
552
553 static bool ide_sect_range_ok(IDEState *s,
554 uint64_t sector, uint64_t nb_sectors)
555 {
556 uint64_t total_sectors;
557
558 blk_get_geometry(s->blk, &total_sectors);
559 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
560 return false;
561 }
562 return true;
563 }
564
565 static void ide_buffered_readv_cb(void *opaque, int ret)
566 {
567 IDEBufferedRequest *req = opaque;
568 if (!req->orphaned) {
569 if (!ret) {
570 qemu_iovec_from_buf(req->original_qiov, 0, req->iov.iov_base,
571 req->original_qiov->size);
572 }
573 req->original_cb(req->original_opaque, ret);
574 }
575 QLIST_REMOVE(req, list);
576 qemu_vfree(req->iov.iov_base);
577 g_free(req);
578 }
579
580 #define MAX_BUFFERED_REQS 16
581
582 BlockAIOCB *ide_buffered_readv(IDEState *s, int64_t sector_num,
583 QEMUIOVector *iov, int nb_sectors,
584 BlockCompletionFunc *cb, void *opaque)
585 {
586 BlockAIOCB *aioreq;
587 IDEBufferedRequest *req;
588 int c = 0;
589
590 QLIST_FOREACH(req, &s->buffered_requests, list) {
591 c++;
592 }
593 if (c > MAX_BUFFERED_REQS) {
594 return blk_abort_aio_request(s->blk, cb, opaque, -EIO);
595 }
596
597 req = g_new0(IDEBufferedRequest, 1);
598 req->original_qiov = iov;
599 req->original_cb = cb;
600 req->original_opaque = opaque;
601 req->iov.iov_base = qemu_blockalign(blk_bs(s->blk), iov->size);
602 req->iov.iov_len = iov->size;
603 qemu_iovec_init_external(&req->qiov, &req->iov, 1);
604
605 aioreq = blk_aio_readv(s->blk, sector_num, &req->qiov, nb_sectors,
606 ide_buffered_readv_cb, req);
607
608 QLIST_INSERT_HEAD(&s->buffered_requests, req, list);
609 return aioreq;
610 }
611
612 /**
613 * Cancel all pending DMA requests.
614 * Any buffered DMA requests are instantly canceled,
615 * but any pending unbuffered DMA requests must be waited on.
616 */
617 void ide_cancel_dma_sync(IDEState *s)
618 {
619 IDEBufferedRequest *req;
620
621 /* First invoke the callbacks of all buffered requests
622 * and flag those requests as orphaned. Ideally there
623 * are no unbuffered (Scatter Gather DMA Requests or
624 * write requests) pending and we can avoid to drain. */
625 QLIST_FOREACH(req, &s->buffered_requests, list) {
626 if (!req->orphaned) {
627 #ifdef DEBUG_IDE
628 printf("%s: invoking cb %p of buffered request %p with"
629 " -ECANCELED\n", __func__, req->original_cb, req);
630 #endif
631 req->original_cb(req->original_opaque, -ECANCELED);
632 }
633 req->orphaned = true;
634 }
635
636 /*
637 * We can't cancel Scatter Gather DMA in the middle of the
638 * operation or a partial (not full) DMA transfer would reach
639 * the storage so we wait for completion instead (we beahve
640 * like if the DMA was completed by the time the guest trying
641 * to cancel dma with bmdma_cmd_writeb with BM_CMD_START not
642 * set).
643 *
644 * In the future we'll be able to safely cancel the I/O if the
645 * whole DMA operation will be submitted to disk with a single
646 * aio operation with preadv/pwritev.
647 */
648 if (s->bus->dma->aiocb) {
649 #ifdef DEBUG_IDE
650 printf("%s: draining all remaining requests", __func__);
651 #endif
652 blk_drain(s->blk);
653 assert(s->bus->dma->aiocb == NULL);
654 }
655 }
656
657 static void ide_sector_read(IDEState *s);
658
659 static void ide_sector_read_cb(void *opaque, int ret)
660 {
661 IDEState *s = opaque;
662 int n;
663
664 s->pio_aiocb = NULL;
665 s->status &= ~BUSY_STAT;
666
667 if (ret == -ECANCELED) {
668 return;
669 }
670 if (ret != 0) {
671 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
672 IDE_RETRY_READ)) {
673 return;
674 }
675 }
676
677 block_acct_done(blk_get_stats(s->blk), &s->acct);
678
679 n = s->nsector;
680 if (n > s->req_nb_sectors) {
681 n = s->req_nb_sectors;
682 }
683
684 ide_set_sector(s, ide_get_sector(s) + n);
685 s->nsector -= n;
686 /* Allow the guest to read the io_buffer */
687 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
688 ide_set_irq(s->bus);
689 }
690
691 static void ide_sector_read(IDEState *s)
692 {
693 int64_t sector_num;
694 int n;
695
696 s->status = READY_STAT | SEEK_STAT;
697 s->error = 0; /* not needed by IDE spec, but needed by Windows */
698 sector_num = ide_get_sector(s);
699 n = s->nsector;
700
701 if (n == 0) {
702 ide_transfer_stop(s);
703 return;
704 }
705
706 s->status |= BUSY_STAT;
707
708 if (n > s->req_nb_sectors) {
709 n = s->req_nb_sectors;
710 }
711
712 #if defined(DEBUG_IDE)
713 printf("sector=%" PRId64 "\n", sector_num);
714 #endif
715
716 if (!ide_sect_range_ok(s, sector_num, n)) {
717 ide_rw_error(s);
718 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_READ);
719 return;
720 }
721
722 s->iov.iov_base = s->io_buffer;
723 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
724 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
725
726 block_acct_start(blk_get_stats(s->blk), &s->acct,
727 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
728 s->pio_aiocb = ide_buffered_readv(s, sector_num, &s->qiov, n,
729 ide_sector_read_cb, s);
730 }
731
732 void dma_buf_commit(IDEState *s, uint32_t tx_bytes)
733 {
734 if (s->bus->dma->ops->commit_buf) {
735 s->bus->dma->ops->commit_buf(s->bus->dma, tx_bytes);
736 }
737 s->io_buffer_offset += tx_bytes;
738 qemu_sglist_destroy(&s->sg);
739 }
740
741 void ide_set_inactive(IDEState *s, bool more)
742 {
743 s->bus->dma->aiocb = NULL;
744 s->bus->retry_unit = -1;
745 s->bus->retry_sector_num = 0;
746 s->bus->retry_nsector = 0;
747 if (s->bus->dma->ops->set_inactive) {
748 s->bus->dma->ops->set_inactive(s->bus->dma, more);
749 }
750 ide_cmd_done(s);
751 }
752
753 void ide_dma_error(IDEState *s)
754 {
755 dma_buf_commit(s, 0);
756 ide_abort_command(s);
757 ide_set_inactive(s, false);
758 ide_set_irq(s->bus);
759 }
760
761 static int ide_handle_rw_error(IDEState *s, int error, int op)
762 {
763 bool is_read = (op & IDE_RETRY_READ) != 0;
764 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
765
766 if (action == BLOCK_ERROR_ACTION_STOP) {
767 assert(s->bus->retry_unit == s->unit);
768 s->bus->error_status = op;
769 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
770 block_acct_failed(blk_get_stats(s->blk), &s->acct);
771 if (op & IDE_RETRY_DMA) {
772 ide_dma_error(s);
773 } else {
774 ide_rw_error(s);
775 }
776 }
777 blk_error_action(s->blk, action, is_read, error);
778 return action != BLOCK_ERROR_ACTION_IGNORE;
779 }
780
781 static void ide_dma_cb(void *opaque, int ret)
782 {
783 IDEState *s = opaque;
784 int n;
785 int64_t sector_num;
786 bool stay_active = false;
787
788 if (ret == -ECANCELED) {
789 return;
790 }
791 if (ret < 0) {
792 int op = IDE_RETRY_DMA;
793
794 if (s->dma_cmd == IDE_DMA_READ)
795 op |= IDE_RETRY_READ;
796 else if (s->dma_cmd == IDE_DMA_TRIM)
797 op |= IDE_RETRY_TRIM;
798
799 if (ide_handle_rw_error(s, -ret, op)) {
800 return;
801 }
802 }
803
804 n = s->io_buffer_size >> 9;
805 if (n > s->nsector) {
806 /* The PRDs were longer than needed for this request. Shorten them so
807 * we don't get a negative remainder. The Active bit must remain set
808 * after the request completes. */
809 n = s->nsector;
810 stay_active = true;
811 }
812
813 sector_num = ide_get_sector(s);
814 if (n > 0) {
815 assert(n * 512 == s->sg.size);
816 dma_buf_commit(s, s->sg.size);
817 sector_num += n;
818 ide_set_sector(s, sector_num);
819 s->nsector -= n;
820 }
821
822 /* end of transfer ? */
823 if (s->nsector == 0) {
824 s->status = READY_STAT | SEEK_STAT;
825 ide_set_irq(s->bus);
826 goto eot;
827 }
828
829 /* launch next transfer */
830 n = s->nsector;
831 s->io_buffer_index = 0;
832 s->io_buffer_size = n * 512;
833 if (s->bus->dma->ops->prepare_buf(s->bus->dma, s->io_buffer_size) < 512) {
834 /* The PRDs were too short. Reset the Active bit, but don't raise an
835 * interrupt. */
836 s->status = READY_STAT | SEEK_STAT;
837 dma_buf_commit(s, 0);
838 goto eot;
839 }
840
841 #ifdef DEBUG_AIO
842 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
843 sector_num, n, s->dma_cmd);
844 #endif
845
846 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
847 !ide_sect_range_ok(s, sector_num, n)) {
848 ide_dma_error(s);
849 block_acct_invalid(blk_get_stats(s->blk), s->acct.type);
850 return;
851 }
852
853 switch (s->dma_cmd) {
854 case IDE_DMA_READ:
855 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
856 ide_dma_cb, s);
857 break;
858 case IDE_DMA_WRITE:
859 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
860 ide_dma_cb, s);
861 break;
862 case IDE_DMA_TRIM:
863 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
864 ide_issue_trim, ide_dma_cb, s,
865 DMA_DIRECTION_TO_DEVICE);
866 break;
867 }
868 return;
869
870 eot:
871 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
872 block_acct_done(blk_get_stats(s->blk), &s->acct);
873 }
874 ide_set_inactive(s, stay_active);
875 }
876
877 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
878 {
879 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
880 s->io_buffer_size = 0;
881 s->dma_cmd = dma_cmd;
882
883 switch (dma_cmd) {
884 case IDE_DMA_READ:
885 block_acct_start(blk_get_stats(s->blk), &s->acct,
886 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
887 break;
888 case IDE_DMA_WRITE:
889 block_acct_start(blk_get_stats(s->blk), &s->acct,
890 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
891 break;
892 default:
893 break;
894 }
895
896 ide_start_dma(s, ide_dma_cb);
897 }
898
899 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
900 {
901 s->io_buffer_index = 0;
902 s->bus->retry_unit = s->unit;
903 s->bus->retry_sector_num = ide_get_sector(s);
904 s->bus->retry_nsector = s->nsector;
905 if (s->bus->dma->ops->start_dma) {
906 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
907 }
908 }
909
910 static void ide_sector_write(IDEState *s);
911
912 static void ide_sector_write_timer_cb(void *opaque)
913 {
914 IDEState *s = opaque;
915 ide_set_irq(s->bus);
916 }
917
918 static void ide_sector_write_cb(void *opaque, int ret)
919 {
920 IDEState *s = opaque;
921 int n;
922
923 if (ret == -ECANCELED) {
924 return;
925 }
926
927 s->pio_aiocb = NULL;
928 s->status &= ~BUSY_STAT;
929
930 if (ret != 0) {
931 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
932 return;
933 }
934 }
935
936 block_acct_done(blk_get_stats(s->blk), &s->acct);
937
938 n = s->nsector;
939 if (n > s->req_nb_sectors) {
940 n = s->req_nb_sectors;
941 }
942 s->nsector -= n;
943
944 ide_set_sector(s, ide_get_sector(s) + n);
945 if (s->nsector == 0) {
946 /* no more sectors to write */
947 ide_transfer_stop(s);
948 } else {
949 int n1 = s->nsector;
950 if (n1 > s->req_nb_sectors) {
951 n1 = s->req_nb_sectors;
952 }
953 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
954 ide_sector_write);
955 }
956
957 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
958 /* It seems there is a bug in the Windows 2000 installer HDD
959 IDE driver which fills the disk with empty logs when the
960 IDE write IRQ comes too early. This hack tries to correct
961 that at the expense of slower write performances. Use this
962 option _only_ to install Windows 2000. You must disable it
963 for normal use. */
964 timer_mod(s->sector_write_timer,
965 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
966 } else {
967 ide_set_irq(s->bus);
968 }
969 }
970
971 static void ide_sector_write(IDEState *s)
972 {
973 int64_t sector_num;
974 int n;
975
976 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
977 sector_num = ide_get_sector(s);
978 #if defined(DEBUG_IDE)
979 printf("sector=%" PRId64 "\n", sector_num);
980 #endif
981 n = s->nsector;
982 if (n > s->req_nb_sectors) {
983 n = s->req_nb_sectors;
984 }
985
986 if (!ide_sect_range_ok(s, sector_num, n)) {
987 ide_rw_error(s);
988 block_acct_invalid(blk_get_stats(s->blk), BLOCK_ACCT_WRITE);
989 return;
990 }
991
992 s->iov.iov_base = s->io_buffer;
993 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
994 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
995
996 block_acct_start(blk_get_stats(s->blk), &s->acct,
997 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
998 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
999 ide_sector_write_cb, s);
1000 }
1001
1002 static void ide_flush_cb(void *opaque, int ret)
1003 {
1004 IDEState *s = opaque;
1005
1006 s->pio_aiocb = NULL;
1007
1008 if (ret == -ECANCELED) {
1009 return;
1010 }
1011 if (ret < 0) {
1012 /* XXX: What sector number to set here? */
1013 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
1014 return;
1015 }
1016 }
1017
1018 if (s->blk) {
1019 block_acct_done(blk_get_stats(s->blk), &s->acct);
1020 }
1021 s->status = READY_STAT | SEEK_STAT;
1022 ide_cmd_done(s);
1023 ide_set_irq(s->bus);
1024 }
1025
1026 static void ide_flush_cache(IDEState *s)
1027 {
1028 if (s->blk == NULL) {
1029 ide_flush_cb(s, 0);
1030 return;
1031 }
1032
1033 s->status |= BUSY_STAT;
1034 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
1035 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
1036 }
1037
1038 static void ide_cfata_metadata_inquiry(IDEState *s)
1039 {
1040 uint16_t *p;
1041 uint32_t spd;
1042
1043 p = (uint16_t *) s->io_buffer;
1044 memset(p, 0, 0x200);
1045 spd = ((s->mdata_size - 1) >> 9) + 1;
1046
1047 put_le16(p + 0, 0x0001); /* Data format revision */
1048 put_le16(p + 1, 0x0000); /* Media property: silicon */
1049 put_le16(p + 2, s->media_changed); /* Media status */
1050 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
1051 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
1052 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
1053 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
1054 }
1055
1056 static void ide_cfata_metadata_read(IDEState *s)
1057 {
1058 uint16_t *p;
1059
1060 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1061 s->status = ERR_STAT;
1062 s->error = ABRT_ERR;
1063 return;
1064 }
1065
1066 p = (uint16_t *) s->io_buffer;
1067 memset(p, 0, 0x200);
1068
1069 put_le16(p + 0, s->media_changed); /* Media status */
1070 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1071 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1072 s->nsector << 9), 0x200 - 2));
1073 }
1074
1075 static void ide_cfata_metadata_write(IDEState *s)
1076 {
1077 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1078 s->status = ERR_STAT;
1079 s->error = ABRT_ERR;
1080 return;
1081 }
1082
1083 s->media_changed = 0;
1084
1085 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1086 s->io_buffer + 2,
1087 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1088 s->nsector << 9), 0x200 - 2));
1089 }
1090
1091 /* called when the inserted state of the media has changed */
1092 static void ide_cd_change_cb(void *opaque, bool load)
1093 {
1094 IDEState *s = opaque;
1095 uint64_t nb_sectors;
1096
1097 s->tray_open = !load;
1098 blk_get_geometry(s->blk, &nb_sectors);
1099 s->nb_sectors = nb_sectors;
1100
1101 /*
1102 * First indicate to the guest that a CD has been removed. That's
1103 * done on the next command the guest sends us.
1104 *
1105 * Then we set UNIT_ATTENTION, by which the guest will
1106 * detect a new CD in the drive. See ide_atapi_cmd() for details.
1107 */
1108 s->cdrom_changed = 1;
1109 s->events.new_media = true;
1110 s->events.eject_request = false;
1111 ide_set_irq(s->bus);
1112 }
1113
1114 static void ide_cd_eject_request_cb(void *opaque, bool force)
1115 {
1116 IDEState *s = opaque;
1117
1118 s->events.eject_request = true;
1119 if (force) {
1120 s->tray_locked = false;
1121 }
1122 ide_set_irq(s->bus);
1123 }
1124
1125 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1126 {
1127 s->lba48 = lba48;
1128
1129 /* handle the 'magic' 0 nsector count conversion here. to avoid
1130 * fiddling with the rest of the read logic, we just store the
1131 * full sector count in ->nsector and ignore ->hob_nsector from now
1132 */
1133 if (!s->lba48) {
1134 if (!s->nsector)
1135 s->nsector = 256;
1136 } else {
1137 if (!s->nsector && !s->hob_nsector)
1138 s->nsector = 65536;
1139 else {
1140 int lo = s->nsector;
1141 int hi = s->hob_nsector;
1142
1143 s->nsector = (hi << 8) | lo;
1144 }
1145 }
1146 }
1147
1148 static void ide_clear_hob(IDEBus *bus)
1149 {
1150 /* any write clears HOB high bit of device control register */
1151 bus->ifs[0].select &= ~(1 << 7);
1152 bus->ifs[1].select &= ~(1 << 7);
1153 }
1154
1155 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1156 {
1157 IDEBus *bus = opaque;
1158
1159 #ifdef DEBUG_IDE
1160 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1161 #endif
1162
1163 addr &= 7;
1164
1165 /* ignore writes to command block while busy with previous command */
1166 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
1167 return;
1168
1169 switch(addr) {
1170 case 0:
1171 break;
1172 case 1:
1173 ide_clear_hob(bus);
1174 /* NOTE: data is written to the two drives */
1175 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1176 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1177 bus->ifs[0].feature = val;
1178 bus->ifs[1].feature = val;
1179 break;
1180 case 2:
1181 ide_clear_hob(bus);
1182 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1183 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1184 bus->ifs[0].nsector = val;
1185 bus->ifs[1].nsector = val;
1186 break;
1187 case 3:
1188 ide_clear_hob(bus);
1189 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1190 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1191 bus->ifs[0].sector = val;
1192 bus->ifs[1].sector = val;
1193 break;
1194 case 4:
1195 ide_clear_hob(bus);
1196 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1197 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1198 bus->ifs[0].lcyl = val;
1199 bus->ifs[1].lcyl = val;
1200 break;
1201 case 5:
1202 ide_clear_hob(bus);
1203 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1204 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1205 bus->ifs[0].hcyl = val;
1206 bus->ifs[1].hcyl = val;
1207 break;
1208 case 6:
1209 /* FIXME: HOB readback uses bit 7 */
1210 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1211 bus->ifs[1].select = (val | 0x10) | 0xa0;
1212 /* select drive */
1213 bus->unit = (val >> 4) & 1;
1214 break;
1215 default:
1216 case 7:
1217 /* command */
1218 ide_exec_cmd(bus, val);
1219 break;
1220 }
1221 }
1222
1223 static void ide_reset(IDEState *s)
1224 {
1225 #ifdef DEBUG_IDE
1226 printf("ide: reset\n");
1227 #endif
1228
1229 if (s->pio_aiocb) {
1230 blk_aio_cancel(s->pio_aiocb);
1231 s->pio_aiocb = NULL;
1232 }
1233
1234 if (s->drive_kind == IDE_CFATA)
1235 s->mult_sectors = 0;
1236 else
1237 s->mult_sectors = MAX_MULT_SECTORS;
1238 /* ide regs */
1239 s->feature = 0;
1240 s->error = 0;
1241 s->nsector = 0;
1242 s->sector = 0;
1243 s->lcyl = 0;
1244 s->hcyl = 0;
1245
1246 /* lba48 */
1247 s->hob_feature = 0;
1248 s->hob_sector = 0;
1249 s->hob_nsector = 0;
1250 s->hob_lcyl = 0;
1251 s->hob_hcyl = 0;
1252
1253 s->select = 0xa0;
1254 s->status = READY_STAT | SEEK_STAT;
1255
1256 s->lba48 = 0;
1257
1258 /* ATAPI specific */
1259 s->sense_key = 0;
1260 s->asc = 0;
1261 s->cdrom_changed = 0;
1262 s->packet_transfer_size = 0;
1263 s->elementary_transfer_size = 0;
1264 s->io_buffer_index = 0;
1265 s->cd_sector_size = 0;
1266 s->atapi_dma = 0;
1267 s->tray_locked = 0;
1268 s->tray_open = 0;
1269 /* ATA DMA state */
1270 s->io_buffer_size = 0;
1271 s->req_nb_sectors = 0;
1272
1273 ide_set_signature(s);
1274 /* init the transfer handler so that 0xffff is returned on data
1275 accesses */
1276 s->end_transfer_func = ide_dummy_transfer_stop;
1277 ide_dummy_transfer_stop(s);
1278 s->media_changed = 0;
1279 }
1280
1281 static bool cmd_nop(IDEState *s, uint8_t cmd)
1282 {
1283 return true;
1284 }
1285
1286 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1287 {
1288 switch (s->feature) {
1289 case DSM_TRIM:
1290 if (s->blk) {
1291 ide_sector_start_dma(s, IDE_DMA_TRIM);
1292 return false;
1293 }
1294 break;
1295 }
1296
1297 ide_abort_command(s);
1298 return true;
1299 }
1300
1301 static bool cmd_identify(IDEState *s, uint8_t cmd)
1302 {
1303 if (s->blk && s->drive_kind != IDE_CD) {
1304 if (s->drive_kind != IDE_CFATA) {
1305 ide_identify(s);
1306 } else {
1307 ide_cfata_identify(s);
1308 }
1309 s->status = READY_STAT | SEEK_STAT;
1310 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1311 ide_set_irq(s->bus);
1312 return false;
1313 } else {
1314 if (s->drive_kind == IDE_CD) {
1315 ide_set_signature(s);
1316 }
1317 ide_abort_command(s);
1318 }
1319
1320 return true;
1321 }
1322
1323 static bool cmd_verify(IDEState *s, uint8_t cmd)
1324 {
1325 bool lba48 = (cmd == WIN_VERIFY_EXT);
1326
1327 /* do sector number check ? */
1328 ide_cmd_lba48_transform(s, lba48);
1329
1330 return true;
1331 }
1332
1333 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1334 {
1335 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1336 /* Disable Read and Write Multiple */
1337 s->mult_sectors = 0;
1338 } else if ((s->nsector & 0xff) != 0 &&
1339 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1340 (s->nsector & (s->nsector - 1)) != 0)) {
1341 ide_abort_command(s);
1342 } else {
1343 s->mult_sectors = s->nsector & 0xff;
1344 }
1345
1346 return true;
1347 }
1348
1349 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1350 {
1351 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1352
1353 if (!s->blk || !s->mult_sectors) {
1354 ide_abort_command(s);
1355 return true;
1356 }
1357
1358 ide_cmd_lba48_transform(s, lba48);
1359 s->req_nb_sectors = s->mult_sectors;
1360 ide_sector_read(s);
1361 return false;
1362 }
1363
1364 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1365 {
1366 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1367 int n;
1368
1369 if (!s->blk || !s->mult_sectors) {
1370 ide_abort_command(s);
1371 return true;
1372 }
1373
1374 ide_cmd_lba48_transform(s, lba48);
1375
1376 s->req_nb_sectors = s->mult_sectors;
1377 n = MIN(s->nsector, s->req_nb_sectors);
1378
1379 s->status = SEEK_STAT | READY_STAT;
1380 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1381
1382 s->media_changed = 1;
1383
1384 return false;
1385 }
1386
1387 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1388 {
1389 bool lba48 = (cmd == WIN_READ_EXT);
1390
1391 if (s->drive_kind == IDE_CD) {
1392 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1393 ide_abort_command(s);
1394 return true;
1395 }
1396
1397 if (!s->blk) {
1398 ide_abort_command(s);
1399 return true;
1400 }
1401
1402 ide_cmd_lba48_transform(s, lba48);
1403 s->req_nb_sectors = 1;
1404 ide_sector_read(s);
1405
1406 return false;
1407 }
1408
1409 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1410 {
1411 bool lba48 = (cmd == WIN_WRITE_EXT);
1412
1413 if (!s->blk) {
1414 ide_abort_command(s);
1415 return true;
1416 }
1417
1418 ide_cmd_lba48_transform(s, lba48);
1419
1420 s->req_nb_sectors = 1;
1421 s->status = SEEK_STAT | READY_STAT;
1422 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1423
1424 s->media_changed = 1;
1425
1426 return false;
1427 }
1428
1429 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1430 {
1431 bool lba48 = (cmd == WIN_READDMA_EXT);
1432
1433 if (!s->blk) {
1434 ide_abort_command(s);
1435 return true;
1436 }
1437
1438 ide_cmd_lba48_transform(s, lba48);
1439 ide_sector_start_dma(s, IDE_DMA_READ);
1440
1441 return false;
1442 }
1443
1444 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1445 {
1446 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1447
1448 if (!s->blk) {
1449 ide_abort_command(s);
1450 return true;
1451 }
1452
1453 ide_cmd_lba48_transform(s, lba48);
1454 ide_sector_start_dma(s, IDE_DMA_WRITE);
1455
1456 s->media_changed = 1;
1457
1458 return false;
1459 }
1460
1461 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1462 {
1463 ide_flush_cache(s);
1464 return false;
1465 }
1466
1467 static bool cmd_seek(IDEState *s, uint8_t cmd)
1468 {
1469 /* XXX: Check that seek is within bounds */
1470 return true;
1471 }
1472
1473 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1474 {
1475 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1476
1477 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1478 if (s->nb_sectors == 0) {
1479 ide_abort_command(s);
1480 return true;
1481 }
1482
1483 ide_cmd_lba48_transform(s, lba48);
1484 ide_set_sector(s, s->nb_sectors - 1);
1485
1486 return true;
1487 }
1488
1489 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1490 {
1491 s->nsector = 0xff; /* device active or idle */
1492 return true;
1493 }
1494
1495 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1496 {
1497 uint16_t *identify_data;
1498
1499 if (!s->blk) {
1500 ide_abort_command(s);
1501 return true;
1502 }
1503
1504 /* XXX: valid for CDROM ? */
1505 switch (s->feature) {
1506 case 0x02: /* write cache enable */
1507 blk_set_enable_write_cache(s->blk, true);
1508 identify_data = (uint16_t *)s->identify_data;
1509 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1510 return true;
1511 case 0x82: /* write cache disable */
1512 blk_set_enable_write_cache(s->blk, false);
1513 identify_data = (uint16_t *)s->identify_data;
1514 put_le16(identify_data + 85, (1 << 14) | 1);
1515 ide_flush_cache(s);
1516 return false;
1517 case 0xcc: /* reverting to power-on defaults enable */
1518 case 0x66: /* reverting to power-on defaults disable */
1519 case 0xaa: /* read look-ahead enable */
1520 case 0x55: /* read look-ahead disable */
1521 case 0x05: /* set advanced power management mode */
1522 case 0x85: /* disable advanced power management mode */
1523 case 0x69: /* NOP */
1524 case 0x67: /* NOP */
1525 case 0x96: /* NOP */
1526 case 0x9a: /* NOP */
1527 case 0x42: /* enable Automatic Acoustic Mode */
1528 case 0xc2: /* disable Automatic Acoustic Mode */
1529 return true;
1530 case 0x03: /* set transfer mode */
1531 {
1532 uint8_t val = s->nsector & 0x07;
1533 identify_data = (uint16_t *)s->identify_data;
1534
1535 switch (s->nsector >> 3) {
1536 case 0x00: /* pio default */
1537 case 0x01: /* pio mode */
1538 put_le16(identify_data + 62, 0x07);
1539 put_le16(identify_data + 63, 0x07);
1540 put_le16(identify_data + 88, 0x3f);
1541 break;
1542 case 0x02: /* sigle word dma mode*/
1543 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1544 put_le16(identify_data + 63, 0x07);
1545 put_le16(identify_data + 88, 0x3f);
1546 break;
1547 case 0x04: /* mdma mode */
1548 put_le16(identify_data + 62, 0x07);
1549 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1550 put_le16(identify_data + 88, 0x3f);
1551 break;
1552 case 0x08: /* udma mode */
1553 put_le16(identify_data + 62, 0x07);
1554 put_le16(identify_data + 63, 0x07);
1555 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1556 break;
1557 default:
1558 goto abort_cmd;
1559 }
1560 return true;
1561 }
1562 }
1563
1564 abort_cmd:
1565 ide_abort_command(s);
1566 return true;
1567 }
1568
1569
1570 /*** ATAPI commands ***/
1571
1572 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1573 {
1574 ide_atapi_identify(s);
1575 s->status = READY_STAT | SEEK_STAT;
1576 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1577 ide_set_irq(s->bus);
1578 return false;
1579 }
1580
1581 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1582 {
1583 ide_set_signature(s);
1584
1585 if (s->drive_kind == IDE_CD) {
1586 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1587 * devices to return a clear status register
1588 * with READY_STAT *not* set. */
1589 s->error = 0x01;
1590 } else {
1591 s->status = READY_STAT | SEEK_STAT;
1592 /* The bits of the error register are not as usual for this command!
1593 * They are part of the regular output (this is why ERR_STAT isn't set)
1594 * Device 0 passed, Device 1 passed or not present. */
1595 s->error = 0x01;
1596 ide_set_irq(s->bus);
1597 }
1598
1599 return false;
1600 }
1601
1602 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1603 {
1604 ide_set_signature(s);
1605 s->status = 0x00; /* NOTE: READY is _not_ set */
1606 s->error = 0x01;
1607
1608 return false;
1609 }
1610
1611 static bool cmd_packet(IDEState *s, uint8_t cmd)
1612 {
1613 /* overlapping commands not supported */
1614 if (s->feature & 0x02) {
1615 ide_abort_command(s);
1616 return true;
1617 }
1618
1619 s->status = READY_STAT | SEEK_STAT;
1620 s->atapi_dma = s->feature & 1;
1621 s->nsector = 1;
1622 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1623 ide_atapi_cmd);
1624 return false;
1625 }
1626
1627
1628 /*** CF-ATA commands ***/
1629
1630 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1631 {
1632 s->error = 0x09; /* miscellaneous error */
1633 s->status = READY_STAT | SEEK_STAT;
1634 ide_set_irq(s->bus);
1635
1636 return false;
1637 }
1638
1639 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1640 {
1641 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1642 * required for Windows 8 to work with AHCI */
1643
1644 if (cmd == CFA_WEAR_LEVEL) {
1645 s->nsector = 0;
1646 }
1647
1648 if (cmd == CFA_ERASE_SECTORS) {
1649 s->media_changed = 1;
1650 }
1651
1652 return true;
1653 }
1654
1655 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1656 {
1657 s->status = READY_STAT | SEEK_STAT;
1658
1659 memset(s->io_buffer, 0, 0x200);
1660 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1661 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1662 s->io_buffer[0x02] = s->select; /* Head */
1663 s->io_buffer[0x03] = s->sector; /* Sector */
1664 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1665 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1666 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1667 s->io_buffer[0x13] = 0x00; /* Erase flag */
1668 s->io_buffer[0x18] = 0x00; /* Hot count */
1669 s->io_buffer[0x19] = 0x00; /* Hot count */
1670 s->io_buffer[0x1a] = 0x01; /* Hot count */
1671
1672 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1673 ide_set_irq(s->bus);
1674
1675 return false;
1676 }
1677
1678 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1679 {
1680 switch (s->feature) {
1681 case 0x02: /* Inquiry Metadata Storage */
1682 ide_cfata_metadata_inquiry(s);
1683 break;
1684 case 0x03: /* Read Metadata Storage */
1685 ide_cfata_metadata_read(s);
1686 break;
1687 case 0x04: /* Write Metadata Storage */
1688 ide_cfata_metadata_write(s);
1689 break;
1690 default:
1691 ide_abort_command(s);
1692 return true;
1693 }
1694
1695 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1696 s->status = 0x00; /* NOTE: READY is _not_ set */
1697 ide_set_irq(s->bus);
1698
1699 return false;
1700 }
1701
1702 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1703 {
1704 switch (s->feature) {
1705 case 0x01: /* sense temperature in device */
1706 s->nsector = 0x50; /* +20 C */
1707 break;
1708 default:
1709 ide_abort_command(s);
1710 return true;
1711 }
1712
1713 return true;
1714 }
1715
1716
1717 /*** SMART commands ***/
1718
1719 static bool cmd_smart(IDEState *s, uint8_t cmd)
1720 {
1721 int n;
1722
1723 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1724 goto abort_cmd;
1725 }
1726
1727 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1728 goto abort_cmd;
1729 }
1730
1731 switch (s->feature) {
1732 case SMART_DISABLE:
1733 s->smart_enabled = 0;
1734 return true;
1735
1736 case SMART_ENABLE:
1737 s->smart_enabled = 1;
1738 return true;
1739
1740 case SMART_ATTR_AUTOSAVE:
1741 switch (s->sector) {
1742 case 0x00:
1743 s->smart_autosave = 0;
1744 break;
1745 case 0xf1:
1746 s->smart_autosave = 1;
1747 break;
1748 default:
1749 goto abort_cmd;
1750 }
1751 return true;
1752
1753 case SMART_STATUS:
1754 if (!s->smart_errors) {
1755 s->hcyl = 0xc2;
1756 s->lcyl = 0x4f;
1757 } else {
1758 s->hcyl = 0x2c;
1759 s->lcyl = 0xf4;
1760 }
1761 return true;
1762
1763 case SMART_READ_THRESH:
1764 memset(s->io_buffer, 0, 0x200);
1765 s->io_buffer[0] = 0x01; /* smart struct version */
1766
1767 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1768 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1769 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1770 }
1771
1772 /* checksum */
1773 for (n = 0; n < 511; n++) {
1774 s->io_buffer[511] += s->io_buffer[n];
1775 }
1776 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1777
1778 s->status = READY_STAT | SEEK_STAT;
1779 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1780 ide_set_irq(s->bus);
1781 return false;
1782
1783 case SMART_READ_DATA:
1784 memset(s->io_buffer, 0, 0x200);
1785 s->io_buffer[0] = 0x01; /* smart struct version */
1786
1787 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1788 int i;
1789 for (i = 0; i < 11; i++) {
1790 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1791 }
1792 }
1793
1794 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1795 if (s->smart_selftest_count == 0) {
1796 s->io_buffer[363] = 0;
1797 } else {
1798 s->io_buffer[363] =
1799 s->smart_selftest_data[3 +
1800 (s->smart_selftest_count - 1) *
1801 24];
1802 }
1803 s->io_buffer[364] = 0x20;
1804 s->io_buffer[365] = 0x01;
1805 /* offline data collection capacity: execute + self-test*/
1806 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1807 s->io_buffer[368] = 0x03; /* smart capability (1) */
1808 s->io_buffer[369] = 0x00; /* smart capability (2) */
1809 s->io_buffer[370] = 0x01; /* error logging supported */
1810 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1811 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1812 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1813
1814 for (n = 0; n < 511; n++) {
1815 s->io_buffer[511] += s->io_buffer[n];
1816 }
1817 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1818
1819 s->status = READY_STAT | SEEK_STAT;
1820 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1821 ide_set_irq(s->bus);
1822 return false;
1823
1824 case SMART_READ_LOG:
1825 switch (s->sector) {
1826 case 0x01: /* summary smart error log */
1827 memset(s->io_buffer, 0, 0x200);
1828 s->io_buffer[0] = 0x01;
1829 s->io_buffer[1] = 0x00; /* no error entries */
1830 s->io_buffer[452] = s->smart_errors & 0xff;
1831 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1832
1833 for (n = 0; n < 511; n++) {
1834 s->io_buffer[511] += s->io_buffer[n];
1835 }
1836 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1837 break;
1838 case 0x06: /* smart self test log */
1839 memset(s->io_buffer, 0, 0x200);
1840 s->io_buffer[0] = 0x01;
1841 if (s->smart_selftest_count == 0) {
1842 s->io_buffer[508] = 0;
1843 } else {
1844 s->io_buffer[508] = s->smart_selftest_count;
1845 for (n = 2; n < 506; n++) {
1846 s->io_buffer[n] = s->smart_selftest_data[n];
1847 }
1848 }
1849
1850 for (n = 0; n < 511; n++) {
1851 s->io_buffer[511] += s->io_buffer[n];
1852 }
1853 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1854 break;
1855 default:
1856 goto abort_cmd;
1857 }
1858 s->status = READY_STAT | SEEK_STAT;
1859 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1860 ide_set_irq(s->bus);
1861 return false;
1862
1863 case SMART_EXECUTE_OFFLINE:
1864 switch (s->sector) {
1865 case 0: /* off-line routine */
1866 case 1: /* short self test */
1867 case 2: /* extended self test */
1868 s->smart_selftest_count++;
1869 if (s->smart_selftest_count > 21) {
1870 s->smart_selftest_count = 1;
1871 }
1872 n = 2 + (s->smart_selftest_count - 1) * 24;
1873 s->smart_selftest_data[n] = s->sector;
1874 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1875 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1876 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1877 break;
1878 default:
1879 goto abort_cmd;
1880 }
1881 return true;
1882 }
1883
1884 abort_cmd:
1885 ide_abort_command(s);
1886 return true;
1887 }
1888
1889 #define HD_OK (1u << IDE_HD)
1890 #define CD_OK (1u << IDE_CD)
1891 #define CFA_OK (1u << IDE_CFATA)
1892 #define HD_CFA_OK (HD_OK | CFA_OK)
1893 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1894
1895 /* Set the Disk Seek Completed status bit during completion */
1896 #define SET_DSC (1u << 8)
1897
1898 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1899 static const struct {
1900 /* Returns true if the completion code should be run */
1901 bool (*handler)(IDEState *s, uint8_t cmd);
1902 int flags;
1903 } ide_cmd_table[0x100] = {
1904 /* NOP not implemented, mandatory for CD */
1905 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1906 [WIN_DSM] = { cmd_data_set_management, HD_CFA_OK },
1907 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1908 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1909 [WIN_READ] = { cmd_read_pio, ALL_OK },
1910 [WIN_READ_ONCE] = { cmd_read_pio, HD_CFA_OK },
1911 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1912 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1913 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1914 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1915 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1916 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1917 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1918 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1919 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1920 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1921 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1922 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1923 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1924 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1925 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1926 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1927 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1928 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1929 [WIN_STANDBYNOW2] = { cmd_nop, HD_CFA_OK },
1930 [WIN_IDLEIMMEDIATE2] = { cmd_nop, HD_CFA_OK },
1931 [WIN_STANDBY2] = { cmd_nop, HD_CFA_OK },
1932 [WIN_SETIDLE2] = { cmd_nop, HD_CFA_OK },
1933 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1934 [WIN_SLEEPNOW2] = { cmd_nop, HD_CFA_OK },
1935 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1936 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1937 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1938 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1939 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1940 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1941 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1942 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1943 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1944 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1945 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1946 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1947 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1948 [WIN_STANDBYNOW1] = { cmd_nop, HD_CFA_OK },
1949 [WIN_IDLEIMMEDIATE] = { cmd_nop, HD_CFA_OK },
1950 [WIN_STANDBY] = { cmd_nop, HD_CFA_OK },
1951 [WIN_SETIDLE1] = { cmd_nop, HD_CFA_OK },
1952 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, HD_CFA_OK | SET_DSC },
1953 [WIN_SLEEPNOW1] = { cmd_nop, HD_CFA_OK },
1954 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1955 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1956 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1957 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1958 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1959 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1960 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1961 };
1962
1963 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1964 {
1965 return cmd < ARRAY_SIZE(ide_cmd_table)
1966 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1967 }
1968
1969 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1970 {
1971 IDEState *s;
1972 bool complete;
1973
1974 #if defined(DEBUG_IDE)
1975 printf("ide: CMD=%02x\n", val);
1976 #endif
1977 s = idebus_active_if(bus);
1978 /* ignore commands to non existent slave */
1979 if (s != bus->ifs && !s->blk) {
1980 return;
1981 }
1982
1983 /* Only RESET is allowed while BSY and/or DRQ are set,
1984 * and only to ATAPI devices. */
1985 if (s->status & (BUSY_STAT|DRQ_STAT)) {
1986 if (val != WIN_DEVICE_RESET || s->drive_kind != IDE_CD) {
1987 return;
1988 }
1989 }
1990
1991 if (!ide_cmd_permitted(s, val)) {
1992 ide_abort_command(s);
1993 ide_set_irq(s->bus);
1994 return;
1995 }
1996
1997 s->status = READY_STAT | BUSY_STAT;
1998 s->error = 0;
1999 s->io_buffer_offset = 0;
2000
2001 complete = ide_cmd_table[val].handler(s, val);
2002 if (complete) {
2003 s->status &= ~BUSY_STAT;
2004 assert(!!s->error == !!(s->status & ERR_STAT));
2005
2006 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
2007 s->status |= SEEK_STAT;
2008 }
2009
2010 ide_cmd_done(s);
2011 ide_set_irq(s->bus);
2012 }
2013 }
2014
2015 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
2016 {
2017 IDEBus *bus = opaque;
2018 IDEState *s = idebus_active_if(bus);
2019 uint32_t addr;
2020 int ret, hob;
2021
2022 addr = addr1 & 7;
2023 /* FIXME: HOB readback uses bit 7, but it's always set right now */
2024 //hob = s->select & (1 << 7);
2025 hob = 0;
2026 switch(addr) {
2027 case 0:
2028 ret = 0xff;
2029 break;
2030 case 1:
2031 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2032 (s != bus->ifs && !s->blk)) {
2033 ret = 0;
2034 } else if (!hob) {
2035 ret = s->error;
2036 } else {
2037 ret = s->hob_feature;
2038 }
2039 break;
2040 case 2:
2041 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2042 ret = 0;
2043 } else if (!hob) {
2044 ret = s->nsector & 0xff;
2045 } else {
2046 ret = s->hob_nsector;
2047 }
2048 break;
2049 case 3:
2050 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2051 ret = 0;
2052 } else if (!hob) {
2053 ret = s->sector;
2054 } else {
2055 ret = s->hob_sector;
2056 }
2057 break;
2058 case 4:
2059 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2060 ret = 0;
2061 } else if (!hob) {
2062 ret = s->lcyl;
2063 } else {
2064 ret = s->hob_lcyl;
2065 }
2066 break;
2067 case 5:
2068 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2069 ret = 0;
2070 } else if (!hob) {
2071 ret = s->hcyl;
2072 } else {
2073 ret = s->hob_hcyl;
2074 }
2075 break;
2076 case 6:
2077 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
2078 ret = 0;
2079 } else {
2080 ret = s->select;
2081 }
2082 break;
2083 default:
2084 case 7:
2085 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2086 (s != bus->ifs && !s->blk)) {
2087 ret = 0;
2088 } else {
2089 ret = s->status;
2090 }
2091 qemu_irq_lower(bus->irq);
2092 break;
2093 }
2094 #ifdef DEBUG_IDE
2095 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
2096 #endif
2097 return ret;
2098 }
2099
2100 uint32_t ide_status_read(void *opaque, uint32_t addr)
2101 {
2102 IDEBus *bus = opaque;
2103 IDEState *s = idebus_active_if(bus);
2104 int ret;
2105
2106 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
2107 (s != bus->ifs && !s->blk)) {
2108 ret = 0;
2109 } else {
2110 ret = s->status;
2111 }
2112 #ifdef DEBUG_IDE
2113 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
2114 #endif
2115 return ret;
2116 }
2117
2118 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
2119 {
2120 IDEBus *bus = opaque;
2121 IDEState *s;
2122 int i;
2123
2124 #ifdef DEBUG_IDE
2125 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
2126 #endif
2127 /* common for both drives */
2128 if (!(bus->cmd & IDE_CMD_RESET) &&
2129 (val & IDE_CMD_RESET)) {
2130 /* reset low to high */
2131 for(i = 0;i < 2; i++) {
2132 s = &bus->ifs[i];
2133 s->status = BUSY_STAT | SEEK_STAT;
2134 s->error = 0x01;
2135 }
2136 } else if ((bus->cmd & IDE_CMD_RESET) &&
2137 !(val & IDE_CMD_RESET)) {
2138 /* high to low */
2139 for(i = 0;i < 2; i++) {
2140 s = &bus->ifs[i];
2141 if (s->drive_kind == IDE_CD)
2142 s->status = 0x00; /* NOTE: READY is _not_ set */
2143 else
2144 s->status = READY_STAT | SEEK_STAT;
2145 ide_set_signature(s);
2146 }
2147 }
2148
2149 bus->cmd = val;
2150 }
2151
2152 /*
2153 * Returns true if the running PIO transfer is a PIO out (i.e. data is
2154 * transferred from the device to the guest), false if it's a PIO in
2155 */
2156 static bool ide_is_pio_out(IDEState *s)
2157 {
2158 if (s->end_transfer_func == ide_sector_write ||
2159 s->end_transfer_func == ide_atapi_cmd) {
2160 return false;
2161 } else if (s->end_transfer_func == ide_sector_read ||
2162 s->end_transfer_func == ide_transfer_stop ||
2163 s->end_transfer_func == ide_atapi_cmd_reply_end ||
2164 s->end_transfer_func == ide_dummy_transfer_stop) {
2165 return true;
2166 }
2167
2168 abort();
2169 }
2170
2171 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2172 {
2173 IDEBus *bus = opaque;
2174 IDEState *s = idebus_active_if(bus);
2175 uint8_t *p;
2176
2177 /* PIO data access allowed only when DRQ bit is set. The result of a write
2178 * during PIO out is indeterminate, just ignore it. */
2179 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2180 return;
2181 }
2182
2183 p = s->data_ptr;
2184 if (p + 2 > s->data_end) {
2185 return;
2186 }
2187
2188 *(uint16_t *)p = le16_to_cpu(val);
2189 p += 2;
2190 s->data_ptr = p;
2191 if (p >= s->data_end) {
2192 s->status &= ~DRQ_STAT;
2193 s->end_transfer_func(s);
2194 }
2195 }
2196
2197 uint32_t ide_data_readw(void *opaque, uint32_t addr)
2198 {
2199 IDEBus *bus = opaque;
2200 IDEState *s = idebus_active_if(bus);
2201 uint8_t *p;
2202 int ret;
2203
2204 /* PIO data access allowed only when DRQ bit is set. The result of a read
2205 * during PIO in is indeterminate, return 0 and don't move forward. */
2206 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2207 return 0;
2208 }
2209
2210 p = s->data_ptr;
2211 if (p + 2 > s->data_end) {
2212 return 0;
2213 }
2214
2215 ret = cpu_to_le16(*(uint16_t *)p);
2216 p += 2;
2217 s->data_ptr = p;
2218 if (p >= s->data_end) {
2219 s->status &= ~DRQ_STAT;
2220 s->end_transfer_func(s);
2221 }
2222 return ret;
2223 }
2224
2225 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2226 {
2227 IDEBus *bus = opaque;
2228 IDEState *s = idebus_active_if(bus);
2229 uint8_t *p;
2230
2231 /* PIO data access allowed only when DRQ bit is set. The result of a write
2232 * during PIO out is indeterminate, just ignore it. */
2233 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2234 return;
2235 }
2236
2237 p = s->data_ptr;
2238 if (p + 4 > s->data_end) {
2239 return;
2240 }
2241
2242 *(uint32_t *)p = le32_to_cpu(val);
2243 p += 4;
2244 s->data_ptr = p;
2245 if (p >= s->data_end) {
2246 s->status &= ~DRQ_STAT;
2247 s->end_transfer_func(s);
2248 }
2249 }
2250
2251 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2252 {
2253 IDEBus *bus = opaque;
2254 IDEState *s = idebus_active_if(bus);
2255 uint8_t *p;
2256 int ret;
2257
2258 /* PIO data access allowed only when DRQ bit is set. The result of a read
2259 * during PIO in is indeterminate, return 0 and don't move forward. */
2260 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2261 return 0;
2262 }
2263
2264 p = s->data_ptr;
2265 if (p + 4 > s->data_end) {
2266 return 0;
2267 }
2268
2269 ret = cpu_to_le32(*(uint32_t *)p);
2270 p += 4;
2271 s->data_ptr = p;
2272 if (p >= s->data_end) {
2273 s->status &= ~DRQ_STAT;
2274 s->end_transfer_func(s);
2275 }
2276 return ret;
2277 }
2278
2279 static void ide_dummy_transfer_stop(IDEState *s)
2280 {
2281 s->data_ptr = s->io_buffer;
2282 s->data_end = s->io_buffer;
2283 s->io_buffer[0] = 0xff;
2284 s->io_buffer[1] = 0xff;
2285 s->io_buffer[2] = 0xff;
2286 s->io_buffer[3] = 0xff;
2287 }
2288
2289 void ide_bus_reset(IDEBus *bus)
2290 {
2291 bus->unit = 0;
2292 bus->cmd = 0;
2293 ide_reset(&bus->ifs[0]);
2294 ide_reset(&bus->ifs[1]);
2295 ide_clear_hob(bus);
2296
2297 /* pending async DMA */
2298 if (bus->dma->aiocb) {
2299 #ifdef DEBUG_AIO
2300 printf("aio_cancel\n");
2301 #endif
2302 blk_aio_cancel(bus->dma->aiocb);
2303 bus->dma->aiocb = NULL;
2304 }
2305
2306 /* reset dma provider too */
2307 if (bus->dma->ops->reset) {
2308 bus->dma->ops->reset(bus->dma);
2309 }
2310 }
2311
2312 static bool ide_cd_is_tray_open(void *opaque)
2313 {
2314 return ((IDEState *)opaque)->tray_open;
2315 }
2316
2317 static bool ide_cd_is_medium_locked(void *opaque)
2318 {
2319 return ((IDEState *)opaque)->tray_locked;
2320 }
2321
2322 static void ide_resize_cb(void *opaque)
2323 {
2324 IDEState *s = opaque;
2325 uint64_t nb_sectors;
2326
2327 if (!s->identify_set) {
2328 return;
2329 }
2330
2331 blk_get_geometry(s->blk, &nb_sectors);
2332 s->nb_sectors = nb_sectors;
2333
2334 /* Update the identify data buffer. */
2335 if (s->drive_kind == IDE_CFATA) {
2336 ide_cfata_identify_size(s);
2337 } else {
2338 /* IDE_CD uses a different set of callbacks entirely. */
2339 assert(s->drive_kind != IDE_CD);
2340 ide_identify_size(s);
2341 }
2342 }
2343
2344 static const BlockDevOps ide_cd_block_ops = {
2345 .change_media_cb = ide_cd_change_cb,
2346 .eject_request_cb = ide_cd_eject_request_cb,
2347 .is_tray_open = ide_cd_is_tray_open,
2348 .is_medium_locked = ide_cd_is_medium_locked,
2349 };
2350
2351 static const BlockDevOps ide_hd_block_ops = {
2352 .resize_cb = ide_resize_cb,
2353 };
2354
2355 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
2356 const char *version, const char *serial, const char *model,
2357 uint64_t wwn,
2358 uint32_t cylinders, uint32_t heads, uint32_t secs,
2359 int chs_trans)
2360 {
2361 uint64_t nb_sectors;
2362
2363 s->blk = blk;
2364 s->drive_kind = kind;
2365
2366 blk_get_geometry(blk, &nb_sectors);
2367 s->cylinders = cylinders;
2368 s->heads = heads;
2369 s->sectors = secs;
2370 s->chs_trans = chs_trans;
2371 s->nb_sectors = nb_sectors;
2372 s->wwn = wwn;
2373 /* The SMART values should be preserved across power cycles
2374 but they aren't. */
2375 s->smart_enabled = 1;
2376 s->smart_autosave = 1;
2377 s->smart_errors = 0;
2378 s->smart_selftest_count = 0;
2379 if (kind == IDE_CD) {
2380 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2381 blk_set_guest_block_size(blk, 2048);
2382 } else {
2383 if (!blk_is_inserted(s->blk)) {
2384 error_report("Device needs media, but drive is empty");
2385 return -1;
2386 }
2387 if (blk_is_read_only(blk)) {
2388 error_report("Can't use a read-only drive");
2389 return -1;
2390 }
2391 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
2392 }
2393 if (serial) {
2394 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2395 } else {
2396 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2397 "QM%05d", s->drive_serial);
2398 }
2399 if (model) {
2400 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2401 } else {
2402 switch (kind) {
2403 case IDE_CD:
2404 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2405 break;
2406 case IDE_CFATA:
2407 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2408 break;
2409 default:
2410 strcpy(s->drive_model_str, "QEMU HARDDISK");
2411 break;
2412 }
2413 }
2414
2415 if (version) {
2416 pstrcpy(s->version, sizeof(s->version), version);
2417 } else {
2418 pstrcpy(s->version, sizeof(s->version), qemu_hw_version());
2419 }
2420
2421 ide_reset(s);
2422 blk_iostatus_enable(blk);
2423 return 0;
2424 }
2425
2426 static void ide_init1(IDEBus *bus, int unit)
2427 {
2428 static int drive_serial = 1;
2429 IDEState *s = &bus->ifs[unit];
2430
2431 s->bus = bus;
2432 s->unit = unit;
2433 s->drive_serial = drive_serial++;
2434 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2435 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2436 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2437 memset(s->io_buffer, 0, s->io_buffer_total_len);
2438
2439 s->smart_selftest_data = blk_blockalign(s->blk, 512);
2440 memset(s->smart_selftest_data, 0, 512);
2441
2442 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2443 ide_sector_write_timer_cb, s);
2444 }
2445
2446 static int ide_nop_int(IDEDMA *dma, int x)
2447 {
2448 return 0;
2449 }
2450
2451 static void ide_nop(IDEDMA *dma)
2452 {
2453 }
2454
2455 static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
2456 {
2457 return 0;
2458 }
2459
2460 static const IDEDMAOps ide_dma_nop_ops = {
2461 .prepare_buf = ide_nop_int32,
2462 .restart_dma = ide_nop,
2463 .rw_buf = ide_nop_int,
2464 };
2465
2466 static void ide_restart_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
2467 {
2468 s->unit = s->bus->retry_unit;
2469 ide_set_sector(s, s->bus->retry_sector_num);
2470 s->nsector = s->bus->retry_nsector;
2471 s->bus->dma->ops->restart_dma(s->bus->dma);
2472 s->io_buffer_size = 0;
2473 s->dma_cmd = dma_cmd;
2474 ide_start_dma(s, ide_dma_cb);
2475 }
2476
2477 static void ide_restart_bh(void *opaque)
2478 {
2479 IDEBus *bus = opaque;
2480 IDEState *s;
2481 bool is_read;
2482 int error_status;
2483
2484 qemu_bh_delete(bus->bh);
2485 bus->bh = NULL;
2486
2487 error_status = bus->error_status;
2488 if (bus->error_status == 0) {
2489 return;
2490 }
2491
2492 s = idebus_active_if(bus);
2493 is_read = (bus->error_status & IDE_RETRY_READ) != 0;
2494
2495 /* The error status must be cleared before resubmitting the request: The
2496 * request may fail again, and this case can only be distinguished if the
2497 * called function can set a new error status. */
2498 bus->error_status = 0;
2499
2500 /* The HBA has generically asked to be kicked on retry */
2501 if (error_status & IDE_RETRY_HBA) {
2502 if (s->bus->dma->ops->restart) {
2503 s->bus->dma->ops->restart(s->bus->dma);
2504 }
2505 }
2506
2507 if (error_status & IDE_RETRY_DMA) {
2508 if (error_status & IDE_RETRY_TRIM) {
2509 ide_restart_dma(s, IDE_DMA_TRIM);
2510 } else {
2511 ide_restart_dma(s, is_read ? IDE_DMA_READ : IDE_DMA_WRITE);
2512 }
2513 } else if (error_status & IDE_RETRY_PIO) {
2514 if (is_read) {
2515 ide_sector_read(s);
2516 } else {
2517 ide_sector_write(s);
2518 }
2519 } else if (error_status & IDE_RETRY_FLUSH) {
2520 ide_flush_cache(s);
2521 } else {
2522 /*
2523 * We've not got any bits to tell us about ATAPI - but
2524 * we do have the end_transfer_func that tells us what
2525 * we're trying to do.
2526 */
2527 if (s->end_transfer_func == ide_atapi_cmd) {
2528 ide_atapi_dma_restart(s);
2529 }
2530 }
2531 }
2532
2533 static void ide_restart_cb(void *opaque, int running, RunState state)
2534 {
2535 IDEBus *bus = opaque;
2536
2537 if (!running)
2538 return;
2539
2540 if (!bus->bh) {
2541 bus->bh = qemu_bh_new(ide_restart_bh, bus);
2542 qemu_bh_schedule(bus->bh);
2543 }
2544 }
2545
2546 void ide_register_restart_cb(IDEBus *bus)
2547 {
2548 if (bus->dma->ops->restart_dma) {
2549 qemu_add_vm_change_state_handler(ide_restart_cb, bus);
2550 }
2551 }
2552
2553 static IDEDMA ide_dma_nop = {
2554 .ops = &ide_dma_nop_ops,
2555 .aiocb = NULL,
2556 };
2557
2558 void ide_init2(IDEBus *bus, qemu_irq irq)
2559 {
2560 int i;
2561
2562 for(i = 0; i < 2; i++) {
2563 ide_init1(bus, i);
2564 ide_reset(&bus->ifs[i]);
2565 }
2566 bus->irq = irq;
2567 bus->dma = &ide_dma_nop;
2568 }
2569
2570 static const MemoryRegionPortio ide_portio_list[] = {
2571 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2572 { 0, 1, 2, .read = ide_data_readw, .write = ide_data_writew },
2573 { 0, 1, 4, .read = ide_data_readl, .write = ide_data_writel },
2574 PORTIO_END_OF_LIST(),
2575 };
2576
2577 static const MemoryRegionPortio ide_portio2_list[] = {
2578 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2579 PORTIO_END_OF_LIST(),
2580 };
2581
2582 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2583 {
2584 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2585 bridge has been setup properly to always register with ISA. */
2586 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2587
2588 if (iobase2) {
2589 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2590 }
2591 }
2592
2593 static bool is_identify_set(void *opaque, int version_id)
2594 {
2595 IDEState *s = opaque;
2596
2597 return s->identify_set != 0;
2598 }
2599
2600 static EndTransferFunc* transfer_end_table[] = {
2601 ide_sector_read,
2602 ide_sector_write,
2603 ide_transfer_stop,
2604 ide_atapi_cmd_reply_end,
2605 ide_atapi_cmd,
2606 ide_dummy_transfer_stop,
2607 };
2608
2609 static int transfer_end_table_idx(EndTransferFunc *fn)
2610 {
2611 int i;
2612
2613 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2614 if (transfer_end_table[i] == fn)
2615 return i;
2616
2617 return -1;
2618 }
2619
2620 static int ide_drive_post_load(void *opaque, int version_id)
2621 {
2622 IDEState *s = opaque;
2623
2624 if (s->blk && s->identify_set) {
2625 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
2626 }
2627 return 0;
2628 }
2629
2630 static int ide_drive_pio_post_load(void *opaque, int version_id)
2631 {
2632 IDEState *s = opaque;
2633
2634 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2635 return -EINVAL;
2636 }
2637 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2638 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2639 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2640 s->atapi_dma = s->feature & 1; /* as per cmd_packet */
2641
2642 return 0;
2643 }
2644
2645 static void ide_drive_pio_pre_save(void *opaque)
2646 {
2647 IDEState *s = opaque;
2648 int idx;
2649
2650 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2651 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2652
2653 idx = transfer_end_table_idx(s->end_transfer_func);
2654 if (idx == -1) {
2655 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2656 __func__);
2657 s->end_transfer_fn_idx = 2;
2658 } else {
2659 s->end_transfer_fn_idx = idx;
2660 }
2661 }
2662
2663 static bool ide_drive_pio_state_needed(void *opaque)
2664 {
2665 IDEState *s = opaque;
2666
2667 return ((s->status & DRQ_STAT) != 0)
2668 || (s->bus->error_status & IDE_RETRY_PIO);
2669 }
2670
2671 static bool ide_tray_state_needed(void *opaque)
2672 {
2673 IDEState *s = opaque;
2674
2675 return s->tray_open || s->tray_locked;
2676 }
2677
2678 static bool ide_atapi_gesn_needed(void *opaque)
2679 {
2680 IDEState *s = opaque;
2681
2682 return s->events.new_media || s->events.eject_request;
2683 }
2684
2685 static bool ide_error_needed(void *opaque)
2686 {
2687 IDEBus *bus = opaque;
2688
2689 return (bus->error_status != 0);
2690 }
2691
2692 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2693 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2694 .name ="ide_drive/atapi/gesn_state",
2695 .version_id = 1,
2696 .minimum_version_id = 1,
2697 .needed = ide_atapi_gesn_needed,
2698 .fields = (VMStateField[]) {
2699 VMSTATE_BOOL(events.new_media, IDEState),
2700 VMSTATE_BOOL(events.eject_request, IDEState),
2701 VMSTATE_END_OF_LIST()
2702 }
2703 };
2704
2705 static const VMStateDescription vmstate_ide_tray_state = {
2706 .name = "ide_drive/tray_state",
2707 .version_id = 1,
2708 .minimum_version_id = 1,
2709 .needed = ide_tray_state_needed,
2710 .fields = (VMStateField[]) {
2711 VMSTATE_BOOL(tray_open, IDEState),
2712 VMSTATE_BOOL(tray_locked, IDEState),
2713 VMSTATE_END_OF_LIST()
2714 }
2715 };
2716
2717 static const VMStateDescription vmstate_ide_drive_pio_state = {
2718 .name = "ide_drive/pio_state",
2719 .version_id = 1,
2720 .minimum_version_id = 1,
2721 .pre_save = ide_drive_pio_pre_save,
2722 .post_load = ide_drive_pio_post_load,
2723 .needed = ide_drive_pio_state_needed,
2724 .fields = (VMStateField[]) {
2725 VMSTATE_INT32(req_nb_sectors, IDEState),
2726 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2727 vmstate_info_uint8, uint8_t),
2728 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2729 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2730 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2731 VMSTATE_INT32(elementary_transfer_size, IDEState),
2732 VMSTATE_INT32(packet_transfer_size, IDEState),
2733 VMSTATE_END_OF_LIST()
2734 }
2735 };
2736
2737 const VMStateDescription vmstate_ide_drive = {
2738 .name = "ide_drive",
2739 .version_id = 3,
2740 .minimum_version_id = 0,
2741 .post_load = ide_drive_post_load,
2742 .fields = (VMStateField[]) {
2743 VMSTATE_INT32(mult_sectors, IDEState),
2744 VMSTATE_INT32(identify_set, IDEState),
2745 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2746 VMSTATE_UINT8(feature, IDEState),
2747 VMSTATE_UINT8(error, IDEState),
2748 VMSTATE_UINT32(nsector, IDEState),
2749 VMSTATE_UINT8(sector, IDEState),
2750 VMSTATE_UINT8(lcyl, IDEState),
2751 VMSTATE_UINT8(hcyl, IDEState),
2752 VMSTATE_UINT8(hob_feature, IDEState),
2753 VMSTATE_UINT8(hob_sector, IDEState),
2754 VMSTATE_UINT8(hob_nsector, IDEState),
2755 VMSTATE_UINT8(hob_lcyl, IDEState),
2756 VMSTATE_UINT8(hob_hcyl, IDEState),
2757 VMSTATE_UINT8(select, IDEState),
2758 VMSTATE_UINT8(status, IDEState),
2759 VMSTATE_UINT8(lba48, IDEState),
2760 VMSTATE_UINT8(sense_key, IDEState),
2761 VMSTATE_UINT8(asc, IDEState),
2762 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2763 VMSTATE_END_OF_LIST()
2764 },
2765 .subsections = (const VMStateDescription*[]) {
2766 &vmstate_ide_drive_pio_state,
2767 &vmstate_ide_tray_state,
2768 &vmstate_ide_atapi_gesn_state,
2769 NULL
2770 }
2771 };
2772
2773 static const VMStateDescription vmstate_ide_error_status = {
2774 .name ="ide_bus/error",
2775 .version_id = 2,
2776 .minimum_version_id = 1,
2777 .needed = ide_error_needed,
2778 .fields = (VMStateField[]) {
2779 VMSTATE_INT32(error_status, IDEBus),
2780 VMSTATE_INT64_V(retry_sector_num, IDEBus, 2),
2781 VMSTATE_UINT32_V(retry_nsector, IDEBus, 2),
2782 VMSTATE_UINT8_V(retry_unit, IDEBus, 2),
2783 VMSTATE_END_OF_LIST()
2784 }
2785 };
2786
2787 const VMStateDescription vmstate_ide_bus = {
2788 .name = "ide_bus",
2789 .version_id = 1,
2790 .minimum_version_id = 1,
2791 .fields = (VMStateField[]) {
2792 VMSTATE_UINT8(cmd, IDEBus),
2793 VMSTATE_UINT8(unit, IDEBus),
2794 VMSTATE_END_OF_LIST()
2795 },
2796 .subsections = (const VMStateDescription*[]) {
2797 &vmstate_ide_error_status,
2798 NULL
2799 }
2800 };
2801
2802 void ide_drive_get(DriveInfo **hd, int n)
2803 {
2804 int i;
2805 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2806 int max_devs = drive_get_max_devs(IF_IDE);
2807 int n_buses = max_devs ? (n / max_devs) : n;
2808
2809 /*
2810 * Note: The number of actual buses available is not known.
2811 * We compute this based on the size of the DriveInfo* array, n.
2812 * If it is less than max_devs * <num_real_buses>,
2813 * We will stop looking for drives prematurely instead of overfilling
2814 * the array.
2815 */
2816
2817 if (highest_bus > n_buses) {
2818 error_report("Too many IDE buses defined (%d > %d)",
2819 highest_bus, n_buses);
2820 exit(1);
2821 }
2822
2823 for (i = 0; i < n; i++) {
2824 hd[i] = drive_get_by_index(IF_IDE, i);
2825 }
2826 }
QEmu