hw/i2c/aspeed_i2c.c

   1 /*
   2  * ARM Aspeed I2C controller
   3  *
   4  * Copyright (C) 2016 IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/sysbus.h"
  23 #include "migration/vmstate.h"
  24 #include "qemu/log.h"
  25 #include "qemu/module.h"
  26 #include "hw/i2c/aspeed_i2c.h"
  27 #include "hw/irq.h"
  28
  29 /* I2C Global Register */
  30
  31 #define I2C_CTRL_STATUS         0x00        /* Device Interrupt Status */
  32 #define I2C_CTRL_ASSIGN         0x08        /* Device Interrupt Target
  33                                                Assignment */
  34
  35 /* I2C Device (Bus) Register */
  36
  37 #define I2CD_FUN_CTRL_REG       0x00       /* I2CD Function Control  */
  38 #define   I2CD_BUFF_SEL_MASK               (0x7 << 20)
  39 #define   I2CD_BUFF_SEL(x)                 (x << 20)
  40 #define   I2CD_M_SDA_LOCK_EN               (0x1 << 16)
  41 #define   I2CD_MULTI_MASTER_DIS            (0x1 << 15)
  42 #define   I2CD_M_SCL_DRIVE_EN              (0x1 << 14)
  43 #define   I2CD_MSB_STS                     (0x1 << 9)
  44 #define   I2CD_SDA_DRIVE_1T_EN             (0x1 << 8)
  45 #define   I2CD_M_SDA_DRIVE_1T_EN           (0x1 << 7)
  46 #define   I2CD_M_HIGH_SPEED_EN             (0x1 << 6)
  47 #define   I2CD_DEF_ADDR_EN                 (0x1 << 5)
  48 #define   I2CD_DEF_ALERT_EN                (0x1 << 4)
  49 #define   I2CD_DEF_ARP_EN                  (0x1 << 3)
  50 #define   I2CD_DEF_GCALL_EN                (0x1 << 2)
  51 #define   I2CD_SLAVE_EN                    (0x1 << 1)
  52 #define   I2CD_MASTER_EN                   (0x1)
  53
  54 #define I2CD_AC_TIMING_REG1     0x04       /* Clock and AC Timing Control #1 */
  55 #define I2CD_AC_TIMING_REG2     0x08       /* Clock and AC Timing Control #1 */
  56 #define I2CD_INTR_CTRL_REG      0x0c       /* I2CD Interrupt Control */
  57 #define I2CD_INTR_STS_REG       0x10       /* I2CD Interrupt Status */
  58
  59 #define   I2CD_INTR_SLAVE_ADDR_MATCH       (0x1 << 31) /* 0: addr1 1: addr2 */
  60 #define   I2CD_INTR_SLAVE_ADDR_RX_PENDING  (0x1 << 30)
  61 /* bits[19-16] Reserved */
  62
  63 /* All bits below are cleared by writing 1 */
  64 #define   I2CD_INTR_SLAVE_INACTIVE_TIMEOUT (0x1 << 15)
  65 #define   I2CD_INTR_SDA_DL_TIMEOUT         (0x1 << 14)
  66 #define   I2CD_INTR_BUS_RECOVER_DONE       (0x1 << 13)
  67 #define   I2CD_INTR_SMBUS_ALERT            (0x1 << 12) /* Bus [0-3] only */
  68 #define   I2CD_INTR_SMBUS_ARP_ADDR         (0x1 << 11) /* Removed */
  69 #define   I2CD_INTR_SMBUS_DEV_ALERT_ADDR   (0x1 << 10) /* Removed */
  70 #define   I2CD_INTR_SMBUS_DEF_ADDR         (0x1 << 9)  /* Removed */
  71 #define   I2CD_INTR_GCALL_ADDR             (0x1 << 8)  /* Removed */
  72 #define   I2CD_INTR_SLAVE_ADDR_RX_MATCH    (0x1 << 7)  /* use RX_DONE */
  73 #define   I2CD_INTR_SCL_TIMEOUT            (0x1 << 6)
  74 #define   I2CD_INTR_ABNORMAL               (0x1 << 5)
  75 #define   I2CD_INTR_NORMAL_STOP            (0x1 << 4)
  76 #define   I2CD_INTR_ARBIT_LOSS             (0x1 << 3)
  77 #define   I2CD_INTR_RX_DONE                (0x1 << 2)
  78 #define   I2CD_INTR_TX_NAK                 (0x1 << 1)
  79 #define   I2CD_INTR_TX_ACK                 (0x1 << 0)
  80
  81 #define I2CD_CMD_REG            0x14       /* I2CD Command/Status */
  82 #define   I2CD_SDA_OE                      (0x1 << 28)
  83 #define   I2CD_SDA_O                       (0x1 << 27)
  84 #define   I2CD_SCL_OE                      (0x1 << 26)
  85 #define   I2CD_SCL_O                       (0x1 << 25)
  86 #define   I2CD_TX_TIMING                   (0x1 << 24)
  87 #define   I2CD_TX_STATUS                   (0x1 << 23)
  88
  89 #define   I2CD_TX_STATE_SHIFT              19 /* Tx State Machine */
  90 #define   I2CD_TX_STATE_MASK                  0xf
  91 #define     I2CD_IDLE                         0x0
  92 #define     I2CD_MACTIVE                      0x8
  93 #define     I2CD_MSTART                       0x9
  94 #define     I2CD_MSTARTR                      0xa
  95 #define     I2CD_MSTOP                        0xb
  96 #define     I2CD_MTXD                         0xc
  97 #define     I2CD_MRXACK                       0xd
  98 #define     I2CD_MRXD                         0xe
  99 #define     I2CD_MTXACK                       0xf
 100 #define     I2CD_SWAIT                        0x1
 101 #define     I2CD_SRXD                         0x4
 102 #define     I2CD_STXACK                       0x5
 103 #define     I2CD_STXD                         0x6
 104 #define     I2CD_SRXACK                       0x7
 105 #define     I2CD_RECOVER                      0x3
 106
 107 #define   I2CD_SCL_LINE_STS                (0x1 << 18)
 108 #define   I2CD_SDA_LINE_STS                (0x1 << 17)
 109 #define   I2CD_BUS_BUSY_STS                (0x1 << 16)
 110 #define   I2CD_SDA_OE_OUT_DIR              (0x1 << 15)
 111 #define   I2CD_SDA_O_OUT_DIR               (0x1 << 14)
 112 #define   I2CD_SCL_OE_OUT_DIR              (0x1 << 13)
 113 #define   I2CD_SCL_O_OUT_DIR               (0x1 << 12)
 114 #define   I2CD_BUS_RECOVER_CMD_EN          (0x1 << 11)
 115 #define   I2CD_S_ALT_EN                    (0x1 << 10)
 116 #define   I2CD_RX_DMA_ENABLE               (0x1 << 9)
 117 #define   I2CD_TX_DMA_ENABLE               (0x1 << 8)
 118
 119 /* Command Bit */
 120 #define   I2CD_M_STOP_CMD                  (0x1 << 5)
 121 #define   I2CD_M_S_RX_CMD_LAST             (0x1 << 4)
 122 #define   I2CD_M_RX_CMD                    (0x1 << 3)
 123 #define   I2CD_S_TX_CMD                    (0x1 << 2)
 124 #define   I2CD_M_TX_CMD                    (0x1 << 1)
 125 #define   I2CD_M_START_CMD                 (0x1)
 126
 127 #define I2CD_DEV_ADDR_REG       0x18       /* Slave Device Address */
 128 #define I2CD_BUF_CTRL_REG       0x1c       /* Pool Buffer Control */
 129 #define I2CD_BYTE_BUF_REG       0x20       /* Transmit/Receive Byte Buffer */
 130 #define   I2CD_BYTE_BUF_TX_SHIFT           0
 131 #define   I2CD_BYTE_BUF_TX_MASK            0xff
 132 #define   I2CD_BYTE_BUF_RX_SHIFT           8
 133 #define   I2CD_BYTE_BUF_RX_MASK            0xff
 134
 135
 136 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
 137 {
 138     return bus->ctrl & I2CD_MASTER_EN;
 139 }
 140
 141 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
 142 {
 143     return bus->ctrl & (I2CD_MASTER_EN | I2CD_SLAVE_EN);
 144 }
 145
 146 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus)
 147 {
 148     AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
 149
 150     bus->intr_status &= bus->intr_ctrl;
 151     if (bus->intr_status) {
 152         bus->controller->intr_status |= 1 << bus->id;
 153         qemu_irq_raise(aic->bus_get_irq(bus));
 154     }
 155 }
 156
 157 static uint64_t aspeed_i2c_bus_read(void *opaque, hwaddr offset,
 158                                     unsigned size)
 159 {
 160     AspeedI2CBus *bus = opaque;
 161
 162     switch (offset) {
 163     case I2CD_FUN_CTRL_REG:
 164         return bus->ctrl;
 165     case I2CD_AC_TIMING_REG1:
 166         return bus->timing[0];
 167     case I2CD_AC_TIMING_REG2:
 168         return bus->timing[1];
 169     case I2CD_INTR_CTRL_REG:
 170         return bus->intr_ctrl;
 171     case I2CD_INTR_STS_REG:
 172         return bus->intr_status;
 173     case I2CD_BYTE_BUF_REG:
 174         return bus->buf;
 175     case I2CD_CMD_REG:
 176         return bus->cmd | (i2c_bus_busy(bus->bus) << 16);
 177     default:
 178         qemu_log_mask(LOG_GUEST_ERROR,
 179                       "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, offset);
 180         return -1;
 181     }
 182 }
 183
 184 static void aspeed_i2c_set_state(AspeedI2CBus *bus, uint8_t state)
 185 {
 186     bus->cmd &= ~(I2CD_TX_STATE_MASK << I2CD_TX_STATE_SHIFT);
 187     bus->cmd |= (state & I2CD_TX_STATE_MASK) << I2CD_TX_STATE_SHIFT;
 188 }
 189
 190 static uint8_t aspeed_i2c_get_state(AspeedI2CBus *bus)
 191 {
 192     return (bus->cmd >> I2CD_TX_STATE_SHIFT) & I2CD_TX_STATE_MASK;
 193 }
 194
 195 static void aspeed_i2c_handle_rx_cmd(AspeedI2CBus *bus)
 196 {
 197     uint8_t ret;
 198
 199     aspeed_i2c_set_state(bus, I2CD_MRXD);
 200     ret = i2c_recv(bus->bus);
 201     bus->intr_status |= I2CD_INTR_RX_DONE;
 202     bus->buf = (ret & I2CD_BYTE_BUF_RX_MASK) << I2CD_BYTE_BUF_RX_SHIFT;
 203     if (bus->cmd & I2CD_M_S_RX_CMD_LAST) {
 204         i2c_nack(bus->bus);
 205     }
 206     bus->cmd &= ~(I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST);
 207     aspeed_i2c_set_state(bus, I2CD_MACTIVE);
 208 }
 209
 210 /*
 211  * The state machine needs some refinement. It is only used to track
 212  * invalid STOP commands for the moment.
 213  */
 214 static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
 215 {
 216     bus->cmd &= ~0xFFFF;
 217     bus->cmd |= value & 0xFFFF;
 218
 219     if (bus->cmd & I2CD_M_START_CMD) {
 220         uint8_t state = aspeed_i2c_get_state(bus) & I2CD_MACTIVE ?
 221             I2CD_MSTARTR : I2CD_MSTART;
 222
 223         aspeed_i2c_set_state(bus, state);
 224
 225         if (i2c_start_transfer(bus->bus, extract32(bus->buf, 1, 7),
 226                                extract32(bus->buf, 0, 1))) {
 227             bus->intr_status |= I2CD_INTR_TX_NAK;
 228         } else {
 229             bus->intr_status |= I2CD_INTR_TX_ACK;
 230         }
 231
 232         /* START command is also a TX command, as the slave address is
 233          * sent on the bus */
 234         bus->cmd &= ~(I2CD_M_START_CMD | I2CD_M_TX_CMD);
 235
 236         /* No slave found */
 237         if (!i2c_bus_busy(bus->bus)) {
 238             return;
 239         }
 240         aspeed_i2c_set_state(bus, I2CD_MACTIVE);
 241     }
 242
 243     if (bus->cmd & I2CD_M_TX_CMD) {
 244         aspeed_i2c_set_state(bus, I2CD_MTXD);
 245         if (i2c_send(bus->bus, bus->buf)) {
 246             bus->intr_status |= (I2CD_INTR_TX_NAK);
 247             i2c_end_transfer(bus->bus);
 248         } else {
 249             bus->intr_status |= I2CD_INTR_TX_ACK;
 250         }
 251         bus->cmd &= ~I2CD_M_TX_CMD;
 252         aspeed_i2c_set_state(bus, I2CD_MACTIVE);
 253     }
 254
 255     if ((bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST)) &&
 256         !(bus->intr_status & I2CD_INTR_RX_DONE)) {
 257         aspeed_i2c_handle_rx_cmd(bus);
 258     }
 259
 260     if (bus->cmd & I2CD_M_STOP_CMD) {
 261         if (!(aspeed_i2c_get_state(bus) & I2CD_MACTIVE)) {
 262             qemu_log_mask(LOG_GUEST_ERROR, "%s: abnormal stop\n", __func__);
 263             bus->intr_status |= I2CD_INTR_ABNORMAL;
 264         } else {
 265             aspeed_i2c_set_state(bus, I2CD_MSTOP);
 266             i2c_end_transfer(bus->bus);
 267             bus->intr_status |= I2CD_INTR_NORMAL_STOP;
 268         }
 269         bus->cmd &= ~I2CD_M_STOP_CMD;
 270         aspeed_i2c_set_state(bus, I2CD_IDLE);
 271     }
 272 }
 273
 274 static void aspeed_i2c_bus_write(void *opaque, hwaddr offset,
 275                                  uint64_t value, unsigned size)
 276 {
 277     AspeedI2CBus *bus = opaque;
 278     AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller);
 279     bool handle_rx;
 280
 281     switch (offset) {
 282     case I2CD_FUN_CTRL_REG:
 283         if (value & I2CD_SLAVE_EN) {
 284             qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
 285                           __func__);
 286             break;
 287         }
 288         bus->ctrl = value & 0x0071C3FF;
 289         break;
 290     case I2CD_AC_TIMING_REG1:
 291         bus->timing[0] = value & 0xFFFFF0F;
 292         break;
 293     case I2CD_AC_TIMING_REG2:
 294         bus->timing[1] = value & 0x7;
 295         break;
 296     case I2CD_INTR_CTRL_REG:
 297         bus->intr_ctrl = value & 0x7FFF;
 298         break;
 299     case I2CD_INTR_STS_REG:
 300         handle_rx = (bus->intr_status & I2CD_INTR_RX_DONE) &&
 301                 (value & I2CD_INTR_RX_DONE);
 302         bus->intr_status &= ~(value & 0x7FFF);
 303         if (!bus->intr_status) {
 304             bus->controller->intr_status &= ~(1 << bus->id);
 305             qemu_irq_lower(aic->bus_get_irq(bus));
 306         }
 307         if (handle_rx && (bus->cmd & (I2CD_M_RX_CMD | I2CD_M_S_RX_CMD_LAST))) {
 308             aspeed_i2c_handle_rx_cmd(bus);
 309             aspeed_i2c_bus_raise_interrupt(bus);
 310         }
 311         break;
 312     case I2CD_DEV_ADDR_REG:
 313         qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
 314                       __func__);
 315         break;
 316     case I2CD_BYTE_BUF_REG:
 317         bus->buf = (value & I2CD_BYTE_BUF_TX_MASK) << I2CD_BYTE_BUF_TX_SHIFT;
 318         break;
 319     case I2CD_CMD_REG:
 320         if (!aspeed_i2c_bus_is_enabled(bus)) {
 321             break;
 322         }
 323
 324         if (!aspeed_i2c_bus_is_master(bus)) {
 325             qemu_log_mask(LOG_UNIMP, "%s: slave mode not implemented\n",
 326                           __func__);
 327             break;
 328         }
 329
 330         aspeed_i2c_bus_handle_cmd(bus, value);
 331         aspeed_i2c_bus_raise_interrupt(bus);
 332         break;
 333
 334     default:
 335         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
 336                       __func__, offset);
 337     }
 338 }
 339
 340 static uint64_t aspeed_i2c_ctrl_read(void *opaque, hwaddr offset,
 341                                    unsigned size)
 342 {
 343     AspeedI2CState *s = opaque;
 344
 345     switch (offset) {
 346     case I2C_CTRL_STATUS:
 347         return s->intr_status;
 348     default:
 349         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
 350                       __func__, offset);
 351         break;
 352     }
 353
 354     return -1;
 355 }
 356
 357 static void aspeed_i2c_ctrl_write(void *opaque, hwaddr offset,
 358                                   uint64_t value, unsigned size)
 359 {
 360     switch (offset) {
 361     case I2C_CTRL_STATUS:
 362     default:
 363         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
 364                       __func__, offset);
 365         break;
 366     }
 367 }
 368
 369 static const MemoryRegionOps aspeed_i2c_bus_ops = {
 370     .read = aspeed_i2c_bus_read,
 371     .write = aspeed_i2c_bus_write,
 372     .endianness = DEVICE_LITTLE_ENDIAN,
 373 };
 374
 375 static const MemoryRegionOps aspeed_i2c_ctrl_ops = {
 376     .read = aspeed_i2c_ctrl_read,
 377     .write = aspeed_i2c_ctrl_write,
 378     .endianness = DEVICE_LITTLE_ENDIAN,
 379 };
 380
 381 static const VMStateDescription aspeed_i2c_bus_vmstate = {
 382     .name = TYPE_ASPEED_I2C,
 383     .version_id = 1,
 384     .minimum_version_id = 1,
 385     .fields = (VMStateField[]) {
 386         VMSTATE_UINT8(id, AspeedI2CBus),
 387         VMSTATE_UINT32(ctrl, AspeedI2CBus),
 388         VMSTATE_UINT32_ARRAY(timing, AspeedI2CBus, 2),
 389         VMSTATE_UINT32(intr_ctrl, AspeedI2CBus),
 390         VMSTATE_UINT32(intr_status, AspeedI2CBus),
 391         VMSTATE_UINT32(cmd, AspeedI2CBus),
 392         VMSTATE_UINT32(buf, AspeedI2CBus),
 393         VMSTATE_END_OF_LIST()
 394     }
 395 };
 396
 397 static const VMStateDescription aspeed_i2c_vmstate = {
 398     .name = TYPE_ASPEED_I2C,
 399     .version_id = 1,
 400     .minimum_version_id = 1,
 401     .fields = (VMStateField[]) {
 402         VMSTATE_UINT32(intr_status, AspeedI2CState),
 403         VMSTATE_STRUCT_ARRAY(busses, AspeedI2CState,
 404                              ASPEED_I2C_NR_BUSSES, 1, aspeed_i2c_bus_vmstate,
 405                              AspeedI2CBus),
 406         VMSTATE_END_OF_LIST()
 407     }
 408 };
 409
 410 static void aspeed_i2c_reset(DeviceState *dev)
 411 {
 412     int i;
 413     AspeedI2CState *s = ASPEED_I2C(dev);
 414     AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
 415
 416     s->intr_status = 0;
 417
 418     for (i = 0; i < aic->num_busses; i++) {
 419         s->busses[i].intr_ctrl = 0;
 420         s->busses[i].intr_status = 0;
 421         s->busses[i].cmd = 0;
 422         s->busses[i].buf = 0;
 423         i2c_end_transfer(s->busses[i].bus);
 424     }
 425 }
 426
 427 /*
 428  * Address Definitions (AST2400 and AST2500)
 429  *
 430  *   0x000 ... 0x03F: Global Register
 431  *   0x040 ... 0x07F: Device 1
 432  *   0x080 ... 0x0BF: Device 2
 433  *   0x0C0 ... 0x0FF: Device 3
 434  *   0x100 ... 0x13F: Device 4
 435  *   0x140 ... 0x17F: Device 5
 436  *   0x180 ... 0x1BF: Device 6
 437  *   0x1C0 ... 0x1FF: Device 7
 438  *   0x200 ... 0x2FF: Buffer Pool  (unused in linux driver)
 439  *   0x300 ... 0x33F: Device 8
 440  *   0x340 ... 0x37F: Device 9
 441  *   0x380 ... 0x3BF: Device 10
 442  *   0x3C0 ... 0x3FF: Device 11
 443  *   0x400 ... 0x43F: Device 12
 444  *   0x440 ... 0x47F: Device 13
 445  *   0x480 ... 0x4BF: Device 14
 446  *   0x800 ... 0xFFF: Buffer Pool  (unused in linux driver)
 447  */
 448 static void aspeed_i2c_realize(DeviceState *dev, Error **errp)
 449 {
 450     int i;
 451     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 452     AspeedI2CState *s = ASPEED_I2C(dev);
 453     AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
 454
 455     sysbus_init_irq(sbd, &s->irq);
 456     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i2c_ctrl_ops, s,
 457                           "aspeed.i2c", 0x1000);
 458     sysbus_init_mmio(sbd, &s->iomem);
 459
 460     for (i = 0; i < aic->num_busses; i++) {
 461         char name[32];
 462         int offset = i < aic->gap ? 1 : 5;
 463
 464         sysbus_init_irq(sbd, &s->busses[i].irq);
 465         snprintf(name, sizeof(name), "aspeed.i2c.%d", i);
 466         s->busses[i].controller = s;
 467         s->busses[i].id = i;
 468         s->busses[i].bus = i2c_init_bus(dev, name);
 469         memory_region_init_io(&s->busses[i].mr, OBJECT(dev),
 470                               &aspeed_i2c_bus_ops, &s->busses[i], name,
 471                               aic->reg_size);
 472         memory_region_add_subregion(&s->iomem, aic->reg_size * (i + offset),
 473                                     &s->busses[i].mr);
 474     }
 475 }
 476
 477 static void aspeed_i2c_class_init(ObjectClass *klass, void *data)
 478 {
 479     DeviceClass *dc = DEVICE_CLASS(klass);
 480
 481     dc->vmsd = &aspeed_i2c_vmstate;
 482     dc->reset = aspeed_i2c_reset;
 483     dc->realize = aspeed_i2c_realize;
 484     dc->desc = "Aspeed I2C Controller";
 485 }
 486
 487 static const TypeInfo aspeed_i2c_info = {
 488     .name          = TYPE_ASPEED_I2C,
 489     .parent        = TYPE_SYS_BUS_DEVICE,
 490     .instance_size = sizeof(AspeedI2CState),
 491     .class_init    = aspeed_i2c_class_init,
 492     .class_size = sizeof(AspeedI2CClass),
 493     .abstract   = true,
 494 };
 495
 496 static qemu_irq aspeed_2400_i2c_bus_get_irq(AspeedI2CBus *bus)
 497 {
 498     return bus->controller->irq;
 499 }
 500
 501 static void aspeed_2400_i2c_class_init(ObjectClass *klass, void *data)
 502 {
 503     DeviceClass *dc = DEVICE_CLASS(klass);
 504     AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
 505
 506     dc->desc = "ASPEED 2400 I2C Controller";
 507
 508     aic->num_busses = 14;
 509     aic->reg_size = 0x40;
 510     aic->gap = 7;
 511     aic->bus_get_irq = aspeed_2400_i2c_bus_get_irq;
 512 }
 513
 514 static const TypeInfo aspeed_2400_i2c_info = {
 515     .name = TYPE_ASPEED_2400_I2C,
 516     .parent = TYPE_ASPEED_I2C,
 517     .class_init = aspeed_2400_i2c_class_init,
 518 };
 519
 520 static qemu_irq aspeed_2500_i2c_bus_get_irq(AspeedI2CBus *bus)
 521 {
 522     return bus->controller->irq;
 523 }
 524
 525 static void aspeed_2500_i2c_class_init(ObjectClass *klass, void *data)
 526 {
 527     DeviceClass *dc = DEVICE_CLASS(klass);
 528     AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
 529
 530     dc->desc = "ASPEED 2500 I2C Controller";
 531
 532     aic->num_busses = 14;
 533     aic->reg_size = 0x40;
 534     aic->gap = 7;
 535     aic->bus_get_irq = aspeed_2500_i2c_bus_get_irq;
 536 }
 537
 538 static const TypeInfo aspeed_2500_i2c_info = {
 539     .name = TYPE_ASPEED_2500_I2C,
 540     .parent = TYPE_ASPEED_I2C,
 541     .class_init = aspeed_2500_i2c_class_init,
 542 };
 543
 544 static qemu_irq aspeed_2600_i2c_bus_get_irq(AspeedI2CBus *bus)
 545 {
 546     return bus->irq;
 547 }
 548
 549 static void aspeed_2600_i2c_class_init(ObjectClass *klass, void *data)
 550 {
 551     DeviceClass *dc = DEVICE_CLASS(klass);
 552     AspeedI2CClass *aic = ASPEED_I2C_CLASS(klass);
 553
 554     dc->desc = "ASPEED 2600 I2C Controller";
 555
 556     aic->num_busses = 16;
 557     aic->reg_size = 0x80;
 558     aic->gap = -1; /* no gap */
 559     aic->bus_get_irq = aspeed_2600_i2c_bus_get_irq;
 560 }
 561
 562 static const TypeInfo aspeed_2600_i2c_info = {
 563     .name = TYPE_ASPEED_2600_I2C,
 564     .parent = TYPE_ASPEED_I2C,
 565     .class_init = aspeed_2600_i2c_class_init,
 566 };
 567
 568 static void aspeed_i2c_register_types(void)
 569 {
 570     type_register_static(&aspeed_i2c_info);
 571     type_register_static(&aspeed_2400_i2c_info);
 572     type_register_static(&aspeed_2500_i2c_info);
 573     type_register_static(&aspeed_2600_i2c_info);
 574 }
 575
 576 type_init(aspeed_i2c_register_types)
 577
 578
 579 I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr)
 580 {
 581     AspeedI2CState *s = ASPEED_I2C(dev);
 582     AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
 583     I2CBus *bus = NULL;
 584
 585     if (busnr >= 0 && busnr < aic->num_busses) {
 586         bus = s->busses[busnr].bus;
 587     }
 588
 589     return bus;
 590 }