hw/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "sh.h"
  28 #include "devices.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31 #include "pci.h"
  32 #include "sh_pci.h"
  33 #include "net.h"
  34 #include "sh7750_regs.h"
  35 #include "ide.h"
  36 #include "loader.h"
  37
  38 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  39 #define SDRAM_SIZE 0x04000000
  40
  41 #define SM501_VRAM_SIZE 0x800000
  42
  43 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  44 #define LINUX_LOAD_OFFSET 0x800000
  45
  46 #define PA_IRLMSK       0x00
  47 #define PA_POWOFF       0x30
  48 #define PA_VERREG       0x32
  49 #define PA_OUTPORT      0x36
  50
  51 typedef struct {
  52     uint16_t bcr;
  53     uint16_t irlmsk;
  54     uint16_t irlmon;
  55     uint16_t cfctl;
  56     uint16_t cfpow;
  57     uint16_t dispctl;
  58     uint16_t sdmpow;
  59     uint16_t rtcce;
  60     uint16_t pcicd;
  61     uint16_t voyagerrts;
  62     uint16_t cfrst;
  63     uint16_t admrts;
  64     uint16_t extrst;
  65     uint16_t cfcdintclr;
  66     uint16_t keyctlclr;
  67     uint16_t pad0;
  68     uint16_t pad1;
  69     uint16_t powoff;
  70     uint16_t verreg;
  71     uint16_t inport;
  72     uint16_t outport;
  73     uint16_t bverreg;
  74
  75 /* output pin */
  76     qemu_irq irl;
  77 } r2d_fpga_t;
  78
  79 enum r2d_fpga_irq {
  80     PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  81     SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  82     NR_IRQS
  83 };
  84
  85 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
  86     [CF_IDE]    = {  1, 1<<9 },
  87     [CF_CD]     = {  2, 1<<8 },
  88     [PCI_INTA]  = {  9, 1<<14 },
  89     [PCI_INTB]  = { 10, 1<<13 },
  90     [PCI_INTC]  = {  3, 1<<12 },
  91     [PCI_INTD]  = {  0, 1<<11 },
  92     [SM501]     = {  4, 1<<10 },
  93     [KEY]       = {  5, 1<<6 },
  94     [RTC_A]     = {  6, 1<<5 },
  95     [RTC_T]     = {  7, 1<<4 },
  96     [SDCARD]    = {  8, 1<<7 },
  97     [EXT]       = { 11, 1<<0 },
  98     [TP]        = { 12, 1<<15 },
  99 };
 100
 101 static void update_irl(r2d_fpga_t *fpga)
 102 {
 103     int i, irl = 15;
 104     for (i = 0; i < NR_IRQS; i++)
 105         if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 106             if (irqtab[i].irl < irl)
 107                 irl = irqtab[i].irl;
 108     qemu_set_irq(fpga->irl, irl ^ 15);
 109 }
 110
 111 static void r2d_fpga_irq_set(void *opaque, int n, int level)
 112 {
 113     r2d_fpga_t *fpga = opaque;
 114     if (level)
 115         fpga->irlmon |= irqtab[n].msk;
 116     else
 117         fpga->irlmon &= ~irqtab[n].msk;
 118     update_irl(fpga);
 119 }
 120
 121 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
 122 {
 123     r2d_fpga_t *s = opaque;
 124
 125     switch (addr) {
 126     case PA_IRLMSK:
 127         return s->irlmsk;
 128     case PA_OUTPORT:
 129         return s->outport;
 130     case PA_POWOFF:
 131         return s->powoff;
 132     case PA_VERREG:
 133         return 0x10;
 134     }
 135
 136     return 0;
 137 }
 138
 139 static void
 140 r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 141 {
 142     r2d_fpga_t *s = opaque;
 143
 144     switch (addr) {
 145     case PA_IRLMSK:
 146         s->irlmsk = value;
 147         update_irl(s);
 148         break;
 149     case PA_OUTPORT:
 150         s->outport = value;
 151         break;
 152     case PA_POWOFF:
 153         s->powoff = value;
 154         break;
 155     case PA_VERREG:
 156         /* Discard writes */
 157         break;
 158     }
 159 }
 160
 161 static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
 162     r2d_fpga_read,
 163     r2d_fpga_read,
 164     NULL,
 165 };
 166
 167 static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
 168     r2d_fpga_write,
 169     r2d_fpga_write,
 170     NULL,
 171 };
 172
 173 static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
 174 {
 175     int iomemtype;
 176     r2d_fpga_t *s;
 177
 178     s = qemu_mallocz(sizeof(r2d_fpga_t));
 179
 180     s->irl = irl;
 181
 182     iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
 183                                        r2d_fpga_writefn, s);
 184     cpu_register_physical_memory(base, 0x40, iomemtype);
 185     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 186 }
 187
 188 static void r2d_pci_set_irq(void *opaque, int n, int l)
 189 {
 190     qemu_irq *p = opaque;
 191
 192     qemu_set_irq(p[n], l);
 193 }
 194
 195 static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
 196 {
 197     const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
 198     return intx[d->devfn >> 3];
 199 }
 200
 201 static void r2d_init(ram_addr_t ram_size,
 202               const char *boot_device,
 203               const char *kernel_filename, const char *kernel_cmdline,
 204               const char *initrd_filename, const char *cpu_model)
 205 {
 206     CPUState *env;
 207     struct SH7750State *s;
 208     ram_addr_t sdram_addr;
 209     qemu_irq *irq;
 210     PCIBus *pci;
 211     DriveInfo *dinfo;
 212     int i;
 213
 214     if (!cpu_model)
 215         cpu_model = "SH7751R";
 216
 217     env = cpu_init(cpu_model);
 218     if (!env) {
 219         fprintf(stderr, "Unable to find CPU definition\n");
 220         exit(1);
 221     }
 222
 223     /* Allocate memory space */
 224     sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
 225     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
 226     /* Register peripherals */
 227     s = sh7750_init(env);
 228     irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
 229     pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
 230
 231     sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
 232
 233     /* onboard CF (True IDE mode, Master only). */
 234     if ((dinfo = drive_get(IF_IDE, 0, 0)) != NULL)
 235         mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
 236                       dinfo, NULL);
 237
 238     /* NIC: rtl8139 on-board, and 2 slots. */
 239     for (i = 0; i < nb_nics; i++)
 240         pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
 241
 242     /* Todo: register on board registers */
 243     if (kernel_filename) {
 244       int kernel_size;
 245       /* initialization which should be done by firmware */
 246       stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
 247       stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
 248
 249       if (kernel_cmdline) {
 250           kernel_size = load_image_targphys(kernel_filename,
 251                                    SDRAM_BASE + LINUX_LOAD_OFFSET,
 252                                    SDRAM_SIZE - LINUX_LOAD_OFFSET);
 253           env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
 254           pstrcpy_targphys("cmdline", SDRAM_BASE + 0x10100, 256, kernel_cmdline);
 255       } else {
 256           kernel_size = load_image_targphys(kernel_filename, SDRAM_BASE, SDRAM_SIZE);
 257           env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
 258       }
 259
 260       if (kernel_size < 0) {
 261         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 262         exit(1);
 263       }
 264     }
 265 }
 266
 267 static QEMUMachine r2d_machine = {
 268     .name = "r2d",
 269     .desc = "r2d-plus board",
 270     .init = r2d_init,
 271 };
 272
 273 static void r2d_machine_init(void)
 274 {
 275     qemu_register_machine(&r2d_machine);
 276 }
 277
 278 machine_init(r2d_machine_init);