hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "hpet_emul.h"
  30
  31 //#define DEBUG_CMOS
  32
  33 #define RTC_SECONDS             0
  34 #define RTC_SECONDS_ALARM       1
  35 #define RTC_MINUTES             2
  36 #define RTC_MINUTES_ALARM       3
  37 #define RTC_HOURS               4
  38 #define RTC_HOURS_ALARM         5
  39 #define RTC_ALARM_DONT_CARE    0xC0
  40
  41 #define RTC_DAY_OF_WEEK         6
  42 #define RTC_DAY_OF_MONTH        7
  43 #define RTC_MONTH               8
  44 #define RTC_YEAR                9
  45
  46 #define RTC_REG_A               10
  47 #define RTC_REG_B               11
  48 #define RTC_REG_C               12
  49 #define RTC_REG_D               13
  50
  51 #define REG_A_UIP 0x80
  52
  53 #define REG_B_SET  0x80
  54 #define REG_B_PIE  0x40
  55 #define REG_B_AIE  0x20
  56 #define REG_B_UIE  0x10
  57 #define REG_B_SQWE 0x08
  58 #define REG_B_DM   0x04
  59
  60 #define REG_C_UF   0x10
  61 #define REG_C_IRQF 0x80
  62 #define REG_C_PF   0x40
  63 #define REG_C_AF   0x20
  64
  65 struct RTCState {
  66     ISADevice dev;
  67     uint8_t cmos_data[128];
  68     uint8_t cmos_index;
  69     struct tm current_tm;
  70     int32_t base_year;
  71     qemu_irq irq;
  72     qemu_irq sqw_irq;
  73     int it_shift;
  74     /* periodic timer */
  75     QEMUTimer *periodic_timer;
  76     int64_t next_periodic_time;
  77     /* second update */
  78     int64_t next_second_time;
  79     uint32_t irq_coalesced;
  80     uint32_t period;
  81     QEMUTimer *coalesced_timer;
  82     QEMUTimer *second_timer;
  83     QEMUTimer *second_timer2;
  84 };
  85
  86 static void rtc_irq_raise(qemu_irq irq)
  87 {
  88     /* When HPET is operating in legacy mode, RTC interrupts are disabled
  89      * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
  90      * mode is established while interrupt is raised. We want it to
  91      * be lowered in any case
  92      */
  93 #if defined TARGET_I386
  94     if (!hpet_in_legacy_mode())
  95 #endif
  96         qemu_irq_raise(irq);
  97 }
  98
  99 static void rtc_set_time(RTCState *s);
 100 static void rtc_copy_date(RTCState *s);
 101
 102 #ifdef TARGET_I386
 103 static void rtc_coalesced_timer_update(RTCState *s)
 104 {
 105     if (s->irq_coalesced == 0) {
 106         qemu_del_timer(s->coalesced_timer);
 107     } else {
 108         /* divide each RTC interval to 2 - 8 smaller intervals */
 109         int c = MIN(s->irq_coalesced, 7) + 1;
 110         int64_t next_clock = qemu_get_clock(rtc_clock) +
 111             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 112         qemu_mod_timer(s->coalesced_timer, next_clock);
 113     }
 114 }
 115
 116 static void rtc_coalesced_timer(void *opaque)
 117 {
 118     RTCState *s = opaque;
 119
 120     if (s->irq_coalesced != 0) {
 121         apic_reset_irq_delivered();
 122         s->cmos_data[RTC_REG_C] |= 0xc0;
 123         rtc_irq_raise(s->irq);
 124         if (apic_get_irq_delivered()) {
 125             s->irq_coalesced--;
 126         }
 127     }
 128
 129     rtc_coalesced_timer_update(s);
 130 }
 131 #endif
 132
 133 static void rtc_timer_update(RTCState *s, int64_t current_time)
 134 {
 135     int period_code, period;
 136     int64_t cur_clock, next_irq_clock;
 137     int enable_pie;
 138
 139     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 140 #if defined TARGET_I386
 141     /* disable periodic timer if hpet is in legacy mode, since interrupts are
 142      * disabled anyway.
 143      */
 144     enable_pie = !hpet_in_legacy_mode();
 145 #else
 146     enable_pie = 1;
 147 #endif
 148     if (period_code != 0
 149         && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
 150             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 151         if (period_code <= 2)
 152             period_code += 7;
 153         /* period in 32 Khz cycles */
 154         period = 1 << (period_code - 1);
 155 #ifdef TARGET_I386
 156         if(period != s->period)
 157             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 158         s->period = period;
 159 #endif
 160         /* compute 32 khz clock */
 161         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 162         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 163         s->next_periodic_time =
 164             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 165         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 166     } else {
 167 #ifdef TARGET_I386
 168         s->irq_coalesced = 0;
 169 #endif
 170         qemu_del_timer(s->periodic_timer);
 171     }
 172 }
 173
 174 static void rtc_periodic_timer(void *opaque)
 175 {
 176     RTCState *s = opaque;
 177
 178     rtc_timer_update(s, s->next_periodic_time);
 179     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 180         s->cmos_data[RTC_REG_C] |= 0xc0;
 181 #ifdef TARGET_I386
 182         if(rtc_td_hack) {
 183             apic_reset_irq_delivered();
 184             rtc_irq_raise(s->irq);
 185             if (!apic_get_irq_delivered()) {
 186                 s->irq_coalesced++;
 187                 rtc_coalesced_timer_update(s);
 188             }
 189         } else
 190 #endif
 191         rtc_irq_raise(s->irq);
 192     }
 193     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 194         /* Not square wave at all but we don't want 2048Hz interrupts!
 195            Must be seen as a pulse.  */
 196         qemu_irq_raise(s->sqw_irq);
 197     }
 198 }
 199
 200 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 201 {
 202     RTCState *s = opaque;
 203
 204     if ((addr & 1) == 0) {
 205         s->cmos_index = data & 0x7f;
 206     } else {
 207 #ifdef DEBUG_CMOS
 208         printf("cmos: write index=0x%02x val=0x%02x\n",
 209                s->cmos_index, data);
 210 #endif
 211         switch(s->cmos_index) {
 212         case RTC_SECONDS_ALARM:
 213         case RTC_MINUTES_ALARM:
 214         case RTC_HOURS_ALARM:
 215             /* XXX: not supported */
 216             s->cmos_data[s->cmos_index] = data;
 217             break;
 218         case RTC_SECONDS:
 219         case RTC_MINUTES:
 220         case RTC_HOURS:
 221         case RTC_DAY_OF_WEEK:
 222         case RTC_DAY_OF_MONTH:
 223         case RTC_MONTH:
 224         case RTC_YEAR:
 225             s->cmos_data[s->cmos_index] = data;
 226             /* if in set mode, do not update the time */
 227             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 228                 rtc_set_time(s);
 229             }
 230             break;
 231         case RTC_REG_A:
 232             /* UIP bit is read only */
 233             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 234                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 235             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 236             break;
 237         case RTC_REG_B:
 238             if (data & REG_B_SET) {
 239                 /* set mode: reset UIP mode */
 240                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 241                 data &= ~REG_B_UIE;
 242             } else {
 243                 /* if disabling set mode, update the time */
 244                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 245                     rtc_set_time(s);
 246                 }
 247             }
 248             s->cmos_data[RTC_REG_B] = data;
 249             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 250             break;
 251         case RTC_REG_C:
 252         case RTC_REG_D:
 253             /* cannot write to them */
 254             break;
 255         default:
 256             s->cmos_data[s->cmos_index] = data;
 257             break;
 258         }
 259     }
 260 }
 261
 262 static inline int rtc_to_bcd(RTCState *s, int a)
 263 {
 264     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 265         return a;
 266     } else {
 267         return ((a / 10) << 4) | (a % 10);
 268     }
 269 }
 270
 271 static inline int rtc_from_bcd(RTCState *s, int a)
 272 {
 273     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 274         return a;
 275     } else {
 276         return ((a >> 4) * 10) + (a & 0x0f);
 277     }
 278 }
 279
 280 static void rtc_set_time(RTCState *s)
 281 {
 282     struct tm *tm = &s->current_tm;
 283
 284     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 285     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 286     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 287     if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
 288         (s->cmos_data[RTC_HOURS] & 0x80)) {
 289         tm->tm_hour += 12;
 290     }
 291     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 292     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 293     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 294     tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 295 }
 296
 297 static void rtc_copy_date(RTCState *s)
 298 {
 299     const struct tm *tm = &s->current_tm;
 300     int year;
 301
 302     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 303     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 304     if (s->cmos_data[RTC_REG_B] & 0x02) {
 305         /* 24 hour format */
 306         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 307     } else {
 308         /* 12 hour format */
 309         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
 310         if (tm->tm_hour >= 12)
 311             s->cmos_data[RTC_HOURS] |= 0x80;
 312     }
 313     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 314     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 315     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 316     year = (tm->tm_year - s->base_year) % 100;
 317     if (year < 0)
 318         year += 100;
 319     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
 320 }
 321
 322 /* month is between 0 and 11. */
 323 static int get_days_in_month(int month, int year)
 324 {
 325     static const int days_tab[12] = {
 326         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 327     };
 328     int d;
 329     if ((unsigned )month >= 12)
 330         return 31;
 331     d = days_tab[month];
 332     if (month == 1) {
 333         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 334             d++;
 335     }
 336     return d;
 337 }
 338
 339 /* update 'tm' to the next second */
 340 static void rtc_next_second(struct tm *tm)
 341 {
 342     int days_in_month;
 343
 344     tm->tm_sec++;
 345     if ((unsigned)tm->tm_sec >= 60) {
 346         tm->tm_sec = 0;
 347         tm->tm_min++;
 348         if ((unsigned)tm->tm_min >= 60) {
 349             tm->tm_min = 0;
 350             tm->tm_hour++;
 351             if ((unsigned)tm->tm_hour >= 24) {
 352                 tm->tm_hour = 0;
 353                 /* next day */
 354                 tm->tm_wday++;
 355                 if ((unsigned)tm->tm_wday >= 7)
 356                     tm->tm_wday = 0;
 357                 days_in_month = get_days_in_month(tm->tm_mon,
 358                                                   tm->tm_year + 1900);
 359                 tm->tm_mday++;
 360                 if (tm->tm_mday < 1) {
 361                     tm->tm_mday = 1;
 362                 } else if (tm->tm_mday > days_in_month) {
 363                     tm->tm_mday = 1;
 364                     tm->tm_mon++;
 365                     if (tm->tm_mon >= 12) {
 366                         tm->tm_mon = 0;
 367                         tm->tm_year++;
 368                     }
 369                 }
 370             }
 371         }
 372     }
 373 }
 374
 375
 376 static void rtc_update_second(void *opaque)
 377 {
 378     RTCState *s = opaque;
 379     int64_t delay;
 380
 381     /* if the oscillator is not in normal operation, we do not update */
 382     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 383         s->next_second_time += get_ticks_per_sec();
 384         qemu_mod_timer(s->second_timer, s->next_second_time);
 385     } else {
 386         rtc_next_second(&s->current_tm);
 387
 388         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 389             /* update in progress bit */
 390             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 391         }
 392         /* should be 244 us = 8 / 32768 seconds, but currently the
 393            timers do not have the necessary resolution. */
 394         delay = (get_ticks_per_sec() * 1) / 100;
 395         if (delay < 1)
 396             delay = 1;
 397         qemu_mod_timer(s->second_timer2,
 398                        s->next_second_time + delay);
 399     }
 400 }
 401
 402 static void rtc_update_second2(void *opaque)
 403 {
 404     RTCState *s = opaque;
 405
 406     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 407         rtc_copy_date(s);
 408     }
 409
 410     /* check alarm */
 411     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 412         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 413              s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
 414             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 415              s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
 416             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 417              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 418
 419             s->cmos_data[RTC_REG_C] |= 0xa0;
 420             rtc_irq_raise(s->irq);
 421         }
 422     }
 423
 424     /* update ended interrupt */
 425     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 426     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 427       s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 428       rtc_irq_raise(s->irq);
 429     }
 430
 431     /* clear update in progress bit */
 432     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 433
 434     s->next_second_time += get_ticks_per_sec();
 435     qemu_mod_timer(s->second_timer, s->next_second_time);
 436 }
 437
 438 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 439 {
 440     RTCState *s = opaque;
 441     int ret;
 442     if ((addr & 1) == 0) {
 443         return 0xff;
 444     } else {
 445         switch(s->cmos_index) {
 446         case RTC_SECONDS:
 447         case RTC_MINUTES:
 448         case RTC_HOURS:
 449         case RTC_DAY_OF_WEEK:
 450         case RTC_DAY_OF_MONTH:
 451         case RTC_MONTH:
 452         case RTC_YEAR:
 453             ret = s->cmos_data[s->cmos_index];
 454             break;
 455         case RTC_REG_A:
 456             ret = s->cmos_data[s->cmos_index];
 457             break;
 458         case RTC_REG_C:
 459             ret = s->cmos_data[s->cmos_index];
 460             qemu_irq_lower(s->irq);
 461             s->cmos_data[RTC_REG_C] = 0x00;
 462             break;
 463         default:
 464             ret = s->cmos_data[s->cmos_index];
 465             break;
 466         }
 467 #ifdef DEBUG_CMOS
 468         printf("cmos: read index=0x%02x val=0x%02x\n",
 469                s->cmos_index, ret);
 470 #endif
 471         return ret;
 472     }
 473 }
 474
 475 void rtc_set_memory(RTCState *s, int addr, int val)
 476 {
 477     if (addr >= 0 && addr <= 127)
 478         s->cmos_data[addr] = val;
 479 }
 480
 481 void rtc_set_date(RTCState *s, const struct tm *tm)
 482 {
 483     s->current_tm = *tm;
 484     rtc_copy_date(s);
 485 }
 486
 487 /* PC cmos mappings */
 488 #define REG_IBM_CENTURY_BYTE        0x32
 489 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 490
 491 static void rtc_set_date_from_host(RTCState *s)
 492 {
 493     struct tm tm;
 494     int val;
 495
 496     /* set the CMOS date */
 497     qemu_get_timedate(&tm, 0);
 498     rtc_set_date(s, &tm);
 499
 500     val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
 501     rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
 502     rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
 503 }
 504
 505 static int rtc_post_load(void *opaque, int version_id)
 506 {
 507 #ifdef TARGET_I386
 508     RTCState *s = opaque;
 509
 510     if (version_id >= 2) {
 511         if (rtc_td_hack) {
 512             rtc_coalesced_timer_update(s);
 513         }
 514     }
 515 #endif
 516     return 0;
 517 }
 518
 519 static const VMStateDescription vmstate_rtc = {
 520     .name = "mc146818rtc",
 521     .version_id = 2,
 522     .minimum_version_id = 1,
 523     .minimum_version_id_old = 1,
 524     .post_load = rtc_post_load,
 525     .fields      = (VMStateField []) {
 526         VMSTATE_BUFFER(cmos_data, RTCState),
 527         VMSTATE_UINT8(cmos_index, RTCState),
 528         VMSTATE_INT32(current_tm.tm_sec, RTCState),
 529         VMSTATE_INT32(current_tm.tm_min, RTCState),
 530         VMSTATE_INT32(current_tm.tm_hour, RTCState),
 531         VMSTATE_INT32(current_tm.tm_wday, RTCState),
 532         VMSTATE_INT32(current_tm.tm_mday, RTCState),
 533         VMSTATE_INT32(current_tm.tm_mon, RTCState),
 534         VMSTATE_INT32(current_tm.tm_year, RTCState),
 535         VMSTATE_TIMER(periodic_timer, RTCState),
 536         VMSTATE_INT64(next_periodic_time, RTCState),
 537         VMSTATE_INT64(next_second_time, RTCState),
 538         VMSTATE_TIMER(second_timer, RTCState),
 539         VMSTATE_TIMER(second_timer2, RTCState),
 540         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 541         VMSTATE_UINT32_V(period, RTCState, 2),
 542         VMSTATE_END_OF_LIST()
 543     }
 544 };
 545
 546 static void rtc_reset(void *opaque)
 547 {
 548     RTCState *s = opaque;
 549
 550     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 551     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 552
 553     qemu_irq_lower(s->irq);
 554
 555 #ifdef TARGET_I386
 556     if (rtc_td_hack)
 557             s->irq_coalesced = 0;
 558 #endif
 559 }
 560
 561 static int rtc_initfn(ISADevice *dev)
 562 {
 563     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 564     int base = 0x70;
 565     int isairq = 8;
 566
 567     isa_init_irq(dev, &s->irq, isairq);
 568
 569     s->cmos_data[RTC_REG_A] = 0x26;
 570     s->cmos_data[RTC_REG_B] = 0x02;
 571     s->cmos_data[RTC_REG_C] = 0x00;
 572     s->cmos_data[RTC_REG_D] = 0x80;
 573
 574     rtc_set_date_from_host(s);
 575
 576     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 577 #ifdef TARGET_I386
 578     if (rtc_td_hack)
 579         s->coalesced_timer =
 580             qemu_new_timer(rtc_clock, rtc_coalesced_timer, s);
 581 #endif
 582     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 583     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 584
 585     s->next_second_time =
 586         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 587     qemu_mod_timer(s->second_timer2, s->next_second_time);
 588
 589     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 590     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 591
 592     vmstate_register(base, &vmstate_rtc, s);
 593     qemu_register_reset(rtc_reset, s);
 594     return 0;
 595 }
 596
 597 RTCState *rtc_init(int base_year)
 598 {
 599     ISADevice *dev;
 600
 601     dev = isa_create("mc146818rtc");
 602     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 603     qdev_init_nofail(&dev->qdev);
 604     return DO_UPCAST(RTCState, dev, dev);
 605 }
 606
 607 static ISADeviceInfo mc146818rtc_info = {
 608     .qdev.name     = "mc146818rtc",
 609     .qdev.size     = sizeof(RTCState),
 610     .qdev.no_user  = 1,
 611     .init          = rtc_initfn,
 612     .qdev.props    = (Property[]) {
 613         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 614         DEFINE_PROP_END_OF_LIST(),
 615     }
 616 };
 617
 618 static void mc146818rtc_register(void)
 619 {
 620     isa_qdev_register(&mc146818rtc_info);
 621 }
 622 device_init(mc146818rtc_register)