hw/pci-host/xilinx-pcie.c

   1 /*
   2  * Xilinx PCIe host controller emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/module.h"
  22 #include "qemu/units.h"
  23 #include "qapi/error.h"
  24 #include "hw/pci/pci_bridge.h"
  25 #include "hw/qdev-properties.h"
  26 #include "hw/irq.h"
  27 #include "hw/pci-host/xilinx-pcie.h"
  28
  29 enum root_cfg_reg {
  30     /* Interrupt Decode Register */
  31     ROOTCFG_INTDEC              = 0x138,
  32
  33     /* Interrupt Mask Register */
  34     ROOTCFG_INTMASK             = 0x13c,
  35     /* INTx Interrupt Received */
  36 #define ROOTCFG_INTMASK_INTX    (1 << 16)
  37     /* MSI Interrupt Received */
  38 #define ROOTCFG_INTMASK_MSI     (1 << 17)
  39
  40     /* PHY Status/Control Register */
  41     ROOTCFG_PSCR                = 0x144,
  42     /* Link Up */
  43 #define ROOTCFG_PSCR_LINK_UP    (1 << 11)
  44
  45     /* Root Port Status/Control Register */
  46     ROOTCFG_RPSCR               = 0x148,
  47     /* Bridge Enable */
  48 #define ROOTCFG_RPSCR_BRIDGEEN  (1 << 0)
  49     /* Interrupt FIFO Not Empty */
  50 #define ROOTCFG_RPSCR_INTNEMPTY (1 << 18)
  51     /* Interrupt FIFO Overflow */
  52 #define ROOTCFG_RPSCR_INTOVF    (1 << 19)
  53
  54     /* Root Port Interrupt FIFO Read Register 1 */
  55     ROOTCFG_RPIFR1              = 0x158,
  56 #define ROOTCFG_RPIFR1_INT_LANE_SHIFT   27
  57 #define ROOTCFG_RPIFR1_INT_ASSERT_SHIFT 29
  58 #define ROOTCFG_RPIFR1_INT_VALID_SHIFT  31
  59     /* Root Port Interrupt FIFO Read Register 2 */
  60     ROOTCFG_RPIFR2              = 0x15c,
  61 };
  62
  63 static void xilinx_pcie_update_intr(XilinxPCIEHost *s,
  64                                     uint32_t set, uint32_t clear)
  65 {
  66     int level;
  67
  68     s->intr |= set;
  69     s->intr &= ~clear;
  70
  71     if (s->intr_fifo_r != s->intr_fifo_w) {
  72         s->intr |= ROOTCFG_INTMASK_INTX;
  73     }
  74
  75     level = !!(s->intr & s->intr_mask);
  76     qemu_set_irq(s->irq, level);
  77 }
  78
  79 static void xilinx_pcie_queue_intr(XilinxPCIEHost *s,
  80                                    uint32_t fifo_reg1, uint32_t fifo_reg2)
  81 {
  82     XilinxPCIEInt *intr;
  83     unsigned int new_w;
  84
  85     new_w = (s->intr_fifo_w + 1) % ARRAY_SIZE(s->intr_fifo);
  86     if (new_w == s->intr_fifo_r) {
  87         s->rpscr |= ROOTCFG_RPSCR_INTOVF;
  88         return;
  89     }
  90
  91     intr = &s->intr_fifo[s->intr_fifo_w];
  92     s->intr_fifo_w = new_w;
  93
  94     intr->fifo_reg1 = fifo_reg1;
  95     intr->fifo_reg2 = fifo_reg2;
  96
  97     xilinx_pcie_update_intr(s, ROOTCFG_INTMASK_INTX, 0);
  98 }
  99
 100 static void xilinx_pcie_set_irq(void *opaque, int irq_num, int level)
 101 {
 102     XilinxPCIEHost *s = XILINX_PCIE_HOST(opaque);
 103
 104     xilinx_pcie_queue_intr(s,
 105        (irq_num << ROOTCFG_RPIFR1_INT_LANE_SHIFT) |
 106            (level << ROOTCFG_RPIFR1_INT_ASSERT_SHIFT) |
 107            (1 << ROOTCFG_RPIFR1_INT_VALID_SHIFT),
 108        0);
 109 }
 110
 111 static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp)
 112 {
 113     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
 114     XilinxPCIEHost *s = XILINX_PCIE_HOST(dev);
 115     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 116     PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
 117
 118     snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr);
 119
 120     /* PCI configuration space */
 121     pcie_host_mmcfg_init(pex, s->cfg_size);
 122
 123     /* MMIO region */
 124     memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX);
 125     memory_region_set_enabled(&s->mmio, false);
 126
 127     /* dummy PCI I/O region (not visible to the CPU) */
 128     memory_region_init(&s->io, OBJECT(s), "io", 16);
 129
 130     /* interrupt out */
 131     qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1);
 132
 133     sysbus_init_mmio(sbd, &pex->mmio);
 134     sysbus_init_mmio(sbd, &s->mmio);
 135
 136     pci->bus = pci_register_root_bus(dev, s->name, xilinx_pcie_set_irq,
 137                                      pci_swizzle_map_irq_fn, s, &s->mmio,
 138                                      &s->io, 0, 4, TYPE_PCIE_BUS);
 139
 140     qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal);
 141 }
 142
 143 static const char *xilinx_pcie_host_root_bus_path(PCIHostState *host_bridge,
 144                                                   PCIBus *rootbus)
 145 {
 146     return "0000:00";
 147 }
 148
 149 static void xilinx_pcie_host_init(Object *obj)
 150 {
 151     XilinxPCIEHost *s = XILINX_PCIE_HOST(obj);
 152     XilinxPCIERoot *root = &s->root;
 153
 154     object_initialize_child(obj, "root", root, TYPE_XILINX_PCIE_ROOT);
 155     qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
 156     qdev_prop_set_bit(DEVICE(root), "multifunction", false);
 157 }
 158
 159 static Property xilinx_pcie_host_props[] = {
 160     DEFINE_PROP_UINT32("bus_nr", XilinxPCIEHost, bus_nr, 0),
 161     DEFINE_PROP_SIZE("cfg_base", XilinxPCIEHost, cfg_base, 0),
 162     DEFINE_PROP_SIZE("cfg_size", XilinxPCIEHost, cfg_size, 32 * MiB),
 163     DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0),
 164     DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * MiB),
 165     DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true),
 166     DEFINE_PROP_END_OF_LIST(),
 167 };
 168
 169 static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data)
 170 {
 171     DeviceClass *dc = DEVICE_CLASS(klass);
 172     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 173
 174     hc->root_bus_path = xilinx_pcie_host_root_bus_path;
 175     dc->realize = xilinx_pcie_host_realize;
 176     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 177     dc->fw_name = "pci";
 178     device_class_set_props(dc, xilinx_pcie_host_props);
 179 }
 180
 181 static const TypeInfo xilinx_pcie_host_info = {
 182     .name       = TYPE_XILINX_PCIE_HOST,
 183     .parent     = TYPE_PCIE_HOST_BRIDGE,
 184     .instance_size = sizeof(XilinxPCIEHost),
 185     .instance_init = xilinx_pcie_host_init,
 186     .class_init = xilinx_pcie_host_class_init,
 187 };
 188
 189 static uint32_t xilinx_pcie_root_config_read(PCIDevice *d,
 190                                              uint32_t address, int len)
 191 {
 192     XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
 193     uint32_t val;
 194
 195     switch (address) {
 196     case ROOTCFG_INTDEC:
 197         val = s->intr;
 198         break;
 199     case ROOTCFG_INTMASK:
 200         val = s->intr_mask;
 201         break;
 202     case ROOTCFG_PSCR:
 203         val = s->link_up ? ROOTCFG_PSCR_LINK_UP : 0;
 204         break;
 205     case ROOTCFG_RPSCR:
 206         if (s->intr_fifo_r != s->intr_fifo_w) {
 207             s->rpscr &= ~ROOTCFG_RPSCR_INTNEMPTY;
 208         } else {
 209             s->rpscr |= ROOTCFG_RPSCR_INTNEMPTY;
 210         }
 211         val = s->rpscr;
 212         break;
 213     case ROOTCFG_RPIFR1:
 214         if (s->intr_fifo_w == s->intr_fifo_r) {
 215             /* FIFO empty */
 216             val = 0;
 217         } else {
 218             val = s->intr_fifo[s->intr_fifo_r].fifo_reg1;
 219         }
 220         break;
 221     case ROOTCFG_RPIFR2:
 222         if (s->intr_fifo_w == s->intr_fifo_r) {
 223             /* FIFO empty */
 224             val = 0;
 225         } else {
 226             val = s->intr_fifo[s->intr_fifo_r].fifo_reg2;
 227         }
 228         break;
 229     default:
 230         val = pci_default_read_config(d, address, len);
 231         break;
 232     }
 233     return val;
 234 }
 235
 236 static void xilinx_pcie_root_config_write(PCIDevice *d, uint32_t address,
 237                                           uint32_t val, int len)
 238 {
 239     XilinxPCIEHost *s = XILINX_PCIE_HOST(OBJECT(d)->parent);
 240     switch (address) {
 241     case ROOTCFG_INTDEC:
 242         xilinx_pcie_update_intr(s, 0, val);
 243         break;
 244     case ROOTCFG_INTMASK:
 245         s->intr_mask = val;
 246         xilinx_pcie_update_intr(s, 0, 0);
 247         break;
 248     case ROOTCFG_RPSCR:
 249         s->rpscr &= ~ROOTCFG_RPSCR_BRIDGEEN;
 250         s->rpscr |= val & ROOTCFG_RPSCR_BRIDGEEN;
 251         memory_region_set_enabled(&s->mmio, val & ROOTCFG_RPSCR_BRIDGEEN);
 252
 253         if (val & ROOTCFG_INTMASK_INTX) {
 254             s->rpscr &= ~ROOTCFG_INTMASK_INTX;
 255         }
 256         break;
 257     case ROOTCFG_RPIFR1:
 258     case ROOTCFG_RPIFR2:
 259         if (s->intr_fifo_w == s->intr_fifo_r) {
 260             /* FIFO empty */
 261             return;
 262         } else {
 263             s->intr_fifo_r = (s->intr_fifo_r + 1) % ARRAY_SIZE(s->intr_fifo);
 264         }
 265         break;
 266     default:
 267         pci_default_write_config(d, address, val, len);
 268         break;
 269     }
 270 }
 271
 272 static void xilinx_pcie_root_realize(PCIDevice *pci_dev, Error **errp)
 273 {
 274     BusState *bus = qdev_get_parent_bus(DEVICE(pci_dev));
 275     XilinxPCIEHost *s = XILINX_PCIE_HOST(bus->parent);
 276
 277     pci_set_word(pci_dev->config + PCI_COMMAND,
 278                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 279     pci_set_word(pci_dev->config + PCI_MEMORY_BASE, s->mmio_base >> 16);
 280     pci_set_word(pci_dev->config + PCI_MEMORY_LIMIT,
 281                  ((s->mmio_base + s->mmio_size - 1) >> 16) & 0xfff0);
 282
 283     pci_bridge_initfn(pci_dev, TYPE_PCI_BUS);
 284
 285     if (pcie_endpoint_cap_v1_init(pci_dev, 0x80) < 0) {
 286         error_setg(errp, "Failed to initialize PCIe capability");
 287     }
 288 }
 289
 290 static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data)
 291 {
 292     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 293     DeviceClass *dc = DEVICE_CLASS(klass);
 294
 295     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 296     dc->desc = "Xilinx AXI-PCIe Host Bridge";
 297     k->vendor_id = PCI_VENDOR_ID_XILINX;
 298     k->device_id = 0x7021;
 299     k->revision = 0;
 300     k->class_id = PCI_CLASS_BRIDGE_HOST;
 301     k->is_bridge = true;
 302     k->realize = xilinx_pcie_root_realize;
 303     k->exit = pci_bridge_exitfn;
 304     dc->reset = pci_bridge_reset;
 305     k->config_read = xilinx_pcie_root_config_read;
 306     k->config_write = xilinx_pcie_root_config_write;
 307     /*
 308      * PCI-facing part of the host bridge, not usable without the
 309      * host-facing part, which can't be device_add'ed, yet.
 310      */
 311     dc->user_creatable = false;
 312 }
 313
 314 static const TypeInfo xilinx_pcie_root_info = {
 315     .name = TYPE_XILINX_PCIE_ROOT,
 316     .parent = TYPE_PCI_BRIDGE,
 317     .instance_size = sizeof(XilinxPCIERoot),
 318     .class_init = xilinx_pcie_root_class_init,
 319     .interfaces = (InterfaceInfo[]) {
 320         { INTERFACE_PCIE_DEVICE },
 321         { }
 322     },
 323 };
 324
 325 static void xilinx_pcie_register(void)
 326 {
 327     type_register_static(&xilinx_pcie_root_info);
 328     type_register_static(&xilinx_pcie_host_info);
 329 }
 330
 331 type_init(xilinx_pcie_register)