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Merge tag 'pull-arm-20220914' of https://gitlab.com/rth7680/qemu into staging
[qemu.git] / hw / ppc / pnv.c
blob354aa289d18cebfd511ce5cbda34f92a47c43b28
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
39 #include "hw/nmi.h"
40 #include "qapi/visitor.h"
41 #include "monitor/monitor.h"
42 #include "hw/intc/intc.h"
43 #include "hw/ipmi/ipmi.h"
44 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci-host/pnv_phb.h"
47
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
52
53 #include "hw/isa/isa.h"
54 #include "hw/char/serial.h"
55 #include "hw/rtc/mc146818rtc.h"
56
57 #include <libfdt.h>
58
59 #define FDT_MAX_SIZE (1 * MiB)
60
61 #define FW_FILE_NAME "skiboot.lid"
62 #define FW_LOAD_ADDR 0x0
63 #define FW_MAX_SIZE (16 * MiB)
64
65 #define KERNEL_LOAD_ADDR 0x20000000
66 #define KERNEL_MAX_SIZE (128 * MiB)
67 #define INITRD_LOAD_ADDR 0x28000000
68 #define INITRD_MAX_SIZE (128 * MiB)
69
70 static const char *pnv_chip_core_typename(const PnvChip *o)
71 {
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78 }
79
80 /*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85 #define MAX_CPUS 2048
86
87 /*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
93 {
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109 }
110
111 static int get_cpus_node(void *fdt)
112 {
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124 }
125
126 /*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
134 {
135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
138 int smt_threads = CPU_CORE(pc)->nr_threads;
139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
183 warn_report("Unknown L1 dcache size for cpu");
184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
189 warn_report("Unknown L1 icache size for cpu");
190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (ppc_has_spr(cpu, SPR_PURR)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
208 /*
209 * Advertise VMX/VSX (vector extensions) if available
210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
212 * 2 == VSX available
213 */
214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
220 /*
221 * Advertise DFP (Decimal Floating Point) if available
222 * 0 / no property == no DFP
223 * 1 == DFP available
224 */
225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245 }
246
247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
249 {
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282 }
283
284 static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
285 Error **errp)
286 {
287 PnvPHB *phb_base = phb->phb_base;
288 PnvPhb4PecState *pecs = NULL;
289 int chip_id = phb->chip_id;
290 int index = phb->phb_id;
291 int i, j;
292
293 if (phb_base->version == 4) {
294 Pnv9Chip *chip9 = PNV9_CHIP(chip);
295
296 pecs = chip9->pecs;
297 } else if (phb_base->version == 5) {
298 Pnv10Chip *chip10 = PNV10_CHIP(chip);
299
300 pecs = chip10->pecs;
301 } else {
302 g_assert_not_reached();
303 }
304
305 for (i = 0; i < chip->num_pecs; i++) {
306 /*
307 * For each PEC, check the amount of phbs it supports
308 * and see if the given phb4 index matches an index.
309 */
310 PnvPhb4PecState *pec = &pecs[i];
311
312 for (j = 0; j < pec->num_phbs; j++) {
313 if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
314 return pec;
315 }
316 }
317 }
318 error_setg(errp,
319 "pnv-phb4 chip-id %d index %d didn't match any existing PEC",
320 chip_id, index);
321
322 return NULL;
323 }
324
325 /*
326 * Adds a PnvPHB to the chip. Returns the parent obj of the
327 * PHB which varies with each version (phb version 3 is parented
328 * by the chip, version 4 and 5 are parented by the PEC
329 * device).
330 *
331 * TODO: for version 3 we're still parenting the PHB with the
332 * chip. We should parent with a (so far not implemented)
333 * PHB3 PEC device.
334 */
335 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
336 {
337 if (phb->version == 3) {
338 Pnv8Chip *chip8 = PNV8_CHIP(chip);
339
340 phb->chip = chip;
341
342 chip8->phbs[chip8->num_phbs] = phb;
343 chip8->num_phbs++;
344
345 return OBJECT(chip);
346 }
347
348 phb->pec = pnv_phb4_get_pec(chip, PNV_PHB4(phb->backend), errp);
349
350 return OBJECT(phb->pec);
351 }
352
353 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
354 {
355 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
356 int i;
357
358 pnv_dt_xscom(chip, fdt, 0,
359 cpu_to_be64(PNV_XSCOM_BASE(chip)),
360 cpu_to_be64(PNV_XSCOM_SIZE),
361 compat, sizeof(compat));
362
363 for (i = 0; i < chip->nr_cores; i++) {
364 PnvCore *pnv_core = chip->cores[i];
365
366 pnv_dt_core(chip, pnv_core, fdt);
367
368 /* Interrupt Control Presenters (ICP). One per core. */
369 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
370 }
371
372 if (chip->ram_size) {
373 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
374 }
375 }
376
377 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
378 {
379 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
380 int i;
381
382 pnv_dt_xscom(chip, fdt, 0,
383 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
384 cpu_to_be64(PNV9_XSCOM_SIZE),
385 compat, sizeof(compat));
386
387 for (i = 0; i < chip->nr_cores; i++) {
388 PnvCore *pnv_core = chip->cores[i];
389
390 pnv_dt_core(chip, pnv_core, fdt);
391 }
392
393 if (chip->ram_size) {
394 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
395 }
396
397 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
398 }
399
400 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
401 {
402 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
403 int i;
404
405 pnv_dt_xscom(chip, fdt, 0,
406 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
407 cpu_to_be64(PNV10_XSCOM_SIZE),
408 compat, sizeof(compat));
409
410 for (i = 0; i < chip->nr_cores; i++) {
411 PnvCore *pnv_core = chip->cores[i];
412
413 pnv_dt_core(chip, pnv_core, fdt);
414 }
415
416 if (chip->ram_size) {
417 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
418 }
419
420 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
421 }
422
423 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
424 {
425 uint32_t io_base = d->ioport_id;
426 uint32_t io_regs[] = {
427 cpu_to_be32(1),
428 cpu_to_be32(io_base),
429 cpu_to_be32(2)
430 };
431 char *name;
432 int node;
433
434 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
435 node = fdt_add_subnode(fdt, lpc_off, name);
436 _FDT(node);
437 g_free(name);
438
439 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
440 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
441 }
442
443 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
444 {
445 const char compatible[] = "ns16550\0pnpPNP,501";
446 uint32_t io_base = d->ioport_id;
447 uint32_t io_regs[] = {
448 cpu_to_be32(1),
449 cpu_to_be32(io_base),
450 cpu_to_be32(8)
451 };
452 uint32_t irq;
453 char *name;
454 int node;
455
456 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
457
458 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
459 node = fdt_add_subnode(fdt, lpc_off, name);
460 _FDT(node);
461 g_free(name);
462
463 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
464 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
465 sizeof(compatible))));
466
467 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
468 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
469 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
470 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
471 fdt_get_phandle(fdt, lpc_off))));
472
473 /* This is needed by Linux */
474 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
475 }
476
477 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
478 {
479 const char compatible[] = "bt\0ipmi-bt";
480 uint32_t io_base;
481 uint32_t io_regs[] = {
482 cpu_to_be32(1),
483 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
484 cpu_to_be32(3)
485 };
486 uint32_t irq;
487 char *name;
488 int node;
489
490 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
491 io_regs[1] = cpu_to_be32(io_base);
492
493 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
494
495 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
496 node = fdt_add_subnode(fdt, lpc_off, name);
497 _FDT(node);
498 g_free(name);
499
500 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
501 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
502 sizeof(compatible))));
503
504 /* Mark it as reserved to avoid Linux trying to claim it */
505 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
506 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
507 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
508 fdt_get_phandle(fdt, lpc_off))));
509 }
510
511 typedef struct ForeachPopulateArgs {
512 void *fdt;
513 int offset;
514 } ForeachPopulateArgs;
515
516 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
517 {
518 ForeachPopulateArgs *args = opaque;
519 ISADevice *d = ISA_DEVICE(dev);
520
521 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
522 pnv_dt_rtc(d, args->fdt, args->offset);
523 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
524 pnv_dt_serial(d, args->fdt, args->offset);
525 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
526 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
527 } else {
528 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
529 d->ioport_id);
530 }
531
532 return 0;
533 }
534
535 /*
536 * The default LPC bus of a multichip system is on chip 0. It's
537 * recognized by the firmware (skiboot) using a "primary" property.
538 */
539 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
540 {
541 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
542 ForeachPopulateArgs args = {
543 .fdt = fdt,
544 .offset = isa_offset,
545 };
546 uint32_t phandle;
547
548 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
549
550 phandle = qemu_fdt_alloc_phandle(fdt);
551 assert(phandle > 0);
552 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
553
554 /*
555 * ISA devices are not necessarily parented to the ISA bus so we
556 * can not use object_child_foreach()
557 */
558 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
559 &args);
560 }
561
562 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
563 {
564 int off;
565
566 off = fdt_add_subnode(fdt, 0, "ibm,opal");
567 off = fdt_add_subnode(fdt, off, "power-mgt");
568
569 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
570 }
571
572 static void *pnv_dt_create(MachineState *machine)
573 {
574 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
575 PnvMachineState *pnv = PNV_MACHINE(machine);
576 void *fdt;
577 char *buf;
578 int off;
579 int i;
580
581 fdt = g_malloc0(FDT_MAX_SIZE);
582 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
583
584 /* /qemu node */
585 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
586
587 /* Root node */
588 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
589 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
590 _FDT((fdt_setprop_string(fdt, 0, "model",
591 "IBM PowerNV (emulated by qemu)")));
592 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
593
594 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
595 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
596 if (qemu_uuid_set) {
597 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
598 }
599 g_free(buf);
600
601 off = fdt_add_subnode(fdt, 0, "chosen");
602 if (machine->kernel_cmdline) {
603 _FDT((fdt_setprop_string(fdt, off, "bootargs",
604 machine->kernel_cmdline)));
605 }
606
607 if (pnv->initrd_size) {
608 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
609 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
610
611 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
612 &start_prop, sizeof(start_prop))));
613 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
614 &end_prop, sizeof(end_prop))));
615 }
616
617 /* Populate device tree for each chip */
618 for (i = 0; i < pnv->num_chips; i++) {
619 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
620 }
621
622 /* Populate ISA devices on chip 0 */
623 pnv_dt_isa(pnv, fdt);
624
625 if (pnv->bmc) {
626 pnv_dt_bmc_sensors(pnv->bmc, fdt);
627 }
628
629 /* Create an extra node for power management on machines that support it */
630 if (pmc->dt_power_mgt) {
631 pmc->dt_power_mgt(pnv, fdt);
632 }
633
634 return fdt;
635 }
636
637 static void pnv_powerdown_notify(Notifier *n, void *opaque)
638 {
639 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
640
641 if (pnv->bmc) {
642 pnv_bmc_powerdown(pnv->bmc);
643 }
644 }
645
646 static void pnv_reset(MachineState *machine)
647 {
648 PnvMachineState *pnv = PNV_MACHINE(machine);
649 IPMIBmc *bmc;
650 void *fdt;
651
652 qemu_devices_reset();
653
654 /*
655 * The machine should provide by default an internal BMC simulator.
656 * If not, try to use the BMC device that was provided on the command
657 * line.
658 */
659 bmc = pnv_bmc_find(&error_fatal);
660 if (!pnv->bmc) {
661 if (!bmc) {
662 if (!qtest_enabled()) {
663 warn_report("machine has no BMC device. Use '-device "
664 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
665 "to define one");
666 }
667 } else {
668 pnv_bmc_set_pnor(bmc, pnv->pnor);
669 pnv->bmc = bmc;
670 }
671 }
672
673 fdt = pnv_dt_create(machine);
674
675 /* Pack resulting tree */
676 _FDT((fdt_pack(fdt)));
677
678 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
679 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
680
681 g_free(fdt);
682 }
683
684 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
685 {
686 Pnv8Chip *chip8 = PNV8_CHIP(chip);
687 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
688
689 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
690 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
691 }
692
693 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
694 {
695 Pnv8Chip *chip8 = PNV8_CHIP(chip);
696 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
697
698 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
699 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
700 }
701
702 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
703 {
704 Pnv9Chip *chip9 = PNV9_CHIP(chip);
705 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
706
707 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
708 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
709 }
710
711 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
712 {
713 Pnv10Chip *chip10 = PNV10_CHIP(chip);
714 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
715
716 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
717 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
718 }
719
720 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
721 {
722 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
723 }
724
725 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
726 {
727 Pnv8Chip *chip8 = PNV8_CHIP(chip);
728 int i;
729
730 ics_pic_print_info(&chip8->psi.ics, mon);
731
732 for (i = 0; i < chip8->num_phbs; i++) {
733 PnvPHB *phb = chip8->phbs[i];
734 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
735
736 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
737 ics_pic_print_info(&phb3->lsis, mon);
738 }
739 }
740
741 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
742 {
743 Monitor *mon = opaque;
744 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
745
746 if (!phb) {
747 return 0;
748 }
749
750 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
751
752 return 0;
753 }
754
755 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
756 {
757 Pnv9Chip *chip9 = PNV9_CHIP(chip);
758
759 pnv_xive_pic_print_info(&chip9->xive, mon);
760 pnv_psi_pic_print_info(&chip9->psi, mon);
761
762 object_child_foreach_recursive(OBJECT(chip),
763 pnv_chip_power9_pic_print_info_child, mon);
764 }
765
766 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
767 uint32_t core_id)
768 {
769 return PNV_XSCOM_EX_BASE(core_id);
770 }
771
772 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
773 uint32_t core_id)
774 {
775 return PNV9_XSCOM_EC_BASE(core_id);
776 }
777
778 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
779 uint32_t core_id)
780 {
781 return PNV10_XSCOM_EC_BASE(core_id);
782 }
783
784 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
785 {
786 PowerPCCPUClass *ppc_default =
787 POWERPC_CPU_CLASS(object_class_by_name(default_type));
788 PowerPCCPUClass *ppc =
789 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
790
791 return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
792 }
793
794 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
795 {
796 ISADevice *dev = isa_new("isa-ipmi-bt");
797
798 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
799 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
800 isa_realize_and_unref(dev, bus, &error_fatal);
801 }
802
803 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
804 {
805 Pnv10Chip *chip10 = PNV10_CHIP(chip);
806
807 pnv_xive2_pic_print_info(&chip10->xive, mon);
808 pnv_psi_pic_print_info(&chip10->psi, mon);
809
810 object_child_foreach_recursive(OBJECT(chip),
811 pnv_chip_power9_pic_print_info_child, mon);
812 }
813
814 /* Always give the first 1GB to chip 0 else we won't boot */
815 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
816 {
817 MachineState *machine = MACHINE(pnv);
818 uint64_t ram_per_chip;
819
820 assert(machine->ram_size >= 1 * GiB);
821
822 ram_per_chip = machine->ram_size / pnv->num_chips;
823 if (ram_per_chip >= 1 * GiB) {
824 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
825 }
826
827 assert(pnv->num_chips > 1);
828
829 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
830 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
831 }
832
833 static void pnv_init(MachineState *machine)
834 {
835 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
836 PnvMachineState *pnv = PNV_MACHINE(machine);
837 MachineClass *mc = MACHINE_GET_CLASS(machine);
838 char *fw_filename;
839 long fw_size;
840 uint64_t chip_ram_start = 0;
841 int i;
842 char *chip_typename;
843 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
844 DeviceState *dev;
845
846 if (kvm_enabled()) {
847 error_report("The powernv machine does not work with KVM acceleration");
848 exit(EXIT_FAILURE);
849 }
850
851 /* allocate RAM */
852 if (machine->ram_size < mc->default_ram_size) {
853 char *sz = size_to_str(mc->default_ram_size);
854 error_report("Invalid RAM size, should be bigger than %s", sz);
855 g_free(sz);
856 exit(EXIT_FAILURE);
857 }
858 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
859
860 /*
861 * Create our simple PNOR device
862 */
863 dev = qdev_new(TYPE_PNV_PNOR);
864 if (pnor) {
865 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
866 }
867 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
868 pnv->pnor = PNV_PNOR(dev);
869
870 /* load skiboot firmware */
871 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
872 if (!fw_filename) {
873 error_report("Could not find OPAL firmware '%s'", bios_name);
874 exit(1);
875 }
876
877 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
878 if (fw_size < 0) {
879 error_report("Could not load OPAL firmware '%s'", fw_filename);
880 exit(1);
881 }
882 g_free(fw_filename);
883
884 /* load kernel */
885 if (machine->kernel_filename) {
886 long kernel_size;
887
888 kernel_size = load_image_targphys(machine->kernel_filename,
889 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
890 if (kernel_size < 0) {
891 error_report("Could not load kernel '%s'",
892 machine->kernel_filename);
893 exit(1);
894 }
895 }
896
897 /* load initrd */
898 if (machine->initrd_filename) {
899 pnv->initrd_base = INITRD_LOAD_ADDR;
900 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
901 pnv->initrd_base, INITRD_MAX_SIZE);
902 if (pnv->initrd_size < 0) {
903 error_report("Could not load initial ram disk '%s'",
904 machine->initrd_filename);
905 exit(1);
906 }
907 }
908
909 /* MSIs are supported on this platform */
910 msi_nonbroken = true;
911
912 /*
913 * Check compatibility of the specified CPU with the machine
914 * default.
915 */
916 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
917 error_report("invalid CPU model '%s' for %s machine",
918 machine->cpu_type, mc->name);
919 exit(1);
920 }
921
922 /* Create the processor chips */
923 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
924 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
925 i, machine->cpu_type);
926 if (!object_class_by_name(chip_typename)) {
927 error_report("invalid chip model '%.*s' for %s machine",
928 i, machine->cpu_type, mc->name);
929 exit(1);
930 }
931
932 pnv->num_chips =
933 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
934 /*
935 * TODO: should we decide on how many chips we can create based
936 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
937 */
938 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
939 error_report("invalid number of chips: '%d'", pnv->num_chips);
940 error_printf(
941 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
942 exit(1);
943 }
944
945 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
946 for (i = 0; i < pnv->num_chips; i++) {
947 char chip_name[32];
948 Object *chip = OBJECT(qdev_new(chip_typename));
949 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
950
951 pnv->chips[i] = PNV_CHIP(chip);
952
953 /* Distribute RAM among the chips */
954 object_property_set_int(chip, "ram-start", chip_ram_start,
955 &error_fatal);
956 object_property_set_int(chip, "ram-size", chip_ram_size,
957 &error_fatal);
958 chip_ram_start += chip_ram_size;
959
960 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
961 object_property_add_child(OBJECT(pnv), chip_name, chip);
962 object_property_set_int(chip, "chip-id", i, &error_fatal);
963 object_property_set_int(chip, "nr-cores", machine->smp.cores,
964 &error_fatal);
965 object_property_set_int(chip, "nr-threads", machine->smp.threads,
966 &error_fatal);
967 /*
968 * The POWER8 machine use the XICS interrupt interface.
969 * Propagate the XICS fabric to the chip and its controllers.
970 */
971 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
972 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
973 }
974 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
975 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
976 &error_abort);
977 }
978 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
979 }
980 g_free(chip_typename);
981
982 /* Instantiate ISA bus on chip 0 */
983 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
984
985 /* Create serial port */
986 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
987
988 /* Create an RTC ISA device too */
989 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
990
991 /*
992 * Create the machine BMC simulator and the IPMI BT device for
993 * communication with the BMC
994 */
995 if (defaults_enabled()) {
996 pnv->bmc = pnv_bmc_create(pnv->pnor);
997 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
998 }
999
1000 /*
1001 * The PNOR is mapped on the LPC FW address space by the BMC.
1002 * Since we can not reach the remote BMC machine with LPC memops,
1003 * map it always for now.
1004 */
1005 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
1006 &pnv->pnor->mmio);
1007
1008 /*
1009 * OpenPOWER systems use a IPMI SEL Event message to notify the
1010 * host to powerdown
1011 */
1012 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
1013 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
1014 }
1015
1016 /*
1017 * 0:21 Reserved - Read as zeros
1018 * 22:24 Chip ID
1019 * 25:28 Core number
1020 * 29:31 Thread ID
1021 */
1022 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
1023 {
1024 return (chip->chip_id << 7) | (core_id << 3);
1025 }
1026
1027 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1028 Error **errp)
1029 {
1030 Pnv8Chip *chip8 = PNV8_CHIP(chip);
1031 Error *local_err = NULL;
1032 Object *obj;
1033 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1034
1035 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
1036 if (local_err) {
1037 error_propagate(errp, local_err);
1038 return;
1039 }
1040
1041 pnv_cpu->intc = obj;
1042 }
1043
1044
1045 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1046 {
1047 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1048
1049 icp_reset(ICP(pnv_cpu->intc));
1050 }
1051
1052 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1053 {
1054 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1055
1056 icp_destroy(ICP(pnv_cpu->intc));
1057 pnv_cpu->intc = NULL;
1058 }
1059
1060 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1061 Monitor *mon)
1062 {
1063 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1064 }
1065
1066 /*
1067 * 0:48 Reserved - Read as zeroes
1068 * 49:52 Node ID
1069 * 53:55 Chip ID
1070 * 56 Reserved - Read as zero
1071 * 57:61 Core number
1072 * 62:63 Thread ID
1073 *
1074 * We only care about the lower bits. uint32_t is fine for the moment.
1075 */
1076 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
1077 {
1078 return (chip->chip_id << 8) | (core_id << 2);
1079 }
1080
1081 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
1082 {
1083 return (chip->chip_id << 8) | (core_id << 2);
1084 }
1085
1086 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1087 Error **errp)
1088 {
1089 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1090 Error *local_err = NULL;
1091 Object *obj;
1092 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1093
1094 /*
1095 * The core creates its interrupt presenter but the XIVE interrupt
1096 * controller object is initialized afterwards. Hopefully, it's
1097 * only used at runtime.
1098 */
1099 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1100 &local_err);
1101 if (local_err) {
1102 error_propagate(errp, local_err);
1103 return;
1104 }
1105
1106 pnv_cpu->intc = obj;
1107 }
1108
1109 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1110 {
1111 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1112
1113 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1114 }
1115
1116 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1117 {
1118 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1119
1120 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1121 pnv_cpu->intc = NULL;
1122 }
1123
1124 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1125 Monitor *mon)
1126 {
1127 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1128 }
1129
1130 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1131 Error **errp)
1132 {
1133 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1134 Error *local_err = NULL;
1135 Object *obj;
1136 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1137
1138 /*
1139 * The core creates its interrupt presenter but the XIVE2 interrupt
1140 * controller object is initialized afterwards. Hopefully, it's
1141 * only used at runtime.
1142 */
1143 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1144 &local_err);
1145 if (local_err) {
1146 error_propagate(errp, local_err);
1147 return;
1148 }
1149
1150 pnv_cpu->intc = obj;
1151 }
1152
1153 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1154 {
1155 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1156
1157 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1158 }
1159
1160 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1161 {
1162 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1163
1164 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1165 pnv_cpu->intc = NULL;
1166 }
1167
1168 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1169 Monitor *mon)
1170 {
1171 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1172 }
1173
1174 /*
1175 * Allowed core identifiers on a POWER8 Processor Chip :
1176 *
1177 * <EX0 reserved>
1178 * EX1 - Venice only
1179 * EX2 - Venice only
1180 * EX3 - Venice only
1181 * EX4
1182 * EX5
1183 * EX6
1184 * <EX7,8 reserved> <reserved>
1185 * EX9 - Venice only
1186 * EX10 - Venice only
1187 * EX11 - Venice only
1188 * EX12
1189 * EX13
1190 * EX14
1191 * <EX15 reserved>
1192 */
1193 #define POWER8E_CORE_MASK (0x7070ull)
1194 #define POWER8_CORE_MASK (0x7e7eull)
1195
1196 /*
1197 * POWER9 has 24 cores, ids starting at 0x0
1198 */
1199 #define POWER9_CORE_MASK (0xffffffffffffffull)
1200
1201
1202 #define POWER10_CORE_MASK (0xffffffffffffffull)
1203
1204 static void pnv_chip_power8_instance_init(Object *obj)
1205 {
1206 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1207 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1208 int i;
1209
1210 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1211 (Object **)&chip8->xics,
1212 object_property_allow_set_link,
1213 OBJ_PROP_LINK_STRONG);
1214
1215 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1216
1217 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1218
1219 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1220
1221 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1222
1223 if (defaults_enabled()) {
1224 chip8->num_phbs = pcc->num_phbs;
1225
1226 for (i = 0; i < chip8->num_phbs; i++) {
1227 Object *phb = object_new(TYPE_PNV_PHB);
1228
1229 /*
1230 * We need the chip to parent the PHB to allow the DT
1231 * to build correctly (via pnv_xscom_dt()).
1232 *
1233 * TODO: the PHB should be parented by a PEC device that, at
1234 * this moment, is not modelled powernv8/phb3.
1235 */
1236 object_property_add_child(obj, "phb[*]", phb);
1237 chip8->phbs[i] = PNV_PHB(phb);
1238 }
1239 }
1240
1241 }
1242
1243 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1244 {
1245 PnvChip *chip = PNV_CHIP(chip8);
1246 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1247 int i, j;
1248 char *name;
1249
1250 name = g_strdup_printf("icp-%x", chip->chip_id);
1251 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1252 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1253 g_free(name);
1254
1255 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1256
1257 /* Map the ICP registers for each thread */
1258 for (i = 0; i < chip->nr_cores; i++) {
1259 PnvCore *pnv_core = chip->cores[i];
1260 int core_hwid = CPU_CORE(pnv_core)->core_id;
1261
1262 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1263 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1264 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1265
1266 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1267 &icp->mmio);
1268 }
1269 }
1270 }
1271
1272 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1273 {
1274 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1275 PnvChip *chip = PNV_CHIP(dev);
1276 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1277 Pnv8Psi *psi8 = &chip8->psi;
1278 Error *local_err = NULL;
1279 int i;
1280
1281 assert(chip8->xics);
1282
1283 /* XSCOM bridge is first */
1284 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1285 if (local_err) {
1286 error_propagate(errp, local_err);
1287 return;
1288 }
1289 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1290
1291 pcc->parent_realize(dev, &local_err);
1292 if (local_err) {
1293 error_propagate(errp, local_err);
1294 return;
1295 }
1296
1297 /* Processor Service Interface (PSI) Host Bridge */
1298 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1299 &error_fatal);
1300 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1301 OBJECT(chip8->xics), &error_abort);
1302 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1303 return;
1304 }
1305 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1306 &PNV_PSI(psi8)->xscom_regs);
1307
1308 /* Create LPC controller */
1309 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1310 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1311
1312 chip->fw_mr = &chip8->lpc.isa_fw;
1313 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1314 (uint64_t) PNV_XSCOM_BASE(chip),
1315 PNV_XSCOM_LPC_BASE);
1316
1317 /*
1318 * Interrupt Management Area. This is the memory region holding
1319 * all the Interrupt Control Presenter (ICP) registers
1320 */
1321 pnv_chip_icp_realize(chip8, &local_err);
1322 if (local_err) {
1323 error_propagate(errp, local_err);
1324 return;
1325 }
1326
1327 /* Create the simplified OCC model */
1328 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1329 return;
1330 }
1331 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1332 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1333 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
1334
1335 /* OCC SRAM model */
1336 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1337 &chip8->occ.sram_regs);
1338
1339 /* HOMER */
1340 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1341 &error_abort);
1342 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1343 return;
1344 }
1345 /* Homer Xscom region */
1346 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1347
1348 /* Homer mmio region */
1349 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1350 &chip8->homer.regs);
1351
1352 /* PHB controllers */
1353 for (i = 0; i < chip8->num_phbs; i++) {
1354 PnvPHB *phb = chip8->phbs[i];
1355
1356 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1357 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1358 &error_fatal);
1359 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1360 &error_fatal);
1361 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1362 return;
1363 }
1364 }
1365 }
1366
1367 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1368 {
1369 addr &= (PNV_XSCOM_SIZE - 1);
1370 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1371 }
1372
1373 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1374 {
1375 DeviceClass *dc = DEVICE_CLASS(klass);
1376 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1377
1378 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1379 k->cores_mask = POWER8E_CORE_MASK;
1380 k->num_phbs = 3;
1381 k->core_pir = pnv_chip_core_pir_p8;
1382 k->intc_create = pnv_chip_power8_intc_create;
1383 k->intc_reset = pnv_chip_power8_intc_reset;
1384 k->intc_destroy = pnv_chip_power8_intc_destroy;
1385 k->intc_print_info = pnv_chip_power8_intc_print_info;
1386 k->isa_create = pnv_chip_power8_isa_create;
1387 k->dt_populate = pnv_chip_power8_dt_populate;
1388 k->pic_print_info = pnv_chip_power8_pic_print_info;
1389 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1390 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1391 dc->desc = "PowerNV Chip POWER8E";
1392
1393 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1394 &k->parent_realize);
1395 }
1396
1397 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1398 {
1399 DeviceClass *dc = DEVICE_CLASS(klass);
1400 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1401
1402 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1403 k->cores_mask = POWER8_CORE_MASK;
1404 k->num_phbs = 3;
1405 k->core_pir = pnv_chip_core_pir_p8;
1406 k->intc_create = pnv_chip_power8_intc_create;
1407 k->intc_reset = pnv_chip_power8_intc_reset;
1408 k->intc_destroy = pnv_chip_power8_intc_destroy;
1409 k->intc_print_info = pnv_chip_power8_intc_print_info;
1410 k->isa_create = pnv_chip_power8_isa_create;
1411 k->dt_populate = pnv_chip_power8_dt_populate;
1412 k->pic_print_info = pnv_chip_power8_pic_print_info;
1413 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1414 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1415 dc->desc = "PowerNV Chip POWER8";
1416
1417 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1418 &k->parent_realize);
1419 }
1420
1421 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1422 {
1423 DeviceClass *dc = DEVICE_CLASS(klass);
1424 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1425
1426 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1427 k->cores_mask = POWER8_CORE_MASK;
1428 k->num_phbs = 4;
1429 k->core_pir = pnv_chip_core_pir_p8;
1430 k->intc_create = pnv_chip_power8_intc_create;
1431 k->intc_reset = pnv_chip_power8_intc_reset;
1432 k->intc_destroy = pnv_chip_power8_intc_destroy;
1433 k->intc_print_info = pnv_chip_power8_intc_print_info;
1434 k->isa_create = pnv_chip_power8nvl_isa_create;
1435 k->dt_populate = pnv_chip_power8_dt_populate;
1436 k->pic_print_info = pnv_chip_power8_pic_print_info;
1437 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1438 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1439 dc->desc = "PowerNV Chip POWER8NVL";
1440
1441 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1442 &k->parent_realize);
1443 }
1444
1445 static void pnv_chip_power9_instance_init(Object *obj)
1446 {
1447 PnvChip *chip = PNV_CHIP(obj);
1448 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1449 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1450 int i;
1451
1452 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1453 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1454 "xive-fabric");
1455
1456 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1457
1458 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1459
1460 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1461
1462 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1463
1464 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1465
1466 /* Number of PECs is the chip default */
1467 chip->num_pecs = pcc->num_pecs;
1468
1469 for (i = 0; i < chip->num_pecs; i++) {
1470 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1471 TYPE_PNV_PHB4_PEC);
1472 }
1473 }
1474
1475 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1476 PnvCore *pnv_core)
1477 {
1478 char eq_name[32];
1479 int core_id = CPU_CORE(pnv_core)->core_id;
1480
1481 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1482 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1483 sizeof(*eq), TYPE_PNV_QUAD,
1484 &error_fatal, NULL);
1485
1486 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1487 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1488 }
1489
1490 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1491 {
1492 PnvChip *chip = PNV_CHIP(chip9);
1493 int i;
1494
1495 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1496 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1497
1498 for (i = 0; i < chip9->nr_quads; i++) {
1499 PnvQuad *eq = &chip9->quads[i];
1500
1501 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1502
1503 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1504 &eq->xscom_regs);
1505 }
1506 }
1507
1508 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1509 {
1510 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1511 int i;
1512
1513 for (i = 0; i < chip->num_pecs; i++) {
1514 PnvPhb4PecState *pec = &chip9->pecs[i];
1515 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1516 uint32_t pec_nest_base;
1517 uint32_t pec_pci_base;
1518
1519 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1520 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1521 &error_fatal);
1522 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1523 &error_fatal);
1524 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1525 return;
1526 }
1527
1528 pec_nest_base = pecc->xscom_nest_base(pec);
1529 pec_pci_base = pecc->xscom_pci_base(pec);
1530
1531 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1532 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1533 }
1534 }
1535
1536 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1537 {
1538 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1539 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1540 PnvChip *chip = PNV_CHIP(dev);
1541 Pnv9Psi *psi9 = &chip9->psi;
1542 Error *local_err = NULL;
1543
1544 /* XSCOM bridge is first */
1545 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1546 if (local_err) {
1547 error_propagate(errp, local_err);
1548 return;
1549 }
1550 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1551
1552 pcc->parent_realize(dev, &local_err);
1553 if (local_err) {
1554 error_propagate(errp, local_err);
1555 return;
1556 }
1557
1558 pnv_chip_quad_realize(chip9, &local_err);
1559 if (local_err) {
1560 error_propagate(errp, local_err);
1561 return;
1562 }
1563
1564 /* XIVE interrupt controller (POWER9) */
1565 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1566 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1567 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1568 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1569 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1570 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1571 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1572 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1573 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1574 &error_abort);
1575 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1576 return;
1577 }
1578 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1579 &chip9->xive.xscom_regs);
1580
1581 /* Processor Service Interface (PSI) Host Bridge */
1582 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1583 &error_fatal);
1584 /* This is the only device with 4k ESB pages */
1585 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
1586 &error_fatal);
1587 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1588 return;
1589 }
1590 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1591 &PNV_PSI(psi9)->xscom_regs);
1592
1593 /* LPC */
1594 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1595 return;
1596 }
1597 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1598 &chip9->lpc.xscom_regs);
1599
1600 chip->fw_mr = &chip9->lpc.isa_fw;
1601 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1602 (uint64_t) PNV9_LPCM_BASE(chip));
1603
1604 /* Create the simplified OCC model */
1605 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1606 return;
1607 }
1608 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1609 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
1610 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
1611
1612 /* OCC SRAM model */
1613 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1614 &chip9->occ.sram_regs);
1615
1616 /* SBE */
1617 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
1618 return;
1619 }
1620 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
1621 &chip9->sbe.xscom_ctrl_regs);
1622 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
1623 &chip9->sbe.xscom_mbox_regs);
1624 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
1625 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU));
1626
1627 /* HOMER */
1628 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1629 &error_abort);
1630 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1631 return;
1632 }
1633 /* Homer Xscom region */
1634 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1635
1636 /* Homer mmio region */
1637 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1638 &chip9->homer.regs);
1639
1640 /* PEC PHBs */
1641 pnv_chip_power9_pec_realize(chip, &local_err);
1642 if (local_err) {
1643 error_propagate(errp, local_err);
1644 return;
1645 }
1646 }
1647
1648 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1649 {
1650 addr &= (PNV9_XSCOM_SIZE - 1);
1651 return addr >> 3;
1652 }
1653
1654 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1655 {
1656 DeviceClass *dc = DEVICE_CLASS(klass);
1657 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1658
1659 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1660 k->cores_mask = POWER9_CORE_MASK;
1661 k->core_pir = pnv_chip_core_pir_p9;
1662 k->intc_create = pnv_chip_power9_intc_create;
1663 k->intc_reset = pnv_chip_power9_intc_reset;
1664 k->intc_destroy = pnv_chip_power9_intc_destroy;
1665 k->intc_print_info = pnv_chip_power9_intc_print_info;
1666 k->isa_create = pnv_chip_power9_isa_create;
1667 k->dt_populate = pnv_chip_power9_dt_populate;
1668 k->pic_print_info = pnv_chip_power9_pic_print_info;
1669 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1670 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1671 dc->desc = "PowerNV Chip POWER9";
1672 k->num_pecs = PNV9_CHIP_MAX_PEC;
1673
1674 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1675 &k->parent_realize);
1676 }
1677
1678 static void pnv_chip_power10_instance_init(Object *obj)
1679 {
1680 PnvChip *chip = PNV_CHIP(obj);
1681 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1682 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1683 int i;
1684
1685 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1686 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1687 "xive-fabric");
1688 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1689 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1690 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
1691 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
1692 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1693
1694 chip->num_pecs = pcc->num_pecs;
1695
1696 for (i = 0; i < chip->num_pecs; i++) {
1697 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1698 TYPE_PNV_PHB5_PEC);
1699 }
1700 }
1701
1702 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1703 {
1704 PnvChip *chip = PNV_CHIP(chip10);
1705 int i;
1706
1707 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1708 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1709
1710 for (i = 0; i < chip10->nr_quads; i++) {
1711 PnvQuad *eq = &chip10->quads[i];
1712
1713 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1714
1715 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1716 &eq->xscom_regs);
1717 }
1718 }
1719
1720 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1721 {
1722 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1723 int i;
1724
1725 for (i = 0; i < chip->num_pecs; i++) {
1726 PnvPhb4PecState *pec = &chip10->pecs[i];
1727 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1728 uint32_t pec_nest_base;
1729 uint32_t pec_pci_base;
1730
1731 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1732 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1733 &error_fatal);
1734 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1735 &error_fatal);
1736 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1737 return;
1738 }
1739
1740 pec_nest_base = pecc->xscom_nest_base(pec);
1741 pec_pci_base = pecc->xscom_pci_base(pec);
1742
1743 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1744 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1745 }
1746 }
1747
1748 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1749 {
1750 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1751 PnvChip *chip = PNV_CHIP(dev);
1752 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1753 Error *local_err = NULL;
1754
1755 /* XSCOM bridge is first */
1756 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1757 if (local_err) {
1758 error_propagate(errp, local_err);
1759 return;
1760 }
1761 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1762
1763 pcc->parent_realize(dev, &local_err);
1764 if (local_err) {
1765 error_propagate(errp, local_err);
1766 return;
1767 }
1768
1769 pnv_chip_power10_quad_realize(chip10, &local_err);
1770 if (local_err) {
1771 error_propagate(errp, local_err);
1772 return;
1773 }
1774
1775 /* XIVE2 interrupt controller (POWER10) */
1776 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1777 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1778 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1779 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1780 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1781 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1782 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1783 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1784 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1785 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1786 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1787 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1788 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1789 &error_abort);
1790 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1791 return;
1792 }
1793 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1794 &chip10->xive.xscom_regs);
1795
1796 /* Processor Service Interface (PSI) Host Bridge */
1797 object_property_set_int(OBJECT(&chip10->psi), "bar",
1798 PNV10_PSIHB_BASE(chip), &error_fatal);
1799 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1800 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
1801 &error_fatal);
1802 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1803 return;
1804 }
1805 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1806 &PNV_PSI(&chip10->psi)->xscom_regs);
1807
1808 /* LPC */
1809 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1810 return;
1811 }
1812 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1813 &chip10->lpc.xscom_regs);
1814
1815 chip->fw_mr = &chip10->lpc.isa_fw;
1816 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1817 (uint64_t) PNV10_LPCM_BASE(chip));
1818
1819 /* Create the simplified OCC model */
1820 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
1821 return;
1822 }
1823 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
1824 &chip10->occ.xscom_regs);
1825 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
1826 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
1827
1828 /* OCC SRAM model */
1829 memory_region_add_subregion(get_system_memory(),
1830 PNV10_OCC_SENSOR_BASE(chip),
1831 &chip10->occ.sram_regs);
1832
1833 /* SBE */
1834 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
1835 return;
1836 }
1837 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
1838 &chip10->sbe.xscom_ctrl_regs);
1839 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
1840 &chip10->sbe.xscom_mbox_regs);
1841 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
1842 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
1843
1844 /* HOMER */
1845 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
1846 &error_abort);
1847 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
1848 return;
1849 }
1850 /* Homer Xscom region */
1851 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
1852 &chip10->homer.pba_regs);
1853
1854 /* Homer mmio region */
1855 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
1856 &chip10->homer.regs);
1857
1858 /* PHBs */
1859 pnv_chip_power10_phb_realize(chip, &local_err);
1860 if (local_err) {
1861 error_propagate(errp, local_err);
1862 return;
1863 }
1864 }
1865
1866 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1867 {
1868 addr &= (PNV10_XSCOM_SIZE - 1);
1869 return addr >> 3;
1870 }
1871
1872 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1873 {
1874 DeviceClass *dc = DEVICE_CLASS(klass);
1875 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1876
1877 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1878 k->cores_mask = POWER10_CORE_MASK;
1879 k->core_pir = pnv_chip_core_pir_p10;
1880 k->intc_create = pnv_chip_power10_intc_create;
1881 k->intc_reset = pnv_chip_power10_intc_reset;
1882 k->intc_destroy = pnv_chip_power10_intc_destroy;
1883 k->intc_print_info = pnv_chip_power10_intc_print_info;
1884 k->isa_create = pnv_chip_power10_isa_create;
1885 k->dt_populate = pnv_chip_power10_dt_populate;
1886 k->pic_print_info = pnv_chip_power10_pic_print_info;
1887 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1888 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1889 dc->desc = "PowerNV Chip POWER10";
1890 k->num_pecs = PNV10_CHIP_MAX_PEC;
1891
1892 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1893 &k->parent_realize);
1894 }
1895
1896 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1897 {
1898 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1899 int cores_max;
1900
1901 /*
1902 * No custom mask for this chip, let's use the default one from *
1903 * the chip class
1904 */
1905 if (!chip->cores_mask) {
1906 chip->cores_mask = pcc->cores_mask;
1907 }
1908
1909 /* filter alien core ids ! some are reserved */
1910 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1911 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1912 chip->cores_mask);
1913 return;
1914 }
1915 chip->cores_mask &= pcc->cores_mask;
1916
1917 /* now that we have a sane layout, let check the number of cores */
1918 cores_max = ctpop64(chip->cores_mask);
1919 if (chip->nr_cores > cores_max) {
1920 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1921 cores_max);
1922 return;
1923 }
1924 }
1925
1926 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1927 {
1928 Error *error = NULL;
1929 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1930 const char *typename = pnv_chip_core_typename(chip);
1931 int i, core_hwid;
1932 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1933
1934 if (!object_class_by_name(typename)) {
1935 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1936 return;
1937 }
1938
1939 /* Cores */
1940 pnv_chip_core_sanitize(chip, &error);
1941 if (error) {
1942 error_propagate(errp, error);
1943 return;
1944 }
1945
1946 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1947
1948 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1949 && (i < chip->nr_cores); core_hwid++) {
1950 char core_name[32];
1951 PnvCore *pnv_core;
1952 uint64_t xscom_core_base;
1953
1954 if (!(chip->cores_mask & (1ull << core_hwid))) {
1955 continue;
1956 }
1957
1958 pnv_core = PNV_CORE(object_new(typename));
1959
1960 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1961 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1962 chip->cores[i] = pnv_core;
1963 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1964 chip->nr_threads, &error_fatal);
1965 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1966 core_hwid, &error_fatal);
1967 object_property_set_int(OBJECT(pnv_core), "pir",
1968 pcc->core_pir(chip, core_hwid), &error_fatal);
1969 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1970 &error_fatal);
1971 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1972 &error_abort);
1973 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1974
1975 /* Each core has an XSCOM MMIO region */
1976 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1977
1978 pnv_xscom_add_subregion(chip, xscom_core_base,
1979 &pnv_core->xscom_regs);
1980 i++;
1981 }
1982 }
1983
1984 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1985 {
1986 PnvChip *chip = PNV_CHIP(dev);
1987 Error *error = NULL;
1988
1989 /* Cores */
1990 pnv_chip_core_realize(chip, &error);
1991 if (error) {
1992 error_propagate(errp, error);
1993 return;
1994 }
1995 }
1996
1997 static Property pnv_chip_properties[] = {
1998 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1999 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
2000 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
2001 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
2002 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
2003 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
2004 DEFINE_PROP_END_OF_LIST(),
2005 };
2006
2007 static void pnv_chip_class_init(ObjectClass *klass, void *data)
2008 {
2009 DeviceClass *dc = DEVICE_CLASS(klass);
2010
2011 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
2012 dc->realize = pnv_chip_realize;
2013 device_class_set_props(dc, pnv_chip_properties);
2014 dc->desc = "PowerNV Chip";
2015 }
2016
2017 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
2018 {
2019 int i, j;
2020
2021 for (i = 0; i < chip->nr_cores; i++) {
2022 PnvCore *pc = chip->cores[i];
2023 CPUCore *cc = CPU_CORE(pc);
2024
2025 for (j = 0; j < cc->nr_threads; j++) {
2026 if (ppc_cpu_pir(pc->threads[j]) == pir) {
2027 return pc->threads[j];
2028 }
2029 }
2030 }
2031 return NULL;
2032 }
2033
2034 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
2035 {
2036 PnvMachineState *pnv = PNV_MACHINE(xi);
2037 int i, j;
2038
2039 for (i = 0; i < pnv->num_chips; i++) {
2040 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2041
2042 if (ics_valid_irq(&chip8->psi.ics, irq)) {
2043 return &chip8->psi.ics;
2044 }
2045
2046 for (j = 0; j < chip8->num_phbs; j++) {
2047 PnvPHB *phb = chip8->phbs[j];
2048 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2049
2050 if (ics_valid_irq(&phb3->lsis, irq)) {
2051 return &phb3->lsis;
2052 }
2053
2054 if (ics_valid_irq(ICS(&phb3->msis), irq)) {
2055 return ICS(&phb3->msis);
2056 }
2057 }
2058 }
2059 return NULL;
2060 }
2061
2062 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
2063 {
2064 int i;
2065
2066 for (i = 0; i < pnv->num_chips; i++) {
2067 PnvChip *chip = pnv->chips[i];
2068 if (chip->chip_id == chip_id) {
2069 return chip;
2070 }
2071 }
2072 return NULL;
2073 }
2074
2075 static void pnv_ics_resend(XICSFabric *xi)
2076 {
2077 PnvMachineState *pnv = PNV_MACHINE(xi);
2078 int i, j;
2079
2080 for (i = 0; i < pnv->num_chips; i++) {
2081 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2082
2083 ics_resend(&chip8->psi.ics);
2084
2085 for (j = 0; j < chip8->num_phbs; j++) {
2086 PnvPHB *phb = chip8->phbs[j];
2087 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2088
2089 ics_resend(&phb3->lsis);
2090 ics_resend(ICS(&phb3->msis));
2091 }
2092 }
2093 }
2094
2095 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2096 {
2097 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2098
2099 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2100 }
2101
2102 static void pnv_pic_print_info(InterruptStatsProvider *obj,
2103 Monitor *mon)
2104 {
2105 PnvMachineState *pnv = PNV_MACHINE(obj);
2106 int i;
2107 CPUState *cs;
2108
2109 CPU_FOREACH(cs) {
2110 PowerPCCPU *cpu = POWERPC_CPU(cs);
2111
2112 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2113 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
2114 mon);
2115 }
2116
2117 for (i = 0; i < pnv->num_chips; i++) {
2118 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
2119 }
2120 }
2121
2122 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2123 uint8_t nvt_blk, uint32_t nvt_idx,
2124 bool cam_ignore, uint8_t priority,
2125 uint32_t logic_serv,
2126 XiveTCTXMatch *match)
2127 {
2128 PnvMachineState *pnv = PNV_MACHINE(xfb);
2129 int total_count = 0;
2130 int i;
2131
2132 for (i = 0; i < pnv->num_chips; i++) {
2133 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2134 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2135 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2136 int count;
2137
2138 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2139 priority, logic_serv, match);
2140
2141 if (count < 0) {
2142 return count;
2143 }
2144
2145 total_count += count;
2146 }
2147
2148 return total_count;
2149 }
2150
2151 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2152 uint8_t nvt_blk, uint32_t nvt_idx,
2153 bool cam_ignore, uint8_t priority,
2154 uint32_t logic_serv,
2155 XiveTCTXMatch *match)
2156 {
2157 PnvMachineState *pnv = PNV_MACHINE(xfb);
2158 int total_count = 0;
2159 int i;
2160
2161 for (i = 0; i < pnv->num_chips; i++) {
2162 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2163 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2164 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2165 int count;
2166
2167 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2168 priority, logic_serv, match);
2169
2170 if (count < 0) {
2171 return count;
2172 }
2173
2174 total_count += count;
2175 }
2176
2177 return total_count;
2178 }
2179
2180 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2181 {
2182 MachineClass *mc = MACHINE_CLASS(oc);
2183 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2184 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2185 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2186
2187 static GlobalProperty phb_compat[] = {
2188 { TYPE_PNV_PHB, "version", "3" },
2189 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
2190 };
2191
2192 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2193 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2194 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2195
2196 xic->icp_get = pnv_icp_get;
2197 xic->ics_get = pnv_ics_get;
2198 xic->ics_resend = pnv_ics_resend;
2199
2200 pmc->compat = compat;
2201 pmc->compat_size = sizeof(compat);
2202
2203 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2204 }
2205
2206 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2207 {
2208 MachineClass *mc = MACHINE_CLASS(oc);
2209 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2210 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2211 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2212
2213 static GlobalProperty phb_compat[] = {
2214 { TYPE_PNV_PHB, "version", "4" },
2215 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
2216 };
2217
2218 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2219 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
2220 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2221
2222 xfc->match_nvt = pnv_match_nvt;
2223
2224 mc->alias = "powernv";
2225
2226 pmc->compat = compat;
2227 pmc->compat_size = sizeof(compat);
2228 pmc->dt_power_mgt = pnv_dt_power_mgt;
2229
2230 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2231 }
2232
2233 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2234 {
2235 MachineClass *mc = MACHINE_CLASS(oc);
2236 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2237 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2238 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2239
2240 static GlobalProperty phb_compat[] = {
2241 { TYPE_PNV_PHB, "version", "5" },
2242 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
2243 };
2244
2245 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2246 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2247 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2248
2249 pmc->compat = compat;
2250 pmc->compat_size = sizeof(compat);
2251 pmc->dt_power_mgt = pnv_dt_power_mgt;
2252
2253 xfc->match_nvt = pnv10_xive_match_nvt;
2254
2255 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2256 }
2257
2258 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2259 {
2260 PnvMachineState *pnv = PNV_MACHINE(obj);
2261
2262 return !!pnv->fw_load_addr;
2263 }
2264
2265 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2266 {
2267 PnvMachineState *pnv = PNV_MACHINE(obj);
2268
2269 if (value) {
2270 pnv->fw_load_addr = 0x8000000;
2271 }
2272 }
2273
2274 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2275 {
2276 PowerPCCPU *cpu = POWERPC_CPU(cs);
2277 CPUPPCState *env = &cpu->env;
2278
2279 cpu_synchronize_state(cs);
2280 ppc_cpu_do_system_reset(cs);
2281 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2282 /*
2283 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2284 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2285 * (PPC_BIT(43)).
2286 */
2287 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2288 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2289 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2290 }
2291 } else {
2292 /*
2293 * For non-powersave system resets, SRR1[42:45] are defined to be
2294 * implementation-dependent. The POWER9 User Manual specifies that
2295 * an external (SCOM driven, which may come from a BMC nmi command or
2296 * another CPU requesting a NMI IPI) system reset exception should be
2297 * 0b0010 (PPC_BIT(44)).
2298 */
2299 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2300 }
2301 }
2302
2303 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2304 {
2305 CPUState *cs;
2306
2307 CPU_FOREACH(cs) {
2308 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2309 }
2310 }
2311
2312 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2313 {
2314 MachineClass *mc = MACHINE_CLASS(oc);
2315 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2316 NMIClass *nc = NMI_CLASS(oc);
2317
2318 mc->desc = "IBM PowerNV (Non-Virtualized)";
2319 mc->init = pnv_init;
2320 mc->reset = pnv_reset;
2321 mc->max_cpus = MAX_CPUS;
2322 /* Pnv provides a AHCI device for storage */
2323 mc->block_default_type = IF_IDE;
2324 mc->no_parallel = 1;
2325 mc->default_boot_order = NULL;
2326 /*
2327 * RAM defaults to less than 2048 for 32-bit hosts, and large
2328 * enough to fit the maximum initrd size at it's load address
2329 */
2330 mc->default_ram_size = 1 * GiB;
2331 mc->default_ram_id = "pnv.ram";
2332 ispc->print_info = pnv_pic_print_info;
2333 nc->nmi_monitor_handler = pnv_nmi;
2334
2335 object_class_property_add_bool(oc, "hb-mode",
2336 pnv_machine_get_hb, pnv_machine_set_hb);
2337 object_class_property_set_description(oc, "hb-mode",
2338 "Use a hostboot like boot loader");
2339 }
2340
2341 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2342 { \
2343 .name = type, \
2344 .class_init = class_initfn, \
2345 .parent = TYPE_PNV8_CHIP, \
2346 }
2347
2348 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2349 { \
2350 .name = type, \
2351 .class_init = class_initfn, \
2352 .parent = TYPE_PNV9_CHIP, \
2353 }
2354
2355 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2356 { \
2357 .name = type, \
2358 .class_init = class_initfn, \
2359 .parent = TYPE_PNV10_CHIP, \
2360 }
2361
2362 static const TypeInfo types[] = {
2363 {
2364 .name = MACHINE_TYPE_NAME("powernv10"),
2365 .parent = TYPE_PNV_MACHINE,
2366 .class_init = pnv_machine_power10_class_init,
2367 .interfaces = (InterfaceInfo[]) {
2368 { TYPE_XIVE_FABRIC },
2369 { },
2370 },
2371 },
2372 {
2373 .name = MACHINE_TYPE_NAME("powernv9"),
2374 .parent = TYPE_PNV_MACHINE,
2375 .class_init = pnv_machine_power9_class_init,
2376 .interfaces = (InterfaceInfo[]) {
2377 { TYPE_XIVE_FABRIC },
2378 { },
2379 },
2380 },
2381 {
2382 .name = MACHINE_TYPE_NAME("powernv8"),
2383 .parent = TYPE_PNV_MACHINE,
2384 .class_init = pnv_machine_power8_class_init,
2385 .interfaces = (InterfaceInfo[]) {
2386 { TYPE_XICS_FABRIC },
2387 { },
2388 },
2389 },
2390 {
2391 .name = TYPE_PNV_MACHINE,
2392 .parent = TYPE_MACHINE,
2393 .abstract = true,
2394 .instance_size = sizeof(PnvMachineState),
2395 .class_init = pnv_machine_class_init,
2396 .class_size = sizeof(PnvMachineClass),
2397 .interfaces = (InterfaceInfo[]) {
2398 { TYPE_INTERRUPT_STATS_PROVIDER },
2399 { TYPE_NMI },
2400 { },
2401 },
2402 },
2403 {
2404 .name = TYPE_PNV_CHIP,
2405 .parent = TYPE_SYS_BUS_DEVICE,
2406 .class_init = pnv_chip_class_init,
2407 .instance_size = sizeof(PnvChip),
2408 .class_size = sizeof(PnvChipClass),
2409 .abstract = true,
2410 },
2411
2412 /*
2413 * P10 chip and variants
2414 */
2415 {
2416 .name = TYPE_PNV10_CHIP,
2417 .parent = TYPE_PNV_CHIP,
2418 .instance_init = pnv_chip_power10_instance_init,
2419 .instance_size = sizeof(Pnv10Chip),
2420 },
2421 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2422
2423 /*
2424 * P9 chip and variants
2425 */
2426 {
2427 .name = TYPE_PNV9_CHIP,
2428 .parent = TYPE_PNV_CHIP,
2429 .instance_init = pnv_chip_power9_instance_init,
2430 .instance_size = sizeof(Pnv9Chip),
2431 },
2432 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2433
2434 /*
2435 * P8 chip and variants
2436 */
2437 {
2438 .name = TYPE_PNV8_CHIP,
2439 .parent = TYPE_PNV_CHIP,
2440 .instance_init = pnv_chip_power8_instance_init,
2441 .instance_size = sizeof(Pnv8Chip),
2442 },
2443 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2444 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2445 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2446 pnv_chip_power8nvl_class_init),
2447 };
2448
2449 DEFINE_TYPES(types)
QEmu