hw/ppc/mac_oldworld.c

   1
   2 /*
   3  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   4  *
   5  * Copyright (c) 2004-2007 Fabrice Bellard
   6  * Copyright (c) 2007 Jocelyn Mayer
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "qemu/datadir.h"
  29 #include "qemu/units.h"
  30 #include "qapi/error.h"
  31 #include "hw/ppc/ppc.h"
  32 #include "hw/qdev-properties.h"
  33 #include "mac.h"
  34 #include "hw/input/adb.h"
  35 #include "sysemu/sysemu.h"
  36 #include "net/net.h"
  37 #include "hw/isa/isa.h"
  38 #include "hw/pci/pci.h"
  39 #include "hw/pci/pci_host.h"
  40 #include "hw/nvram/fw_cfg.h"
  41 #include "hw/char/escc.h"
  42 #include "hw/misc/macio/macio.h"
  43 #include "hw/loader.h"
  44 #include "hw/fw-path-provider.h"
  45 #include "elf.h"
  46 #include "qemu/error-report.h"
  47 #include "sysemu/kvm.h"
  48 #include "sysemu/reset.h"
  49 #include "kvm_ppc.h"
  50
  51 #define MAX_IDE_BUS 2
  52 #define CFG_ADDR 0xf0000510
  53 #define TBFREQ 16600000UL
  54 #define CLOCKFREQ 266000000UL
  55 #define BUSFREQ 66000000UL
  56
  57 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
  58
  59 #define GRACKLE_BASE 0xfec00000
  60 #define PROM_BASE 0xffc00000
  61 #define PROM_SIZE (4 * MiB)
  62
  63 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
  64                             Error **errp)
  65 {
  66     fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  67 }
  68
  69 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
  70 {
  71     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
  72 }
  73
  74 static void ppc_heathrow_reset(void *opaque)
  75 {
  76     PowerPCCPU *cpu = opaque;
  77
  78     cpu_reset(CPU(cpu));
  79 }
  80
  81 static void ppc_heathrow_init(MachineState *machine)
  82 {
  83     ram_addr_t ram_size = machine->ram_size;
  84     const char *bios_name = machine->firmware ?: PROM_FILENAME;
  85     const char *boot_device = machine->boot_config.order;
  86     PowerPCCPU *cpu = NULL;
  87     CPUPPCState *env = NULL;
  88     char *filename;
  89     int i;
  90     MemoryRegion *bios = g_new(MemoryRegion, 1);
  91     uint32_t kernel_base, initrd_base, cmdline_base = 0;
  92     int32_t kernel_size, initrd_size;
  93     PCIBus *pci_bus;
  94     PCIDevice *macio;
  95     MACIOIDEState *macio_ide;
  96     ESCCState *escc;
  97     SysBusDevice *s;
  98     DeviceState *dev, *pic_dev, *grackle_dev;
  99     BusState *adb_bus;
 100     uint64_t bios_addr;
 101     int bios_size;
 102     unsigned int smp_cpus = machine->smp.cpus;
 103     uint16_t ppc_boot_device;
 104     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 105     void *fw_cfg;
 106     uint64_t tbfreq;
 107
 108     /* init CPUs */
 109     for (i = 0; i < smp_cpus; i++) {
 110         cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
 111         env = &cpu->env;
 112
 113         /* Set time-base frequency to 16.6 Mhz */
 114         cpu_ppc_tb_init(env,  TBFREQ);
 115         qemu_register_reset(ppc_heathrow_reset, cpu);
 116     }
 117
 118     /* allocate RAM */
 119     if (ram_size > 2047 * MiB) {
 120         error_report("Too much memory for this machine: %" PRId64 " MB, "
 121                      "maximum 2047 MB", ram_size / MiB);
 122         exit(1);
 123     }
 124
 125     memory_region_add_subregion(get_system_memory(), 0, machine->ram);
 126
 127     /* allocate and load firmware ROM */
 128     memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE,
 129                            &error_fatal);
 130     memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
 131
 132     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 133     if (filename) {
 134         /* Load OpenBIOS (ELF) */
 135         bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr,
 136                              NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 137         /* Unfortunately, load_elf sign-extends reading elf32 */
 138         bios_addr = (uint32_t)bios_addr;
 139
 140         if (bios_size <= 0) {
 141             /* or if could not load ELF try loading a binary ROM image */
 142             bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
 143             bios_addr = PROM_BASE;
 144         }
 145         g_free(filename);
 146     } else {
 147         bios_size = -1;
 148     }
 149     if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) {
 150         error_report("could not load PowerPC bios '%s'", bios_name);
 151         exit(1);
 152     }
 153
 154     if (machine->kernel_filename) {
 155         int bswap_needed;
 156
 157 #ifdef BSWAP_NEEDED
 158         bswap_needed = 1;
 159 #else
 160         bswap_needed = 0;
 161 #endif
 162         kernel_base = KERNEL_LOAD_ADDR;
 163         kernel_size = load_elf(machine->kernel_filename, NULL,
 164                                translate_kernel_address, NULL, NULL, NULL,
 165                                NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
 166         if (kernel_size < 0)
 167             kernel_size = load_aout(machine->kernel_filename, kernel_base,
 168                                     ram_size - kernel_base, bswap_needed,
 169                                     TARGET_PAGE_SIZE);
 170         if (kernel_size < 0)
 171             kernel_size = load_image_targphys(machine->kernel_filename,
 172                                               kernel_base,
 173                                               ram_size - kernel_base);
 174         if (kernel_size < 0) {
 175             error_report("could not load kernel '%s'",
 176                          machine->kernel_filename);
 177             exit(1);
 178         }
 179         /* load initrd */
 180         if (machine->initrd_filename) {
 181             initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
 182                                             KERNEL_GAP);
 183             initrd_size = load_image_targphys(machine->initrd_filename,
 184                                               initrd_base,
 185                                               ram_size - initrd_base);
 186             if (initrd_size < 0) {
 187                 error_report("could not load initial ram disk '%s'",
 188                              machine->initrd_filename);
 189                 exit(1);
 190             }
 191             cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
 192         } else {
 193             initrd_base = 0;
 194             initrd_size = 0;
 195             cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
 196         }
 197         ppc_boot_device = 'm';
 198     } else {
 199         kernel_base = 0;
 200         kernel_size = 0;
 201         initrd_base = 0;
 202         initrd_size = 0;
 203         ppc_boot_device = '\0';
 204         for (i = 0; boot_device[i] != '\0'; i++) {
 205             /* TOFIX: for now, the second IDE channel is not properly
 206              *        used by OHW. The Mac floppy disk are not emulated.
 207              *        For now, OHW cannot boot from the network.
 208              */
 209 #if 0
 210             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 211                 ppc_boot_device = boot_device[i];
 212                 break;
 213             }
 214 #else
 215             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 216                 ppc_boot_device = boot_device[i];
 217                 break;
 218             }
 219 #endif
 220         }
 221         if (ppc_boot_device == '\0') {
 222             error_report("No valid boot device for G3 Beige machine");
 223             exit(1);
 224         }
 225     }
 226
 227     /* Timebase Frequency */
 228     if (kvm_enabled()) {
 229         tbfreq = kvmppc_get_tbfreq();
 230     } else {
 231         tbfreq = TBFREQ;
 232     }
 233
 234     /* Grackle PCI host bridge */
 235     grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
 236     qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000);
 237     s = SYS_BUS_DEVICE(grackle_dev);
 238     sysbus_realize_and_unref(s, &error_fatal);
 239
 240     sysbus_mmio_map(s, 0, GRACKLE_BASE);
 241     sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
 242     /* PCI hole */
 243     memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
 244                                 sysbus_mmio_get_region(s, 2));
 245     /* Register 2 MB of ISA IO space */
 246     memory_region_add_subregion(get_system_memory(), 0xfe000000,
 247                                 sysbus_mmio_get_region(s, 3));
 248
 249     pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus;
 250
 251     /* MacIO */
 252     macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
 253     dev = DEVICE(macio);
 254     qdev_prop_set_uint64(dev, "frequency", tbfreq);
 255
 256     escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
 257     qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
 258     qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
 259
 260     pci_realize_and_unref(macio, pci_bus, &error_fatal);
 261
 262     pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic"));
 263     for (i = 0; i < 4; i++) {
 264         qdev_connect_gpio_out(grackle_dev, i,
 265                               qdev_get_gpio_in(pic_dev, 0x15 + i));
 266     }
 267
 268     /* Connect the heathrow PIC outputs to the 6xx bus */
 269     for (i = 0; i < smp_cpus; i++) {
 270         switch (PPC_INPUT(env)) {
 271         case PPC_FLAGS_INPUT_6xx:
 272             /* XXX: we register only 1 output pin for heathrow PIC */
 273             qdev_connect_gpio_out(pic_dev, 0,
 274                               qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
 275             break;
 276         default:
 277             error_report("Bus model not supported on OldWorld Mac machine");
 278             exit(1);
 279         }
 280     }
 281
 282     pci_vga_init(pci_bus);
 283
 284     for (i = 0; i < nb_nics; i++) {
 285         pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 286     }
 287
 288     /* MacIO IDE */
 289     ide_drive_get(hd, ARRAY_SIZE(hd));
 290     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
 291                                                         "ide[0]"));
 292     macio_ide_init_drives(macio_ide, hd);
 293
 294     macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
 295                                                         "ide[1]"));
 296     macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
 297
 298     /* MacIO CUDA/ADB */
 299     dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
 300     adb_bus = qdev_get_child_bus(dev, "adb.0");
 301     dev = qdev_new(TYPE_ADB_KEYBOARD);
 302     qdev_realize_and_unref(dev, adb_bus, &error_fatal);
 303     dev = qdev_new(TYPE_ADB_MOUSE);
 304     qdev_realize_and_unref(dev, adb_bus, &error_fatal);
 305
 306     if (machine_usb(machine)) {
 307         pci_create_simple(pci_bus, -1, "pci-ohci");
 308     }
 309
 310     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 311         graphic_depth = 15;
 312
 313     /* No PCI init: the BIOS will do it */
 314
 315     dev = qdev_new(TYPE_FW_CFG_MEM);
 316     fw_cfg = FW_CFG(dev);
 317     qdev_prop_set_uint32(dev, "data_width", 1);
 318     qdev_prop_set_bit(dev, "dma_enabled", false);
 319     object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
 320                               OBJECT(fw_cfg));
 321     s = SYS_BUS_DEVICE(dev);
 322     sysbus_realize_and_unref(s, &error_fatal);
 323     sysbus_mmio_map(s, 0, CFG_ADDR);
 324     sysbus_mmio_map(s, 1, CFG_ADDR + 2);
 325
 326     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
 327     fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
 328     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 329     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 330     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 331     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 332     if (machine->kernel_cmdline) {
 333         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
 334         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 335                          machine->kernel_cmdline);
 336     } else {
 337         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 338     }
 339     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 340     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 341     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 342
 343     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 344     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 345     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 346
 347     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 348     if (kvm_enabled()) {
 349         uint8_t *hypercall;
 350
 351         hypercall = g_malloc(16);
 352         kvmppc_get_hypercall(env, hypercall, 16);
 353         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 354         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 355     }
 356     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
 357     /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
 358     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
 359     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
 360
 361     /* MacOS NDRV VGA driver */
 362     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
 363     if (filename) {
 364         gchar *ndrv_file;
 365         gsize ndrv_size;
 366
 367         if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
 368             fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
 369         }
 370         g_free(filename);
 371     }
 372
 373     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 374 }
 375
 376 /*
 377  * Implementation of an interface to adjust firmware path
 378  * for the bootindex property handling.
 379  */
 380 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
 381                                   DeviceState *dev)
 382 {
 383     PCIDevice *pci;
 384     MACIOIDEState *macio_ide;
 385
 386     if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
 387         pci = PCI_DEVICE(dev);
 388         return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
 389     }
 390
 391     if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
 392         macio_ide = MACIO_IDE(dev);
 393         return g_strdup_printf("ata-3@%x", macio_ide->addr);
 394     }
 395
 396     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
 397         return g_strdup("disk");
 398     }
 399
 400     if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
 401         return g_strdup("cdrom");
 402     }
 403
 404     if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
 405         return g_strdup("disk");
 406     }
 407
 408     return NULL;
 409 }
 410
 411 static int heathrow_kvm_type(MachineState *machine, const char *arg)
 412 {
 413     /* Always force PR KVM */
 414     return 2;
 415 }
 416
 417 static void heathrow_class_init(ObjectClass *oc, void *data)
 418 {
 419     MachineClass *mc = MACHINE_CLASS(oc);
 420     FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
 421
 422     mc->desc = "Heathrow based PowerMAC";
 423     mc->init = ppc_heathrow_init;
 424     mc->block_default_type = IF_IDE;
 425     /* SMP is not supported currently */
 426     mc->max_cpus = 1;
 427 #ifndef TARGET_PPC64
 428     mc->is_default = true;
 429 #endif
 430     /* TOFIX "cad" when Mac floppy is implemented */
 431     mc->default_boot_order = "cd";
 432     mc->kvm_type = heathrow_kvm_type;
 433     mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
 434     mc->default_display = "std";
 435     mc->ignore_boot_device_suffixes = true;
 436     mc->default_ram_id = "ppc_heathrow.ram";
 437     fwc->get_dev_path = heathrow_fw_dev_path;
 438 }
 439
 440 static const TypeInfo ppc_heathrow_machine_info = {
 441     .name          = MACHINE_TYPE_NAME("g3beige"),
 442     .parent        = TYPE_MACHINE,
 443     .class_init    = heathrow_class_init,
 444     .interfaces = (InterfaceInfo[]) {
 445         { TYPE_FW_PATH_PROVIDER },
 446         { }
 447     },
 448 };
 449
 450 static void ppc_heathrow_register_types(void)
 451 {
 452     type_register_static(&ppc_heathrow_machine_info);
 453 }
 454
 455 type_init(ppc_heathrow_register_types);