hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26 #include "acpi.h"
  27
  28 //#define DEBUG
  29
  30 #ifdef DEBUG
  31 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  32 #else
  33 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  34 #endif
  35
  36 #define ACPI_DBG_IO_ADDR  0xb044
  37
  38 #define GPE_BASE 0xafe0
  39 #define PCI_BASE 0xae00
  40 #define PCI_EJ_BASE 0xae08
  41
  42 struct gpe_regs {
  43     uint16_t sts; /* status */
  44     uint16_t en;  /* enabled */
  45 };
  46
  47 struct pci_status {
  48     uint32_t up;
  49     uint32_t down;
  50 };
  51
  52 typedef struct PIIX4PMState {
  53     PCIDevice dev;
  54     uint16_t pmsts;
  55     uint16_t pmen;
  56     uint16_t pmcntrl;
  57
  58     APMState apm;
  59
  60     QEMUTimer *tmr_timer;
  61     int64_t tmr_overflow_time;
  62
  63     PMSMBus smb;
  64     uint32_t smb_io_base;
  65
  66     qemu_irq irq;
  67     qemu_irq cmos_s3;
  68     qemu_irq smi_irq;
  69     int kvm_enabled;
  70
  71     /* for pci hotplug */
  72     struct gpe_regs gpe;
  73     struct pci_status pci0_status;
  74 } PIIX4PMState;
  75
  76 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  77
  78 #define ACPI_ENABLE 0xf1
  79 #define ACPI_DISABLE 0xf0
  80
  81 static uint32_t get_pmtmr(PIIX4PMState *s)
  82 {
  83     uint32_t d;
  84     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
  85     return d & 0xffffff;
  86 }
  87
  88 static int get_pmsts(PIIX4PMState *s)
  89 {
  90     int64_t d;
  91
  92     d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
  93                  get_ticks_per_sec());
  94     if (d >= s->tmr_overflow_time)
  95         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
  96     return s->pmsts;
  97 }
  98
  99 static void pm_update_sci(PIIX4PMState *s)
 100 {
 101     int sci_level, pmsts;
 102     int64_t expire_time;
 103
 104     pmsts = get_pmsts(s);
 105     sci_level = (((pmsts & s->pmen) &
 106                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 107                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 108                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 109                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
 110     qemu_set_irq(s->irq, sci_level);
 111     /* schedule a timer interruption if needed */
 112     if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
 113         !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
 114         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
 115                                PM_TIMER_FREQUENCY);
 116         qemu_mod_timer(s->tmr_timer, expire_time);
 117     } else {
 118         qemu_del_timer(s->tmr_timer);
 119     }
 120 }
 121
 122 static void pm_tmr_timer(void *opaque)
 123 {
 124     PIIX4PMState *s = opaque;
 125     pm_update_sci(s);
 126 }
 127
 128 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 129 {
 130     PIIX4PMState *s = opaque;
 131     addr &= 0x3f;
 132     switch(addr) {
 133     case 0x00:
 134         {
 135             int64_t d;
 136             int pmsts;
 137             pmsts = get_pmsts(s);
 138             if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
 139                 /* if TMRSTS is reset, then compute the new overflow time */
 140                 d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
 141                              get_ticks_per_sec());
 142                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 143             }
 144             s->pmsts &= ~val;
 145             pm_update_sci(s);
 146         }
 147         break;
 148     case 0x02:
 149         s->pmen = val;
 150         pm_update_sci(s);
 151         break;
 152     case 0x04:
 153         {
 154             int sus_typ;
 155             s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
 156             if (val & ACPI_BITMASK_SLEEP_ENABLE) {
 157                 /* change suspend type */
 158                 sus_typ = (val >> 10) & 7;
 159                 switch(sus_typ) {
 160                 case 0: /* soft power off */
 161                     qemu_system_shutdown_request();
 162                     break;
 163                 case 1:
 164                     /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
 165                        Pretend that resume was caused by power button */
 166                     s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
 167                                  ACPI_BITMASK_POWER_BUTTON_STATUS);
 168                     qemu_system_reset_request();
 169                     if (s->cmos_s3) {
 170                         qemu_irq_raise(s->cmos_s3);
 171                     }
 172                 default:
 173                     break;
 174                 }
 175             }
 176         }
 177         break;
 178     default:
 179         break;
 180     }
 181     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
 182 }
 183
 184 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 185 {
 186     PIIX4PMState *s = opaque;
 187     uint32_t val;
 188
 189     addr &= 0x3f;
 190     switch(addr) {
 191     case 0x00:
 192         val = get_pmsts(s);
 193         break;
 194     case 0x02:
 195         val = s->pmen;
 196         break;
 197     case 0x04:
 198         val = s->pmcntrl;
 199         break;
 200     default:
 201         val = 0;
 202         break;
 203     }
 204     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
 205     return val;
 206 }
 207
 208 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 209 {
 210     //    PIIX4PMState *s = opaque;
 211     PIIX4_DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr & 0x3f, val);
 212 }
 213
 214 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 215 {
 216     PIIX4PMState *s = opaque;
 217     uint32_t val;
 218
 219     addr &= 0x3f;
 220     switch(addr) {
 221     case 0x08:
 222         val = get_pmtmr(s);
 223         break;
 224     default:
 225         val = 0;
 226         break;
 227     }
 228     PIIX4_DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
 229     return val;
 230 }
 231
 232 static void apm_ctrl_changed(uint32_t val, void *arg)
 233 {
 234     PIIX4PMState *s = arg;
 235
 236     /* ACPI specs 3.0, 4.7.2.5 */
 237     if (val == ACPI_ENABLE) {
 238         s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
 239     } else if (val == ACPI_DISABLE) {
 240         s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
 241     }
 242
 243     if (s->dev.config[0x5b] & (1 << 1)) {
 244         if (s->smi_irq) {
 245             qemu_irq_raise(s->smi_irq);
 246         }
 247     }
 248 }
 249
 250 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 251 {
 252     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 253 }
 254
 255 static void pm_io_space_update(PIIX4PMState *s)
 256 {
 257     uint32_t pm_io_base;
 258
 259     if (s->dev.config[0x80] & 1) {
 260         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 261         pm_io_base &= 0xffc0;
 262
 263         /* XXX: need to improve memory and ioport allocation */
 264         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 265         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 266         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 267         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 268         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 269     }
 270 }
 271
 272 static void pm_write_config(PCIDevice *d,
 273                             uint32_t address, uint32_t val, int len)
 274 {
 275     pci_default_write_config(d, address, val, len);
 276     if (range_covers_byte(address, len, 0x80))
 277         pm_io_space_update((PIIX4PMState *)d);
 278 }
 279
 280 static int vmstate_acpi_post_load(void *opaque, int version_id)
 281 {
 282     PIIX4PMState *s = opaque;
 283
 284     pm_io_space_update(s);
 285     return 0;
 286 }
 287
 288 static const VMStateDescription vmstate_acpi = {
 289     .name = "piix4_pm",
 290     .version_id = 1,
 291     .minimum_version_id = 1,
 292     .minimum_version_id_old = 1,
 293     .post_load = vmstate_acpi_post_load,
 294     .fields      = (VMStateField []) {
 295         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 296         VMSTATE_UINT16(pmsts, PIIX4PMState),
 297         VMSTATE_UINT16(pmen, PIIX4PMState),
 298         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 299         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 300         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 301         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 302         VMSTATE_END_OF_LIST()
 303     }
 304 };
 305
 306 static void piix4_reset(void *opaque)
 307 {
 308     PIIX4PMState *s = opaque;
 309     uint8_t *pci_conf = s->dev.config;
 310
 311     pci_conf[0x58] = 0;
 312     pci_conf[0x59] = 0;
 313     pci_conf[0x5a] = 0;
 314     pci_conf[0x5b] = 0;
 315
 316     if (s->kvm_enabled) {
 317         /* Mark SMM as already inited (until KVM supports SMM). */
 318         pci_conf[0x5B] = 0x02;
 319     }
 320 }
 321
 322 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 323 {
 324     PIIX4PMState *s = opaque;
 325
 326     if (!s) {
 327         qemu_system_shutdown_request();
 328     } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
 329         s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
 330         pm_update_sci(s);
 331     }
 332 }
 333
 334 static int piix4_pm_initfn(PCIDevice *dev)
 335 {
 336     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 337     uint8_t *pci_conf;
 338
 339     pci_conf = s->dev.config;
 340     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 341     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 342     pci_conf[0x06] = 0x80;
 343     pci_conf[0x07] = 0x02;
 344     pci_conf[0x08] = 0x03; // revision number
 345     pci_conf[0x09] = 0x00;
 346     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 347     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 348     pci_conf[0x3d] = 0x01; // interrupt pin 1
 349
 350     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 351
 352     /* APM */
 353     apm_init(&s->apm, apm_ctrl_changed, s);
 354
 355     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 356
 357     if (s->kvm_enabled) {
 358         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 359          * support SMM mode. */
 360         pci_conf[0x5B] = 0x02;
 361     }
 362
 363     /* XXX: which specification is used ? The i82731AB has different
 364        mappings */
 365     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 366     pci_conf[0x63] = 0x60;
 367     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 368         (serial_hds[1] != NULL ? 0x90 : 0);
 369
 370     pci_conf[0x90] = s->smb_io_base | 1;
 371     pci_conf[0x91] = s->smb_io_base >> 8;
 372     pci_conf[0xd2] = 0x09;
 373     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 374     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 375
 376     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 377
 378     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 379
 380     pm_smbus_init(&s->dev.qdev, &s->smb);
 381     qemu_register_reset(piix4_reset, s);
 382     piix4_acpi_system_hot_add_init(dev->bus, s);
 383
 384     return 0;
 385 }
 386
 387 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 388                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 389                        int kvm_enabled)
 390 {
 391     PCIDevice *dev;
 392     PIIX4PMState *s;
 393
 394     dev = pci_create(bus, devfn, "PIIX4_PM");
 395     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 396
 397     s = DO_UPCAST(PIIX4PMState, dev, dev);
 398     s->irq = sci_irq;
 399     s->cmos_s3 = cmos_s3;
 400     s->smi_irq = smi_irq;
 401     s->kvm_enabled = kvm_enabled;
 402
 403     qdev_init_nofail(&dev->qdev);
 404
 405     return s->smb.smbus;
 406 }
 407
 408 static PCIDeviceInfo piix4_pm_info = {
 409     .qdev.name          = "PIIX4_PM",
 410     .qdev.desc          = "PM",
 411     .qdev.size          = sizeof(PIIX4PMState),
 412     .qdev.vmsd          = &vmstate_acpi,
 413     .init               = piix4_pm_initfn,
 414     .config_write       = pm_write_config,
 415     .qdev.props         = (Property[]) {
 416         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 417         DEFINE_PROP_END_OF_LIST(),
 418     }
 419 };
 420
 421 static void piix4_pm_register(void)
 422 {
 423     pci_qdev_register(&piix4_pm_info);
 424 }
 425
 426 device_init(piix4_pm_register);
 427
 428 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 429 {
 430     if (addr & 1)
 431         return (val >> 8) & 0xff;
 432     return val & 0xff;
 433 }
 434
 435 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 436 {
 437     uint32_t val = 0;
 438     struct gpe_regs *g = opaque;
 439     switch (addr) {
 440         case GPE_BASE:
 441         case GPE_BASE + 1:
 442             val = gpe_read_val(g->sts, addr);
 443             break;
 444         case GPE_BASE + 2:
 445         case GPE_BASE + 3:
 446             val = gpe_read_val(g->en, addr);
 447             break;
 448         default:
 449             break;
 450     }
 451
 452     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 453     return val;
 454 }
 455
 456 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 457 {
 458     if (addr & 1)
 459         *cur = (*cur & 0xff) | (val << 8);
 460     else
 461         *cur = (*cur & 0xff00) | (val & 0xff);
 462 }
 463
 464 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 465 {
 466     uint16_t x1, x0 = val & 0xff;
 467     int shift = (addr & 1) ? 8 : 0;
 468
 469     x1 = (*cur >> shift) & 0xff;
 470
 471     x1 = x1 & ~x0;
 472
 473     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 474 }
 475
 476 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 477 {
 478     struct gpe_regs *g = opaque;
 479     switch (addr) {
 480         case GPE_BASE:
 481         case GPE_BASE + 1:
 482             gpe_reset_val(&g->sts, addr, val);
 483             break;
 484         case GPE_BASE + 2:
 485         case GPE_BASE + 3:
 486             gpe_write_val(&g->en, addr, val);
 487             break;
 488         default:
 489             break;
 490    }
 491
 492     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 493 }
 494
 495 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 496 {
 497     uint32_t val = 0;
 498     struct pci_status *g = opaque;
 499     switch (addr) {
 500         case PCI_BASE:
 501             val = g->up;
 502             break;
 503         case PCI_BASE + 4:
 504             val = g->down;
 505             break;
 506         default:
 507             break;
 508     }
 509
 510     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 511     return val;
 512 }
 513
 514 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 515 {
 516     struct pci_status *g = opaque;
 517     switch (addr) {
 518         case PCI_BASE:
 519             g->up = val;
 520             break;
 521         case PCI_BASE + 4:
 522             g->down = val;
 523             break;
 524    }
 525
 526     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 527 }
 528
 529 static uint32_t pciej_read(void *opaque, uint32_t addr)
 530 {
 531     PIIX4_DPRINTF("pciej read %x\n", addr);
 532     return 0;
 533 }
 534
 535 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 536 {
 537     BusState *bus = opaque;
 538     DeviceState *qdev, *next;
 539     PCIDevice *dev;
 540     int slot = ffs(val) - 1;
 541
 542     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 543         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 544         if (PCI_SLOT(dev->devfn) == slot) {
 545             qdev_free(qdev);
 546         }
 547     }
 548
 549
 550     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 551 }
 552
 553 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state);
 554
 555 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 556 {
 557     struct gpe_regs *gpe = &s->gpe;
 558     struct pci_status *pci0_status = &s->pci0_status;
 559
 560     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe);
 561     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, gpe);
 562
 563     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 564     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 565
 566     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 567     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 568
 569     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 570 }
 571
 572 static void enable_device(PIIX4PMState *s, int slot)
 573 {
 574     s->gpe.sts |= 2;
 575     s->pci0_status.up |= (1 << slot);
 576 }
 577
 578 static void disable_device(PIIX4PMState *s, int slot)
 579 {
 580     s->gpe.sts |= 2;
 581     s->pci0_status.down |= (1 << slot);
 582 }
 583
 584 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, int state)
 585 {
 586     int slot = PCI_SLOT(dev->devfn);
 587     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 588                                 DO_UPCAST(PCIDevice, qdev, qdev));
 589
 590     s->pci0_status.up = 0;
 591     s->pci0_status.down = 0;
 592     if (state) {
 593         enable_device(s, slot);
 594     } else {
 595         disable_device(s, slot);
 596     }
 597     if (s->gpe.en & 2) {
 598         qemu_set_irq(s->irq, 1);
 599         qemu_set_irq(s->irq, 0);
 600     }
 601     return 0;
 602 }