target-arm/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "sysemu/kvm.h"
   4 #include "kvm_arm.h"
   5 #include "internals.h"
   6
   7 static bool vfp_needed(void *opaque)
   8 {
   9     ARMCPU *cpu = opaque;
  10     CPUARMState *env = &cpu->env;
  11
  12     return arm_feature(env, ARM_FEATURE_VFP);
  13 }
  14
  15 static int get_fpscr(QEMUFile *f, void *opaque, size_t size)
  16 {
  17     ARMCPU *cpu = opaque;
  18     CPUARMState *env = &cpu->env;
  19     uint32_t val = qemu_get_be32(f);
  20
  21     vfp_set_fpscr(env, val);
  22     return 0;
  23 }
  24
  25 static void put_fpscr(QEMUFile *f, void *opaque, size_t size)
  26 {
  27     ARMCPU *cpu = opaque;
  28     CPUARMState *env = &cpu->env;
  29
  30     qemu_put_be32(f, vfp_get_fpscr(env));
  31 }
  32
  33 static const VMStateInfo vmstate_fpscr = {
  34     .name = "fpscr",
  35     .get = get_fpscr,
  36     .put = put_fpscr,
  37 };
  38
  39 static const VMStateDescription vmstate_vfp = {
  40     .name = "cpu/vfp",
  41     .version_id = 3,
  42     .minimum_version_id = 3,
  43     .fields = (VMStateField[]) {
  44         VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
  45         /* The xregs array is a little awkward because element 1 (FPSCR)
  46          * requires a specific accessor, so we have to split it up in
  47          * the vmstate:
  48          */
  49         VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU),
  50         VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14),
  51         {
  52             .name = "fpscr",
  53             .version_id = 0,
  54             .size = sizeof(uint32_t),
  55             .info = &vmstate_fpscr,
  56             .flags = VMS_SINGLE,
  57             .offset = 0,
  58         },
  59         VMSTATE_END_OF_LIST()
  60     }
  61 };
  62
  63 static bool iwmmxt_needed(void *opaque)
  64 {
  65     ARMCPU *cpu = opaque;
  66     CPUARMState *env = &cpu->env;
  67
  68     return arm_feature(env, ARM_FEATURE_IWMMXT);
  69 }
  70
  71 static const VMStateDescription vmstate_iwmmxt = {
  72     .name = "cpu/iwmmxt",
  73     .version_id = 1,
  74     .minimum_version_id = 1,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16),
  77         VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16),
  78         VMSTATE_END_OF_LIST()
  79     }
  80 };
  81
  82 static bool m_needed(void *opaque)
  83 {
  84     ARMCPU *cpu = opaque;
  85     CPUARMState *env = &cpu->env;
  86
  87     return arm_feature(env, ARM_FEATURE_M);
  88 }
  89
  90 static const VMStateDescription vmstate_m = {
  91     .name = "cpu/m",
  92     .version_id = 1,
  93     .minimum_version_id = 1,
  94     .fields = (VMStateField[]) {
  95         VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
  96         VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
  97         VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
  98         VMSTATE_UINT32(env.v7m.control, ARMCPU),
  99         VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
 100         VMSTATE_INT32(env.v7m.exception, ARMCPU),
 101         VMSTATE_END_OF_LIST()
 102     }
 103 };
 104
 105 static bool thumb2ee_needed(void *opaque)
 106 {
 107     ARMCPU *cpu = opaque;
 108     CPUARMState *env = &cpu->env;
 109
 110     return arm_feature(env, ARM_FEATURE_THUMB2EE);
 111 }
 112
 113 static const VMStateDescription vmstate_thumb2ee = {
 114     .name = "cpu/thumb2ee",
 115     .version_id = 1,
 116     .minimum_version_id = 1,
 117     .fields = (VMStateField[]) {
 118         VMSTATE_UINT32(env.teecr, ARMCPU),
 119         VMSTATE_UINT32(env.teehbr, ARMCPU),
 120         VMSTATE_END_OF_LIST()
 121     }
 122 };
 123
 124 static int get_cpsr(QEMUFile *f, void *opaque, size_t size)
 125 {
 126     ARMCPU *cpu = opaque;
 127     CPUARMState *env = &cpu->env;
 128     uint32_t val = qemu_get_be32(f);
 129
 130     /* Avoid mode switch when restoring CPSR */
 131     env->uncached_cpsr = val & CPSR_M;
 132     cpsr_write(env, val, 0xffffffff);
 133     return 0;
 134 }
 135
 136 static void put_cpsr(QEMUFile *f, void *opaque, size_t size)
 137 {
 138     ARMCPU *cpu = opaque;
 139     CPUARMState *env = &cpu->env;
 140
 141     qemu_put_be32(f, cpsr_read(env));
 142 }
 143
 144 static const VMStateInfo vmstate_cpsr = {
 145     .name = "cpsr",
 146     .get = get_cpsr,
 147     .put = put_cpsr,
 148 };
 149
 150 static void cpu_pre_save(void *opaque)
 151 {
 152     ARMCPU *cpu = opaque;
 153
 154     if (kvm_enabled()) {
 155         if (!write_kvmstate_to_list(cpu)) {
 156             /* This should never fail */
 157             abort();
 158         }
 159     } else {
 160         if (!write_cpustate_to_list(cpu)) {
 161             /* This should never fail. */
 162             abort();
 163         }
 164     }
 165
 166     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 167     memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes,
 168            cpu->cpreg_array_len * sizeof(uint64_t));
 169     memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values,
 170            cpu->cpreg_array_len * sizeof(uint64_t));
 171 }
 172
 173 static int cpu_post_load(void *opaque, int version_id)
 174 {
 175     ARMCPU *cpu = opaque;
 176     int i, v;
 177
 178     /* Update the values list from the incoming migration data.
 179      * Anything in the incoming data which we don't know about is
 180      * a migration failure; anything we know about but the incoming
 181      * data doesn't specify retains its current (reset) value.
 182      * The indexes list remains untouched -- we only inspect the
 183      * incoming migration index list so we can match the values array
 184      * entries with the right slots in our own values array.
 185      */
 186
 187     for (i = 0, v = 0; i < cpu->cpreg_array_len
 188              && v < cpu->cpreg_vmstate_array_len; i++) {
 189         if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) {
 190             /* register in our list but not incoming : skip it */
 191             continue;
 192         }
 193         if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) {
 194             /* register in their list but not ours: fail migration */
 195             return -1;
 196         }
 197         /* matching register, copy the value over */
 198         cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v];
 199         v++;
 200     }
 201
 202     if (kvm_enabled()) {
 203         if (!write_list_to_kvmstate(cpu)) {
 204             return -1;
 205         }
 206         /* Note that it's OK for the TCG side not to know about
 207          * every register in the list; KVM is authoritative if
 208          * we're using it.
 209          */
 210         write_list_to_cpustate(cpu);
 211     } else {
 212         if (!write_list_to_cpustate(cpu)) {
 213             return -1;
 214         }
 215     }
 216
 217     hw_breakpoint_update_all(cpu);
 218     hw_watchpoint_update_all(cpu);
 219
 220     return 0;
 221 }
 222
 223 const VMStateDescription vmstate_arm_cpu = {
 224     .name = "cpu",
 225     .version_id = 20,
 226     .minimum_version_id = 20,
 227     .pre_save = cpu_pre_save,
 228     .post_load = cpu_post_load,
 229     .fields = (VMStateField[]) {
 230         VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16),
 231         {
 232             .name = "cpsr",
 233             .version_id = 0,
 234             .size = sizeof(uint32_t),
 235             .info = &vmstate_cpsr,
 236             .flags = VMS_SINGLE,
 237             .offset = 0,
 238         },
 239         VMSTATE_UINT32(env.spsr, ARMCPU),
 240         VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
 241         VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
 242         VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
 243         VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
 244         VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
 245         VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4),
 246         VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
 247         /* The length-check must come before the arrays to avoid
 248          * incoming data possibly overflowing the array.
 249          */
 250         VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU),
 251         VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU,
 252                              cpreg_vmstate_array_len,
 253                              0, vmstate_info_uint64, uint64_t),
 254         VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU,
 255                              cpreg_vmstate_array_len,
 256                              0, vmstate_info_uint64, uint64_t),
 257         VMSTATE_UINT64(env.exclusive_addr, ARMCPU),
 258         VMSTATE_UINT64(env.exclusive_val, ARMCPU),
 259         VMSTATE_UINT64(env.exclusive_high, ARMCPU),
 260         VMSTATE_UINT64(env.features, ARMCPU),
 261         VMSTATE_UINT32(env.exception.syndrome, ARMCPU),
 262         VMSTATE_UINT32(env.exception.fsr, ARMCPU),
 263         VMSTATE_UINT64(env.exception.vaddress, ARMCPU),
 264         VMSTATE_TIMER(gt_timer[GTIMER_PHYS], ARMCPU),
 265         VMSTATE_TIMER(gt_timer[GTIMER_VIRT], ARMCPU),
 266         VMSTATE_END_OF_LIST()
 267     },
 268     .subsections = (VMStateSubsection[]) {
 269         {
 270             .vmsd = &vmstate_vfp,
 271             .needed = vfp_needed,
 272         } , {
 273             .vmsd = &vmstate_iwmmxt,
 274             .needed = iwmmxt_needed,
 275         } , {
 276             .vmsd = &vmstate_m,
 277             .needed = m_needed,
 278         } , {
 279             .vmsd = &vmstate_thumb2ee,
 280             .needed = thumb2ee_needed,
 281         } , {
 282             /* empty */
 283         }
 284     }
 285 };