hw/i2c/ppc4xx_i2c.c

   1 /*
   2  * PPC4xx I2C controller emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  * Copyright (c) 2012 François Revol
   6  * Copyright (c) 2016 BALATON Zoltan
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "qapi/error.h"
  29 #include "qemu-common.h"
  30 #include "qemu/log.h"
  31 #include "cpu.h"
  32 #include "hw/hw.h"
  33 #include "hw/i2c/ppc4xx_i2c.h"
  34
  35 #define PPC4xx_I2C_MEM_SIZE 0x12
  36
  37 #define IIC_CNTL_PT         (1 << 0)
  38 #define IIC_CNTL_READ       (1 << 1)
  39 #define IIC_CNTL_CHT        (1 << 2)
  40 #define IIC_CNTL_RPST       (1 << 3)
  41
  42 #define IIC_STS_PT          (1 << 0)
  43 #define IIC_STS_ERR         (1 << 2)
  44 #define IIC_STS_MDBS        (1 << 5)
  45
  46 #define IIC_EXTSTS_XFRA     (1 << 0)
  47
  48 #define IIC_XTCNTLSS_SRST   (1 << 0)
  49
  50 static void ppc4xx_i2c_reset(DeviceState *s)
  51 {
  52     PPC4xxI2CState *i2c = PPC4xx_I2C(s);
  53
  54     /* FIXME: Should also reset bus?
  55      *if (s->address != ADDR_RESET) {
  56      *    i2c_end_transfer(s->bus);
  57      *}
  58      */
  59
  60     i2c->mdata = 0;
  61     i2c->lmadr = 0;
  62     i2c->hmadr = 0;
  63     i2c->cntl = 0;
  64     i2c->mdcntl = 0;
  65     i2c->sts = 0;
  66     i2c->extsts = 0x8f;
  67     i2c->sdata = 0;
  68     i2c->lsadr = 0;
  69     i2c->hsadr = 0;
  70     i2c->clkdiv = 0;
  71     i2c->intrmsk = 0;
  72     i2c->xfrcnt = 0;
  73     i2c->xtcntlss = 0;
  74     i2c->directcntl = 0x0f;
  75     i2c->intr = 0;
  76 }
  77
  78 static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c)
  79 {
  80     return true;
  81 }
  82
  83 static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
  84 {
  85     PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);
  86     uint64_t ret;
  87
  88     switch (addr) {
  89     case 0x00:
  90         ret = i2c->mdata;
  91         if (ppc4xx_i2c_is_master(i2c)) {
  92             ret = 0xff;
  93
  94             if (!(i2c->sts & IIC_STS_MDBS)) {
  95                 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
  96                               "without starting transfer\n",
  97                               TYPE_PPC4xx_I2C, __func__);
  98             } else {
  99                 int pending = (i2c->cntl >> 4) & 3;
 100
 101                 /* get the next byte */
 102                 int byte = i2c_recv(i2c->bus);
 103
 104                 if (byte < 0) {
 105                     qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "
 106                                   "for device 0x%02x\n", TYPE_PPC4xx_I2C,
 107                                   __func__, i2c->lmadr);
 108                     ret = 0xff;
 109                 } else {
 110                     ret = byte;
 111                     /* Raise interrupt if enabled */
 112                     /*ppc4xx_i2c_raise_interrupt(i2c)*/;
 113                 }
 114
 115                 if (!pending) {
 116                     i2c->sts &= ~IIC_STS_MDBS;
 117                     /*i2c_end_transfer(i2c->bus);*/
 118                 /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/
 119                 } else if (pending) {
 120                     /* current smbus implementation doesn't like
 121                        multibyte xfer repeated start */
 122                     i2c_end_transfer(i2c->bus);
 123                     if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {
 124                         /* if non zero is returned, the adress is not valid */
 125                         i2c->sts &= ~IIC_STS_PT;
 126                         i2c->sts |= IIC_STS_ERR;
 127                         i2c->extsts |= IIC_EXTSTS_XFRA;
 128                     } else {
 129                         /*i2c->sts |= IIC_STS_PT;*/
 130                         i2c->sts |= IIC_STS_MDBS;
 131                         i2c->sts &= ~IIC_STS_ERR;
 132                         i2c->extsts = 0;
 133                     }
 134                 }
 135                 pending--;
 136                 i2c->cntl = (i2c->cntl & 0xcf) | (pending << 4);
 137             }
 138         } else {
 139             qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
 140                           TYPE_PPC4xx_I2C, __func__);
 141         }
 142         break;
 143     case 0x02:
 144         ret = i2c->sdata;
 145         break;
 146     case 0x04:
 147         ret = i2c->lmadr;
 148         break;
 149     case 0x05:
 150         ret = i2c->hmadr;
 151         break;
 152     case 0x06:
 153         ret = i2c->cntl;
 154         break;
 155     case 0x07:
 156         ret = i2c->mdcntl;
 157         break;
 158     case 0x08:
 159         ret = i2c->sts;
 160         break;
 161     case 0x09:
 162         ret = i2c->extsts;
 163         break;
 164     case 0x0A:
 165         ret = i2c->lsadr;
 166         break;
 167     case 0x0B:
 168         ret = i2c->hsadr;
 169         break;
 170     case 0x0C:
 171         ret = i2c->clkdiv;
 172         break;
 173     case 0x0D:
 174         ret = i2c->intrmsk;
 175         break;
 176     case 0x0E:
 177         ret = i2c->xfrcnt;
 178         break;
 179     case 0x0F:
 180         ret = i2c->xtcntlss;
 181         break;
 182     case 0x10:
 183         ret = i2c->directcntl;
 184         break;
 185     case 0x11:
 186         ret = i2c->intr;
 187         break;
 188     default:
 189         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
 190                       HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr);
 191         ret = 0;
 192         break;
 193     }
 194
 195     return ret;
 196 }
 197
 198 static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
 199                               unsigned int size)
 200 {
 201     PPC4xxI2CState *i2c = opaque;
 202
 203     switch (addr) {
 204     case 0x00:
 205         i2c->mdata = value;
 206         if (!i2c_bus_busy(i2c->bus)) {
 207             /* assume we start a write transfer */
 208             if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) {
 209                 /* if non zero is returned, the adress is not valid */
 210                 i2c->sts &= ~IIC_STS_PT;
 211                 i2c->sts |= IIC_STS_ERR;
 212                 i2c->extsts |= IIC_EXTSTS_XFRA;
 213             } else {
 214                 i2c->sts |= IIC_STS_PT;
 215                 i2c->sts &= ~IIC_STS_ERR;
 216                 i2c->extsts = 0;
 217             }
 218         }
 219         if (i2c_bus_busy(i2c->bus)) {
 220             if (i2c_send(i2c->bus, i2c->mdata)) {
 221                 /* if the target return non zero then end the transfer */
 222                 i2c->sts &= ~IIC_STS_PT;
 223                 i2c->sts |= IIC_STS_ERR;
 224                 i2c->extsts |= IIC_EXTSTS_XFRA;
 225                 i2c_end_transfer(i2c->bus);
 226             }
 227         }
 228         break;
 229     case 0x02:
 230         i2c->sdata = value;
 231         break;
 232     case 0x04:
 233         i2c->lmadr = value;
 234         if (i2c_bus_busy(i2c->bus)) {
 235             i2c_end_transfer(i2c->bus);
 236         }
 237         break;
 238     case 0x05:
 239         i2c->hmadr = value;
 240         break;
 241     case 0x06:
 242         i2c->cntl = value;
 243         if (i2c->cntl & IIC_CNTL_PT) {
 244             if (i2c->cntl & IIC_CNTL_READ) {
 245                 if (i2c_bus_busy(i2c->bus)) {
 246                     /* end previous transfer */
 247                     i2c->sts &= ~IIC_STS_PT;
 248                     i2c_end_transfer(i2c->bus);
 249                 }
 250                 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {
 251                     /* if non zero is returned, the adress is not valid */
 252                     i2c->sts &= ~IIC_STS_PT;
 253                     i2c->sts |= IIC_STS_ERR;
 254                     i2c->extsts |= IIC_EXTSTS_XFRA;
 255                 } else {
 256                     /*i2c->sts |= IIC_STS_PT;*/
 257                     i2c->sts |= IIC_STS_MDBS;
 258                     i2c->sts &= ~IIC_STS_ERR;
 259                     i2c->extsts = 0;
 260                 }
 261             } else {
 262                 /* we actually already did the write transfer... */
 263                 i2c->sts &= ~IIC_STS_PT;
 264             }
 265         }
 266         break;
 267     case 0x07:
 268         i2c->mdcntl = value & 0xDF;
 269         break;
 270     case 0x08:
 271         i2c->sts &= ~(value & 0x0A);
 272         break;
 273     case 0x09:
 274         i2c->extsts &= ~(value & 0x8F);
 275         break;
 276     case 0x0A:
 277         i2c->lsadr = value;
 278         /*i2c_set_slave_address(i2c->bus, i2c->lsadr);*/
 279         break;
 280     case 0x0B:
 281         i2c->hsadr = value;
 282         break;
 283     case 0x0C:
 284         i2c->clkdiv = value;
 285         break;
 286     case 0x0D:
 287         i2c->intrmsk = value;
 288         break;
 289     case 0x0E:
 290         i2c->xfrcnt = value & 0x77;
 291         break;
 292     case 0x0F:
 293         if (value & IIC_XTCNTLSS_SRST) {
 294             /* Is it actually a full reset? U-Boot sets some regs before */
 295             ppc4xx_i2c_reset(DEVICE(i2c));
 296             break;
 297         }
 298         i2c->xtcntlss = value;
 299         break;
 300     case 0x10:
 301         i2c->directcntl = value & 0x7;
 302         break;
 303     case 0x11:
 304         i2c->intr = value;
 305         break;
 306     default:
 307         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%"
 308                       HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr);
 309         break;
 310     }
 311 }
 312
 313 static const MemoryRegionOps ppc4xx_i2c_ops = {
 314     .read = ppc4xx_i2c_readb,
 315     .write = ppc4xx_i2c_writeb,
 316     .valid.min_access_size = 1,
 317     .valid.max_access_size = 4,
 318     .impl.min_access_size = 1,
 319     .impl.max_access_size = 1,
 320     .endianness = DEVICE_NATIVE_ENDIAN,
 321 };
 322
 323 static void ppc4xx_i2c_init(Object *o)
 324 {
 325     PPC4xxI2CState *s = PPC4xx_I2C(o);
 326
 327     memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
 328                           TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
 329     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 330     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
 331     s->bus = i2c_init_bus(DEVICE(s), "i2c");
 332 }
 333
 334 static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
 335 {
 336     DeviceClass *dc = DEVICE_CLASS(klass);
 337
 338     dc->reset = ppc4xx_i2c_reset;
 339 }
 340
 341 static const TypeInfo ppc4xx_i2c_type_info = {
 342     .name = TYPE_PPC4xx_I2C,
 343     .parent = TYPE_SYS_BUS_DEVICE,
 344     .instance_size = sizeof(PPC4xxI2CState),
 345     .instance_init = ppc4xx_i2c_init,
 346     .class_init = ppc4xx_i2c_class_init,
 347 };
 348
 349 static void ppc4xx_i2c_register_types(void)
 350 {
 351     type_register_static(&ppc4xx_i2c_type_info);
 352 }
 353
 354 type_init(ppc4xx_i2c_register_types)