hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "prep_pci.h"
  33 #include "usb-ohci.h"
  34 #include "ppc.h"
  35 #include "boards.h"
  36 #include "qemu-log.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "mc146818rtc.h"
  40 #include "blockdev.h"
  41
  42 //#define HARD_DEBUG_PPC_IO
  43 //#define DEBUG_PPC_IO
  44
  45 /* SMP is not enabled, for now */
  46 #define MAX_CPUS 1
  47
  48 #define MAX_IDE_BUS 2
  49
  50 #define BIOS_SIZE (1024 * 1024)
  51 #define BIOS_FILENAME "ppc_rom.bin"
  52 #define KERNEL_LOAD_ADDR 0x01000000
  53 #define INITRD_LOAD_ADDR 0x01800000
  54
  55 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  56 #define DEBUG_PPC_IO
  57 #endif
  58
  59 #if defined (HARD_DEBUG_PPC_IO)
  60 #define PPC_IO_DPRINTF(fmt, ...)                         \
  61 do {                                                     \
  62     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  63         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  64     } else {                                             \
  65         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  66     }                                                    \
  67 } while (0)
  68 #elif defined (DEBUG_PPC_IO)
  69 #define PPC_IO_DPRINTF(fmt, ...) \
  70 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  71 #else
  72 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  73 #endif
  74
  75 /* Constants for devices init */
  76 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  77 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  78 static const int ide_irq[2] = { 13, 13 };
  79
  80 #define NE2000_NB_MAX 6
  81
  82 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  83 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  84
  85 //static PITState *pit;
  86
  87 /* ISA IO ports bridge */
  88 #define PPC_IO_BASE 0x80000000
  89
  90 #if 0
  91 /* Speaker port 0x61 */
  92 static int speaker_data_on;
  93 static int dummy_refresh_clock;
  94 #endif
  95
  96 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  97 {
  98 #if 0
  99     speaker_data_on = (val >> 1) & 1;
 100     pit_set_gate(pit, 2, val & 1);
 101 #endif
 102 }
 103
 104 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
 105 {
 106 #if 0
 107     int out;
 108     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
 109     dummy_refresh_clock ^= 1;
 110     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 111         (dummy_refresh_clock << 4);
 112 #endif
 113     return 0;
 114 }
 115
 116 /* PCI intack register */
 117 /* Read-only register (?) */
 118 static void _PPC_intack_write (void *opaque,
 119                                target_phys_addr_t addr, uint32_t value)
 120 {
 121 #if 0
 122     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 123            value);
 124 #endif
 125 }
 126
 127 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
 128 {
 129     uint32_t retval = 0;
 130
 131     if ((addr & 0xf) == 0)
 132         retval = pic_intack_read(isa_pic);
 133 #if 0
 134     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 135            retval);
 136 #endif
 137
 138     return retval;
 139 }
 140
 141 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 142 {
 143     return _PPC_intack_read(addr);
 144 }
 145
 146 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 147 {
 148     return _PPC_intack_read(addr);
 149 }
 150
 151 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 152 {
 153     return _PPC_intack_read(addr);
 154 }
 155
 156 static CPUWriteMemoryFunc * const PPC_intack_write[] = {
 157     &_PPC_intack_write,
 158     &_PPC_intack_write,
 159     &_PPC_intack_write,
 160 };
 161
 162 static CPUReadMemoryFunc * const PPC_intack_read[] = {
 163     &PPC_intack_readb,
 164     &PPC_intack_readw,
 165     &PPC_intack_readl,
 166 };
 167
 168 /* PowerPC control and status registers */
 169 #if 0 // Not used
 170 static struct {
 171     /* IDs */
 172     uint32_t veni_devi;
 173     uint32_t revi;
 174     /* Control and status */
 175     uint32_t gcsr;
 176     uint32_t xcfr;
 177     uint32_t ct32;
 178     uint32_t mcsr;
 179     /* General purpose registers */
 180     uint32_t gprg[6];
 181     /* Exceptions */
 182     uint32_t feen;
 183     uint32_t fest;
 184     uint32_t fema;
 185     uint32_t fecl;
 186     uint32_t eeen;
 187     uint32_t eest;
 188     uint32_t eecl;
 189     uint32_t eeint;
 190     uint32_t eemck0;
 191     uint32_t eemck1;
 192     /* Error diagnostic */
 193 } XCSR;
 194
 195 static void PPC_XCSR_writeb (void *opaque,
 196                              target_phys_addr_t addr, uint32_t value)
 197 {
 198     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 199            value);
 200 }
 201
 202 static void PPC_XCSR_writew (void *opaque,
 203                              target_phys_addr_t addr, uint32_t value)
 204 {
 205     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 206            value);
 207 }
 208
 209 static void PPC_XCSR_writel (void *opaque,
 210                              target_phys_addr_t addr, uint32_t value)
 211 {
 212     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 213            value);
 214 }
 215
 216 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 217 {
 218     uint32_t retval = 0;
 219
 220     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 221            retval);
 222
 223     return retval;
 224 }
 225
 226 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 227 {
 228     uint32_t retval = 0;
 229
 230     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 231            retval);
 232
 233     return retval;
 234 }
 235
 236 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 237 {
 238     uint32_t retval = 0;
 239
 240     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 241            retval);
 242
 243     return retval;
 244 }
 245
 246 static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
 247     &PPC_XCSR_writeb,
 248     &PPC_XCSR_writew,
 249     &PPC_XCSR_writel,
 250 };
 251
 252 static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
 253     &PPC_XCSR_readb,
 254     &PPC_XCSR_readw,
 255     &PPC_XCSR_readl,
 256 };
 257 #endif
 258
 259 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 260 typedef struct sysctrl_t {
 261     qemu_irq reset_irq;
 262     M48t59State *nvram;
 263     uint8_t state;
 264     uint8_t syscontrol;
 265     uint8_t fake_io[2];
 266     int contiguous_map;
 267     int endian;
 268 } sysctrl_t;
 269
 270 enum {
 271     STATE_HARDFILE = 0x01,
 272 };
 273
 274 static sysctrl_t *sysctrl;
 275
 276 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 277 {
 278     sysctrl_t *sysctrl = opaque;
 279
 280     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 281                    val);
 282     sysctrl->fake_io[addr - 0x0398] = val;
 283 }
 284
 285 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 286 {
 287     sysctrl_t *sysctrl = opaque;
 288
 289     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 290                    sysctrl->fake_io[addr - 0x0398]);
 291     return sysctrl->fake_io[addr - 0x0398];
 292 }
 293
 294 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 295 {
 296     sysctrl_t *sysctrl = opaque;
 297
 298     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 299                    addr - PPC_IO_BASE, val);
 300     switch (addr) {
 301     case 0x0092:
 302         /* Special port 92 */
 303         /* Check soft reset asked */
 304         if (val & 0x01) {
 305             qemu_irq_raise(sysctrl->reset_irq);
 306         } else {
 307             qemu_irq_lower(sysctrl->reset_irq);
 308         }
 309         /* Check LE mode */
 310         if (val & 0x02) {
 311             sysctrl->endian = 1;
 312         } else {
 313             sysctrl->endian = 0;
 314         }
 315         break;
 316     case 0x0800:
 317         /* Motorola CPU configuration register : read-only */
 318         break;
 319     case 0x0802:
 320         /* Motorola base module feature register : read-only */
 321         break;
 322     case 0x0803:
 323         /* Motorola base module status register : read-only */
 324         break;
 325     case 0x0808:
 326         /* Hardfile light register */
 327         if (val & 1)
 328             sysctrl->state |= STATE_HARDFILE;
 329         else
 330             sysctrl->state &= ~STATE_HARDFILE;
 331         break;
 332     case 0x0810:
 333         /* Password protect 1 register */
 334         if (sysctrl->nvram != NULL)
 335             m48t59_toggle_lock(sysctrl->nvram, 1);
 336         break;
 337     case 0x0812:
 338         /* Password protect 2 register */
 339         if (sysctrl->nvram != NULL)
 340             m48t59_toggle_lock(sysctrl->nvram, 2);
 341         break;
 342     case 0x0814:
 343         /* L2 invalidate register */
 344         //        tlb_flush(first_cpu, 1);
 345         break;
 346     case 0x081C:
 347         /* system control register */
 348         sysctrl->syscontrol = val & 0x0F;
 349         break;
 350     case 0x0850:
 351         /* I/O map type register */
 352         sysctrl->contiguous_map = val & 0x01;
 353         break;
 354     default:
 355         printf("ERROR: unaffected IO port write: %04" PRIx32
 356                " => %02" PRIx32"\n", addr, val);
 357         break;
 358     }
 359 }
 360
 361 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 362 {
 363     sysctrl_t *sysctrl = opaque;
 364     uint32_t retval = 0xFF;
 365
 366     switch (addr) {
 367     case 0x0092:
 368         /* Special port 92 */
 369         retval = 0x00;
 370         break;
 371     case 0x0800:
 372         /* Motorola CPU configuration register */
 373         retval = 0xEF; /* MPC750 */
 374         break;
 375     case 0x0802:
 376         /* Motorola Base module feature register */
 377         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 378         break;
 379     case 0x0803:
 380         /* Motorola base module status register */
 381         retval = 0xE0; /* Standard MPC750 */
 382         break;
 383     case 0x080C:
 384         /* Equipment present register:
 385          *  no L2 cache
 386          *  no upgrade processor
 387          *  no cards in PCI slots
 388          *  SCSI fuse is bad
 389          */
 390         retval = 0x3C;
 391         break;
 392     case 0x0810:
 393         /* Motorola base module extended feature register */
 394         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 395         break;
 396     case 0x0814:
 397         /* L2 invalidate: don't care */
 398         break;
 399     case 0x0818:
 400         /* Keylock */
 401         retval = 0x00;
 402         break;
 403     case 0x081C:
 404         /* system control register
 405          * 7 - 6 / 1 - 0: L2 cache enable
 406          */
 407         retval = sysctrl->syscontrol;
 408         break;
 409     case 0x0823:
 410         /* */
 411         retval = 0x03; /* no L2 cache */
 412         break;
 413     case 0x0850:
 414         /* I/O map type register */
 415         retval = sysctrl->contiguous_map;
 416         break;
 417     default:
 418         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 419         break;
 420     }
 421     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 422                    addr - PPC_IO_BASE, retval);
 423
 424     return retval;
 425 }
 426
 427 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 428                                                  target_phys_addr_t addr)
 429 {
 430     if (sysctrl->contiguous_map == 0) {
 431         /* 64 KB contiguous space for IOs */
 432         addr &= 0xFFFF;
 433     } else {
 434         /* 8 MB non-contiguous space for IOs */
 435         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 436     }
 437
 438     return addr;
 439 }
 440
 441 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 442                                 uint32_t value)
 443 {
 444     sysctrl_t *sysctrl = opaque;
 445
 446     addr = prep_IO_address(sysctrl, addr);
 447     cpu_outb(addr, value);
 448 }
 449
 450 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 451 {
 452     sysctrl_t *sysctrl = opaque;
 453     uint32_t ret;
 454
 455     addr = prep_IO_address(sysctrl, addr);
 456     ret = cpu_inb(addr);
 457
 458     return ret;
 459 }
 460
 461 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 462                                 uint32_t value)
 463 {
 464     sysctrl_t *sysctrl = opaque;
 465
 466     addr = prep_IO_address(sysctrl, addr);
 467     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 468     cpu_outw(addr, value);
 469 }
 470
 471 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 472 {
 473     sysctrl_t *sysctrl = opaque;
 474     uint32_t ret;
 475
 476     addr = prep_IO_address(sysctrl, addr);
 477     ret = cpu_inw(addr);
 478     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 479
 480     return ret;
 481 }
 482
 483 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 484                                 uint32_t value)
 485 {
 486     sysctrl_t *sysctrl = opaque;
 487
 488     addr = prep_IO_address(sysctrl, addr);
 489     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 490     cpu_outl(addr, value);
 491 }
 492
 493 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 494 {
 495     sysctrl_t *sysctrl = opaque;
 496     uint32_t ret;
 497
 498     addr = prep_IO_address(sysctrl, addr);
 499     ret = cpu_inl(addr);
 500     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 501
 502     return ret;
 503 }
 504
 505 static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
 506     &PPC_prep_io_writeb,
 507     &PPC_prep_io_writew,
 508     &PPC_prep_io_writel,
 509 };
 510
 511 static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
 512     &PPC_prep_io_readb,
 513     &PPC_prep_io_readw,
 514     &PPC_prep_io_readl,
 515 };
 516
 517 #define NVRAM_SIZE        0x2000
 518
 519 static void cpu_request_exit(void *opaque, int irq, int level)
 520 {
 521     CPUState *env = cpu_single_env;
 522
 523     if (env && level) {
 524         cpu_exit(env);
 525     }
 526 }
 527
 528 /* PowerPC PREP hardware initialisation */
 529 static void ppc_prep_init (ram_addr_t ram_size,
 530                            const char *boot_device,
 531                            const char *kernel_filename,
 532                            const char *kernel_cmdline,
 533                            const char *initrd_filename,
 534                            const char *cpu_model)
 535 {
 536     CPUState *env = NULL;
 537     char *filename;
 538     nvram_t nvram;
 539     M48t59State *m48t59;
 540     int PPC_io_memory;
 541     int linux_boot, i, nb_nics1, bios_size;
 542     ram_addr_t ram_offset, bios_offset;
 543     uint32_t kernel_base, initrd_base;
 544     long kernel_size, initrd_size;
 545     PCIBus *pci_bus;
 546     qemu_irq *i8259;
 547     qemu_irq *cpu_exit_irq;
 548     int ppc_boot_device;
 549     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 550     DriveInfo *fd[MAX_FD];
 551
 552     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 553
 554     linux_boot = (kernel_filename != NULL);
 555
 556     /* init CPUs */
 557     if (cpu_model == NULL)
 558         cpu_model = "602";
 559     for (i = 0; i < smp_cpus; i++) {
 560         env = cpu_init(cpu_model);
 561         if (!env) {
 562             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 563             exit(1);
 564         }
 565         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 566             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 567             cpu_ppc_tb_init(env, 7812500UL);
 568         } else {
 569             /* Set time-base frequency to 100 Mhz */
 570             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 571         }
 572         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 573     }
 574
 575     /* allocate RAM */
 576     ram_offset = qemu_ram_alloc(NULL, "ppc_prep.ram", ram_size);
 577     cpu_register_physical_memory(0, ram_size, ram_offset);
 578
 579     /* allocate and load BIOS */
 580     bios_offset = qemu_ram_alloc(NULL, "ppc_prep.bios", BIOS_SIZE);
 581     if (bios_name == NULL)
 582         bios_name = BIOS_FILENAME;
 583     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 584     if (filename) {
 585         bios_size = get_image_size(filename);
 586     } else {
 587         bios_size = -1;
 588     }
 589     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 590         target_phys_addr_t bios_addr;
 591         bios_size = (bios_size + 0xfff) & ~0xfff;
 592         bios_addr = (uint32_t)(-bios_size);
 593         cpu_register_physical_memory(bios_addr, bios_size,
 594                                      bios_offset | IO_MEM_ROM);
 595         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 596     }
 597     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 598         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 599     }
 600     if (filename) {
 601         qemu_free(filename);
 602     }
 603
 604     if (linux_boot) {
 605         kernel_base = KERNEL_LOAD_ADDR;
 606         /* now we can load the kernel */
 607         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 608                                           ram_size - kernel_base);
 609         if (kernel_size < 0) {
 610             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 611             exit(1);
 612         }
 613         /* load initrd */
 614         if (initrd_filename) {
 615             initrd_base = INITRD_LOAD_ADDR;
 616             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 617                                               ram_size - initrd_base);
 618             if (initrd_size < 0) {
 619                 hw_error("qemu: could not load initial ram disk '%s'\n",
 620                           initrd_filename);
 621             }
 622         } else {
 623             initrd_base = 0;
 624             initrd_size = 0;
 625         }
 626         ppc_boot_device = 'm';
 627     } else {
 628         kernel_base = 0;
 629         kernel_size = 0;
 630         initrd_base = 0;
 631         initrd_size = 0;
 632         ppc_boot_device = '\0';
 633         /* For now, OHW cannot boot from the network. */
 634         for (i = 0; boot_device[i] != '\0'; i++) {
 635             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 636                 ppc_boot_device = boot_device[i];
 637                 break;
 638             }
 639         }
 640         if (ppc_boot_device == '\0') {
 641             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 642             exit(1);
 643         }
 644     }
 645
 646     isa_mem_base = 0xc0000000;
 647     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 648         hw_error("Only 6xx bus is supported on PREP machine\n");
 649     }
 650     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 651     pci_bus = pci_prep_init(i8259);
 652     /* Hmm, prep has no pci-isa bridge ??? */
 653     isa_bus_new(NULL);
 654     isa_bus_irqs(i8259);
 655     //    pci_bus = i440fx_init();
 656     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 657     PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
 658                                            PPC_prep_io_write, sysctrl,
 659                                            DEVICE_LITTLE_ENDIAN);
 660     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 661
 662     /* init basic PC hardware */
 663     pci_vga_init(pci_bus);
 664     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 665     //    pit = pit_init(0x40, i8259[0]);
 666     rtc_init(2000, NULL);
 667
 668     if (serial_hds[0])
 669         serial_isa_init(0, serial_hds[0]);
 670     nb_nics1 = nb_nics;
 671     if (nb_nics1 > NE2000_NB_MAX)
 672         nb_nics1 = NE2000_NB_MAX;
 673     for(i = 0; i < nb_nics1; i++) {
 674         if (nd_table[i].model == NULL) {
 675             nd_table[i].model = qemu_strdup("ne2k_isa");
 676         }
 677         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 678             isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
 679         } else {
 680             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 681         }
 682     }
 683
 684     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 685         fprintf(stderr, "qemu: too many IDE bus\n");
 686         exit(1);
 687     }
 688
 689     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 690         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 691     }
 692
 693     for(i = 0; i < 1/*MAX_IDE_BUS*/; i++) {
 694         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 695                      hd[2 * i],
 696                      hd[2 * i + 1]);
 697     }
 698     isa_create_simple("i8042");
 699
 700     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 701     DMA_init(1, cpu_exit_irq);
 702
 703     //    SB16_init();
 704
 705     for(i = 0; i < MAX_FD; i++) {
 706         fd[i] = drive_get(IF_FLOPPY, 0, i);
 707     }
 708     fdctrl_init_isa(fd);
 709
 710     /* Register speaker port */
 711     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 712     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 713     /* Register fake IO ports for PREP */
 714     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 715     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 716     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 717     /* System control ports */
 718     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 719     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 720     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 721     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 722     /* PCI intack location */
 723     PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
 724                                            PPC_intack_write, NULL,
 725                                            DEVICE_LITTLE_ENDIAN);
 726     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 727     /* PowerPC control and status register group */
 728 #if 0
 729     PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
 730                                            NULL, DEVICE_LITTLE_ENDIAN);
 731     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 732 #endif
 733
 734     if (usb_enabled) {
 735         usb_ohci_init_pci(pci_bus, -1);
 736     }
 737
 738     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 739     if (m48t59 == NULL)
 740         return;
 741     sysctrl->nvram = m48t59;
 742
 743     /* Initialise NVRAM */
 744     nvram.opaque = m48t59;
 745     nvram.read_fn = &m48t59_read;
 746     nvram.write_fn = &m48t59_write;
 747     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 748                          kernel_base, kernel_size,
 749                          kernel_cmdline,
 750                          initrd_base, initrd_size,
 751                          /* XXX: need an option to load a NVRAM image */
 752                          0,
 753                          graphic_width, graphic_height, graphic_depth);
 754
 755     /* Special port to get debug messages from Open-Firmware */
 756     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 757 }
 758
 759 static QEMUMachine prep_machine = {
 760     .name = "prep",
 761     .desc = "PowerPC PREP platform",
 762     .init = ppc_prep_init,
 763     .max_cpus = MAX_CPUS,
 764 };
 765
 766 static void prep_machine_init(void)
 767 {
 768     qemu_register_machine(&prep_machine);
 769 }
 770
 771 machine_init(prep_machine_init);