4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2011 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "exec/gdbstub.h"
23 #include "qemu/timer.h"
24 #ifndef CONFIG_USER_ONLY
25 #include "sysemu/sysemu.h"
29 //#define DEBUG_S390_PTE
30 //#define DEBUG_S390_STDOUT
33 #ifdef DEBUG_S390_STDOUT
34 #define DPRINTF(fmt, ...) \
35 do { fprintf(stderr, fmt, ## __VA_ARGS__); \
36 qemu_log(fmt, ##__VA_ARGS__); } while (0)
38 #define DPRINTF(fmt, ...) \
39 do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
42 #define DPRINTF(fmt, ...) \
47 #define PTE_DPRINTF DPRINTF
49 #define PTE_DPRINTF(fmt, ...) \
53 #ifndef CONFIG_USER_ONLY
54 void s390x_tod_timer(void *opaque
)
56 S390CPU
*cpu
= opaque
;
57 CPUS390XState
*env
= &cpu
->env
;
59 env
->pending_int
|= INTERRUPT_TOD
;
60 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_HARD
);
63 void s390x_cpu_timer(void *opaque
)
65 S390CPU
*cpu
= opaque
;
66 CPUS390XState
*env
= &cpu
->env
;
68 env
->pending_int
|= INTERRUPT_CPUTIMER
;
69 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_HARD
);
73 S390CPU
*cpu_s390x_init(const char *cpu_model
)
77 cpu
= S390_CPU(object_new(TYPE_S390_CPU
));
79 object_property_set_bool(OBJECT(cpu
), true, "realized", NULL
);
84 #if defined(CONFIG_USER_ONLY)
86 void s390_cpu_do_interrupt(CPUState
*cs
)
88 cs
->exception_index
= -1;
91 int s390_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
,
94 S390CPU
*cpu
= S390_CPU(cs
);
96 cs
->exception_index
= EXCP_PGM
;
97 cpu
->env
.int_pgm_code
= PGM_ADDRESSING
;
98 /* On real machines this value is dropped into LowMem. Since this
99 is userland, simply put this someplace that cpu_loop can find it. */
100 cpu
->env
.__excp_addr
= address
;
104 #else /* !CONFIG_USER_ONLY */
106 /* Ensure to exit the TB after this call! */
107 static void trigger_pgm_exception(CPUS390XState
*env
, uint32_t code
,
110 CPUState
*cs
= CPU(s390_env_get_cpu(env
));
112 cs
->exception_index
= EXCP_PGM
;
113 env
->int_pgm_code
= code
;
114 env
->int_pgm_ilen
= ilen
;
117 static int trans_bits(CPUS390XState
*env
, uint64_t mode
)
119 S390CPU
*cpu
= s390_env_get_cpu(env
);
123 case PSW_ASC_PRIMARY
:
126 case PSW_ASC_SECONDARY
:
133 cpu_abort(CPU(cpu
), "unknown asc mode\n");
140 static void trigger_prot_fault(CPUS390XState
*env
, target_ulong vaddr
,
143 CPUState
*cs
= CPU(s390_env_get_cpu(env
));
144 int ilen
= ILEN_LATER_INC
;
145 int bits
= trans_bits(env
, mode
) | 4;
147 DPRINTF("%s: vaddr=%016" PRIx64
" bits=%d\n", __func__
, vaddr
, bits
);
150 env
->psa
+ offsetof(LowCore
, trans_exc_code
), vaddr
| bits
);
151 trigger_pgm_exception(env
, PGM_PROTECTION
, ilen
);
154 static void trigger_page_fault(CPUS390XState
*env
, target_ulong vaddr
,
155 uint32_t type
, uint64_t asc
, int rw
)
157 CPUState
*cs
= CPU(s390_env_get_cpu(env
));
158 int ilen
= ILEN_LATER
;
159 int bits
= trans_bits(env
, asc
);
161 /* Code accesses have an undefined ilc. */
166 DPRINTF("%s: vaddr=%016" PRIx64
" bits=%d\n", __func__
, vaddr
, bits
);
169 env
->psa
+ offsetof(LowCore
, trans_exc_code
), vaddr
| bits
);
170 trigger_pgm_exception(env
, type
, ilen
);
174 * Translate real address to absolute (= physical)
175 * address by taking care of the prefix mapping.
177 static target_ulong
mmu_real2abs(CPUS390XState
*env
, target_ulong raddr
)
179 if (raddr
< 0x2000) {
180 return raddr
+ env
->psa
; /* Map the lowcore. */
181 } else if (raddr
>= env
->psa
&& raddr
< env
->psa
+ 0x2000) {
182 return raddr
- env
->psa
; /* Map the 0 page. */
187 /* Decode page table entry (normal 4KB page) */
188 static int mmu_translate_pte(CPUS390XState
*env
, target_ulong vaddr
,
189 uint64_t asc
, uint64_t asce
,
190 target_ulong
*raddr
, int *flags
, int rw
)
192 if (asce
& _PAGE_INVALID
) {
193 DPRINTF("%s: PTE=0x%" PRIx64
" invalid\n", __func__
, asce
);
194 trigger_page_fault(env
, vaddr
, PGM_PAGE_TRANS
, asc
, rw
);
198 if (asce
& _PAGE_RO
) {
199 *flags
&= ~PAGE_WRITE
;
202 *raddr
= asce
& _ASCE_ORIGIN
;
204 PTE_DPRINTF("%s: PTE=0x%" PRIx64
"\n", __func__
, asce
);
209 /* Decode EDAT1 segment frame absolute address (1MB page) */
210 static int mmu_translate_sfaa(CPUS390XState
*env
, target_ulong vaddr
,
211 uint64_t asc
, uint64_t asce
, target_ulong
*raddr
,
214 if (asce
& _SEGMENT_ENTRY_INV
) {
215 DPRINTF("%s: SEG=0x%" PRIx64
" invalid\n", __func__
, asce
);
216 trigger_page_fault(env
, vaddr
, PGM_SEGMENT_TRANS
, asc
, rw
);
220 if (asce
& _SEGMENT_ENTRY_RO
) {
221 *flags
&= ~PAGE_WRITE
;
224 *raddr
= (asce
& 0xfffffffffff00000ULL
) | (vaddr
& 0xfffff);
226 PTE_DPRINTF("%s: SEG=0x%" PRIx64
"\n", __func__
, asce
);
231 static int mmu_translate_asce(CPUS390XState
*env
, target_ulong vaddr
,
232 uint64_t asc
, uint64_t asce
, int level
,
233 target_ulong
*raddr
, int *flags
, int rw
)
235 CPUState
*cs
= CPU(s390_env_get_cpu(env
));
240 PTE_DPRINTF("%s: 0x%" PRIx64
"\n", __func__
, asce
);
242 if (((level
!= _ASCE_TYPE_SEGMENT
) && (asce
& _REGION_ENTRY_INV
)) ||
243 ((level
== _ASCE_TYPE_SEGMENT
) && (asce
& _SEGMENT_ENTRY_INV
))) {
244 /* XXX different regions have different faults */
245 DPRINTF("%s: invalid region\n", __func__
);
246 trigger_page_fault(env
, vaddr
, PGM_SEGMENT_TRANS
, asc
, rw
);
250 if ((level
<= _ASCE_TYPE_MASK
) && ((asce
& _ASCE_TYPE_MASK
) != level
)) {
251 trigger_page_fault(env
, vaddr
, PGM_TRANS_SPEC
, asc
, rw
);
255 if (asce
& _ASCE_REAL_SPACE
) {
262 origin
= asce
& _ASCE_ORIGIN
;
265 case _ASCE_TYPE_REGION1
+ 4:
266 offs
= (vaddr
>> 50) & 0x3ff8;
268 case _ASCE_TYPE_REGION1
:
269 offs
= (vaddr
>> 39) & 0x3ff8;
271 case _ASCE_TYPE_REGION2
:
272 offs
= (vaddr
>> 28) & 0x3ff8;
274 case _ASCE_TYPE_REGION3
:
275 offs
= (vaddr
>> 17) & 0x3ff8;
277 case _ASCE_TYPE_SEGMENT
:
278 offs
= (vaddr
>> 9) & 0x07f8;
279 origin
= asce
& _SEGMENT_ENTRY_ORIGIN
;
283 /* XXX region protection flags */
284 /* *flags &= ~PAGE_WRITE */
286 new_asce
= ldq_phys(cs
->as
, origin
+ offs
);
287 PTE_DPRINTF("%s: 0x%" PRIx64
" + 0x%" PRIx64
" => 0x%016" PRIx64
"\n",
288 __func__
, origin
, offs
, new_asce
);
290 if (level
== _ASCE_TYPE_SEGMENT
) {
292 return mmu_translate_pte(env
, vaddr
, asc
, new_asce
, raddr
, flags
, rw
);
293 } else if (level
- 4 == _ASCE_TYPE_SEGMENT
&&
294 (new_asce
& _SEGMENT_ENTRY_FC
) && (env
->cregs
[0] & CR0_EDAT
)) {
296 return mmu_translate_sfaa(env
, vaddr
, asc
, new_asce
, raddr
, flags
, rw
);
298 /* yet another region */
299 return mmu_translate_asce(env
, vaddr
, asc
, new_asce
, level
- 4, raddr
,
304 static int mmu_translate_asc(CPUS390XState
*env
, target_ulong vaddr
,
305 uint64_t asc
, target_ulong
*raddr
, int *flags
,
309 int level
, new_level
;
313 case PSW_ASC_PRIMARY
:
314 PTE_DPRINTF("%s: asc=primary\n", __func__
);
315 asce
= env
->cregs
[1];
317 case PSW_ASC_SECONDARY
:
318 PTE_DPRINTF("%s: asc=secondary\n", __func__
);
319 asce
= env
->cregs
[7];
322 PTE_DPRINTF("%s: asc=home\n", __func__
);
323 asce
= env
->cregs
[13];
327 switch (asce
& _ASCE_TYPE_MASK
) {
328 case _ASCE_TYPE_REGION1
:
330 case _ASCE_TYPE_REGION2
:
331 if (vaddr
& 0xffe0000000000000ULL
) {
332 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
333 " 0xffe0000000000000ULL\n", __func__
, vaddr
);
334 trigger_page_fault(env
, vaddr
, PGM_TRANS_SPEC
, asc
, rw
);
338 case _ASCE_TYPE_REGION3
:
339 if (vaddr
& 0xfffffc0000000000ULL
) {
340 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
341 " 0xfffffc0000000000ULL\n", __func__
, vaddr
);
342 trigger_page_fault(env
, vaddr
, PGM_TRANS_SPEC
, asc
, rw
);
346 case _ASCE_TYPE_SEGMENT
:
347 if (vaddr
& 0xffffffff80000000ULL
) {
348 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
349 " 0xffffffff80000000ULL\n", __func__
, vaddr
);
350 trigger_page_fault(env
, vaddr
, PGM_TRANS_SPEC
, asc
, rw
);
356 /* fake level above current */
357 level
= asce
& _ASCE_TYPE_MASK
;
358 new_level
= level
+ 4;
359 asce
= (asce
& ~_ASCE_TYPE_MASK
) | (new_level
& _ASCE_TYPE_MASK
);
361 r
= mmu_translate_asce(env
, vaddr
, asc
, asce
, new_level
, raddr
, flags
, rw
);
363 if ((rw
== 1) && !(*flags
& PAGE_WRITE
)) {
364 trigger_prot_fault(env
, vaddr
, asc
);
371 int mmu_translate(CPUS390XState
*env
, target_ulong vaddr
, int rw
, uint64_t asc
,
372 target_ulong
*raddr
, int *flags
)
377 *flags
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
378 vaddr
&= TARGET_PAGE_MASK
;
380 if (!(env
->psw
.mask
& PSW_MASK_DAT
)) {
387 case PSW_ASC_PRIMARY
:
389 r
= mmu_translate_asc(env
, vaddr
, asc
, raddr
, flags
, rw
);
391 case PSW_ASC_SECONDARY
:
393 * Instruction: Primary
397 r
= mmu_translate_asc(env
, vaddr
, PSW_ASC_PRIMARY
, raddr
, flags
,
399 *flags
&= ~(PAGE_READ
| PAGE_WRITE
);
401 r
= mmu_translate_asc(env
, vaddr
, PSW_ASC_SECONDARY
, raddr
, flags
,
403 *flags
&= ~(PAGE_EXEC
);
408 hw_error("guest switched to unknown asc mode\n");
413 /* Convert real address -> absolute address */
414 *raddr
= mmu_real2abs(env
, *raddr
);
416 if (*raddr
<= ram_size
) {
417 sk
= &env
->storage_keys
[*raddr
/ TARGET_PAGE_SIZE
];
418 if (*flags
& PAGE_READ
) {
422 if (*flags
& PAGE_WRITE
) {
430 int s390_cpu_handle_mmu_fault(CPUState
*cs
, vaddr orig_vaddr
,
433 S390CPU
*cpu
= S390_CPU(cs
);
434 CPUS390XState
*env
= &cpu
->env
;
435 uint64_t asc
= env
->psw
.mask
& PSW_MASK_ASC
;
436 target_ulong vaddr
, raddr
;
439 DPRINTF("%s: address 0x%" VADDR_PRIx
" rw %d mmu_idx %d\n",
440 __func__
, orig_vaddr
, rw
, mmu_idx
);
442 orig_vaddr
&= TARGET_PAGE_MASK
;
446 if (!(env
->psw
.mask
& PSW_MASK_64
)) {
450 if (mmu_translate(env
, vaddr
, rw
, asc
, &raddr
, &prot
)) {
451 /* Translation ended in exception */
455 /* check out of RAM access */
456 if (raddr
> (ram_size
+ virtio_size
)) {
457 DPRINTF("%s: raddr %" PRIx64
" > ram_size %" PRIx64
"\n", __func__
,
458 (uint64_t)raddr
, (uint64_t)ram_size
);
459 trigger_pgm_exception(env
, PGM_ADDRESSING
, ILEN_LATER
);
463 DPRINTF("%s: set tlb %" PRIx64
" -> %" PRIx64
" (%x)\n", __func__
,
464 (uint64_t)vaddr
, (uint64_t)raddr
, prot
);
466 tlb_set_page(cs
, orig_vaddr
, raddr
, prot
,
467 mmu_idx
, TARGET_PAGE_SIZE
);
472 hwaddr
s390_cpu_get_phys_page_debug(CPUState
*cs
, vaddr vaddr
)
474 S390CPU
*cpu
= S390_CPU(cs
);
475 CPUS390XState
*env
= &cpu
->env
;
477 int prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
478 int old_exc
= cs
->exception_index
;
479 uint64_t asc
= env
->psw
.mask
& PSW_MASK_ASC
;
482 if (!(env
->psw
.mask
& PSW_MASK_64
)) {
486 mmu_translate(env
, vaddr
, 2, asc
, &raddr
, &prot
);
487 cs
->exception_index
= old_exc
;
492 void load_psw(CPUS390XState
*env
, uint64_t mask
, uint64_t addr
)
494 if (mask
& PSW_MASK_WAIT
) {
495 S390CPU
*cpu
= s390_env_get_cpu(env
);
496 CPUState
*cs
= CPU(cpu
);
497 if (!(mask
& (PSW_MASK_IO
| PSW_MASK_EXT
| PSW_MASK_MCHECK
))) {
498 if (s390_del_running_cpu(cpu
) == 0) {
499 #ifndef CONFIG_USER_ONLY
500 qemu_system_shutdown_request();
505 cs
->exception_index
= EXCP_HLT
;
508 env
->psw
.addr
= addr
;
509 env
->psw
.mask
= mask
;
510 env
->cc_op
= (mask
>> 44) & 3;
513 static uint64_t get_psw_mask(CPUS390XState
*env
)
517 env
->cc_op
= calc_cc(env
, env
->cc_op
, env
->cc_src
, env
->cc_dst
, env
->cc_vr
);
521 assert(!(env
->cc_op
& ~3));
522 r
|= (uint64_t)env
->cc_op
<< 44;
527 static LowCore
*cpu_map_lowcore(CPUS390XState
*env
)
529 S390CPU
*cpu
= s390_env_get_cpu(env
);
531 hwaddr len
= sizeof(LowCore
);
533 lowcore
= cpu_physical_memory_map(env
->psa
, &len
, 1);
535 if (len
< sizeof(LowCore
)) {
536 cpu_abort(CPU(cpu
), "Could not map lowcore\n");
542 static void cpu_unmap_lowcore(LowCore
*lowcore
)
544 cpu_physical_memory_unmap(lowcore
, sizeof(LowCore
), 1, sizeof(LowCore
));
547 void *s390_cpu_physical_memory_map(CPUS390XState
*env
, hwaddr addr
, hwaddr
*len
,
552 /* Mind the prefix area. */
554 /* Map the lowcore. */
556 *len
= MIN(*len
, 8192 - addr
);
557 } else if ((addr
>= env
->psa
) && (addr
< env
->psa
+ 8192)) {
558 /* Map the 0 page. */
560 *len
= MIN(*len
, 8192 - start
);
563 return cpu_physical_memory_map(start
, len
, is_write
);
566 void s390_cpu_physical_memory_unmap(CPUS390XState
*env
, void *addr
, hwaddr len
,
569 cpu_physical_memory_unmap(addr
, len
, is_write
, len
);
572 static void do_svc_interrupt(CPUS390XState
*env
)
577 lowcore
= cpu_map_lowcore(env
);
579 lowcore
->svc_code
= cpu_to_be16(env
->int_svc_code
);
580 lowcore
->svc_ilen
= cpu_to_be16(env
->int_svc_ilen
);
581 lowcore
->svc_old_psw
.mask
= cpu_to_be64(get_psw_mask(env
));
582 lowcore
->svc_old_psw
.addr
= cpu_to_be64(env
->psw
.addr
+ env
->int_svc_ilen
);
583 mask
= be64_to_cpu(lowcore
->svc_new_psw
.mask
);
584 addr
= be64_to_cpu(lowcore
->svc_new_psw
.addr
);
586 cpu_unmap_lowcore(lowcore
);
588 load_psw(env
, mask
, addr
);
591 static void do_program_interrupt(CPUS390XState
*env
)
595 int ilen
= env
->int_pgm_ilen
;
599 ilen
= get_ilen(cpu_ldub_code(env
, env
->psw
.addr
));
602 ilen
= get_ilen(cpu_ldub_code(env
, env
->psw
.addr
));
603 env
->psw
.addr
+= ilen
;
606 assert(ilen
== 2 || ilen
== 4 || ilen
== 6);
609 qemu_log_mask(CPU_LOG_INT
, "%s: code=0x%x ilen=%d\n",
610 __func__
, env
->int_pgm_code
, ilen
);
612 lowcore
= cpu_map_lowcore(env
);
614 lowcore
->pgm_ilen
= cpu_to_be16(ilen
);
615 lowcore
->pgm_code
= cpu_to_be16(env
->int_pgm_code
);
616 lowcore
->program_old_psw
.mask
= cpu_to_be64(get_psw_mask(env
));
617 lowcore
->program_old_psw
.addr
= cpu_to_be64(env
->psw
.addr
);
618 mask
= be64_to_cpu(lowcore
->program_new_psw
.mask
);
619 addr
= be64_to_cpu(lowcore
->program_new_psw
.addr
);
621 cpu_unmap_lowcore(lowcore
);
623 DPRINTF("%s: %x %x %" PRIx64
" %" PRIx64
"\n", __func__
,
624 env
->int_pgm_code
, ilen
, env
->psw
.mask
,
627 load_psw(env
, mask
, addr
);
630 #define VIRTIO_SUBCODE_64 0x0D00
632 static void do_ext_interrupt(CPUS390XState
*env
)
634 S390CPU
*cpu
= s390_env_get_cpu(env
);
639 if (!(env
->psw
.mask
& PSW_MASK_EXT
)) {
640 cpu_abort(CPU(cpu
), "Ext int w/o ext mask\n");
643 if (env
->ext_index
< 0 || env
->ext_index
> MAX_EXT_QUEUE
) {
644 cpu_abort(CPU(cpu
), "Ext queue overrun: %d\n", env
->ext_index
);
647 q
= &env
->ext_queue
[env
->ext_index
];
648 lowcore
= cpu_map_lowcore(env
);
650 lowcore
->ext_int_code
= cpu_to_be16(q
->code
);
651 lowcore
->ext_params
= cpu_to_be32(q
->param
);
652 lowcore
->ext_params2
= cpu_to_be64(q
->param64
);
653 lowcore
->external_old_psw
.mask
= cpu_to_be64(get_psw_mask(env
));
654 lowcore
->external_old_psw
.addr
= cpu_to_be64(env
->psw
.addr
);
655 lowcore
->cpu_addr
= cpu_to_be16(env
->cpu_num
| VIRTIO_SUBCODE_64
);
656 mask
= be64_to_cpu(lowcore
->external_new_psw
.mask
);
657 addr
= be64_to_cpu(lowcore
->external_new_psw
.addr
);
659 cpu_unmap_lowcore(lowcore
);
662 if (env
->ext_index
== -1) {
663 env
->pending_int
&= ~INTERRUPT_EXT
;
666 DPRINTF("%s: %" PRIx64
" %" PRIx64
"\n", __func__
,
667 env
->psw
.mask
, env
->psw
.addr
);
669 load_psw(env
, mask
, addr
);
672 static void do_io_interrupt(CPUS390XState
*env
)
674 S390CPU
*cpu
= s390_env_get_cpu(env
);
681 if (!(env
->psw
.mask
& PSW_MASK_IO
)) {
682 cpu_abort(CPU(cpu
), "I/O int w/o I/O mask\n");
685 for (isc
= 0; isc
< ARRAY_SIZE(env
->io_index
); isc
++) {
688 if (env
->io_index
[isc
] < 0) {
691 if (env
->io_index
[isc
] > MAX_IO_QUEUE
) {
692 cpu_abort(CPU(cpu
), "I/O queue overrun for isc %d: %d\n",
693 isc
, env
->io_index
[isc
]);
696 q
= &env
->io_queue
[env
->io_index
[isc
]][isc
];
697 isc_bits
= ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q
->word
));
698 if (!(env
->cregs
[6] & isc_bits
)) {
706 lowcore
= cpu_map_lowcore(env
);
708 lowcore
->subchannel_id
= cpu_to_be16(q
->id
);
709 lowcore
->subchannel_nr
= cpu_to_be16(q
->nr
);
710 lowcore
->io_int_parm
= cpu_to_be32(q
->parm
);
711 lowcore
->io_int_word
= cpu_to_be32(q
->word
);
712 lowcore
->io_old_psw
.mask
= cpu_to_be64(get_psw_mask(env
));
713 lowcore
->io_old_psw
.addr
= cpu_to_be64(env
->psw
.addr
);
714 mask
= be64_to_cpu(lowcore
->io_new_psw
.mask
);
715 addr
= be64_to_cpu(lowcore
->io_new_psw
.addr
);
717 cpu_unmap_lowcore(lowcore
);
719 env
->io_index
[isc
]--;
721 DPRINTF("%s: %" PRIx64
" %" PRIx64
"\n", __func__
,
722 env
->psw
.mask
, env
->psw
.addr
);
723 load_psw(env
, mask
, addr
);
725 if (env
->io_index
[isc
] >= 0) {
732 env
->pending_int
&= ~INTERRUPT_IO
;
737 static void do_mchk_interrupt(CPUS390XState
*env
)
739 S390CPU
*cpu
= s390_env_get_cpu(env
);
745 if (!(env
->psw
.mask
& PSW_MASK_MCHECK
)) {
746 cpu_abort(CPU(cpu
), "Machine check w/o mchk mask\n");
749 if (env
->mchk_index
< 0 || env
->mchk_index
> MAX_MCHK_QUEUE
) {
750 cpu_abort(CPU(cpu
), "Mchk queue overrun: %d\n", env
->mchk_index
);
753 q
= &env
->mchk_queue
[env
->mchk_index
];
756 /* Don't know how to handle this... */
757 cpu_abort(CPU(cpu
), "Unknown machine check type %d\n", q
->type
);
759 if (!(env
->cregs
[14] & (1 << 28))) {
760 /* CRW machine checks disabled */
764 lowcore
= cpu_map_lowcore(env
);
766 for (i
= 0; i
< 16; i
++) {
767 lowcore
->floating_pt_save_area
[i
] = cpu_to_be64(env
->fregs
[i
].ll
);
768 lowcore
->gpregs_save_area
[i
] = cpu_to_be64(env
->regs
[i
]);
769 lowcore
->access_regs_save_area
[i
] = cpu_to_be32(env
->aregs
[i
]);
770 lowcore
->cregs_save_area
[i
] = cpu_to_be64(env
->cregs
[i
]);
772 lowcore
->prefixreg_save_area
= cpu_to_be32(env
->psa
);
773 lowcore
->fpt_creg_save_area
= cpu_to_be32(env
->fpc
);
774 lowcore
->tod_progreg_save_area
= cpu_to_be32(env
->todpr
);
775 lowcore
->cpu_timer_save_area
[0] = cpu_to_be32(env
->cputm
>> 32);
776 lowcore
->cpu_timer_save_area
[1] = cpu_to_be32((uint32_t)env
->cputm
);
777 lowcore
->clock_comp_save_area
[0] = cpu_to_be32(env
->ckc
>> 32);
778 lowcore
->clock_comp_save_area
[1] = cpu_to_be32((uint32_t)env
->ckc
);
780 lowcore
->mcck_interruption_code
[0] = cpu_to_be32(0x00400f1d);
781 lowcore
->mcck_interruption_code
[1] = cpu_to_be32(0x40330000);
782 lowcore
->mcck_old_psw
.mask
= cpu_to_be64(get_psw_mask(env
));
783 lowcore
->mcck_old_psw
.addr
= cpu_to_be64(env
->psw
.addr
);
784 mask
= be64_to_cpu(lowcore
->mcck_new_psw
.mask
);
785 addr
= be64_to_cpu(lowcore
->mcck_new_psw
.addr
);
787 cpu_unmap_lowcore(lowcore
);
790 if (env
->mchk_index
== -1) {
791 env
->pending_int
&= ~INTERRUPT_MCHK
;
794 DPRINTF("%s: %" PRIx64
" %" PRIx64
"\n", __func__
,
795 env
->psw
.mask
, env
->psw
.addr
);
797 load_psw(env
, mask
, addr
);
800 void s390_cpu_do_interrupt(CPUState
*cs
)
802 S390CPU
*cpu
= S390_CPU(cs
);
803 CPUS390XState
*env
= &cpu
->env
;
805 qemu_log_mask(CPU_LOG_INT
, "%s: %d at pc=%" PRIx64
"\n",
806 __func__
, cs
->exception_index
, env
->psw
.addr
);
808 s390_add_running_cpu(cpu
);
809 /* handle machine checks */
810 if ((env
->psw
.mask
& PSW_MASK_MCHECK
) &&
811 (cs
->exception_index
== -1)) {
812 if (env
->pending_int
& INTERRUPT_MCHK
) {
813 cs
->exception_index
= EXCP_MCHK
;
816 /* handle external interrupts */
817 if ((env
->psw
.mask
& PSW_MASK_EXT
) &&
818 cs
->exception_index
== -1) {
819 if (env
->pending_int
& INTERRUPT_EXT
) {
820 /* code is already in env */
821 cs
->exception_index
= EXCP_EXT
;
822 } else if (env
->pending_int
& INTERRUPT_TOD
) {
823 cpu_inject_ext(cpu
, 0x1004, 0, 0);
824 cs
->exception_index
= EXCP_EXT
;
825 env
->pending_int
&= ~INTERRUPT_EXT
;
826 env
->pending_int
&= ~INTERRUPT_TOD
;
827 } else if (env
->pending_int
& INTERRUPT_CPUTIMER
) {
828 cpu_inject_ext(cpu
, 0x1005, 0, 0);
829 cs
->exception_index
= EXCP_EXT
;
830 env
->pending_int
&= ~INTERRUPT_EXT
;
831 env
->pending_int
&= ~INTERRUPT_TOD
;
834 /* handle I/O interrupts */
835 if ((env
->psw
.mask
& PSW_MASK_IO
) &&
836 (cs
->exception_index
== -1)) {
837 if (env
->pending_int
& INTERRUPT_IO
) {
838 cs
->exception_index
= EXCP_IO
;
842 switch (cs
->exception_index
) {
844 do_program_interrupt(env
);
847 do_svc_interrupt(env
);
850 do_ext_interrupt(env
);
853 do_io_interrupt(env
);
856 do_mchk_interrupt(env
);
859 cs
->exception_index
= -1;
861 if (!env
->pending_int
) {
862 cs
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
866 #endif /* CONFIG_USER_ONLY */