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tcg: Require TCG_TARGET_INSN_UNIT_SIZE
[qemu.git] / target-i386 / smm_helper.c
blob35901c9e898538701587903517f75b69a0b71392
1 /*
2 * x86 SMM helpers
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 /* SMM support */
24
25 #if defined(CONFIG_USER_ONLY)
26
27 void do_smm_enter(X86CPU *cpu)
28 {
29 }
30
31 void helper_rsm(CPUX86State *env)
32 {
33 }
34
35 #else
36
37 #ifdef TARGET_X86_64
38 #define SMM_REVISION_ID 0x00020064
39 #else
40 #define SMM_REVISION_ID 0x00020000
41 #endif
42
43 void do_smm_enter(X86CPU *cpu)
44 {
45 CPUX86State *env = &cpu->env;
46 CPUState *cs = CPU(cpu);
47 target_ulong sm_state;
48 SegmentCache *dt;
49 int i, offset;
50
51 qemu_log_mask(CPU_LOG_INT, "SMM: enter\n");
52 log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
53
54 env->hflags |= HF_SMM_MASK;
55 cpu_smm_update(env);
56
57 sm_state = env->smbase + 0x8000;
58
59 #ifdef TARGET_X86_64
60 for (i = 0; i < 6; i++) {
61 dt = &env->segs[i];
62 offset = 0x7e00 + i * 16;
63 stw_phys(cs->as, sm_state + offset, dt->selector);
64 stw_phys(cs->as, sm_state + offset + 2, (dt->flags >> 8) & 0xf0ff);
65 stl_phys(cs->as, sm_state + offset + 4, dt->limit);
66 stq_phys(cs->as, sm_state + offset + 8, dt->base);
67 }
68
69 stq_phys(cs->as, sm_state + 0x7e68, env->gdt.base);
70 stl_phys(cs->as, sm_state + 0x7e64, env->gdt.limit);
71
72 stw_phys(cs->as, sm_state + 0x7e70, env->ldt.selector);
73 stq_phys(cs->as, sm_state + 0x7e78, env->ldt.base);
74 stl_phys(cs->as, sm_state + 0x7e74, env->ldt.limit);
75 stw_phys(cs->as, sm_state + 0x7e72, (env->ldt.flags >> 8) & 0xf0ff);
76
77 stq_phys(cs->as, sm_state + 0x7e88, env->idt.base);
78 stl_phys(cs->as, sm_state + 0x7e84, env->idt.limit);
79
80 stw_phys(cs->as, sm_state + 0x7e90, env->tr.selector);
81 stq_phys(cs->as, sm_state + 0x7e98, env->tr.base);
82 stl_phys(cs->as, sm_state + 0x7e94, env->tr.limit);
83 stw_phys(cs->as, sm_state + 0x7e92, (env->tr.flags >> 8) & 0xf0ff);
84
85 stq_phys(cs->as, sm_state + 0x7ed0, env->efer);
86
87 stq_phys(cs->as, sm_state + 0x7ff8, env->regs[R_EAX]);
88 stq_phys(cs->as, sm_state + 0x7ff0, env->regs[R_ECX]);
89 stq_phys(cs->as, sm_state + 0x7fe8, env->regs[R_EDX]);
90 stq_phys(cs->as, sm_state + 0x7fe0, env->regs[R_EBX]);
91 stq_phys(cs->as, sm_state + 0x7fd8, env->regs[R_ESP]);
92 stq_phys(cs->as, sm_state + 0x7fd0, env->regs[R_EBP]);
93 stq_phys(cs->as, sm_state + 0x7fc8, env->regs[R_ESI]);
94 stq_phys(cs->as, sm_state + 0x7fc0, env->regs[R_EDI]);
95 for (i = 8; i < 16; i++) {
96 stq_phys(cs->as, sm_state + 0x7ff8 - i * 8, env->regs[i]);
97 }
98 stq_phys(cs->as, sm_state + 0x7f78, env->eip);
99 stl_phys(cs->as, sm_state + 0x7f70, cpu_compute_eflags(env));
100 stl_phys(cs->as, sm_state + 0x7f68, env->dr[6]);
101 stl_phys(cs->as, sm_state + 0x7f60, env->dr[7]);
102
103 stl_phys(cs->as, sm_state + 0x7f48, env->cr[4]);
104 stl_phys(cs->as, sm_state + 0x7f50, env->cr[3]);
105 stl_phys(cs->as, sm_state + 0x7f58, env->cr[0]);
106
107 stl_phys(cs->as, sm_state + 0x7efc, SMM_REVISION_ID);
108 stl_phys(cs->as, sm_state + 0x7f00, env->smbase);
109 #else
110 stl_phys(cs->as, sm_state + 0x7ffc, env->cr[0]);
111 stl_phys(cs->as, sm_state + 0x7ff8, env->cr[3]);
112 stl_phys(cs->as, sm_state + 0x7ff4, cpu_compute_eflags(env));
113 stl_phys(cs->as, sm_state + 0x7ff0, env->eip);
114 stl_phys(cs->as, sm_state + 0x7fec, env->regs[R_EDI]);
115 stl_phys(cs->as, sm_state + 0x7fe8, env->regs[R_ESI]);
116 stl_phys(cs->as, sm_state + 0x7fe4, env->regs[R_EBP]);
117 stl_phys(cs->as, sm_state + 0x7fe0, env->regs[R_ESP]);
118 stl_phys(cs->as, sm_state + 0x7fdc, env->regs[R_EBX]);
119 stl_phys(cs->as, sm_state + 0x7fd8, env->regs[R_EDX]);
120 stl_phys(cs->as, sm_state + 0x7fd4, env->regs[R_ECX]);
121 stl_phys(cs->as, sm_state + 0x7fd0, env->regs[R_EAX]);
122 stl_phys(cs->as, sm_state + 0x7fcc, env->dr[6]);
123 stl_phys(cs->as, sm_state + 0x7fc8, env->dr[7]);
124
125 stl_phys(cs->as, sm_state + 0x7fc4, env->tr.selector);
126 stl_phys(cs->as, sm_state + 0x7f64, env->tr.base);
127 stl_phys(cs->as, sm_state + 0x7f60, env->tr.limit);
128 stl_phys(cs->as, sm_state + 0x7f5c, (env->tr.flags >> 8) & 0xf0ff);
129
130 stl_phys(cs->as, sm_state + 0x7fc0, env->ldt.selector);
131 stl_phys(cs->as, sm_state + 0x7f80, env->ldt.base);
132 stl_phys(cs->as, sm_state + 0x7f7c, env->ldt.limit);
133 stl_phys(cs->as, sm_state + 0x7f78, (env->ldt.flags >> 8) & 0xf0ff);
134
135 stl_phys(cs->as, sm_state + 0x7f74, env->gdt.base);
136 stl_phys(cs->as, sm_state + 0x7f70, env->gdt.limit);
137
138 stl_phys(cs->as, sm_state + 0x7f58, env->idt.base);
139 stl_phys(cs->as, sm_state + 0x7f54, env->idt.limit);
140
141 for (i = 0; i < 6; i++) {
142 dt = &env->segs[i];
143 if (i < 3) {
144 offset = 0x7f84 + i * 12;
145 } else {
146 offset = 0x7f2c + (i - 3) * 12;
147 }
148 stl_phys(cs->as, sm_state + 0x7fa8 + i * 4, dt->selector);
149 stl_phys(cs->as, sm_state + offset + 8, dt->base);
150 stl_phys(cs->as, sm_state + offset + 4, dt->limit);
151 stl_phys(cs->as, sm_state + offset, (dt->flags >> 8) & 0xf0ff);
152 }
153 stl_phys(cs->as, sm_state + 0x7f14, env->cr[4]);
154
155 stl_phys(cs->as, sm_state + 0x7efc, SMM_REVISION_ID);
156 stl_phys(cs->as, sm_state + 0x7ef8, env->smbase);
157 #endif
158 /* init SMM cpu state */
159
160 #ifdef TARGET_X86_64
161 cpu_load_efer(env, 0);
162 #endif
163 cpu_load_eflags(env, 0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C |
164 DF_MASK));
165 env->eip = 0x00008000;
166 cpu_x86_load_seg_cache(env, R_CS, (env->smbase >> 4) & 0xffff, env->smbase,
167 0xffffffff, 0);
168 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffffffff, 0);
169 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffffffff, 0);
170 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffffffff, 0);
171 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffffffff, 0);
172 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffffffff, 0);
173
174 cpu_x86_update_cr0(env,
175 env->cr[0] & ~(CR0_PE_MASK | CR0_EM_MASK | CR0_TS_MASK |
176 CR0_PG_MASK));
177 cpu_x86_update_cr4(env, 0);
178 env->dr[7] = 0x00000400;
179 CC_OP = CC_OP_EFLAGS;
180 }
181
182 void helper_rsm(CPUX86State *env)
183 {
184 X86CPU *cpu = x86_env_get_cpu(env);
185 CPUState *cs = CPU(cpu);
186 target_ulong sm_state;
187 int i, offset;
188 uint32_t val;
189
190 sm_state = env->smbase + 0x8000;
191 #ifdef TARGET_X86_64
192 cpu_load_efer(env, ldq_phys(cs->as, sm_state + 0x7ed0));
193
194 for (i = 0; i < 6; i++) {
195 offset = 0x7e00 + i * 16;
196 cpu_x86_load_seg_cache(env, i,
197 lduw_phys(cs->as, sm_state + offset),
198 ldq_phys(cs->as, sm_state + offset + 8),
199 ldl_phys(cs->as, sm_state + offset + 4),
200 (lduw_phys(cs->as, sm_state + offset + 2) &
201 0xf0ff) << 8);
202 }
203
204 env->gdt.base = ldq_phys(cs->as, sm_state + 0x7e68);
205 env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7e64);
206
207 env->ldt.selector = lduw_phys(cs->as, sm_state + 0x7e70);
208 env->ldt.base = ldq_phys(cs->as, sm_state + 0x7e78);
209 env->ldt.limit = ldl_phys(cs->as, sm_state + 0x7e74);
210 env->ldt.flags = (lduw_phys(cs->as, sm_state + 0x7e72) & 0xf0ff) << 8;
211
212 env->idt.base = ldq_phys(cs->as, sm_state + 0x7e88);
213 env->idt.limit = ldl_phys(cs->as, sm_state + 0x7e84);
214
215 env->tr.selector = lduw_phys(cs->as, sm_state + 0x7e90);
216 env->tr.base = ldq_phys(cs->as, sm_state + 0x7e98);
217 env->tr.limit = ldl_phys(cs->as, sm_state + 0x7e94);
218 env->tr.flags = (lduw_phys(cs->as, sm_state + 0x7e92) & 0xf0ff) << 8;
219
220 env->regs[R_EAX] = ldq_phys(cs->as, sm_state + 0x7ff8);
221 env->regs[R_ECX] = ldq_phys(cs->as, sm_state + 0x7ff0);
222 env->regs[R_EDX] = ldq_phys(cs->as, sm_state + 0x7fe8);
223 env->regs[R_EBX] = ldq_phys(cs->as, sm_state + 0x7fe0);
224 env->regs[R_ESP] = ldq_phys(cs->as, sm_state + 0x7fd8);
225 env->regs[R_EBP] = ldq_phys(cs->as, sm_state + 0x7fd0);
226 env->regs[R_ESI] = ldq_phys(cs->as, sm_state + 0x7fc8);
227 env->regs[R_EDI] = ldq_phys(cs->as, sm_state + 0x7fc0);
228 for (i = 8; i < 16; i++) {
229 env->regs[i] = ldq_phys(cs->as, sm_state + 0x7ff8 - i * 8);
230 }
231 env->eip = ldq_phys(cs->as, sm_state + 0x7f78);
232 cpu_load_eflags(env, ldl_phys(cs->as, sm_state + 0x7f70),
233 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
234 env->dr[6] = ldl_phys(cs->as, sm_state + 0x7f68);
235 env->dr[7] = ldl_phys(cs->as, sm_state + 0x7f60);
236
237 cpu_x86_update_cr4(env, ldl_phys(cs->as, sm_state + 0x7f48));
238 cpu_x86_update_cr3(env, ldl_phys(cs->as, sm_state + 0x7f50));
239 cpu_x86_update_cr0(env, ldl_phys(cs->as, sm_state + 0x7f58));
240
241 val = ldl_phys(cs->as, sm_state + 0x7efc); /* revision ID */
242 if (val & 0x20000) {
243 env->smbase = ldl_phys(cs->as, sm_state + 0x7f00) & ~0x7fff;
244 }
245 #else
246 cpu_x86_update_cr0(env, ldl_phys(cs->as, sm_state + 0x7ffc));
247 cpu_x86_update_cr3(env, ldl_phys(cs->as, sm_state + 0x7ff8));
248 cpu_load_eflags(env, ldl_phys(cs->as, sm_state + 0x7ff4),
249 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
250 env->eip = ldl_phys(cs->as, sm_state + 0x7ff0);
251 env->regs[R_EDI] = ldl_phys(cs->as, sm_state + 0x7fec);
252 env->regs[R_ESI] = ldl_phys(cs->as, sm_state + 0x7fe8);
253 env->regs[R_EBP] = ldl_phys(cs->as, sm_state + 0x7fe4);
254 env->regs[R_ESP] = ldl_phys(cs->as, sm_state + 0x7fe0);
255 env->regs[R_EBX] = ldl_phys(cs->as, sm_state + 0x7fdc);
256 env->regs[R_EDX] = ldl_phys(cs->as, sm_state + 0x7fd8);
257 env->regs[R_ECX] = ldl_phys(cs->as, sm_state + 0x7fd4);
258 env->regs[R_EAX] = ldl_phys(cs->as, sm_state + 0x7fd0);
259 env->dr[6] = ldl_phys(cs->as, sm_state + 0x7fcc);
260 env->dr[7] = ldl_phys(cs->as, sm_state + 0x7fc8);
261
262 env->tr.selector = ldl_phys(cs->as, sm_state + 0x7fc4) & 0xffff;
263 env->tr.base = ldl_phys(cs->as, sm_state + 0x7f64);
264 env->tr.limit = ldl_phys(cs->as, sm_state + 0x7f60);
265 env->tr.flags = (ldl_phys(cs->as, sm_state + 0x7f5c) & 0xf0ff) << 8;
266
267 env->ldt.selector = ldl_phys(cs->as, sm_state + 0x7fc0) & 0xffff;
268 env->ldt.base = ldl_phys(cs->as, sm_state + 0x7f80);
269 env->ldt.limit = ldl_phys(cs->as, sm_state + 0x7f7c);
270 env->ldt.flags = (ldl_phys(cs->as, sm_state + 0x7f78) & 0xf0ff) << 8;
271
272 env->gdt.base = ldl_phys(cs->as, sm_state + 0x7f74);
273 env->gdt.limit = ldl_phys(cs->as, sm_state + 0x7f70);
274
275 env->idt.base = ldl_phys(cs->as, sm_state + 0x7f58);
276 env->idt.limit = ldl_phys(cs->as, sm_state + 0x7f54);
277
278 for (i = 0; i < 6; i++) {
279 if (i < 3) {
280 offset = 0x7f84 + i * 12;
281 } else {
282 offset = 0x7f2c + (i - 3) * 12;
283 }
284 cpu_x86_load_seg_cache(env, i,
285 ldl_phys(cs->as,
286 sm_state + 0x7fa8 + i * 4) & 0xffff,
287 ldl_phys(cs->as, sm_state + offset + 8),
288 ldl_phys(cs->as, sm_state + offset + 4),
289 (ldl_phys(cs->as,
290 sm_state + offset) & 0xf0ff) << 8);
291 }
292 cpu_x86_update_cr4(env, ldl_phys(cs->as, sm_state + 0x7f14));
293
294 val = ldl_phys(cs->as, sm_state + 0x7efc); /* revision ID */
295 if (val & 0x20000) {
296 env->smbase = ldl_phys(cs->as, sm_state + 0x7ef8) & ~0x7fff;
297 }
298 #endif
299 CC_OP = CC_OP_EFLAGS;
300 env->hflags &= ~HF_SMM_MASK;
301 cpu_smm_update(env);
302
303 qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n");
304 log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP);
305 }
306
307 #endif /* !CONFIG_USER_ONLY */
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