4 * Copyright 2014 IBM Corp.
5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
6 * Hong Bo Li <lihbbj@cn.ibm.com>
7 * Yi Min Zhao <zyimin@cn.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
10 * your option) any later version. See the COPYING file in the top-level
14 #include "qemu/osdep.h"
15 #include "s390-pci-bus.h"
16 #include <hw/pci/pci_bus.h>
17 #include <hw/pci/msi.h>
18 #include <qemu/error-report.h>
20 /* #define DEBUG_S390PCI_BUS */
21 #ifdef DEBUG_S390PCI_BUS
22 #define DPRINTF(fmt, ...) \
23 do { fprintf(stderr, "S390pci-bus: " fmt, ## __VA_ARGS__); } while (0)
25 #define DPRINTF(fmt, ...) \
29 int chsc_sei_nt2_get_event(void *res
)
31 ChscSeiNt2Res
*nt2_res
= (ChscSeiNt2Res
*)res
;
35 SeiContainer
*sei_cont
;
36 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
37 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
43 sei_cont
= QTAILQ_FIRST(&s
->pending_sei
);
45 QTAILQ_REMOVE(&s
->pending_sei
, sei_cont
, link
);
47 nt2_res
->cc
= sei_cont
->cc
;
48 nt2_res
->length
= cpu_to_be16(sizeof(ChscSeiNt2Res
));
49 switch (sei_cont
->cc
) {
50 case 1: /* error event */
51 eccdf
= (PciCcdfErr
*)nt2_res
->ccdf
;
52 eccdf
->fid
= cpu_to_be32(sei_cont
->fid
);
53 eccdf
->fh
= cpu_to_be32(sei_cont
->fh
);
54 eccdf
->e
= cpu_to_be32(sei_cont
->e
);
55 eccdf
->faddr
= cpu_to_be64(sei_cont
->faddr
);
56 eccdf
->pec
= cpu_to_be16(sei_cont
->pec
);
58 case 2: /* availability event */
59 accdf
= (PciCcdfAvail
*)nt2_res
->ccdf
;
60 accdf
->fid
= cpu_to_be32(sei_cont
->fid
);
61 accdf
->fh
= cpu_to_be32(sei_cont
->fh
);
62 accdf
->pec
= cpu_to_be16(sei_cont
->pec
);
74 int chsc_sei_nt2_have_event(void)
76 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
77 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
83 return !QTAILQ_EMPTY(&s
->pending_sei
);
86 S390PCIBusDevice
*s390_pci_find_dev_by_fid(uint32_t fid
)
88 S390PCIBusDevice
*pbdev
;
90 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
91 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
97 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
99 if ((pbdev
->fh
!= 0) && (pbdev
->fid
== fid
)) {
107 void s390_pci_sclp_configure(int configure
, SCCB
*sccb
)
109 PciCfgSccb
*psccb
= (PciCfgSccb
*)sccb
;
110 S390PCIBusDevice
*pbdev
= s390_pci_find_dev_by_fid(be32_to_cpu(psccb
->aid
));
114 if ((configure
== 1 && pbdev
->configured
== true) ||
115 (configure
== 0 && pbdev
->configured
== false)) {
116 rc
= SCLP_RC_NO_ACTION_REQUIRED
;
118 pbdev
->configured
= !pbdev
->configured
;
119 rc
= SCLP_RC_NORMAL_COMPLETION
;
122 DPRINTF("sclp config %d no dev found\n", configure
);
123 rc
= SCLP_RC_ADAPTER_ID_NOT_RECOGNIZED
;
126 psccb
->header
.response_code
= cpu_to_be16(rc
);
129 static uint32_t s390_pci_get_pfid(PCIDevice
*pdev
)
131 return PCI_SLOT(pdev
->devfn
);
134 static uint32_t s390_pci_get_pfh(PCIDevice
*pdev
)
136 return PCI_SLOT(pdev
->devfn
) | FH_VIRT
;
139 S390PCIBusDevice
*s390_pci_find_dev_by_idx(uint32_t idx
)
141 S390PCIBusDevice
*pbdev
;
144 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
145 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
151 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
152 pbdev
= &s
->pbdev
[i
];
154 if (pbdev
->fh
== 0) {
167 S390PCIBusDevice
*s390_pci_find_dev_by_fh(uint32_t fh
)
169 S390PCIBusDevice
*pbdev
;
171 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
172 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
178 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
179 pbdev
= &s
->pbdev
[i
];
180 if (pbdev
->fh
== fh
) {
188 static void s390_pci_generate_event(uint8_t cc
, uint16_t pec
, uint32_t fh
,
189 uint32_t fid
, uint64_t faddr
, uint32_t e
)
191 SeiContainer
*sei_cont
;
192 S390pciState
*s
= S390_PCI_HOST_BRIDGE(
193 object_resolve_path(TYPE_S390_PCI_HOST_BRIDGE
, NULL
));
199 sei_cont
= g_malloc0(sizeof(SeiContainer
));
204 sei_cont
->faddr
= faddr
;
207 QTAILQ_INSERT_TAIL(&s
->pending_sei
, sei_cont
, link
);
208 css_generate_css_crws(0);
211 static void s390_pci_generate_plug_event(uint16_t pec
, uint32_t fh
,
214 s390_pci_generate_event(2, pec
, fh
, fid
, 0, 0);
217 static void s390_pci_generate_error_event(uint16_t pec
, uint32_t fh
,
218 uint32_t fid
, uint64_t faddr
,
221 s390_pci_generate_event(1, pec
, fh
, fid
, faddr
, e
);
224 static void s390_pci_set_irq(void *opaque
, int irq
, int level
)
229 static int s390_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
235 static uint64_t s390_pci_get_table_origin(uint64_t iota
)
237 return iota
& ~ZPCI_IOTA_RTTO_FLAG
;
240 static unsigned int calc_rtx(dma_addr_t ptr
)
242 return ((unsigned long) ptr
>> ZPCI_RT_SHIFT
) & ZPCI_INDEX_MASK
;
245 static unsigned int calc_sx(dma_addr_t ptr
)
247 return ((unsigned long) ptr
>> ZPCI_ST_SHIFT
) & ZPCI_INDEX_MASK
;
250 static unsigned int calc_px(dma_addr_t ptr
)
252 return ((unsigned long) ptr
>> PAGE_SHIFT
) & ZPCI_PT_MASK
;
255 static uint64_t get_rt_sto(uint64_t entry
)
257 return ((entry
& ZPCI_TABLE_TYPE_MASK
) == ZPCI_TABLE_TYPE_RTX
)
258 ? (entry
& ZPCI_RTE_ADDR_MASK
)
262 static uint64_t get_st_pto(uint64_t entry
)
264 return ((entry
& ZPCI_TABLE_TYPE_MASK
) == ZPCI_TABLE_TYPE_SX
)
265 ? (entry
& ZPCI_STE_ADDR_MASK
)
269 static uint64_t s390_guest_io_table_walk(uint64_t guest_iota
,
270 uint64_t guest_dma_address
)
272 uint64_t sto_a
, pto_a
, px_a
;
273 uint64_t sto
, pto
, pte
;
274 uint32_t rtx
, sx
, px
;
276 rtx
= calc_rtx(guest_dma_address
);
277 sx
= calc_sx(guest_dma_address
);
278 px
= calc_px(guest_dma_address
);
280 sto_a
= guest_iota
+ rtx
* sizeof(uint64_t);
281 sto
= address_space_ldq(&address_space_memory
, sto_a
,
282 MEMTXATTRS_UNSPECIFIED
, NULL
);
283 sto
= get_rt_sto(sto
);
289 pto_a
= sto
+ sx
* sizeof(uint64_t);
290 pto
= address_space_ldq(&address_space_memory
, pto_a
,
291 MEMTXATTRS_UNSPECIFIED
, NULL
);
292 pto
= get_st_pto(pto
);
298 px_a
= pto
+ px
* sizeof(uint64_t);
299 pte
= address_space_ldq(&address_space_memory
, px_a
,
300 MEMTXATTRS_UNSPECIFIED
, NULL
);
306 static IOMMUTLBEntry
s390_translate_iommu(MemoryRegion
*iommu
, hwaddr addr
,
311 S390PCIBusDevice
*pbdev
= container_of(iommu
, S390PCIBusDevice
, iommu_mr
);
313 IOMMUTLBEntry ret
= {
314 .target_as
= &address_space_memory
,
316 .translated_addr
= 0,
317 .addr_mask
= ~(hwaddr
)0,
321 if (!pbdev
->configured
|| !pbdev
->pdev
|| !(pbdev
->fh
& FH_ENABLED
)) {
325 DPRINTF("iommu trans addr 0x%" PRIx64
"\n", addr
);
327 s
= S390_PCI_HOST_BRIDGE(pci_device_root_bus(pbdev
->pdev
)->qbus
.parent
);
328 /* s390 does not have an APIC mapped to main storage so we use
329 * a separate AddressSpace only for msix notifications
331 if (addr
== ZPCI_MSI_ADDR
) {
332 ret
.target_as
= &s
->msix_notify_as
;
334 ret
.translated_addr
= addr
;
335 ret
.addr_mask
= 0xfff;
340 if (!pbdev
->g_iota
) {
341 pbdev
->error_state
= true;
342 pbdev
->lgstg_blocked
= true;
343 s390_pci_generate_error_event(ERR_EVENT_INVALAS
, pbdev
->fh
, pbdev
->fid
,
348 if (addr
< pbdev
->pba
|| addr
> pbdev
->pal
) {
349 pbdev
->error_state
= true;
350 pbdev
->lgstg_blocked
= true;
351 s390_pci_generate_error_event(ERR_EVENT_OORANGE
, pbdev
->fh
, pbdev
->fid
,
356 pte
= s390_guest_io_table_walk(s390_pci_get_table_origin(pbdev
->g_iota
),
360 pbdev
->error_state
= true;
361 pbdev
->lgstg_blocked
= true;
362 s390_pci_generate_error_event(ERR_EVENT_SERR
, pbdev
->fh
, pbdev
->fid
,
363 addr
, ERR_EVENT_Q_BIT
);
367 flags
= pte
& ZPCI_PTE_FLAG_MASK
;
369 ret
.translated_addr
= pte
& ZPCI_PTE_ADDR_MASK
;
370 ret
.addr_mask
= 0xfff;
372 if (flags
& ZPCI_PTE_INVALID
) {
373 ret
.perm
= IOMMU_NONE
;
381 static const MemoryRegionIOMMUOps s390_iommu_ops
= {
382 .translate
= s390_translate_iommu
,
385 static AddressSpace
*s390_pci_dma_iommu(PCIBus
*bus
, void *opaque
, int devfn
)
387 S390pciState
*s
= opaque
;
389 return &s
->pbdev
[PCI_SLOT(devfn
)].as
;
392 static uint8_t set_ind_atomic(uint64_t ind_loc
, uint8_t to_be_set
)
394 uint8_t ind_old
, ind_new
;
398 ind_addr
= cpu_physical_memory_map(ind_loc
, &len
, 1);
400 s390_pci_generate_error_event(ERR_EVENT_AIRERR
, 0, 0, 0, 0);
405 ind_new
= ind_old
| to_be_set
;
406 } while (atomic_cmpxchg(ind_addr
, ind_old
, ind_new
) != ind_old
);
407 cpu_physical_memory_unmap(ind_addr
, len
, 1, len
);
412 static void s390_msi_ctrl_write(void *opaque
, hwaddr addr
, uint64_t data
,
415 S390PCIBusDevice
*pbdev
;
416 uint32_t io_int_word
;
417 uint32_t fid
= data
>> ZPCI_MSI_VEC_BITS
;
418 uint32_t vec
= data
& ZPCI_MSI_VEC_MASK
;
423 DPRINTF("write_msix data 0x%" PRIx64
" fid %d vec 0x%x\n", data
, fid
, vec
);
425 pbdev
= s390_pci_find_dev_by_fid(fid
);
427 e
|= (vec
<< ERR_EVENT_MVN_OFFSET
);
428 s390_pci_generate_error_event(ERR_EVENT_NOMSI
, 0, fid
, addr
, e
);
432 if (!(pbdev
->fh
& FH_ENABLED
)) {
436 ind_bit
= pbdev
->routes
.adapter
.ind_offset
;
437 sum_bit
= pbdev
->routes
.adapter
.summary_offset
;
439 set_ind_atomic(pbdev
->routes
.adapter
.ind_addr
+ (ind_bit
+ vec
) / 8,
440 0x80 >> ((ind_bit
+ vec
) % 8));
441 if (!set_ind_atomic(pbdev
->routes
.adapter
.summary_addr
+ sum_bit
/ 8,
442 0x80 >> (sum_bit
% 8))) {
443 io_int_word
= (pbdev
->isc
<< 27) | IO_INT_WORD_AI
;
444 s390_io_interrupt(0, 0, 0, io_int_word
);
448 static uint64_t s390_msi_ctrl_read(void *opaque
, hwaddr addr
, unsigned size
)
453 static const MemoryRegionOps s390_msi_ctrl_ops
= {
454 .write
= s390_msi_ctrl_write
,
455 .read
= s390_msi_ctrl_read
,
456 .endianness
= DEVICE_LITTLE_ENDIAN
,
459 void s390_pcihost_iommu_configure(S390PCIBusDevice
*pbdev
, bool enable
)
461 pbdev
->configured
= false;
464 uint64_t size
= pbdev
->pal
- pbdev
->pba
+ 1;
465 memory_region_init_iommu(&pbdev
->iommu_mr
, OBJECT(&pbdev
->mr
),
466 &s390_iommu_ops
, "iommu-s390", size
);
467 memory_region_add_subregion(&pbdev
->mr
, pbdev
->pba
, &pbdev
->iommu_mr
);
469 memory_region_del_subregion(&pbdev
->mr
, &pbdev
->iommu_mr
);
472 pbdev
->configured
= true;
475 static void s390_pcihost_init_as(S390pciState
*s
)
478 S390PCIBusDevice
*pbdev
;
480 for (i
= 0; i
< PCI_SLOT_MAX
; i
++) {
481 pbdev
= &s
->pbdev
[i
];
482 memory_region_init(&pbdev
->mr
, OBJECT(s
),
483 "iommu-root-s390", UINT64_MAX
);
484 address_space_init(&pbdev
->as
, &pbdev
->mr
, "iommu-pci");
487 memory_region_init_io(&s
->msix_notify_mr
, OBJECT(s
),
488 &s390_msi_ctrl_ops
, s
, "msix-s390", UINT64_MAX
);
489 address_space_init(&s
->msix_notify_as
, &s
->msix_notify_mr
, "msix-pci");
492 static int s390_pcihost_init(SysBusDevice
*dev
)
496 PCIHostState
*phb
= PCI_HOST_BRIDGE(dev
);
497 S390pciState
*s
= S390_PCI_HOST_BRIDGE(dev
);
499 DPRINTF("host_init\n");
501 b
= pci_register_bus(DEVICE(dev
), NULL
,
502 s390_pci_set_irq
, s390_pci_map_irq
, NULL
,
503 get_system_memory(), get_system_io(), 0, 64,
505 s390_pcihost_init_as(s
);
506 pci_setup_iommu(b
, s390_pci_dma_iommu
, s
);
509 qbus_set_hotplug_handler(bus
, DEVICE(dev
), NULL
);
511 QTAILQ_INIT(&s
->pending_sei
);
515 static int s390_pcihost_setup_msix(S390PCIBusDevice
*pbdev
)
521 pos
= pci_find_capability(pbdev
->pdev
, PCI_CAP_ID_MSIX
);
523 pbdev
->msix
.available
= false;
527 ctrl
= pci_host_config_read_common(pbdev
->pdev
, pos
+ PCI_MSIX_FLAGS
,
528 pci_config_size(pbdev
->pdev
), sizeof(ctrl
));
529 table
= pci_host_config_read_common(pbdev
->pdev
, pos
+ PCI_MSIX_TABLE
,
530 pci_config_size(pbdev
->pdev
), sizeof(table
));
531 pba
= pci_host_config_read_common(pbdev
->pdev
, pos
+ PCI_MSIX_PBA
,
532 pci_config_size(pbdev
->pdev
), sizeof(pba
));
534 pbdev
->msix
.table_bar
= table
& PCI_MSIX_FLAGS_BIRMASK
;
535 pbdev
->msix
.table_offset
= table
& ~PCI_MSIX_FLAGS_BIRMASK
;
536 pbdev
->msix
.pba_bar
= pba
& PCI_MSIX_FLAGS_BIRMASK
;
537 pbdev
->msix
.pba_offset
= pba
& ~PCI_MSIX_FLAGS_BIRMASK
;
538 pbdev
->msix
.entries
= (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
539 pbdev
->msix
.available
= true;
543 static void s390_pcihost_hot_plug(HotplugHandler
*hotplug_dev
,
544 DeviceState
*dev
, Error
**errp
)
546 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
547 S390PCIBusDevice
*pbdev
;
548 S390pciState
*s
= S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev
)
551 pbdev
= &s
->pbdev
[PCI_SLOT(pci_dev
->devfn
)];
553 pbdev
->fid
= s390_pci_get_pfid(pci_dev
);
554 pbdev
->pdev
= pci_dev
;
555 pbdev
->configured
= true;
556 pbdev
->fh
= s390_pci_get_pfh(pci_dev
);
558 s390_pcihost_setup_msix(pbdev
);
560 if (dev
->hotplugged
) {
561 s390_pci_generate_plug_event(HP_EVENT_RESERVED_TO_STANDBY
,
562 pbdev
->fh
, pbdev
->fid
);
563 s390_pci_generate_plug_event(HP_EVENT_TO_CONFIGURED
,
564 pbdev
->fh
, pbdev
->fid
);
568 static void s390_pcihost_hot_unplug(HotplugHandler
*hotplug_dev
,
569 DeviceState
*dev
, Error
**errp
)
571 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
572 S390pciState
*s
= S390_PCI_HOST_BRIDGE(pci_device_root_bus(pci_dev
)
574 S390PCIBusDevice
*pbdev
= &s
->pbdev
[PCI_SLOT(pci_dev
->devfn
)];
576 if (pbdev
->configured
) {
577 pbdev
->configured
= false;
578 s390_pci_generate_plug_event(HP_EVENT_CONFIGURED_TO_STBRES
,
579 pbdev
->fh
, pbdev
->fid
);
582 s390_pci_generate_plug_event(HP_EVENT_STANDBY_TO_RESERVED
,
583 pbdev
->fh
, pbdev
->fid
);
587 object_unparent(OBJECT(pci_dev
));
590 static void s390_pcihost_class_init(ObjectClass
*klass
, void *data
)
592 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
593 DeviceClass
*dc
= DEVICE_CLASS(klass
);
594 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(klass
);
596 dc
->cannot_instantiate_with_device_add_yet
= true;
597 k
->init
= s390_pcihost_init
;
598 hc
->plug
= s390_pcihost_hot_plug
;
599 hc
->unplug
= s390_pcihost_hot_unplug
;
600 msi_supported
= true;
603 static const TypeInfo s390_pcihost_info
= {
604 .name
= TYPE_S390_PCI_HOST_BRIDGE
,
605 .parent
= TYPE_PCI_HOST_BRIDGE
,
606 .instance_size
= sizeof(S390pciState
),
607 .class_init
= s390_pcihost_class_init
,
608 .interfaces
= (InterfaceInfo
[]) {
609 { TYPE_HOTPLUG_HANDLER
},
614 static void s390_pci_register_types(void)
616 type_register_static(&s390_pcihost_info
);
619 type_init(s390_pci_register_types
)