2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "qemu/error-report.h"
15 #include "target/ppc/cpu.h"
16 #include "sysemu/cpus.h"
17 #include "sysemu/reset.h"
18 #include "migration/vmstate.h"
19 #include "monitor/monitor.h"
20 #include "hw/ppc/fdt.h"
21 #include "hw/ppc/spapr.h"
22 #include "hw/ppc/spapr_cpu_core.h"
23 #include "hw/ppc/spapr_xive.h"
24 #include "hw/ppc/xive.h"
25 #include "hw/ppc/xive_regs.h"
26 #include "hw/qdev-properties.h"
29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
30 * use for the ESB pages and the TIMA pages
32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
36 * The allocation of VP blocks is a complex operation in OPAL and the
37 * VP identifiers have a relation with the number of HW chips, the
38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
39 * controller model does not have the same constraints and can use a
40 * simple mapping scheme of the CPU vcpu_id
42 * These identifiers are never returned to the OS.
45 #define SPAPR_XIVE_NVT_BASE 0x400
48 * sPAPR NVT and END indexing helpers
50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
52 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
55 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
56 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
61 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
65 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
69 static int spapr_xive_target_to_nvt(uint32_t target
,
70 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
72 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
78 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
86 int spapr_xive_end_to_target(uint8_t end_blk
, uint32_t end_idx
,
87 uint32_t *out_server
, uint8_t *out_prio
)
90 assert(end_blk
== SPAPR_XIVE_BLOCK_ID
);
93 *out_server
= end_idx
>> 3;
97 *out_prio
= end_idx
& 0x7;
102 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
103 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
108 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
112 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
116 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
117 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
119 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
125 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
130 * On sPAPR machines, use a simplified output for the XIVE END
131 * structure dumping only the information related to the OS EQ.
133 static void spapr_xive_end_pic_print_info(SpaprXive
*xive
, XiveEND
*end
,
136 uint64_t qaddr_base
= xive_end_qaddr(end
);
137 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
138 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
139 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
140 uint32_t qentries
= 1 << (qsize
+ 10);
141 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
142 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
144 monitor_printf(mon
, "%3d/%d % 6d/%5d @%"PRIx64
" ^%d",
145 spapr_xive_nvt_to_target(0, nvt
),
146 priority
, qindex
, qentries
, qaddr_base
, qgen
);
148 xive_end_queue_pic_print_info(end
, 6, mon
);
151 void spapr_xive_pic_print_info(SpaprXive
*xive
, Monitor
*mon
)
153 XiveSource
*xsrc
= &xive
->source
;
156 if (kvm_irqchip_in_kernel()) {
157 Error
*local_err
= NULL
;
159 kvmppc_xive_synchronize_state(xive
, &local_err
);
161 error_report_err(local_err
);
166 monitor_printf(mon
, " LISN PQ EISN CPU/PRIO EQ\n");
168 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
169 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
170 XiveEAS
*eas
= &xive
->eat
[i
];
172 if (!xive_eas_is_valid(eas
)) {
176 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
177 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
178 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
179 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
180 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
181 xive_eas_is_masked(eas
) ? "M" : " ",
182 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
184 if (!xive_eas_is_masked(eas
)) {
185 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
188 assert(end_idx
< xive
->nr_ends
);
189 end
= &xive
->endt
[end_idx
];
191 if (xive_end_is_valid(end
)) {
192 spapr_xive_end_pic_print_info(xive
, end
, mon
);
195 monitor_printf(mon
, "\n");
199 void spapr_xive_mmio_set_enabled(SpaprXive
*xive
, bool enable
)
201 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
202 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
204 /* Disable the END ESBs until a guest OS makes use of them */
205 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
208 static void spapr_xive_end_reset(XiveEND
*end
)
210 memset(end
, 0, sizeof(*end
));
212 /* switch off the escalation and notification ESBs */
213 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
216 static void spapr_xive_reset(void *dev
)
218 SpaprXive
*xive
= SPAPR_XIVE(dev
);
222 * The XiveSource has its own reset handler, which mask off all
226 /* Mask all valid EASs in the IRQ number space. */
227 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
228 XiveEAS
*eas
= &xive
->eat
[i
];
229 if (xive_eas_is_valid(eas
)) {
230 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
237 for (i
= 0; i
< xive
->nr_ends
; i
++) {
238 spapr_xive_end_reset(&xive
->endt
[i
]);
242 static void spapr_xive_instance_init(Object
*obj
)
244 SpaprXive
*xive
= SPAPR_XIVE(obj
);
246 object_initialize_child(obj
, "source", &xive
->source
, sizeof(xive
->source
),
247 TYPE_XIVE_SOURCE
, &error_abort
, NULL
);
249 object_initialize_child(obj
, "end_source", &xive
->end_source
,
250 sizeof(xive
->end_source
), TYPE_XIVE_END_SOURCE
,
253 /* Not connected to the KVM XIVE device */
257 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
259 SpaprXive
*xive
= SPAPR_XIVE(dev
);
260 XiveSource
*xsrc
= &xive
->source
;
261 XiveENDSource
*end_xsrc
= &xive
->end_source
;
262 Error
*local_err
= NULL
;
264 if (!xive
->nr_irqs
) {
265 error_setg(errp
, "Number of interrupt needs to be greater 0");
269 if (!xive
->nr_ends
) {
270 error_setg(errp
, "Number of interrupt needs to be greater 0");
275 * Initialize the internal sources, for IPIs and virtual devices.
277 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
279 object_property_set_link(OBJECT(xsrc
), OBJECT(xive
), "xive",
281 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
283 error_propagate(errp
, local_err
);
286 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
289 * Initialize the END ESB source
291 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
293 object_property_set_link(OBJECT(end_xsrc
), OBJECT(xive
), "xive",
295 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
297 error_propagate(errp
, local_err
);
300 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
302 /* Set the mapping address of the END ESB pages after the source ESBs */
303 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
306 * Allocate the routing tables
308 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
309 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
311 xive
->nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
312 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
314 qemu_register_reset(spapr_xive_reset
, dev
);
316 /* TIMA initialization */
317 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
318 "xive.tima", 4ull << TM_SHIFT
);
319 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
322 * Map all regions. These will be enabled or disabled at reset and
323 * can also be overridden by KVM memory regions if active
325 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
326 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
327 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
330 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
331 uint32_t eas_idx
, XiveEAS
*eas
)
333 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
335 if (eas_idx
>= xive
->nr_irqs
) {
339 *eas
= xive
->eat
[eas_idx
];
343 static int spapr_xive_get_end(XiveRouter
*xrtr
,
344 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
346 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
348 if (end_idx
>= xive
->nr_ends
) {
352 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
356 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
357 uint32_t end_idx
, XiveEND
*end
,
360 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
362 if (end_idx
>= xive
->nr_ends
) {
366 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
370 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
371 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
373 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
374 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
377 /* TODO: should we assert() if we can find a NVT ? */
382 * sPAPR does not maintain a NVT table. Return that the NVT is
383 * valid if we have found a matching CPU
385 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
389 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
390 uint32_t nvt_idx
, XiveNVT
*nvt
,
394 * We don't need to write back to the NVTs because the sPAPR
395 * machine should never hit a non-scheduled NVT. It should never
398 g_assert_not_reached();
401 static XiveTCTX
*spapr_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
403 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
405 return spapr_cpu_state(cpu
)->tctx
;
408 static int spapr_xive_match_nvt(XivePresenter
*xptr
, uint8_t format
,
409 uint8_t nvt_blk
, uint32_t nvt_idx
,
410 bool cam_ignore
, uint8_t priority
,
411 uint32_t logic_serv
, XiveTCTXMatch
*match
)
417 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
418 XiveTCTX
*tctx
= spapr_cpu_state(cpu
)->tctx
;
422 * Skip partially initialized vCPUs. This can happen when
423 * vCPUs are hotplugged.
430 * Check the thread context CAM lines and record matches.
432 ring
= xive_presenter_tctx_match(xptr
, tctx
, format
, nvt_blk
, nvt_idx
,
433 cam_ignore
, logic_serv
);
435 * Save the matching thread interrupt context and follow on to
436 * check for duplicates which are invalid.
440 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a thread "
441 "context NVT %x/%x\n", nvt_blk
, nvt_idx
);
454 static const VMStateDescription vmstate_spapr_xive_end
= {
455 .name
= TYPE_SPAPR_XIVE
"/end",
457 .minimum_version_id
= 1,
458 .fields
= (VMStateField
[]) {
459 VMSTATE_UINT32(w0
, XiveEND
),
460 VMSTATE_UINT32(w1
, XiveEND
),
461 VMSTATE_UINT32(w2
, XiveEND
),
462 VMSTATE_UINT32(w3
, XiveEND
),
463 VMSTATE_UINT32(w4
, XiveEND
),
464 VMSTATE_UINT32(w5
, XiveEND
),
465 VMSTATE_UINT32(w6
, XiveEND
),
466 VMSTATE_UINT32(w7
, XiveEND
),
467 VMSTATE_END_OF_LIST()
471 static const VMStateDescription vmstate_spapr_xive_eas
= {
472 .name
= TYPE_SPAPR_XIVE
"/eas",
474 .minimum_version_id
= 1,
475 .fields
= (VMStateField
[]) {
476 VMSTATE_UINT64(w
, XiveEAS
),
477 VMSTATE_END_OF_LIST()
481 static int vmstate_spapr_xive_pre_save(void *opaque
)
483 if (kvm_irqchip_in_kernel()) {
484 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque
));
491 * Called by the sPAPR IRQ backend 'post_load' method at the machine
494 static int spapr_xive_post_load(SpaprInterruptController
*intc
, int version_id
)
496 if (kvm_irqchip_in_kernel()) {
497 return kvmppc_xive_post_load(SPAPR_XIVE(intc
), version_id
);
503 static const VMStateDescription vmstate_spapr_xive
= {
504 .name
= TYPE_SPAPR_XIVE
,
506 .minimum_version_id
= 1,
507 .pre_save
= vmstate_spapr_xive_pre_save
,
508 .post_load
= NULL
, /* handled at the machine level */
509 .fields
= (VMStateField
[]) {
510 VMSTATE_UINT32_EQUAL(nr_irqs
, SpaprXive
, NULL
),
511 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, SpaprXive
, nr_irqs
,
512 vmstate_spapr_xive_eas
, XiveEAS
),
513 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, SpaprXive
, nr_ends
,
514 vmstate_spapr_xive_end
, XiveEND
),
515 VMSTATE_END_OF_LIST()
519 static int spapr_xive_claim_irq(SpaprInterruptController
*intc
, int lisn
,
520 bool lsi
, Error
**errp
)
522 SpaprXive
*xive
= SPAPR_XIVE(intc
);
523 XiveSource
*xsrc
= &xive
->source
;
525 assert(lisn
< xive
->nr_irqs
);
527 if (xive_eas_is_valid(&xive
->eat
[lisn
])) {
528 error_setg(errp
, "IRQ %d is not free", lisn
);
533 * Set default values when allocating an IRQ number
535 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
537 xive_source_irq_set_lsi(xsrc
, lisn
);
540 if (kvm_irqchip_in_kernel()) {
541 return kvmppc_xive_source_reset_one(xsrc
, lisn
, errp
);
547 static void spapr_xive_free_irq(SpaprInterruptController
*intc
, int lisn
)
549 SpaprXive
*xive
= SPAPR_XIVE(intc
);
550 assert(lisn
< xive
->nr_irqs
);
552 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
555 static Property spapr_xive_properties
[] = {
556 DEFINE_PROP_UINT32("nr-irqs", SpaprXive
, nr_irqs
, 0),
557 DEFINE_PROP_UINT32("nr-ends", SpaprXive
, nr_ends
, 0),
558 DEFINE_PROP_UINT64("vc-base", SpaprXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
559 DEFINE_PROP_UINT64("tm-base", SpaprXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
560 DEFINE_PROP_END_OF_LIST(),
563 static int spapr_xive_cpu_intc_create(SpaprInterruptController
*intc
,
564 PowerPCCPU
*cpu
, Error
**errp
)
566 SpaprXive
*xive
= SPAPR_XIVE(intc
);
568 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
570 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(xive
), errp
);
575 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
579 static void xive_tctx_set_os_cam(XiveTCTX
*tctx
, uint32_t os_cam
)
581 uint32_t qw1w2
= cpu_to_be32(TM_QW1W2_VO
| os_cam
);
582 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &qw1w2
, 4);
585 static void spapr_xive_cpu_intc_reset(SpaprInterruptController
*intc
,
588 XiveTCTX
*tctx
= spapr_cpu_state(cpu
)->tctx
;
592 xive_tctx_reset(tctx
);
595 * When a Virtual Processor is scheduled to run on a HW thread,
596 * the hypervisor pushes its identifier in the OS CAM line.
597 * Emulate the same behavior under QEMU.
599 spapr_xive_cpu_to_nvt(cpu
, &nvt_blk
, &nvt_idx
);
601 xive_tctx_set_os_cam(tctx
, xive_nvt_cam_line(nvt_blk
, nvt_idx
));
604 static void spapr_xive_cpu_intc_destroy(SpaprInterruptController
*intc
,
607 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
609 xive_tctx_destroy(spapr_cpu
->tctx
);
610 spapr_cpu
->tctx
= NULL
;
613 static void spapr_xive_set_irq(SpaprInterruptController
*intc
, int irq
, int val
)
615 SpaprXive
*xive
= SPAPR_XIVE(intc
);
617 if (kvm_irqchip_in_kernel()) {
618 kvmppc_xive_source_set_irq(&xive
->source
, irq
, val
);
620 xive_source_set_irq(&xive
->source
, irq
, val
);
624 static void spapr_xive_print_info(SpaprInterruptController
*intc
, Monitor
*mon
)
626 SpaprXive
*xive
= SPAPR_XIVE(intc
);
630 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
632 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
635 spapr_xive_pic_print_info(xive
, mon
);
638 static void spapr_xive_dt(SpaprInterruptController
*intc
, uint32_t nr_servers
,
639 void *fdt
, uint32_t phandle
)
641 SpaprXive
*xive
= SPAPR_XIVE(intc
);
643 uint64_t timas
[2 * 2];
644 /* Interrupt number ranges for the IPIs */
645 uint32_t lisn_ranges
[] = {
647 cpu_to_be32(nr_servers
),
650 * EQ size - the sizes of pages supported by the system 4K, 64K,
651 * 2M, 16M. We only advertise 64K for the moment.
653 uint32_t eq_sizes
[] = {
654 cpu_to_be32(16), /* 64K */
657 * The following array is in sync with the reserved priorities
658 * defined by the 'spapr_xive_priority_is_reserved' routine.
660 uint32_t plat_res_int_priorities
[] = {
661 cpu_to_be32(7), /* start */
662 cpu_to_be32(0xf8), /* count */
665 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
666 timas
[0] = cpu_to_be64(xive
->tm_base
+
667 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
668 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
669 timas
[2] = cpu_to_be64(xive
->tm_base
+
670 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
671 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
673 _FDT(node
= fdt_add_subnode(fdt
, 0, xive
->nodename
));
675 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
676 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
678 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
679 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
681 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
682 sizeof(lisn_ranges
)));
684 /* For Linux to link the LSIs to the interrupt controller. */
685 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
686 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
689 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
690 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
693 * The "ibm,plat-res-int-priorities" property defines the priority
694 * ranges reserved by the hypervisor
696 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
697 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));
700 static int spapr_xive_activate(SpaprInterruptController
*intc
,
701 uint32_t nr_servers
, Error
**errp
)
703 SpaprXive
*xive
= SPAPR_XIVE(intc
);
706 int rc
= spapr_irq_init_kvm(kvmppc_xive_connect
, intc
, nr_servers
,
713 /* Activate the XIVE MMIOs */
714 spapr_xive_mmio_set_enabled(xive
, true);
719 static void spapr_xive_deactivate(SpaprInterruptController
*intc
)
721 SpaprXive
*xive
= SPAPR_XIVE(intc
);
723 spapr_xive_mmio_set_enabled(xive
, false);
725 if (kvm_irqchip_in_kernel()) {
726 kvmppc_xive_disconnect(intc
);
730 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
732 DeviceClass
*dc
= DEVICE_CLASS(klass
);
733 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
734 SpaprInterruptControllerClass
*sicc
= SPAPR_INTC_CLASS(klass
);
735 XivePresenterClass
*xpc
= XIVE_PRESENTER_CLASS(klass
);
737 dc
->desc
= "sPAPR XIVE Interrupt Controller";
738 dc
->props
= spapr_xive_properties
;
739 dc
->realize
= spapr_xive_realize
;
740 dc
->vmsd
= &vmstate_spapr_xive
;
742 xrc
->get_eas
= spapr_xive_get_eas
;
743 xrc
->get_end
= spapr_xive_get_end
;
744 xrc
->write_end
= spapr_xive_write_end
;
745 xrc
->get_nvt
= spapr_xive_get_nvt
;
746 xrc
->write_nvt
= spapr_xive_write_nvt
;
747 xrc
->get_tctx
= spapr_xive_get_tctx
;
749 sicc
->activate
= spapr_xive_activate
;
750 sicc
->deactivate
= spapr_xive_deactivate
;
751 sicc
->cpu_intc_create
= spapr_xive_cpu_intc_create
;
752 sicc
->cpu_intc_reset
= spapr_xive_cpu_intc_reset
;
753 sicc
->cpu_intc_destroy
= spapr_xive_cpu_intc_destroy
;
754 sicc
->claim_irq
= spapr_xive_claim_irq
;
755 sicc
->free_irq
= spapr_xive_free_irq
;
756 sicc
->set_irq
= spapr_xive_set_irq
;
757 sicc
->print_info
= spapr_xive_print_info
;
758 sicc
->dt
= spapr_xive_dt
;
759 sicc
->post_load
= spapr_xive_post_load
;
761 xpc
->match_nvt
= spapr_xive_match_nvt
;
764 static const TypeInfo spapr_xive_info
= {
765 .name
= TYPE_SPAPR_XIVE
,
766 .parent
= TYPE_XIVE_ROUTER
,
767 .instance_init
= spapr_xive_instance_init
,
768 .instance_size
= sizeof(SpaprXive
),
769 .class_init
= spapr_xive_class_init
,
770 .interfaces
= (InterfaceInfo
[]) {
776 static void spapr_xive_register_types(void)
778 type_register_static(&spapr_xive_info
);
781 type_init(spapr_xive_register_types
)
786 * The terminology used by the XIVE hcalls is the following :
789 * EQ Event Queue assigned by OS to receive event data
790 * ESB page for source interrupt management
791 * LISN Logical Interrupt Source Number identifying a source in the
793 * EISN Effective Interrupt Source Number used by guest OS to
794 * identify source in the guest
796 * The EAS, END, NVT structures are not exposed.
800 * Linux hosts under OPAL reserve priority 7 for their own escalation
801 * interrupts (DD2.X POWER9). So we only allow the guest to use
804 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
809 case 7: /* OPAL escalation queue */
816 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
817 * real address of the MMIO page through which the Event State Buffer
818 * entry associated with the value of the "lisn" parameter is managed.
824 * - R5: "lisn" is per "interrupts", "interrupt-map", or
825 * "ibm,xive-lisn-ranges" properties, or as returned by the
826 * ibm,query-interrupt-source-number RTAS call, or as returned
827 * by the H_ALLOCATE_VAS_WINDOW hcall
831 * Bits 0-59: Reserved
832 * Bit 60: H_INT_ESB must be used for Event State Buffer
834 * Bit 61: 1 == LSI 0 == MSI
835 * Bit 62: the full function page supports trigger
836 * Bit 63: Store EOI Supported
837 * - R5: Logical Real address of full function Event State Buffer
838 * management page, -1 if H_INT_ESB hcall flag is set to 1.
839 * - R6: Logical Real Address of trigger only Event State Buffer
840 * management page or -1.
841 * - R7: Power of 2 page size for the ESB management pages returned in
845 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
846 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
847 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
849 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
851 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
852 SpaprMachineState
*spapr
,
856 SpaprXive
*xive
= spapr
->xive
;
857 XiveSource
*xsrc
= &xive
->source
;
858 target_ulong flags
= args
[0];
859 target_ulong lisn
= args
[1];
861 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
869 if (lisn
>= xive
->nr_irqs
) {
870 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
875 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
876 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
882 * All sources are emulated under the main XIVE object and share
883 * the same characteristics.
886 if (!xive_source_esb_has_2page(xsrc
)) {
887 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
889 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
890 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
894 * Force the use of the H_INT_ESB hcall in case of an LSI
895 * interrupt. This is necessary under KVM to re-trigger the
896 * interrupt if the level is still asserted
898 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
899 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
902 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
903 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
908 if (xive_source_esb_has_2page(xsrc
) &&
909 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
910 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
915 if (xive_source_esb_has_2page(xsrc
)) {
916 args
[3] = xsrc
->esb_shift
- 1;
918 args
[3] = xsrc
->esb_shift
;
925 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
926 * Interrupt Source to a target. The Logical Interrupt Source is
927 * designated with the "lisn" parameter and the target is designated
928 * with the "target" and "priority" parameters. Upon return from the
929 * hcall(), no additional interrupts will be directed to the old EQ.
934 * Bits 0-61: Reserved
935 * Bit 62: set the "eisn" in the EAS
936 * Bit 63: masks the interrupt source in the hardware interrupt
937 * control structure. An interrupt masked by this mechanism will
938 * be dropped, but it's source state bits will still be
939 * set. There is no race-free way of unmasking and restoring the
940 * source. Thus this should only be used in interrupts that are
941 * also masked at the source, and only in cases where the
942 * interrupt is not meant to be used for a large amount of time
943 * because no valid target exists for it for example
944 * - R5: "lisn" is per "interrupts", "interrupt-map", or
945 * "ibm,xive-lisn-ranges" properties, or as returned by the
946 * ibm,query-interrupt-source-number RTAS call, or as returned by
947 * the H_ALLOCATE_VAS_WINDOW hcall
948 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
949 * "ibm,ppc-interrupt-gserver#s"
950 * - R7: "priority" is a valid priority not in
951 * "ibm,plat-res-int-priorities"
952 * - R8: "eisn" is the guest EISN associated with the "lisn"
958 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
959 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
961 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
962 SpaprMachineState
*spapr
,
966 SpaprXive
*xive
= spapr
->xive
;
967 XiveEAS eas
, new_eas
;
968 target_ulong flags
= args
[0];
969 target_ulong lisn
= args
[1];
970 target_ulong target
= args
[2];
971 target_ulong priority
= args
[3];
972 target_ulong eisn
= args
[4];
976 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
980 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
984 if (lisn
>= xive
->nr_irqs
) {
985 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
990 eas
= xive
->eat
[lisn
];
991 if (!xive_eas_is_valid(&eas
)) {
992 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
997 /* priority 0xff is used to reset the EAS */
998 if (priority
== 0xff) {
999 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
1003 if (flags
& SPAPR_XIVE_SRC_MASK
) {
1004 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
1006 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
1009 if (spapr_xive_priority_is_reserved(priority
)) {
1010 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1011 " is reserved\n", priority
);
1016 * Validate that "target" is part of the list of threads allocated
1017 * to the partition. For that, find the END corresponding to the
1020 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1024 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
1025 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
1027 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
1028 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
1031 if (kvm_irqchip_in_kernel()) {
1032 Error
*local_err
= NULL
;
1034 kvmppc_xive_set_source_config(xive
, lisn
, &new_eas
, &local_err
);
1036 error_report_err(local_err
);
1042 xive
->eat
[lisn
] = new_eas
;
1047 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
1048 * target/priority pair is assigned to the specified Logical Interrupt
1054 * Bits 0-63 Reserved
1055 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1056 * "ibm,xive-lisn-ranges" properties, or as returned by the
1057 * ibm,query-interrupt-source-number RTAS call, or as
1058 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1061 * - R4: Target to which the specified Logical Interrupt Source is
1063 * - R5: Priority to which the specified Logical Interrupt Source is
1065 * - R6: EISN for the specified Logical Interrupt Source (this will be
1066 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
1068 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
1069 SpaprMachineState
*spapr
,
1070 target_ulong opcode
,
1073 SpaprXive
*xive
= spapr
->xive
;
1074 target_ulong flags
= args
[0];
1075 target_ulong lisn
= args
[1];
1079 uint32_t end_idx
, nvt_idx
;
1081 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1089 if (lisn
>= xive
->nr_irqs
) {
1090 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1095 eas
= xive
->eat
[lisn
];
1096 if (!xive_eas_is_valid(&eas
)) {
1097 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1102 /* EAS_END_BLOCK is unused on sPAPR */
1103 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
1105 assert(end_idx
< xive
->nr_ends
);
1106 end
= &xive
->endt
[end_idx
];
1108 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
1109 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1110 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
1112 if (xive_eas_is_masked(&eas
)) {
1115 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1118 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
1124 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
1125 * address of the notification management page associated with the
1126 * specified target and priority.
1131 * Bits 0-63 Reserved
1132 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1133 * "ibm,ppc-interrupt-gserver#s"
1134 * - R6: "priority" is a valid priority not in
1135 * "ibm,plat-res-int-priorities"
1138 * - R4: Logical real address of notification page
1139 * - R5: Power of 2 page size of the notification page
1141 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
1142 SpaprMachineState
*spapr
,
1143 target_ulong opcode
,
1146 SpaprXive
*xive
= spapr
->xive
;
1147 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1148 target_ulong flags
= args
[0];
1149 target_ulong target
= args
[1];
1150 target_ulong priority
= args
[2];
1155 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1164 * H_STATE should be returned if a H_INT_RESET is in progress.
1165 * This is not needed when running the emulation under QEMU
1168 if (spapr_xive_priority_is_reserved(priority
)) {
1169 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1170 " is reserved\n", priority
);
1175 * Validate that "target" is part of the list of threads allocated
1176 * to the partition. For that, find the END corresponding to the
1179 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1183 assert(end_idx
< xive
->nr_ends
);
1184 end
= &xive
->endt
[end_idx
];
1186 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
1187 if (xive_end_is_enqueue(end
)) {
1188 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1197 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
1198 * a given "target" and "priority". It is also used to set the
1199 * notification config associated with the EQ. An EQ size of 0 is
1200 * used to reset the EQ config for a given target and priority. If
1201 * resetting the EQ config, the END associated with the given "target"
1202 * and "priority" will be changed to disable queueing.
1204 * Upon return from the hcall(), no additional interrupts will be
1205 * directed to the old EQ (if one was set). The old EQ (if one was
1206 * set) should be investigated for interrupts that occurred prior to
1207 * or during the hcall().
1212 * Bits 0-62: Reserved
1213 * Bit 63: Unconditional Notify (n) per the XIVE spec
1214 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1215 * "ibm,ppc-interrupt-gserver#s"
1216 * - R6: "priority" is a valid priority not in
1217 * "ibm,plat-res-int-priorities"
1218 * - R7: "eventQueue": The logical real address of the start of the EQ
1219 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1225 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1227 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
1228 SpaprMachineState
*spapr
,
1229 target_ulong opcode
,
1232 SpaprXive
*xive
= spapr
->xive
;
1233 target_ulong flags
= args
[0];
1234 target_ulong target
= args
[1];
1235 target_ulong priority
= args
[2];
1236 target_ulong qpage
= args
[3];
1237 target_ulong qsize
= args
[4];
1239 uint8_t end_blk
, nvt_blk
;
1240 uint32_t end_idx
, nvt_idx
;
1242 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1246 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1251 * H_STATE should be returned if a H_INT_RESET is in progress.
1252 * This is not needed when running the emulation under QEMU
1255 if (spapr_xive_priority_is_reserved(priority
)) {
1256 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1257 " is reserved\n", priority
);
1262 * Validate that "target" is part of the list of threads allocated
1263 * to the partition. For that, find the END corresponding to the
1267 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1271 assert(end_idx
< xive
->nr_ends
);
1272 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
1279 if (!QEMU_IS_ALIGNED(qpage
, 1ul << qsize
)) {
1280 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: EQ @0x%" HWADDR_PRIx
1281 " is not naturally aligned with %" HWADDR_PRIx
"\n",
1282 qpage
, (hwaddr
)1 << qsize
);
1285 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
1286 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
1287 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
1288 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1291 /* reset queue and disable queueing */
1292 spapr_xive_end_reset(&end
);
1296 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1302 hwaddr plen
= 1 << qsize
;
1306 * Validate the guest EQ. We should also check that the queue
1307 * has been zeroed by the OS.
1309 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1310 MEMTXATTRS_UNSPECIFIED
);
1311 if (plen
!= 1 << qsize
) {
1312 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1313 HWADDR_PRIx
"\n", qpage
);
1316 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1319 /* "target" should have been validated above */
1320 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1321 g_assert_not_reached();
1325 * Ensure the priority and target are correctly set (they will not
1326 * be right after allocation)
1328 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1329 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1330 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1332 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1333 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1335 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1339 * The generation bit for the END starts at 1 and The END page
1340 * offset counter starts at 0.
1342 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1343 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1344 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1347 * TODO: issue syncs required to ensure all in-flight interrupts
1348 * are complete on the old END
1352 if (kvm_irqchip_in_kernel()) {
1353 Error
*local_err
= NULL
;
1355 kvmppc_xive_set_queue_config(xive
, end_blk
, end_idx
, &end
, &local_err
);
1357 error_report_err(local_err
);
1363 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1368 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1369 * target and priority.
1374 * Bits 0-62: Reserved
1375 * Bit 63: Debug: Return debug data
1376 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1377 * "ibm,ppc-interrupt-gserver#s"
1378 * - R6: "priority" is a valid priority not in
1379 * "ibm,plat-res-int-priorities"
1383 * Bits 0-61: Reserved
1384 * Bit 62: The value of Event Queue Generation Number (g) per
1385 * the XIVE spec if "Debug" = 1
1386 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1387 * - R5: The logical real address of the start of the EQ
1388 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1389 * - R7: The value of Event Queue Offset Counter per XIVE spec
1390 * if "Debug" = 1, else 0
1394 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1396 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1397 SpaprMachineState
*spapr
,
1398 target_ulong opcode
,
1401 SpaprXive
*xive
= spapr
->xive
;
1402 target_ulong flags
= args
[0];
1403 target_ulong target
= args
[1];
1404 target_ulong priority
= args
[2];
1409 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1413 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1418 * H_STATE should be returned if a H_INT_RESET is in progress.
1419 * This is not needed when running the emulation under QEMU
1422 if (spapr_xive_priority_is_reserved(priority
)) {
1423 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1424 " is reserved\n", priority
);
1429 * Validate that "target" is part of the list of threads allocated
1430 * to the partition. For that, find the END corresponding to the
1433 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1437 assert(end_idx
< xive
->nr_ends
);
1438 end
= &xive
->endt
[end_idx
];
1441 if (xive_end_is_notify(end
)) {
1442 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1445 if (xive_end_is_enqueue(end
)) {
1446 args
[1] = xive_end_qaddr(end
);
1447 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1453 if (kvm_irqchip_in_kernel()) {
1454 Error
*local_err
= NULL
;
1456 kvmppc_xive_get_queue_config(xive
, end_blk
, end_idx
, end
, &local_err
);
1458 error_report_err(local_err
);
1463 /* TODO: do we need any locking on the END ? */
1464 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1465 /* Load the event queue generation number into the return flags */
1466 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1468 /* Load R7 with the event queue offset counter */
1469 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1478 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1479 * reporting cache line pair for the calling thread. The reporting
1480 * cache lines will contain the OS interrupt context when the OS
1481 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1482 * interrupt. The reporting cache lines can be reset by inputting -1
1483 * in "reportingLine". Issuing the CI store byte without reporting
1484 * cache lines registered will result in the data not being accessible
1490 * Bits 0-63: Reserved
1491 * - R5: "reportingLine": The logical real address of the reporting cache
1497 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1498 SpaprMachineState
*spapr
,
1499 target_ulong opcode
,
1502 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1507 * H_STATE should be returned if a H_INT_RESET is in progress.
1508 * This is not needed when running the emulation under QEMU
1511 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1516 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1517 * real address of the reporting cache line pair set for the input
1518 * "target". If no reporting cache line pair has been set, -1 is
1524 * Bits 0-63: Reserved
1525 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1526 * "ibm,ppc-interrupt-gserver#s"
1527 * - R6: "reportingLine": The logical real address of the reporting
1531 * - R4: The logical real address of the reporting line if set, else -1
1533 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1534 SpaprMachineState
*spapr
,
1535 target_ulong opcode
,
1538 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1543 * H_STATE should be returned if a H_INT_RESET is in progress.
1544 * This is not needed when running the emulation under QEMU
1547 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1552 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1553 * page for the input "lisn". This hcall is only supported for LISNs
1554 * that have the ESB hcall flag set to 1 when returned from hcall()
1555 * H_INT_GET_SOURCE_INFO.
1560 * Bits 0-62: Reserved
1561 * bit 63: Store: Store=1, store operation, else load operation
1562 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1563 * "ibm,xive-lisn-ranges" properties, or as returned by the
1564 * ibm,query-interrupt-source-number RTAS call, or as
1565 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1566 * - R6: "esbOffset" is the offset into the ESB page for the load or
1568 * - R7: "storeData" is the data to write for a store operation
1571 * - R4: The value of the load if load operation, else -1
1574 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1576 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1577 SpaprMachineState
*spapr
,
1578 target_ulong opcode
,
1581 SpaprXive
*xive
= spapr
->xive
;
1583 target_ulong flags
= args
[0];
1584 target_ulong lisn
= args
[1];
1585 target_ulong offset
= args
[2];
1586 target_ulong data
= args
[3];
1588 XiveSource
*xsrc
= &xive
->source
;
1590 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1594 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1598 if (lisn
>= xive
->nr_irqs
) {
1599 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1604 eas
= xive
->eat
[lisn
];
1605 if (!xive_eas_is_valid(&eas
)) {
1606 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1611 if (offset
> (1ull << xsrc
->esb_shift
)) {
1615 if (kvm_irqchip_in_kernel()) {
1616 args
[0] = kvmppc_xive_esb_rw(xsrc
, lisn
, offset
, data
,
1617 flags
& SPAPR_XIVE_ESB_STORE
);
1619 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1621 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1622 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1623 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1624 HWADDR_PRIx
"\n", mmio_addr
);
1627 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1633 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1634 * ensure any in flight events for the input lisn are in the event
1640 * Bits 0-63: Reserved
1641 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1642 * "ibm,xive-lisn-ranges" properties, or as returned by the
1643 * ibm,query-interrupt-source-number RTAS call, or as
1644 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1649 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1650 SpaprMachineState
*spapr
,
1651 target_ulong opcode
,
1654 SpaprXive
*xive
= spapr
->xive
;
1656 target_ulong flags
= args
[0];
1657 target_ulong lisn
= args
[1];
1659 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1667 if (lisn
>= xive
->nr_irqs
) {
1668 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1673 eas
= xive
->eat
[lisn
];
1674 if (!xive_eas_is_valid(&eas
)) {
1675 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1681 * H_STATE should be returned if a H_INT_RESET is in progress.
1682 * This is not needed when running the emulation under QEMU
1686 * This is not real hardware. Nothing to be done unless when
1690 if (kvm_irqchip_in_kernel()) {
1691 Error
*local_err
= NULL
;
1693 kvmppc_xive_sync_source(xive
, lisn
, &local_err
);
1695 error_report_err(local_err
);
1703 * The H_INT_RESET hcall() is used to reset all of the partition's
1704 * interrupt exploitation structures to their initial state. This
1705 * means losing all previously set interrupt state set via
1706 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1711 * Bits 0-63: Reserved
1716 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1717 SpaprMachineState
*spapr
,
1718 target_ulong opcode
,
1721 SpaprXive
*xive
= spapr
->xive
;
1722 target_ulong flags
= args
[0];
1724 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1732 device_reset(DEVICE(xive
));
1734 if (kvm_irqchip_in_kernel()) {
1735 Error
*local_err
= NULL
;
1737 kvmppc_xive_reset(xive
, &local_err
);
1739 error_report_err(local_err
);
1746 void spapr_xive_hcall_init(SpaprMachineState
*spapr
)
1748 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1749 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1750 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1751 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1752 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1753 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1754 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1755 h_int_set_os_reporting_line
);
1756 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1757 h_int_get_os_reporting_line
);
1758 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1759 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1760 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);