hw/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU LGPL
   8  */
   9
  10 #include "sysbus.h"
  11 #include "console.h"
  12 #include "framebuffer.h"
  13
  14 #define PL110_CR_EN   0x001
  15 #define PL110_CR_BGR  0x100
  16 #define PL110_CR_BEBO 0x200
  17 #define PL110_CR_BEPO 0x400
  18 #define PL110_CR_PWR  0x800
  19
  20 enum pl110_bppmode
  21 {
  22     BPP_1,
  23     BPP_2,
  24     BPP_4,
  25     BPP_8,
  26     BPP_16,
  27     BPP_32,
  28     BPP_16_565, /* PL111 only */
  29     BPP_12      /* PL111 only */
  30 };
  31
  32
  33 /* The Versatile/PB uses a slightly modified PL110 controller.  */
  34 enum pl110_version
  35 {
  36     PL110,
  37     PL110_VERSATILE,
  38     PL111
  39 };
  40
  41 typedef struct {
  42     SysBusDevice busdev;
  43     DisplayState *ds;
  44
  45     int version;
  46     uint32_t timing[4];
  47     uint32_t cr;
  48     uint32_t upbase;
  49     uint32_t lpbase;
  50     uint32_t int_status;
  51     uint32_t int_mask;
  52     int cols;
  53     int rows;
  54     enum pl110_bppmode bpp;
  55     int invalidate;
  56     uint32_t pallette[256];
  57     uint32_t raw_pallette[128];
  58     qemu_irq irq;
  59 } pl110_state;
  60
  61 static const VMStateDescription vmstate_pl110 = {
  62     .name = "pl110",
  63     .version_id = 1,
  64     .minimum_version_id = 1,
  65     .fields = (VMStateField[]) {
  66         VMSTATE_INT32(version, pl110_state),
  67         VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
  68         VMSTATE_UINT32(cr, pl110_state),
  69         VMSTATE_UINT32(upbase, pl110_state),
  70         VMSTATE_UINT32(lpbase, pl110_state),
  71         VMSTATE_UINT32(int_status, pl110_state),
  72         VMSTATE_UINT32(int_mask, pl110_state),
  73         VMSTATE_INT32(cols, pl110_state),
  74         VMSTATE_INT32(rows, pl110_state),
  75         VMSTATE_UINT32(bpp, pl110_state),
  76         VMSTATE_INT32(invalidate, pl110_state),
  77         VMSTATE_UINT32_ARRAY(pallette, pl110_state, 256),
  78         VMSTATE_UINT32_ARRAY(raw_pallette, pl110_state, 128),
  79         VMSTATE_END_OF_LIST()
  80     }
  81 };
  82
  83 static const unsigned char pl110_id[] =
  84 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  85
  86 /* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
  87    has a different ID.  However Linux only looks for the normal ID.  */
  88 #if 0
  89 static const unsigned char pl110_versatile_id[] =
  90 { 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  91 #else
  92 #define pl110_versatile_id pl110_id
  93 #endif
  94
  95 static const unsigned char pl111_id[] = {
  96     0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
  97 };
  98
  99 /* Indexed by pl110_version */
 100 static const unsigned char *idregs[] = {
 101     pl110_id,
 102     pl110_versatile_id,
 103     pl111_id
 104 };
 105
 106 #include "pixel_ops.h"
 107
 108 #define BITS 8
 109 #include "pl110_template.h"
 110 #define BITS 15
 111 #include "pl110_template.h"
 112 #define BITS 16
 113 #include "pl110_template.h"
 114 #define BITS 24
 115 #include "pl110_template.h"
 116 #define BITS 32
 117 #include "pl110_template.h"
 118
 119 static int pl110_enabled(pl110_state *s)
 120 {
 121   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 122 }
 123
 124 static void pl110_update_display(void *opaque)
 125 {
 126     pl110_state *s = (pl110_state *)opaque;
 127     drawfn* fntable;
 128     drawfn fn;
 129     int dest_width;
 130     int src_width;
 131     int bpp_offset;
 132     int first;
 133     int last;
 134
 135     if (!pl110_enabled(s))
 136         return;
 137
 138     switch (ds_get_bits_per_pixel(s->ds)) {
 139     case 0:
 140         return;
 141     case 8:
 142         fntable = pl110_draw_fn_8;
 143         dest_width = 1;
 144         break;
 145     case 15:
 146         fntable = pl110_draw_fn_15;
 147         dest_width = 2;
 148         break;
 149     case 16:
 150         fntable = pl110_draw_fn_16;
 151         dest_width = 2;
 152         break;
 153     case 24:
 154         fntable = pl110_draw_fn_24;
 155         dest_width = 3;
 156         break;
 157     case 32:
 158         fntable = pl110_draw_fn_32;
 159         dest_width = 4;
 160         break;
 161     default:
 162         fprintf(stderr, "pl110: Bad color depth\n");
 163         exit(1);
 164     }
 165     if (s->cr & PL110_CR_BGR)
 166         bpp_offset = 0;
 167     else
 168         bpp_offset = 24;
 169
 170     if ((s->version != PL111) && (s->bpp == BPP_16)) {
 171         /* The PL110's native 16 bit mode is 5551; however
 172          * most boards with a PL110 implement an external
 173          * mux which allows bits to be reshuffled to give
 174          * 565 format. The mux is typically controlled by
 175          * an external system register.
 176          * This should be controlled by a GPIO input pin
 177          * so boards can wire it up to their register.
 178          * For now, force 16 bit to be 565, to match
 179          * previous QEMU PL110 model behaviour.
 180          *
 181          * The PL111 straightforwardly implements both
 182          * 5551 and 565 under control of the bpp field
 183          * in the LCDControl register.
 184          */
 185         bpp_offset += (BPP_16_565 - BPP_16);
 186     }
 187
 188     if (s->cr & PL110_CR_BEBO)
 189         fn = fntable[s->bpp + 8 + bpp_offset];
 190     else if (s->cr & PL110_CR_BEPO)
 191         fn = fntable[s->bpp + 16 + bpp_offset];
 192     else
 193         fn = fntable[s->bpp + bpp_offset];
 194
 195     src_width = s->cols;
 196     switch (s->bpp) {
 197     case BPP_1:
 198         src_width >>= 3;
 199         break;
 200     case BPP_2:
 201         src_width >>= 2;
 202         break;
 203     case BPP_4:
 204         src_width >>= 1;
 205         break;
 206     case BPP_8:
 207         break;
 208     case BPP_16:
 209     case BPP_16_565:
 210     case BPP_12:
 211         src_width <<= 1;
 212         break;
 213     case BPP_32:
 214         src_width <<= 2;
 215         break;
 216     }
 217     dest_width *= s->cols;
 218     first = 0;
 219     framebuffer_update_display(s->ds,
 220                                s->upbase, s->cols, s->rows,
 221                                src_width, dest_width, 0,
 222                                s->invalidate,
 223                                fn, s->pallette,
 224                                &first, &last);
 225     if (first >= 0) {
 226         dpy_update(s->ds, 0, first, s->cols, last - first + 1);
 227     }
 228     s->invalidate = 0;
 229 }
 230
 231 static void pl110_invalidate_display(void * opaque)
 232 {
 233     pl110_state *s = (pl110_state *)opaque;
 234     s->invalidate = 1;
 235     if (pl110_enabled(s)) {
 236         qemu_console_resize(s->ds, s->cols, s->rows);
 237     }
 238 }
 239
 240 static void pl110_update_pallette(pl110_state *s, int n)
 241 {
 242     int i;
 243     uint32_t raw;
 244     unsigned int r, g, b;
 245
 246     raw = s->raw_pallette[n];
 247     n <<= 1;
 248     for (i = 0; i < 2; i++) {
 249         r = (raw & 0x1f) << 3;
 250         raw >>= 5;
 251         g = (raw & 0x1f) << 3;
 252         raw >>= 5;
 253         b = (raw & 0x1f) << 3;
 254         /* The I bit is ignored.  */
 255         raw >>= 6;
 256         switch (ds_get_bits_per_pixel(s->ds)) {
 257         case 8:
 258             s->pallette[n] = rgb_to_pixel8(r, g, b);
 259             break;
 260         case 15:
 261             s->pallette[n] = rgb_to_pixel15(r, g, b);
 262             break;
 263         case 16:
 264             s->pallette[n] = rgb_to_pixel16(r, g, b);
 265             break;
 266         case 24:
 267         case 32:
 268             s->pallette[n] = rgb_to_pixel32(r, g, b);
 269             break;
 270         }
 271         n++;
 272     }
 273 }
 274
 275 static void pl110_resize(pl110_state *s, int width, int height)
 276 {
 277     if (width != s->cols || height != s->rows) {
 278         if (pl110_enabled(s)) {
 279             qemu_console_resize(s->ds, width, height);
 280         }
 281     }
 282     s->cols = width;
 283     s->rows = height;
 284 }
 285
 286 /* Update interrupts.  */
 287 static void pl110_update(pl110_state *s)
 288 {
 289   /* TODO: Implement interrupts.  */
 290 }
 291
 292 static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
 293 {
 294     pl110_state *s = (pl110_state *)opaque;
 295
 296     if (offset >= 0xfe0 && offset < 0x1000) {
 297         return idregs[s->version][(offset - 0xfe0) >> 2];
 298     }
 299     if (offset >= 0x200 && offset < 0x400) {
 300         return s->raw_pallette[(offset - 0x200) >> 2];
 301     }
 302     switch (offset >> 2) {
 303     case 0: /* LCDTiming0 */
 304         return s->timing[0];
 305     case 1: /* LCDTiming1 */
 306         return s->timing[1];
 307     case 2: /* LCDTiming2 */
 308         return s->timing[2];
 309     case 3: /* LCDTiming3 */
 310         return s->timing[3];
 311     case 4: /* LCDUPBASE */
 312         return s->upbase;
 313     case 5: /* LCDLPBASE */
 314         return s->lpbase;
 315     case 6: /* LCDIMSC */
 316         if (s->version != PL110) {
 317             return s->cr;
 318         }
 319         return s->int_mask;
 320     case 7: /* LCDControl */
 321         if (s->version != PL110) {
 322             return s->int_mask;
 323         }
 324         return s->cr;
 325     case 8: /* LCDRIS */
 326         return s->int_status;
 327     case 9: /* LCDMIS */
 328         return s->int_status & s->int_mask;
 329     case 11: /* LCDUPCURR */
 330         /* TODO: Implement vertical refresh.  */
 331         return s->upbase;
 332     case 12: /* LCDLPCURR */
 333         return s->lpbase;
 334     default:
 335         hw_error("pl110_read: Bad offset %x\n", (int)offset);
 336         return 0;
 337     }
 338 }
 339
 340 static void pl110_write(void *opaque, target_phys_addr_t offset,
 341                         uint32_t val)
 342 {
 343     pl110_state *s = (pl110_state *)opaque;
 344     int n;
 345
 346     /* For simplicity invalidate the display whenever a control register
 347        is writen to.  */
 348     s->invalidate = 1;
 349     if (offset >= 0x200 && offset < 0x400) {
 350         /* Pallette.  */
 351         n = (offset - 0x200) >> 2;
 352         s->raw_pallette[(offset - 0x200) >> 2] = val;
 353         pl110_update_pallette(s, n);
 354         return;
 355     }
 356     switch (offset >> 2) {
 357     case 0: /* LCDTiming0 */
 358         s->timing[0] = val;
 359         n = ((val & 0xfc) + 4) * 4;
 360         pl110_resize(s, n, s->rows);
 361         break;
 362     case 1: /* LCDTiming1 */
 363         s->timing[1] = val;
 364         n = (val & 0x3ff) + 1;
 365         pl110_resize(s, s->cols, n);
 366         break;
 367     case 2: /* LCDTiming2 */
 368         s->timing[2] = val;
 369         break;
 370     case 3: /* LCDTiming3 */
 371         s->timing[3] = val;
 372         break;
 373     case 4: /* LCDUPBASE */
 374         s->upbase = val;
 375         break;
 376     case 5: /* LCDLPBASE */
 377         s->lpbase = val;
 378         break;
 379     case 6: /* LCDIMSC */
 380         if (s->version != PL110) {
 381             goto control;
 382         }
 383     imsc:
 384         s->int_mask = val;
 385         pl110_update(s);
 386         break;
 387     case 7: /* LCDControl */
 388         if (s->version != PL110) {
 389             goto imsc;
 390         }
 391     control:
 392         s->cr = val;
 393         s->bpp = (val >> 1) & 7;
 394         if (pl110_enabled(s)) {
 395             qemu_console_resize(s->ds, s->cols, s->rows);
 396         }
 397         break;
 398     case 10: /* LCDICR */
 399         s->int_status &= ~val;
 400         pl110_update(s);
 401         break;
 402     default:
 403         hw_error("pl110_write: Bad offset %x\n", (int)offset);
 404     }
 405 }
 406
 407 static CPUReadMemoryFunc * const pl110_readfn[] = {
 408    pl110_read,
 409    pl110_read,
 410    pl110_read
 411 };
 412
 413 static CPUWriteMemoryFunc * const pl110_writefn[] = {
 414    pl110_write,
 415    pl110_write,
 416    pl110_write
 417 };
 418
 419 static int pl110_init(SysBusDevice *dev)
 420 {
 421     pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 422     int iomemtype;
 423
 424     iomemtype = cpu_register_io_memory(pl110_readfn,
 425                                        pl110_writefn, s,
 426                                        DEVICE_NATIVE_ENDIAN);
 427     sysbus_init_mmio(dev, 0x1000, iomemtype);
 428     sysbus_init_irq(dev, &s->irq);
 429     s->ds = graphic_console_init(pl110_update_display,
 430                                  pl110_invalidate_display,
 431                                  NULL, NULL, s);
 432     return 0;
 433 }
 434
 435 static int pl110_versatile_init(SysBusDevice *dev)
 436 {
 437     pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 438     s->version = PL110_VERSATILE;
 439     return pl110_init(dev);
 440 }
 441
 442 static int pl111_init(SysBusDevice *dev)
 443 {
 444     pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 445     s->version = PL111;
 446     return pl110_init(dev);
 447 }
 448
 449 static SysBusDeviceInfo pl110_info = {
 450     .init = pl110_init,
 451     .qdev.name = "pl110",
 452     .qdev.size = sizeof(pl110_state),
 453     .qdev.vmsd = &vmstate_pl110,
 454     .qdev.no_user = 1,
 455 };
 456
 457 static SysBusDeviceInfo pl110_versatile_info = {
 458     .init = pl110_versatile_init,
 459     .qdev.name = "pl110_versatile",
 460     .qdev.size = sizeof(pl110_state),
 461     .qdev.vmsd = &vmstate_pl110,
 462     .qdev.no_user = 1,
 463 };
 464
 465 static SysBusDeviceInfo pl111_info = {
 466     .init = pl111_init,
 467     .qdev.name = "pl111",
 468     .qdev.size = sizeof(pl110_state),
 469     .qdev.vmsd = &vmstate_pl110,
 470     .qdev.no_user = 1,
 471 };
 472
 473 static void pl110_register_devices(void)
 474 {
 475     sysbus_register_withprop(&pl110_info);
 476     sysbus_register_withprop(&pl110_versatile_info);
 477     sysbus_register_withprop(&pl111_info);
 478 }
 479
 480 device_init(pl110_register_devices)