2 * QEMU Ultrasparc APB PCI host
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* XXX This file and most of its contents are somewhat misnamed. The
26 Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
27 the secondary PCI bridge. */
37 #define APB_DPRINTF(fmt, ...) \
38 do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
40 #define APB_DPRINTF(fmt, ...)
45 * PBM: "UltraSPARC IIi User's Manual",
46 * http://www.sun.com/processors/manuals/805-0087.pdf
48 * APB: "Advanced PCI Bridge (APB) User's Manual",
49 * http://www.sun.com/processors/manuals/805-1251.pdf
52 typedef struct APBState
{
54 PCIHostState host_state
;
57 static void pci_apb_config_writel (void *opaque
, target_phys_addr_t addr
,
62 #ifdef TARGET_WORDS_BIGENDIAN
65 APB_DPRINTF("config_writel addr " TARGET_FMT_plx
" val %x\n", addr
,
67 s
->host_state
.config_reg
= val
;
70 static uint32_t pci_apb_config_readl (void *opaque
,
71 target_phys_addr_t addr
)
76 val
= s
->host_state
.config_reg
;
77 #ifdef TARGET_WORDS_BIGENDIAN
80 APB_DPRINTF("config_readl addr " TARGET_FMT_plx
" val %x\n", addr
,
85 static CPUWriteMemoryFunc
* const pci_apb_config_write
[] = {
86 &pci_apb_config_writel
,
87 &pci_apb_config_writel
,
88 &pci_apb_config_writel
,
91 static CPUReadMemoryFunc
* const pci_apb_config_read
[] = {
92 &pci_apb_config_readl
,
93 &pci_apb_config_readl
,
94 &pci_apb_config_readl
,
97 static void apb_config_writel (void *opaque
, target_phys_addr_t addr
,
100 //PCIBus *s = opaque;
102 switch (addr
& 0x3f) {
103 case 0x00: // Control/Status
106 case 0x20: // Diagnostic
107 case 0x28: // Target address space
114 static uint32_t apb_config_readl (void *opaque
,
115 target_phys_addr_t addr
)
117 //PCIBus *s = opaque;
120 switch (addr
& 0x3f) {
121 case 0x00: // Control/Status
124 case 0x20: // Diagnostic
125 case 0x28: // Target address space
134 static CPUWriteMemoryFunc
* const apb_config_write
[] = {
140 static CPUReadMemoryFunc
* const apb_config_read
[] = {
146 static void pci_apb_iowriteb (void *opaque
, target_phys_addr_t addr
,
149 cpu_outb(addr
& IOPORTS_MASK
, val
);
152 static void pci_apb_iowritew (void *opaque
, target_phys_addr_t addr
,
155 cpu_outw(addr
& IOPORTS_MASK
, val
);
158 static void pci_apb_iowritel (void *opaque
, target_phys_addr_t addr
,
161 cpu_outl(addr
& IOPORTS_MASK
, val
);
164 static uint32_t pci_apb_ioreadb (void *opaque
, target_phys_addr_t addr
)
168 val
= cpu_inb(addr
& IOPORTS_MASK
);
172 static uint32_t pci_apb_ioreadw (void *opaque
, target_phys_addr_t addr
)
176 val
= cpu_inw(addr
& IOPORTS_MASK
);
180 static uint32_t pci_apb_ioreadl (void *opaque
, target_phys_addr_t addr
)
184 val
= cpu_inl(addr
& IOPORTS_MASK
);
188 static CPUWriteMemoryFunc
* const pci_apb_iowrite
[] = {
194 static CPUReadMemoryFunc
* const pci_apb_ioread
[] = {
200 /* The APB host has an IRQ line for each IRQ line of each slot. */
201 static int pci_apb_map_irq(PCIDevice
*pci_dev
, int irq_num
)
203 return ((pci_dev
->devfn
& 0x18) >> 1) + irq_num
;
206 static int pci_pbm_map_irq(PCIDevice
*pci_dev
, int irq_num
)
209 if (pci_dev
->devfn
& 1)
213 return bus_offset
+ irq_num
;
216 static void pci_apb_set_irq(void *opaque
, int irq_num
, int level
)
218 qemu_irq
*pic
= opaque
;
220 /* PCI IRQ map onto the first 32 INO. */
221 qemu_set_irq(pic
[irq_num
], level
);
224 PCIBus
*pci_apb_init(target_phys_addr_t special_base
,
225 target_phys_addr_t mem_base
,
226 qemu_irq
*pic
, PCIBus
**bus2
, PCIBus
**bus3
)
232 /* Ultrasparc PBM main bus */
233 dev
= qdev_create(NULL
, "pbm");
234 qdev_init_nofail(dev
);
235 s
= sysbus_from_qdev(dev
);
237 sysbus_mmio_map(s
, 0, special_base
+ 0x2000ULL
);
239 sysbus_mmio_map(s
, 1, special_base
+ 0x2000000ULL
);
240 /* mem_config: XXX size should be 4G-prom */
241 sysbus_mmio_map(s
, 2, special_base
+ 0x1000000ULL
);
243 sysbus_mmio_map(s
, 3, mem_base
);
244 d
= FROM_SYSBUS(APBState
, s
);
245 d
->host_state
.bus
= pci_register_bus(&d
->busdev
.qdev
, "pci",
246 pci_apb_set_irq
, pci_pbm_map_irq
, pic
,
248 pci_create_simple(d
->host_state
.bus
, 0, "pbm");
249 /* APB secondary busses */
250 *bus2
= pci_bridge_init(d
->host_state
.bus
, PCI_DEVFN(1, 0),
251 PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_SIMBA
,
253 "Advanced PCI Bus secondary bridge 1");
254 *bus3
= pci_bridge_init(d
->host_state
.bus
, PCI_DEVFN(1, 1),
255 PCI_VENDOR_ID_SUN
, PCI_DEVICE_ID_SUN_SIMBA
,
257 "Advanced PCI Bus secondary bridge 2");
259 return d
->host_state
.bus
;
262 static int pci_pbm_init_device(SysBusDevice
*dev
)
266 int pci_mem_config
, pci_mem_data
, apb_config
, pci_ioport
;
268 s
= FROM_SYSBUS(APBState
, dev
);
270 apb_config
= cpu_register_io_memory(apb_config_read
,
271 apb_config_write
, s
);
272 sysbus_init_mmio(dev
, 0x40ULL
, apb_config
);
274 pci_ioport
= cpu_register_io_memory(pci_apb_ioread
,
276 sysbus_init_mmio(dev
, 0x10000ULL
, pci_ioport
);
278 pci_mem_config
= cpu_register_io_memory(pci_apb_config_read
,
279 pci_apb_config_write
, s
);
280 sysbus_init_mmio(dev
, 0x10ULL
, pci_mem_config
);
282 pci_mem_data
= pci_host_data_register_io_memory(&s
->host_state
);
283 sysbus_init_mmio(dev
, 0x10000000ULL
, pci_mem_data
);
287 static int pbm_pci_host_init(PCIDevice
*d
)
289 pci_config_set_vendor_id(d
->config
, PCI_VENDOR_ID_SUN
);
290 pci_config_set_device_id(d
->config
, PCI_DEVICE_ID_SUN_SABRE
);
291 d
->config
[0x04] = 0x06; // command = bus master, pci mem
292 d
->config
[0x05] = 0x00;
293 d
->config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
294 d
->config
[0x07] = 0x03; // status = medium devsel
295 d
->config
[0x08] = 0x00; // revision
296 d
->config
[0x09] = 0x00; // programming i/f
297 pci_config_set_class(d
->config
, PCI_CLASS_BRIDGE_HOST
);
298 d
->config
[0x0D] = 0x10; // latency_timer
299 d
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
303 static PCIDeviceInfo pbm_pci_host_info
= {
305 .qdev
.size
= sizeof(PCIDevice
),
306 .init
= pbm_pci_host_init
,
309 static void pbm_register_devices(void)
311 sysbus_register_dev("pbm", sizeof(APBState
), pci_pbm_init_device
);
312 pci_qdev_register(&pbm_pci_host_info
);
315 device_init(pbm_register_devices
)