hw/esp.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "scsi.h"
  27 #include "esp.h"
  28 #include "trace.h"
  29
  30 /*
  31  * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
  32  * also produced as NCR89C100. See
  33  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  34  * and
  35  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
  36  */
  37
  38 #define ESP_ERROR(fmt, ...)                                             \
  39     do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  40
  41 #define ESP_REGS 16
  42 #define TI_BUFSZ 16
  43
  44 typedef struct ESPState ESPState;
  45
  46 struct ESPState {
  47     SysBusDevice busdev;
  48     uint8_t rregs[ESP_REGS];
  49     uint8_t wregs[ESP_REGS];
  50     qemu_irq irq;
  51     uint32_t it_shift;
  52     int32_t ti_size;
  53     uint32_t ti_rptr, ti_wptr;
  54     uint32_t status;
  55     uint32_t dma;
  56     uint8_t ti_buf[TI_BUFSZ];
  57     SCSIBus bus;
  58     SCSIDevice *current_dev;
  59     SCSIRequest *current_req;
  60     uint8_t cmdbuf[TI_BUFSZ];
  61     uint32_t cmdlen;
  62     uint32_t do_cmd;
  63
  64     /* The amount of data left in the current DMA transfer.  */
  65     uint32_t dma_left;
  66     /* The size of the current DMA transfer.  Zero if no transfer is in
  67        progress.  */
  68     uint32_t dma_counter;
  69     int dma_enabled;
  70
  71     uint32_t async_len;
  72     uint8_t *async_buf;
  73
  74     ESPDMAMemoryReadWriteFunc dma_memory_read;
  75     ESPDMAMemoryReadWriteFunc dma_memory_write;
  76     void *dma_opaque;
  77     void (*dma_cb)(ESPState *s);
  78 };
  79
  80 #define ESP_TCLO   0x0
  81 #define ESP_TCMID  0x1
  82 #define ESP_FIFO   0x2
  83 #define ESP_CMD    0x3
  84 #define ESP_RSTAT  0x4
  85 #define ESP_WBUSID 0x4
  86 #define ESP_RINTR  0x5
  87 #define ESP_WSEL   0x5
  88 #define ESP_RSEQ   0x6
  89 #define ESP_WSYNTP 0x6
  90 #define ESP_RFLAGS 0x7
  91 #define ESP_WSYNO  0x7
  92 #define ESP_CFG1   0x8
  93 #define ESP_RRES1  0x9
  94 #define ESP_WCCF   0x9
  95 #define ESP_RRES2  0xa
  96 #define ESP_WTEST  0xa
  97 #define ESP_CFG2   0xb
  98 #define ESP_CFG3   0xc
  99 #define ESP_RES3   0xd
 100 #define ESP_TCHI   0xe
 101 #define ESP_RES4   0xf
 102
 103 #define CMD_DMA 0x80
 104 #define CMD_CMD 0x7f
 105
 106 #define CMD_NOP      0x00
 107 #define CMD_FLUSH    0x01
 108 #define CMD_RESET    0x02
 109 #define CMD_BUSRESET 0x03
 110 #define CMD_TI       0x10
 111 #define CMD_ICCS     0x11
 112 #define CMD_MSGACC   0x12
 113 #define CMD_PAD      0x18
 114 #define CMD_SATN     0x1a
 115 #define CMD_SEL      0x41
 116 #define CMD_SELATN   0x42
 117 #define CMD_SELATNS  0x43
 118 #define CMD_ENSEL    0x44
 119
 120 #define STAT_DO 0x00
 121 #define STAT_DI 0x01
 122 #define STAT_CD 0x02
 123 #define STAT_ST 0x03
 124 #define STAT_MO 0x06
 125 #define STAT_MI 0x07
 126 #define STAT_PIO_MASK 0x06
 127
 128 #define STAT_TC 0x10
 129 #define STAT_PE 0x20
 130 #define STAT_GE 0x40
 131 #define STAT_INT 0x80
 132
 133 #define BUSID_DID 0x07
 134
 135 #define INTR_FC 0x08
 136 #define INTR_BS 0x10
 137 #define INTR_DC 0x20
 138 #define INTR_RST 0x80
 139
 140 #define SEQ_0 0x0
 141 #define SEQ_CD 0x4
 142
 143 #define CFG1_RESREPT 0x40
 144
 145 #define TCHI_FAS100A 0x4
 146
 147 static void esp_raise_irq(ESPState *s)
 148 {
 149     if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
 150         s->rregs[ESP_RSTAT] |= STAT_INT;
 151         qemu_irq_raise(s->irq);
 152         trace_esp_raise_irq();
 153     }
 154 }
 155
 156 static void esp_lower_irq(ESPState *s)
 157 {
 158     if (s->rregs[ESP_RSTAT] & STAT_INT) {
 159         s->rregs[ESP_RSTAT] &= ~STAT_INT;
 160         qemu_irq_lower(s->irq);
 161         trace_esp_lower_irq();
 162     }
 163 }
 164
 165 static void esp_dma_enable(void *opaque, int irq, int level)
 166 {
 167     DeviceState *d = opaque;
 168     ESPState *s = container_of(d, ESPState, busdev.qdev);
 169
 170     if (level) {
 171         s->dma_enabled = 1;
 172         trace_esp_dma_enable();
 173         if (s->dma_cb) {
 174             s->dma_cb(s);
 175             s->dma_cb = NULL;
 176         }
 177     } else {
 178         trace_esp_dma_disable();
 179         s->dma_enabled = 0;
 180     }
 181 }
 182
 183 static void esp_request_cancelled(SCSIRequest *req)
 184 {
 185     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 186
 187     if (req == s->current_req) {
 188         scsi_req_unref(s->current_req);
 189         s->current_req = NULL;
 190         s->current_dev = NULL;
 191     }
 192 }
 193
 194 static uint32_t get_cmd(ESPState *s, uint8_t *buf)
 195 {
 196     uint32_t dmalen;
 197     int target;
 198
 199     target = s->wregs[ESP_WBUSID] & BUSID_DID;
 200     if (s->dma) {
 201         dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 202         s->dma_memory_read(s->dma_opaque, buf, dmalen);
 203     } else {
 204         dmalen = s->ti_size;
 205         memcpy(buf, s->ti_buf, dmalen);
 206         buf[0] = buf[2] >> 5;
 207     }
 208     trace_esp_get_cmd(dmalen, target);
 209
 210     s->ti_size = 0;
 211     s->ti_rptr = 0;
 212     s->ti_wptr = 0;
 213
 214     if (s->current_req) {
 215         /* Started a new command before the old one finished.  Cancel it.  */
 216         scsi_req_cancel(s->current_req);
 217         s->async_len = 0;
 218     }
 219
 220     if (target >= ESP_MAX_DEVS || !s->bus.devs[target]) {
 221         // No such drive
 222         s->rregs[ESP_RSTAT] = 0;
 223         s->rregs[ESP_RINTR] = INTR_DC;
 224         s->rregs[ESP_RSEQ] = SEQ_0;
 225         esp_raise_irq(s);
 226         return 0;
 227     }
 228     s->current_dev = s->bus.devs[target];
 229     return dmalen;
 230 }
 231
 232 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
 233 {
 234     int32_t datalen;
 235     int lun;
 236
 237     trace_esp_do_busid_cmd(busid);
 238     lun = busid & 7;
 239     s->current_req = scsi_req_new(s->current_dev, 0, lun, buf, NULL);
 240     datalen = scsi_req_enqueue(s->current_req);
 241     s->ti_size = datalen;
 242     if (datalen != 0) {
 243         s->rregs[ESP_RSTAT] = STAT_TC;
 244         s->dma_left = 0;
 245         s->dma_counter = 0;
 246         if (datalen > 0) {
 247             s->rregs[ESP_RSTAT] |= STAT_DI;
 248         } else {
 249             s->rregs[ESP_RSTAT] |= STAT_DO;
 250         }
 251         scsi_req_continue(s->current_req);
 252     }
 253     s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 254     s->rregs[ESP_RSEQ] = SEQ_CD;
 255     esp_raise_irq(s);
 256 }
 257
 258 static void do_cmd(ESPState *s, uint8_t *buf)
 259 {
 260     uint8_t busid = buf[0];
 261
 262     do_busid_cmd(s, &buf[1], busid);
 263 }
 264
 265 static void handle_satn(ESPState *s)
 266 {
 267     uint8_t buf[32];
 268     int len;
 269
 270     if (!s->dma_enabled) {
 271         s->dma_cb = handle_satn;
 272         return;
 273     }
 274     len = get_cmd(s, buf);
 275     if (len)
 276         do_cmd(s, buf);
 277 }
 278
 279 static void handle_s_without_atn(ESPState *s)
 280 {
 281     uint8_t buf[32];
 282     int len;
 283
 284     if (!s->dma_enabled) {
 285         s->dma_cb = handle_s_without_atn;
 286         return;
 287     }
 288     len = get_cmd(s, buf);
 289     if (len) {
 290         do_busid_cmd(s, buf, 0);
 291     }
 292 }
 293
 294 static void handle_satn_stop(ESPState *s)
 295 {
 296     if (!s->dma_enabled) {
 297         s->dma_cb = handle_satn_stop;
 298         return;
 299     }
 300     s->cmdlen = get_cmd(s, s->cmdbuf);
 301     if (s->cmdlen) {
 302         trace_esp_handle_satn_stop(s->cmdlen);
 303         s->do_cmd = 1;
 304         s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
 305         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 306         s->rregs[ESP_RSEQ] = SEQ_CD;
 307         esp_raise_irq(s);
 308     }
 309 }
 310
 311 static void write_response(ESPState *s)
 312 {
 313     trace_esp_write_response(s->status);
 314     s->ti_buf[0] = s->status;
 315     s->ti_buf[1] = 0;
 316     if (s->dma) {
 317         s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
 318         s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
 319         s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
 320         s->rregs[ESP_RSEQ] = SEQ_CD;
 321     } else {
 322         s->ti_size = 2;
 323         s->ti_rptr = 0;
 324         s->ti_wptr = 0;
 325         s->rregs[ESP_RFLAGS] = 2;
 326     }
 327     esp_raise_irq(s);
 328 }
 329
 330 static void esp_dma_done(ESPState *s)
 331 {
 332     s->rregs[ESP_RSTAT] |= STAT_TC;
 333     s->rregs[ESP_RINTR] = INTR_BS;
 334     s->rregs[ESP_RSEQ] = 0;
 335     s->rregs[ESP_RFLAGS] = 0;
 336     s->rregs[ESP_TCLO] = 0;
 337     s->rregs[ESP_TCMID] = 0;
 338     esp_raise_irq(s);
 339 }
 340
 341 static void esp_do_dma(ESPState *s)
 342 {
 343     uint32_t len;
 344     int to_device;
 345
 346     to_device = (s->ti_size < 0);
 347     len = s->dma_left;
 348     if (s->do_cmd) {
 349         trace_esp_do_dma(s->cmdlen, len);
 350         s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
 351         s->ti_size = 0;
 352         s->cmdlen = 0;
 353         s->do_cmd = 0;
 354         do_cmd(s, s->cmdbuf);
 355         return;
 356     }
 357     if (s->async_len == 0) {
 358         /* Defer until data is available.  */
 359         return;
 360     }
 361     if (len > s->async_len) {
 362         len = s->async_len;
 363     }
 364     if (to_device) {
 365         s->dma_memory_read(s->dma_opaque, s->async_buf, len);
 366     } else {
 367         s->dma_memory_write(s->dma_opaque, s->async_buf, len);
 368     }
 369     s->dma_left -= len;
 370     s->async_buf += len;
 371     s->async_len -= len;
 372     if (to_device)
 373         s->ti_size += len;
 374     else
 375         s->ti_size -= len;
 376     if (s->async_len == 0) {
 377         scsi_req_continue(s->current_req);
 378         /* If there is still data to be read from the device then
 379            complete the DMA operation immediately.  Otherwise defer
 380            until the scsi layer has completed.  */
 381         if (to_device || s->dma_left != 0 || s->ti_size == 0) {
 382             return;
 383         }
 384     }
 385
 386     /* Partially filled a scsi buffer. Complete immediately.  */
 387     esp_dma_done(s);
 388 }
 389
 390 static void esp_command_complete(SCSIRequest *req, uint32_t status)
 391 {
 392     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 393
 394     trace_esp_command_complete();
 395     if (s->ti_size != 0) {
 396         trace_esp_command_complete_unexpected();
 397     }
 398     s->ti_size = 0;
 399     s->dma_left = 0;
 400     s->async_len = 0;
 401     if (status) {
 402         trace_esp_command_complete_fail();
 403     }
 404     s->status = status;
 405     s->rregs[ESP_RSTAT] = STAT_ST;
 406     esp_dma_done(s);
 407     if (s->current_req) {
 408         scsi_req_unref(s->current_req);
 409         s->current_req = NULL;
 410         s->current_dev = NULL;
 411     }
 412 }
 413
 414 static void esp_transfer_data(SCSIRequest *req, uint32_t len)
 415 {
 416     ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
 417
 418     trace_esp_transfer_data(s->dma_left, s->ti_size);
 419     s->async_len = len;
 420     s->async_buf = scsi_req_get_buf(req);
 421     if (s->dma_left) {
 422         esp_do_dma(s);
 423     } else if (s->dma_counter != 0 && s->ti_size <= 0) {
 424         /* If this was the last part of a DMA transfer then the
 425            completion interrupt is deferred to here.  */
 426         esp_dma_done(s);
 427     }
 428 }
 429
 430 static void handle_ti(ESPState *s)
 431 {
 432     uint32_t dmalen, minlen;
 433
 434     dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
 435     if (dmalen==0) {
 436       dmalen=0x10000;
 437     }
 438     s->dma_counter = dmalen;
 439
 440     if (s->do_cmd)
 441         minlen = (dmalen < 32) ? dmalen : 32;
 442     else if (s->ti_size < 0)
 443         minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
 444     else
 445         minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
 446     trace_esp_handle_ti(minlen);
 447     if (s->dma) {
 448         s->dma_left = minlen;
 449         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 450         esp_do_dma(s);
 451     } else if (s->do_cmd) {
 452         trace_esp_handle_ti_cmd(s->cmdlen);
 453         s->ti_size = 0;
 454         s->cmdlen = 0;
 455         s->do_cmd = 0;
 456         do_cmd(s, s->cmdbuf);
 457         return;
 458     }
 459 }
 460
 461 static void esp_hard_reset(DeviceState *d)
 462 {
 463     ESPState *s = container_of(d, ESPState, busdev.qdev);
 464
 465     memset(s->rregs, 0, ESP_REGS);
 466     memset(s->wregs, 0, ESP_REGS);
 467     s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
 468     s->ti_size = 0;
 469     s->ti_rptr = 0;
 470     s->ti_wptr = 0;
 471     s->dma = 0;
 472     s->do_cmd = 0;
 473     s->dma_cb = NULL;
 474
 475     s->rregs[ESP_CFG1] = 7;
 476 }
 477
 478 static void esp_soft_reset(DeviceState *d)
 479 {
 480     ESPState *s = container_of(d, ESPState, busdev.qdev);
 481
 482     qemu_irq_lower(s->irq);
 483     esp_hard_reset(d);
 484 }
 485
 486 static void parent_esp_reset(void *opaque, int irq, int level)
 487 {
 488     if (level) {
 489         esp_soft_reset(opaque);
 490     }
 491 }
 492
 493 static void esp_gpio_demux(void *opaque, int irq, int level)
 494 {
 495     switch (irq) {
 496     case 0:
 497         parent_esp_reset(opaque, irq, level);
 498         break;
 499     case 1:
 500         esp_dma_enable(opaque, irq, level);
 501         break;
 502     }
 503 }
 504
 505 static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
 506 {
 507     ESPState *s = opaque;
 508     uint32_t saddr, old_val;
 509
 510     saddr = addr >> s->it_shift;
 511     trace_esp_mem_readb(saddr, s->rregs[saddr]);
 512     switch (saddr) {
 513     case ESP_FIFO:
 514         if (s->ti_size > 0) {
 515             s->ti_size--;
 516             if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
 517                 /* Data out.  */
 518                 ESP_ERROR("PIO data read not implemented\n");
 519                 s->rregs[ESP_FIFO] = 0;
 520             } else {
 521                 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
 522             }
 523             esp_raise_irq(s);
 524         }
 525         if (s->ti_size == 0) {
 526             s->ti_rptr = 0;
 527             s->ti_wptr = 0;
 528         }
 529         break;
 530     case ESP_RINTR:
 531         /* Clear sequence step, interrupt register and all status bits
 532            except TC */
 533         old_val = s->rregs[ESP_RINTR];
 534         s->rregs[ESP_RINTR] = 0;
 535         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 536         s->rregs[ESP_RSEQ] = SEQ_CD;
 537         esp_lower_irq(s);
 538
 539         return old_val;
 540     default:
 541         break;
 542     }
 543     return s->rregs[saddr];
 544 }
 545
 546 static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 547 {
 548     ESPState *s = opaque;
 549     uint32_t saddr;
 550
 551     saddr = addr >> s->it_shift;
 552     trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
 553     switch (saddr) {
 554     case ESP_TCLO:
 555     case ESP_TCMID:
 556         s->rregs[ESP_RSTAT] &= ~STAT_TC;
 557         break;
 558     case ESP_FIFO:
 559         if (s->do_cmd) {
 560             s->cmdbuf[s->cmdlen++] = val & 0xff;
 561         } else if (s->ti_size == TI_BUFSZ - 1) {
 562             ESP_ERROR("fifo overrun\n");
 563         } else {
 564             s->ti_size++;
 565             s->ti_buf[s->ti_wptr++] = val & 0xff;
 566         }
 567         break;
 568     case ESP_CMD:
 569         s->rregs[saddr] = val;
 570         if (val & CMD_DMA) {
 571             s->dma = 1;
 572             /* Reload DMA counter.  */
 573             s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
 574             s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
 575         } else {
 576             s->dma = 0;
 577         }
 578         switch(val & CMD_CMD) {
 579         case CMD_NOP:
 580             trace_esp_mem_writeb_cmd_nop(val);
 581             break;
 582         case CMD_FLUSH:
 583             trace_esp_mem_writeb_cmd_flush(val);
 584             //s->ti_size = 0;
 585             s->rregs[ESP_RINTR] = INTR_FC;
 586             s->rregs[ESP_RSEQ] = 0;
 587             s->rregs[ESP_RFLAGS] = 0;
 588             break;
 589         case CMD_RESET:
 590             trace_esp_mem_writeb_cmd_reset(val);
 591             esp_soft_reset(&s->busdev.qdev);
 592             break;
 593         case CMD_BUSRESET:
 594             trace_esp_mem_writeb_cmd_bus_reset(val);
 595             s->rregs[ESP_RINTR] = INTR_RST;
 596             if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
 597                 esp_raise_irq(s);
 598             }
 599             break;
 600         case CMD_TI:
 601             handle_ti(s);
 602             break;
 603         case CMD_ICCS:
 604             trace_esp_mem_writeb_cmd_iccs(val);
 605             write_response(s);
 606             s->rregs[ESP_RINTR] = INTR_FC;
 607             s->rregs[ESP_RSTAT] |= STAT_MI;
 608             break;
 609         case CMD_MSGACC:
 610             trace_esp_mem_writeb_cmd_msgacc(val);
 611             s->rregs[ESP_RINTR] = INTR_DC;
 612             s->rregs[ESP_RSEQ] = 0;
 613             s->rregs[ESP_RFLAGS] = 0;
 614             esp_raise_irq(s);
 615             break;
 616         case CMD_PAD:
 617             trace_esp_mem_writeb_cmd_pad(val);
 618             s->rregs[ESP_RSTAT] = STAT_TC;
 619             s->rregs[ESP_RINTR] = INTR_FC;
 620             s->rregs[ESP_RSEQ] = 0;
 621             break;
 622         case CMD_SATN:
 623             trace_esp_mem_writeb_cmd_satn(val);
 624             break;
 625         case CMD_SEL:
 626             trace_esp_mem_writeb_cmd_sel(val);
 627             handle_s_without_atn(s);
 628             break;
 629         case CMD_SELATN:
 630             trace_esp_mem_writeb_cmd_selatn(val);
 631             handle_satn(s);
 632             break;
 633         case CMD_SELATNS:
 634             trace_esp_mem_writeb_cmd_selatns(val);
 635             handle_satn_stop(s);
 636             break;
 637         case CMD_ENSEL:
 638             trace_esp_mem_writeb_cmd_ensel(val);
 639             s->rregs[ESP_RINTR] = 0;
 640             break;
 641         default:
 642             ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
 643             break;
 644         }
 645         break;
 646     case ESP_WBUSID ... ESP_WSYNO:
 647         break;
 648     case ESP_CFG1:
 649         s->rregs[saddr] = val;
 650         break;
 651     case ESP_WCCF ... ESP_WTEST:
 652         break;
 653     case ESP_CFG2 ... ESP_RES4:
 654         s->rregs[saddr] = val;
 655         break;
 656     default:
 657         ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
 658         return;
 659     }
 660     s->wregs[saddr] = val;
 661 }
 662
 663 static CPUReadMemoryFunc * const esp_mem_read[3] = {
 664     esp_mem_readb,
 665     NULL,
 666     NULL,
 667 };
 668
 669 static CPUWriteMemoryFunc * const esp_mem_write[3] = {
 670     esp_mem_writeb,
 671     NULL,
 672     esp_mem_writeb,
 673 };
 674
 675 static const VMStateDescription vmstate_esp = {
 676     .name ="esp",
 677     .version_id = 3,
 678     .minimum_version_id = 3,
 679     .minimum_version_id_old = 3,
 680     .fields      = (VMStateField []) {
 681         VMSTATE_BUFFER(rregs, ESPState),
 682         VMSTATE_BUFFER(wregs, ESPState),
 683         VMSTATE_INT32(ti_size, ESPState),
 684         VMSTATE_UINT32(ti_rptr, ESPState),
 685         VMSTATE_UINT32(ti_wptr, ESPState),
 686         VMSTATE_BUFFER(ti_buf, ESPState),
 687         VMSTATE_UINT32(status, ESPState),
 688         VMSTATE_UINT32(dma, ESPState),
 689         VMSTATE_BUFFER(cmdbuf, ESPState),
 690         VMSTATE_UINT32(cmdlen, ESPState),
 691         VMSTATE_UINT32(do_cmd, ESPState),
 692         VMSTATE_UINT32(dma_left, ESPState),
 693         VMSTATE_END_OF_LIST()
 694     }
 695 };
 696
 697 void esp_init(target_phys_addr_t espaddr, int it_shift,
 698               ESPDMAMemoryReadWriteFunc dma_memory_read,
 699               ESPDMAMemoryReadWriteFunc dma_memory_write,
 700               void *dma_opaque, qemu_irq irq, qemu_irq *reset,
 701               qemu_irq *dma_enable)
 702 {
 703     DeviceState *dev;
 704     SysBusDevice *s;
 705     ESPState *esp;
 706
 707     dev = qdev_create(NULL, "esp");
 708     esp = DO_UPCAST(ESPState, busdev.qdev, dev);
 709     esp->dma_memory_read = dma_memory_read;
 710     esp->dma_memory_write = dma_memory_write;
 711     esp->dma_opaque = dma_opaque;
 712     esp->it_shift = it_shift;
 713     /* XXX for now until rc4030 has been changed to use DMA enable signal */
 714     esp->dma_enabled = 1;
 715     qdev_init_nofail(dev);
 716     s = sysbus_from_qdev(dev);
 717     sysbus_connect_irq(s, 0, irq);
 718     sysbus_mmio_map(s, 0, espaddr);
 719     *reset = qdev_get_gpio_in(dev, 0);
 720     *dma_enable = qdev_get_gpio_in(dev, 1);
 721 }
 722
 723 static const struct SCSIBusOps esp_scsi_ops = {
 724     .transfer_data = esp_transfer_data,
 725     .complete = esp_command_complete,
 726     .cancel = esp_request_cancelled
 727 };
 728
 729 static int esp_init1(SysBusDevice *dev)
 730 {
 731     ESPState *s = FROM_SYSBUS(ESPState, dev);
 732     int esp_io_memory;
 733
 734     sysbus_init_irq(dev, &s->irq);
 735     assert(s->it_shift != -1);
 736
 737     esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
 738                                            DEVICE_NATIVE_ENDIAN);
 739     sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
 740
 741     qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
 742
 743     scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, &esp_scsi_ops);
 744     return scsi_bus_legacy_handle_cmdline(&s->bus);
 745 }
 746
 747 static SysBusDeviceInfo esp_info = {
 748     .init = esp_init1,
 749     .qdev.name  = "esp",
 750     .qdev.size  = sizeof(ESPState),
 751     .qdev.vmsd  = &vmstate_esp,
 752     .qdev.reset = esp_hard_reset,
 753     .qdev.props = (Property[]) {
 754         {.name = NULL}
 755     }
 756 };
 757
 758 static void esp_register_devices(void)
 759 {
 760     sysbus_register_withprop(&esp_info);
 761 }
 762
 763 device_init(esp_register_devices)