target/s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #ifndef S390X_CPU_H
  24 #define S390X_CPU_H
  25
  26 #include "qemu-common.h"
  27 #include "cpu-qom.h"
  28
  29 #define TARGET_LONG_BITS 64
  30
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46 #define TARGET_INSN_START_EXTRA_WORDS 1
  47
  48 #define MMU_MODE0_SUFFIX _primary
  49 #define MMU_MODE1_SUFFIX _secondary
  50 #define MMU_MODE2_SUFFIX _home
  51
  52 #define MMU_USER_IDX 0
  53
  54 #define MAX_EXT_QUEUE 16
  55 #define MAX_IO_QUEUE 16
  56 #define MAX_MCHK_QUEUE 16
  57
  58 #define PSW_MCHK_MASK 0x0004000000000000
  59 #define PSW_IO_MASK 0x0200000000000000
  60
  61 typedef struct PSW {
  62     uint64_t mask;
  63     uint64_t addr;
  64 } PSW;
  65
  66 typedef struct ExtQueue {
  67     uint32_t code;
  68     uint32_t param;
  69     uint32_t param64;
  70 } ExtQueue;
  71
  72 typedef struct IOIntQueue {
  73     uint16_t id;
  74     uint16_t nr;
  75     uint32_t parm;
  76     uint32_t word;
  77 } IOIntQueue;
  78
  79 typedef struct MchkQueue {
  80     uint16_t type;
  81 } MchkQueue;
  82
  83 typedef struct CPUS390XState {
  84     uint64_t regs[16];     /* GP registers */
  85     /*
  86      * The floating point registers are part of the vector registers.
  87      * vregs[0][0] -> vregs[15][0] are 16 floating point registers
  88      */
  89     CPU_DoubleU vregs[32][2];  /* vector registers */
  90     uint32_t aregs[16];    /* access registers */
  91     uint8_t riccb[64];     /* runtime instrumentation control */
  92     uint64_t gscb[4];      /* guarded storage control */
  93
  94     /* Fields up to this point are not cleared by initial CPU reset */
  95     struct {} start_initial_reset_fields;
  96
  97     uint32_t fpc;          /* floating-point control register */
  98     uint32_t cc_op;
  99
 100     float_status fpu_status; /* passed to softfloat lib */
 101
 102     /* The low part of a 128-bit return, or remainder of a divide.  */
 103     uint64_t retxl;
 104
 105     PSW psw;
 106
 107     uint64_t cc_src;
 108     uint64_t cc_dst;
 109     uint64_t cc_vr;
 110
 111     uint64_t ex_value;
 112
 113     uint64_t __excp_addr;
 114     uint64_t psa;
 115
 116     uint32_t int_pgm_code;
 117     uint32_t int_pgm_ilen;
 118
 119     uint32_t int_svc_code;
 120     uint32_t int_svc_ilen;
 121
 122     uint64_t per_address;
 123     uint16_t per_perc_atmid;
 124
 125     uint64_t cregs[16]; /* control registers */
 126
 127     ExtQueue ext_queue[MAX_EXT_QUEUE];
 128     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 129     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 130
 131     int pending_int;
 132     int ext_index;
 133     int io_index[8];
 134     int mchk_index;
 135
 136     uint64_t ckc;
 137     uint64_t cputm;
 138     uint32_t todpr;
 139
 140     uint64_t pfault_token;
 141     uint64_t pfault_compare;
 142     uint64_t pfault_select;
 143
 144     uint64_t gbea;
 145     uint64_t pp;
 146
 147     /* Fields up to this point are cleared by a CPU reset */
 148     struct {} end_reset_fields;
 149
 150     CPU_COMMON
 151
 152     uint32_t cpu_num;
 153     uint64_t cpuid;
 154
 155     uint64_t tod_offset;
 156     uint64_t tod_basetime;
 157     QEMUTimer *tod_timer;
 158
 159     QEMUTimer *cpu_timer;
 160
 161     /*
 162      * The cpu state represents the logical state of a cpu. In contrast to other
 163      * architectures, there is a difference between a halt and a stop on s390.
 164      * If all cpus are either stopped (including check stop) or in the disabled
 165      * wait state, the vm can be shut down.
 166      */
 167 #define CPU_STATE_UNINITIALIZED        0x00
 168 #define CPU_STATE_STOPPED              0x01
 169 #define CPU_STATE_CHECK_STOP           0x02
 170 #define CPU_STATE_OPERATING            0x03
 171 #define CPU_STATE_LOAD                 0x04
 172     uint8_t cpu_state;
 173
 174     /* currently processed sigp order */
 175     uint8_t sigp_order;
 176
 177 } CPUS390XState;
 178
 179 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
 180 {
 181     return &cs->vregs[nr][0];
 182 }
 183
 184 /**
 185  * S390CPU:
 186  * @env: #CPUS390XState.
 187  *
 188  * An S/390 CPU.
 189  */
 190 struct S390CPU {
 191     /*< private >*/
 192     CPUState parent_obj;
 193     /*< public >*/
 194
 195     CPUS390XState env;
 196     int64_t id;
 197     S390CPUModel *model;
 198     /* needed for live migration */
 199     void *irqstate;
 200     uint32_t irqstate_saved_size;
 201 };
 202
 203 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
 204 {
 205     return container_of(env, S390CPU, env);
 206 }
 207
 208 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
 209
 210 #define ENV_OFFSET offsetof(S390CPU, env)
 211
 212 #ifndef CONFIG_USER_ONLY
 213 extern const struct VMStateDescription vmstate_s390_cpu;
 214 #endif
 215
 216 #include "sysemu/kvm.h"
 217
 218 /* distinguish between 24 bit and 31 bit addressing */
 219 #define HIGH_ORDER_BIT 0x80000000
 220
 221 /* Interrupt Codes */
 222 /* Program Interrupts */
 223 #define PGM_OPERATION                   0x0001
 224 #define PGM_PRIVILEGED                  0x0002
 225 #define PGM_EXECUTE                     0x0003
 226 #define PGM_PROTECTION                  0x0004
 227 #define PGM_ADDRESSING                  0x0005
 228 #define PGM_SPECIFICATION               0x0006
 229 #define PGM_DATA                        0x0007
 230 #define PGM_FIXPT_OVERFLOW              0x0008
 231 #define PGM_FIXPT_DIVIDE                0x0009
 232 #define PGM_DEC_OVERFLOW                0x000a
 233 #define PGM_DEC_DIVIDE                  0x000b
 234 #define PGM_HFP_EXP_OVERFLOW            0x000c
 235 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 236 #define PGM_HFP_SIGNIFICANCE            0x000e
 237 #define PGM_HFP_DIVIDE                  0x000f
 238 #define PGM_SEGMENT_TRANS               0x0010
 239 #define PGM_PAGE_TRANS                  0x0011
 240 #define PGM_TRANS_SPEC                  0x0012
 241 #define PGM_SPECIAL_OP                  0x0013
 242 #define PGM_OPERAND                     0x0015
 243 #define PGM_TRACE_TABLE                 0x0016
 244 #define PGM_SPACE_SWITCH                0x001c
 245 #define PGM_HFP_SQRT                    0x001d
 246 #define PGM_PC_TRANS_SPEC               0x001f
 247 #define PGM_AFX_TRANS                   0x0020
 248 #define PGM_ASX_TRANS                   0x0021
 249 #define PGM_LX_TRANS                    0x0022
 250 #define PGM_EX_TRANS                    0x0023
 251 #define PGM_PRIM_AUTH                   0x0024
 252 #define PGM_SEC_AUTH                    0x0025
 253 #define PGM_ALET_SPEC                   0x0028
 254 #define PGM_ALEN_SPEC                   0x0029
 255 #define PGM_ALE_SEQ                     0x002a
 256 #define PGM_ASTE_VALID                  0x002b
 257 #define PGM_ASTE_SEQ                    0x002c
 258 #define PGM_EXT_AUTH                    0x002d
 259 #define PGM_STACK_FULL                  0x0030
 260 #define PGM_STACK_EMPTY                 0x0031
 261 #define PGM_STACK_SPEC                  0x0032
 262 #define PGM_STACK_TYPE                  0x0033
 263 #define PGM_STACK_OP                    0x0034
 264 #define PGM_ASCE_TYPE                   0x0038
 265 #define PGM_REG_FIRST_TRANS             0x0039
 266 #define PGM_REG_SEC_TRANS               0x003a
 267 #define PGM_REG_THIRD_TRANS             0x003b
 268 #define PGM_MONITOR                     0x0040
 269 #define PGM_PER                         0x0080
 270 #define PGM_CRYPTO                      0x0119
 271
 272 /* External Interrupts */
 273 #define EXT_INTERRUPT_KEY               0x0040
 274 #define EXT_CLOCK_COMP                  0x1004
 275 #define EXT_CPU_TIMER                   0x1005
 276 #define EXT_MALFUNCTION                 0x1200
 277 #define EXT_EMERGENCY                   0x1201
 278 #define EXT_EXTERNAL_CALL               0x1202
 279 #define EXT_ETR                         0x1406
 280 #define EXT_SERVICE                     0x2401
 281 #define EXT_VIRTIO                      0x2603
 282
 283 /* PSW defines */
 284 #undef PSW_MASK_PER
 285 #undef PSW_MASK_DAT
 286 #undef PSW_MASK_IO
 287 #undef PSW_MASK_EXT
 288 #undef PSW_MASK_KEY
 289 #undef PSW_SHIFT_KEY
 290 #undef PSW_MASK_MCHECK
 291 #undef PSW_MASK_WAIT
 292 #undef PSW_MASK_PSTATE
 293 #undef PSW_MASK_ASC
 294 #undef PSW_SHIFT_ASC
 295 #undef PSW_MASK_CC
 296 #undef PSW_MASK_PM
 297 #undef PSW_MASK_64
 298 #undef PSW_MASK_32
 299 #undef PSW_MASK_ESA_ADDR
 300
 301 #define PSW_MASK_PER            0x4000000000000000ULL
 302 #define PSW_MASK_DAT            0x0400000000000000ULL
 303 #define PSW_MASK_IO             0x0200000000000000ULL
 304 #define PSW_MASK_EXT            0x0100000000000000ULL
 305 #define PSW_MASK_KEY            0x00F0000000000000ULL
 306 #define PSW_SHIFT_KEY           52
 307 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 308 #define PSW_MASK_WAIT           0x0002000000000000ULL
 309 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 310 #define PSW_MASK_ASC            0x0000C00000000000ULL
 311 #define PSW_SHIFT_ASC           46
 312 #define PSW_MASK_CC             0x0000300000000000ULL
 313 #define PSW_MASK_PM             0x00000F0000000000ULL
 314 #define PSW_MASK_64             0x0000000100000000ULL
 315 #define PSW_MASK_32             0x0000000080000000ULL
 316 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 317
 318 #undef PSW_ASC_PRIMARY
 319 #undef PSW_ASC_ACCREG
 320 #undef PSW_ASC_SECONDARY
 321 #undef PSW_ASC_HOME
 322
 323 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 324 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 325 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 326 #define PSW_ASC_HOME            0x0000C00000000000ULL
 327
 328 /* the address space values shifted */
 329 #define AS_PRIMARY              0
 330 #define AS_ACCREG               1
 331 #define AS_SECONDARY            2
 332 #define AS_HOME                 3
 333
 334 /* tb flags */
 335
 336 #define FLAG_MASK_PSW_SHIFT     31
 337 #define FLAG_MASK_PER           (PSW_MASK_PER    >> FLAG_MASK_PSW_SHIFT)
 338 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
 339 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> FLAG_MASK_PSW_SHIFT)
 340 #define FLAG_MASK_64            (PSW_MASK_64     >> FLAG_MASK_PSW_SHIFT)
 341 #define FLAG_MASK_32            (PSW_MASK_32     >> FLAG_MASK_PSW_SHIFT)
 342 #define FLAG_MASK_PSW           (FLAG_MASK_PER | FLAG_MASK_PSTATE \
 343                                 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
 344
 345 /* Control register 0 bits */
 346 #define CR0_LOWPROT             0x0000000010000000ULL
 347 #define CR0_SECONDARY           0x0000000004000000ULL
 348 #define CR0_EDAT                0x0000000000800000ULL
 349
 350 /* MMU */
 351 #define MMU_PRIMARY_IDX         0
 352 #define MMU_SECONDARY_IDX       1
 353 #define MMU_HOME_IDX            2
 354
 355 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
 356 {
 357     switch (env->psw.mask & PSW_MASK_ASC) {
 358     case PSW_ASC_PRIMARY:
 359         return MMU_PRIMARY_IDX;
 360     case PSW_ASC_SECONDARY:
 361         return MMU_SECONDARY_IDX;
 362     case PSW_ASC_HOME:
 363         return MMU_HOME_IDX;
 364     case PSW_ASC_ACCREG:
 365         /* Fallthrough: access register mode is not yet supported */
 366     default:
 367         abort();
 368     }
 369 }
 370
 371 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 372                                         target_ulong *cs_base, uint32_t *flags)
 373 {
 374     *pc = env->psw.addr;
 375     *cs_base = env->ex_value;
 376     *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
 377 }
 378
 379 /* PER bits from control register 9 */
 380 #define PER_CR9_EVENT_BRANCH           0x80000000
 381 #define PER_CR9_EVENT_IFETCH           0x40000000
 382 #define PER_CR9_EVENT_STORE            0x20000000
 383 #define PER_CR9_EVENT_STORE_REAL       0x08000000
 384 #define PER_CR9_EVENT_NULLIFICATION    0x01000000
 385 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
 386 #define PER_CR9_CONTROL_ALTERATION     0x00200000
 387
 388 /* PER bits from the PER CODE/ATMID/AI in lowcore */
 389 #define PER_CODE_EVENT_BRANCH          0x8000
 390 #define PER_CODE_EVENT_IFETCH          0x4000
 391 #define PER_CODE_EVENT_STORE           0x2000
 392 #define PER_CODE_EVENT_STORE_REAL      0x0800
 393 #define PER_CODE_EVENT_NULLIFICATION   0x0100
 394
 395 S390CPU *cpu_s390x_init(const char *cpu_model);
 396 S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
 397
 398 /* you can call this signal handler from your SIGBUS and SIGSEGV
 399    signal handlers to inform the virtual CPU of exceptions. non zero
 400    is returned if the signal was handled by the virtual CPU.  */
 401 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 402                            void *puc);
 403
 404
 405 #ifndef CONFIG_USER_ONLY
 406
 407 int s390_virtio_hypercall(CPUS390XState *env);
 408
 409 #ifdef CONFIG_KVM
 410 void kvm_s390_service_interrupt(uint32_t parm);
 411 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
 412 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
 413 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
 414 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
 415 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
 416                     int len, bool is_write);
 417 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
 418 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
 419 #else
 420 static inline void kvm_s390_service_interrupt(uint32_t parm)
 421 {
 422 }
 423 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 424 {
 425     return -ENOSYS;
 426 }
 427 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 428 {
 429     return -ENOSYS;
 430 }
 431 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
 432                                   void *hostbuf, int len, bool is_write)
 433 {
 434     return -ENOSYS;
 435 }
 436 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
 437                                              uint64_t te_code)
 438 {
 439 }
 440 #endif
 441
 442 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
 443 {
 444     if (kvm_enabled()) {
 445         return kvm_s390_get_clock(tod_high, tod_low);
 446     }
 447     /* Fixme TCG */
 448     *tod_high = 0;
 449     *tod_low = 0;
 450     return 0;
 451 }
 452
 453 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
 454 {
 455     if (kvm_enabled()) {
 456         return kvm_s390_set_clock(tod_high, tod_low);
 457     }
 458     /* Fixme TCG */
 459     return 0;
 460 }
 461
 462 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 463 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
 464
 465 /* service interrupts are floating therefore we must not pass an cpustate */
 466 void s390_sclp_extint(uint32_t parm);
 467
 468 #else
 469 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
 470 {
 471     return 0;
 472 }
 473 #endif
 474
 475 extern void subsystem_reset(void);
 476
 477 #define cpu_init(model) CPU(cpu_s390x_init(model))
 478 #define cpu_signal_handler cpu_s390x_signal_handler
 479
 480 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 481 #define cpu_list s390_cpu_list
 482 const char *s390_default_cpu_model_name(void);
 483
 484 #define EXCP_EXT 1 /* external interrupt */
 485 #define EXCP_SVC 2 /* supervisor call (syscall) */
 486 #define EXCP_PGM 3 /* program interruption */
 487 #define EXCP_IO  7 /* I/O interrupt */
 488 #define EXCP_MCHK 8 /* machine check */
 489
 490 #define INTERRUPT_EXT        (1 << 0)
 491 #define INTERRUPT_TOD        (1 << 1)
 492 #define INTERRUPT_CPUTIMER   (1 << 2)
 493 #define INTERRUPT_IO         (1 << 3)
 494 #define INTERRUPT_MCHK       (1 << 4)
 495
 496 /* Program Status Word.  */
 497 #define S390_PSWM_REGNUM 0
 498 #define S390_PSWA_REGNUM 1
 499 /* General Purpose Registers.  */
 500 #define S390_R0_REGNUM 2
 501 #define S390_R1_REGNUM 3
 502 #define S390_R2_REGNUM 4
 503 #define S390_R3_REGNUM 5
 504 #define S390_R4_REGNUM 6
 505 #define S390_R5_REGNUM 7
 506 #define S390_R6_REGNUM 8
 507 #define S390_R7_REGNUM 9
 508 #define S390_R8_REGNUM 10
 509 #define S390_R9_REGNUM 11
 510 #define S390_R10_REGNUM 12
 511 #define S390_R11_REGNUM 13
 512 #define S390_R12_REGNUM 14
 513 #define S390_R13_REGNUM 15
 514 #define S390_R14_REGNUM 16
 515 #define S390_R15_REGNUM 17
 516 /* Total Core Registers. */
 517 #define S390_NUM_CORE_REGS 18
 518
 519 static inline void setcc(S390CPU *cpu, uint64_t cc)
 520 {
 521     CPUS390XState *env = &cpu->env;
 522
 523     env->psw.mask &= ~(3ull << 44);
 524     env->psw.mask |= (cc & 3) << 44;
 525     env->cc_op = cc;
 526 }
 527
 528 /* STSI */
 529 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 530 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 531 #define STSI_LEVEL_1            0x0000000010000000ULL
 532 #define STSI_LEVEL_2            0x0000000020000000ULL
 533 #define STSI_LEVEL_3            0x0000000030000000ULL
 534 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 535 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 536 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 537 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 538
 539 /* Basic Machine Configuration */
 540 struct sysib_111 {
 541     uint32_t res1[8];
 542     uint8_t  manuf[16];
 543     uint8_t  type[4];
 544     uint8_t  res2[12];
 545     uint8_t  model[16];
 546     uint8_t  sequence[16];
 547     uint8_t  plant[4];
 548     uint8_t  res3[156];
 549 };
 550
 551 /* Basic Machine CPU */
 552 struct sysib_121 {
 553     uint32_t res1[80];
 554     uint8_t  sequence[16];
 555     uint8_t  plant[4];
 556     uint8_t  res2[2];
 557     uint16_t cpu_addr;
 558     uint8_t  res3[152];
 559 };
 560
 561 /* Basic Machine CPUs */
 562 struct sysib_122 {
 563     uint8_t res1[32];
 564     uint32_t capability;
 565     uint16_t total_cpus;
 566     uint16_t active_cpus;
 567     uint16_t standby_cpus;
 568     uint16_t reserved_cpus;
 569     uint16_t adjustments[2026];
 570 };
 571
 572 /* LPAR CPU */
 573 struct sysib_221 {
 574     uint32_t res1[80];
 575     uint8_t  sequence[16];
 576     uint8_t  plant[4];
 577     uint16_t cpu_id;
 578     uint16_t cpu_addr;
 579     uint8_t  res3[152];
 580 };
 581
 582 /* LPAR CPUs */
 583 struct sysib_222 {
 584     uint32_t res1[32];
 585     uint16_t lpar_num;
 586     uint8_t  res2;
 587     uint8_t  lcpuc;
 588     uint16_t total_cpus;
 589     uint16_t conf_cpus;
 590     uint16_t standby_cpus;
 591     uint16_t reserved_cpus;
 592     uint8_t  name[8];
 593     uint32_t caf;
 594     uint8_t  res3[16];
 595     uint16_t dedicated_cpus;
 596     uint16_t shared_cpus;
 597     uint8_t  res4[180];
 598 };
 599
 600 /* VM CPUs */
 601 struct sysib_322 {
 602     uint8_t  res1[31];
 603     uint8_t  count;
 604     struct {
 605         uint8_t  res2[4];
 606         uint16_t total_cpus;
 607         uint16_t conf_cpus;
 608         uint16_t standby_cpus;
 609         uint16_t reserved_cpus;
 610         uint8_t  name[8];
 611         uint32_t caf;
 612         uint8_t  cpi[16];
 613         uint8_t res5[3];
 614         uint8_t ext_name_encoding;
 615         uint32_t res3;
 616         uint8_t uuid[16];
 617     } vm[8];
 618     uint8_t res4[1504];
 619     uint8_t ext_names[8][256];
 620 };
 621
 622 /* MMU defines */
 623 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 624 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 625 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 626 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 627 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 628 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 629 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 630 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 631 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 632 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 633 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 634 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 635
 636 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 637 #define _REGION_ENTRY_RO        0x200     /* region/segment protection bit    */
 638 #define _REGION_ENTRY_TF        0xc0      /* region/segment table offset      */
 639 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 640 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 641 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 642 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 643 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 644 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 645
 646 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 647 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 648 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 649 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 650
 651 #define VADDR_PX                0xff000   /* page index bits                  */
 652
 653 #define _PAGE_RO        0x200            /* HW read-only bit  */
 654 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 655 #define _PAGE_RES0      0x800            /* bit must be zero  */
 656
 657 #define SK_C                    (0x1 << 1)
 658 #define SK_R                    (0x1 << 2)
 659 #define SK_F                    (0x1 << 3)
 660 #define SK_ACC_MASK             (0xf << 4)
 661
 662 /* SIGP order codes */
 663 #define SIGP_SENSE             0x01
 664 #define SIGP_EXTERNAL_CALL     0x02
 665 #define SIGP_EMERGENCY         0x03
 666 #define SIGP_START             0x04
 667 #define SIGP_STOP              0x05
 668 #define SIGP_RESTART           0x06
 669 #define SIGP_STOP_STORE_STATUS 0x09
 670 #define SIGP_INITIAL_CPU_RESET 0x0b
 671 #define SIGP_CPU_RESET         0x0c
 672 #define SIGP_SET_PREFIX        0x0d
 673 #define SIGP_STORE_STATUS_ADDR 0x0e
 674 #define SIGP_SET_ARCH          0x12
 675 #define SIGP_STORE_ADTL_STATUS 0x17
 676
 677 /* SIGP condition codes */
 678 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
 679 #define SIGP_CC_STATUS_STORED       1
 680 #define SIGP_CC_BUSY                2
 681 #define SIGP_CC_NOT_OPERATIONAL     3
 682
 683 /* SIGP status bits */
 684 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 685 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 686 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 687 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 688 #define SIGP_STAT_STOPPED           0x00000040UL
 689 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 690 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 691 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 692 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 693 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 694
 695 /* SIGP SET ARCHITECTURE modes */
 696 #define SIGP_MODE_ESA_S390 0
 697 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
 698 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
 699
 700 /* SIGP order code mask corresponding to bit positions 56-63 */
 701 #define SIGP_ORDER_MASK 0x000000ff
 702
 703 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
 704
 705 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
 706                          int len, bool is_write);
 707
 708 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len)    \
 709         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
 710 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len)       \
 711         s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
 712 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len)   \
 713         s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
 714
 715 /* from s390-virtio-ccw */
 716 #define MEM_SECTION_SIZE             0x10000000UL
 717 #define MAX_AVAIL_SLOTS              32
 718
 719 /* automatically detect the instruction length */
 720 #define ILEN_AUTO                   0xff
 721 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
 722
 723 #ifdef CONFIG_KVM
 724 void kvm_s390_program_interrupt(S390CPU *cpu, uint16_t code);
 725 void kvm_s390_io_interrupt(uint16_t subchannel_id,
 726                            uint16_t subchannel_nr, uint32_t io_int_parm,
 727                            uint32_t io_int_word);
 728 void kvm_s390_crw_mchk(void);
 729 void kvm_s390_enable_css_support(S390CPU *cpu);
 730 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
 731                                     int vq, bool assign);
 732 int kvm_s390_cpu_restart(S390CPU *cpu);
 733 int kvm_s390_get_memslot_count(void);
 734 int kvm_s390_cmma_active(void);
 735 void kvm_s390_cmma_reset(void);
 736 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
 737 void kvm_s390_reset_vcpu(S390CPU *cpu);
 738 int kvm_s390_set_mem_limit(uint64_t new_limit, uint64_t *hw_limit);
 739 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
 740 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
 741 int kvm_s390_get_ri(void);
 742 int kvm_s390_get_gs(void);
 743 void kvm_s390_crypto_reset(void);
 744 #else
 745 static inline void kvm_s390_program_interrupt(S390CPU *cpu, uint16_t code)
 746 {
 747 }
 748 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
 749                                         uint16_t subchannel_nr,
 750                                         uint32_t io_int_parm,
 751                                         uint32_t io_int_word)
 752 {
 753 }
 754 static inline void kvm_s390_crw_mchk(void)
 755 {
 756 }
 757 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
 758 {
 759 }
 760 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
 761                                                   uint32_t sch, int vq,
 762                                                   bool assign)
 763 {
 764     return -ENOSYS;
 765 }
 766 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
 767 {
 768     return -ENOSYS;
 769 }
 770 static inline void kvm_s390_cmma_reset(void)
 771 {
 772 }
 773 static inline int kvm_s390_get_memslot_count(void)
 774 {
 775   return MAX_AVAIL_SLOTS;
 776 }
 777 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
 778 {
 779     return -ENOSYS;
 780 }
 781 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
 782 {
 783 }
 784 static inline int kvm_s390_set_mem_limit(uint64_t new_limit, uint64_t *hw_limit)
 785 {
 786     return 0;
 787 }
 788 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
 789 {
 790 }
 791 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
 792 {
 793     return 0;
 794 }
 795 static inline int kvm_s390_get_ri(void)
 796 {
 797     return 0;
 798 }
 799 static inline int kvm_s390_get_gs(void)
 800 {
 801     return 0;
 802 }
 803 static inline void kvm_s390_crypto_reset(void)
 804 {
 805 }
 806 #endif
 807
 808 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
 809 {
 810     if (kvm_enabled()) {
 811         return kvm_s390_set_mem_limit(new_limit, hw_limit);
 812     }
 813     return 0;
 814 }
 815
 816 static inline void s390_cmma_reset(void)
 817 {
 818     if (kvm_enabled()) {
 819         kvm_s390_cmma_reset();
 820     }
 821 }
 822
 823 static inline int s390_cpu_restart(S390CPU *cpu)
 824 {
 825     if (kvm_enabled()) {
 826         return kvm_s390_cpu_restart(cpu);
 827     }
 828     return -ENOSYS;
 829 }
 830
 831 static inline int s390_get_memslot_count(void)
 832 {
 833     if (kvm_enabled()) {
 834         return kvm_s390_get_memslot_count();
 835     } else {
 836         return MAX_AVAIL_SLOTS;
 837     }
 838 }
 839
 840 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
 841                        uint32_t io_int_parm, uint32_t io_int_word);
 842 void s390_crw_mchk(void);
 843
 844 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
 845                                               uint32_t sch_id, int vq,
 846                                               bool assign)
 847 {
 848     if (kvm_enabled()) {
 849         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
 850     } else {
 851         return 0;
 852     }
 853 }
 854
 855 static inline void s390_crypto_reset(void)
 856 {
 857     if (kvm_enabled()) {
 858         kvm_s390_crypto_reset();
 859     }
 860 }
 861
 862 static inline bool s390_get_squash_mcss(void)
 863 {
 864     if (object_property_get_bool(OBJECT(qdev_get_machine()), "s390-squash-mcss",
 865                                  NULL)) {
 866         return true;
 867     }
 868
 869     return false;
 870 }
 871
 872 /* machine check interruption code */
 873
 874 /* subclasses */
 875 #define MCIC_SC_SD 0x8000000000000000ULL
 876 #define MCIC_SC_PD 0x4000000000000000ULL
 877 #define MCIC_SC_SR 0x2000000000000000ULL
 878 #define MCIC_SC_CD 0x0800000000000000ULL
 879 #define MCIC_SC_ED 0x0400000000000000ULL
 880 #define MCIC_SC_DG 0x0100000000000000ULL
 881 #define MCIC_SC_W  0x0080000000000000ULL
 882 #define MCIC_SC_CP 0x0040000000000000ULL
 883 #define MCIC_SC_SP 0x0020000000000000ULL
 884 #define MCIC_SC_CK 0x0010000000000000ULL
 885
 886 /* subclass modifiers */
 887 #define MCIC_SCM_B  0x0002000000000000ULL
 888 #define MCIC_SCM_DA 0x0000000020000000ULL
 889 #define MCIC_SCM_AP 0x0000000000080000ULL
 890
 891 /* storage errors */
 892 #define MCIC_SE_SE 0x0000800000000000ULL
 893 #define MCIC_SE_SC 0x0000400000000000ULL
 894 #define MCIC_SE_KE 0x0000200000000000ULL
 895 #define MCIC_SE_DS 0x0000100000000000ULL
 896 #define MCIC_SE_IE 0x0000000080000000ULL
 897
 898 /* validity bits */
 899 #define MCIC_VB_WP 0x0000080000000000ULL
 900 #define MCIC_VB_MS 0x0000040000000000ULL
 901 #define MCIC_VB_PM 0x0000020000000000ULL
 902 #define MCIC_VB_IA 0x0000010000000000ULL
 903 #define MCIC_VB_FA 0x0000008000000000ULL
 904 #define MCIC_VB_VR 0x0000004000000000ULL
 905 #define MCIC_VB_EC 0x0000002000000000ULL
 906 #define MCIC_VB_FP 0x0000001000000000ULL
 907 #define MCIC_VB_GR 0x0000000800000000ULL
 908 #define MCIC_VB_CR 0x0000000400000000ULL
 909 #define MCIC_VB_ST 0x0000000100000000ULL
 910 #define MCIC_VB_AR 0x0000000040000000ULL
 911 #define MCIC_VB_GS 0x0000000008000000ULL
 912 #define MCIC_VB_PR 0x0000000000200000ULL
 913 #define MCIC_VB_FC 0x0000000000100000ULL
 914 #define MCIC_VB_CT 0x0000000000020000ULL
 915 #define MCIC_VB_CC 0x0000000000010000ULL
 916
 917 #endif