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ipxe: add vmxnet3 rom
[qemu.git] / target-mips / msa_helper.c
blobae92fcbe28ec94a7515bcc990f5ae0ab70d9558e
1 /*
2 * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2014 Imagination Technologies
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24
25 /* Data format min and max values */
26 #define DF_BITS(df) (1 << ((df) + 3))
27
28 #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
29 #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
30
31 #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
32 #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
33
34 #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
35 #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
36
37 #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
38 #define SIGNED(x, df) \
39 ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
40
41 /* Element-by-element access macros */
42 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
43
44 static inline void msa_move_v(wr_t *pwd, wr_t *pws)
45 {
46 uint32_t i;
47
48 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
49 pwd->d[i] = pws->d[i];
50 }
51 }
52
53 #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
54 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
55 uint32_t i8) \
56 { \
57 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
58 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
59 uint32_t i; \
60 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
61 DEST = OPERATION; \
62 } \
63 }
64
65 MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
66 MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
67 MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
68 MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
69
70 #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
71 UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
72 MSA_FN_IMM8(bmnzi_b, pwd->b[i],
73 BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
74
75 #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
76 UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
77 MSA_FN_IMM8(bmzi_b, pwd->b[i],
78 BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
79
80 #define BIT_SELECT(dest, arg1, arg2, df) \
81 UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
82 MSA_FN_IMM8(bseli_b, pwd->b[i],
83 BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
84
85 #undef MSA_FN_IMM8
86
87 #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
88
89 void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
90 uint32_t ws, uint32_t imm)
91 {
92 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
93 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
94 wr_t wx, *pwx = &wx;
95 uint32_t i;
96
97 switch (df) {
98 case DF_BYTE:
99 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
100 pwx->b[i] = pws->b[SHF_POS(i, imm)];
101 }
102 break;
103 case DF_HALF:
104 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
105 pwx->h[i] = pws->h[SHF_POS(i, imm)];
106 }
107 break;
108 case DF_WORD:
109 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
110 pwx->w[i] = pws->w[SHF_POS(i, imm)];
111 }
112 break;
113 default:
114 assert(0);
115 }
116 msa_move_v(pwd, pwx);
117 }
118
119 #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
120 void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
121 uint32_t wt) \
122 { \
123 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
124 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
125 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
126 uint32_t i; \
127 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
128 DEST = OPERATION; \
129 } \
130 }
131
132 MSA_FN_VECTOR(and_v, pwd->d[i], pws->d[i] & pwt->d[i])
133 MSA_FN_VECTOR(or_v, pwd->d[i], pws->d[i] | pwt->d[i])
134 MSA_FN_VECTOR(nor_v, pwd->d[i], ~(pws->d[i] | pwt->d[i]))
135 MSA_FN_VECTOR(xor_v, pwd->d[i], pws->d[i] ^ pwt->d[i])
136 MSA_FN_VECTOR(bmnz_v, pwd->d[i],
137 BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
138 MSA_FN_VECTOR(bmz_v, pwd->d[i],
139 BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
140 MSA_FN_VECTOR(bsel_v, pwd->d[i],
141 BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
142 #undef BIT_MOVE_IF_NOT_ZERO
143 #undef BIT_MOVE_IF_ZERO
144 #undef BIT_SELECT
145 #undef MSA_FN_VECTOR
146
147 static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
148 {
149 return arg1 + arg2;
150 }
151
152 static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
153 {
154 return arg1 - arg2;
155 }
156
157 static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
158 {
159 return arg1 == arg2 ? -1 : 0;
160 }
161
162 static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
163 {
164 return arg1 <= arg2 ? -1 : 0;
165 }
166
167 static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
168 {
169 uint64_t u_arg1 = UNSIGNED(arg1, df);
170 uint64_t u_arg2 = UNSIGNED(arg2, df);
171 return u_arg1 <= u_arg2 ? -1 : 0;
172 }
173
174 static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
175 {
176 return arg1 < arg2 ? -1 : 0;
177 }
178
179 static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
180 {
181 uint64_t u_arg1 = UNSIGNED(arg1, df);
182 uint64_t u_arg2 = UNSIGNED(arg2, df);
183 return u_arg1 < u_arg2 ? -1 : 0;
184 }
185
186 static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
187 {
188 return arg1 > arg2 ? arg1 : arg2;
189 }
190
191 static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
192 {
193 uint64_t u_arg1 = UNSIGNED(arg1, df);
194 uint64_t u_arg2 = UNSIGNED(arg2, df);
195 return u_arg1 > u_arg2 ? arg1 : arg2;
196 }
197
198 static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
199 {
200 return arg1 < arg2 ? arg1 : arg2;
201 }
202
203 static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
204 {
205 uint64_t u_arg1 = UNSIGNED(arg1, df);
206 uint64_t u_arg2 = UNSIGNED(arg2, df);
207 return u_arg1 < u_arg2 ? arg1 : arg2;
208 }
209
210 #define MSA_BINOP_IMM_DF(helper, func) \
211 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
212 uint32_t wd, uint32_t ws, int32_t u5) \
213 { \
214 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
215 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
216 uint32_t i; \
217 \
218 switch (df) { \
219 case DF_BYTE: \
220 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
221 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
222 } \
223 break; \
224 case DF_HALF: \
225 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
226 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
227 } \
228 break; \
229 case DF_WORD: \
230 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
231 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
232 } \
233 break; \
234 case DF_DOUBLE: \
235 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
236 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
237 } \
238 break; \
239 default: \
240 assert(0); \
241 } \
242 }
243
244 MSA_BINOP_IMM_DF(addvi, addv)
245 MSA_BINOP_IMM_DF(subvi, subv)
246 MSA_BINOP_IMM_DF(ceqi, ceq)
247 MSA_BINOP_IMM_DF(clei_s, cle_s)
248 MSA_BINOP_IMM_DF(clei_u, cle_u)
249 MSA_BINOP_IMM_DF(clti_s, clt_s)
250 MSA_BINOP_IMM_DF(clti_u, clt_u)
251 MSA_BINOP_IMM_DF(maxi_s, max_s)
252 MSA_BINOP_IMM_DF(maxi_u, max_u)
253 MSA_BINOP_IMM_DF(mini_s, min_s)
254 MSA_BINOP_IMM_DF(mini_u, min_u)
255 #undef MSA_BINOP_IMM_DF
256
257 void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
258 int32_t s10)
259 {
260 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
261 uint32_t i;
262
263 switch (df) {
264 case DF_BYTE:
265 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
266 pwd->b[i] = (int8_t)s10;
267 }
268 break;
269 case DF_HALF:
270 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
271 pwd->h[i] = (int16_t)s10;
272 }
273 break;
274 case DF_WORD:
275 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
276 pwd->w[i] = (int32_t)s10;
277 }
278 break;
279 case DF_DOUBLE:
280 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
281 pwd->d[i] = (int64_t)s10;
282 }
283 break;
284 default:
285 assert(0);
286 }
287 }
288
289 /* Data format bit position and unsigned values */
290 #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
291
292 static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
293 {
294 int32_t b_arg2 = BIT_POSITION(arg2, df);
295 return arg1 << b_arg2;
296 }
297
298 static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
299 {
300 int32_t b_arg2 = BIT_POSITION(arg2, df);
301 return arg1 >> b_arg2;
302 }
303
304 static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
305 {
306 uint64_t u_arg1 = UNSIGNED(arg1, df);
307 int32_t b_arg2 = BIT_POSITION(arg2, df);
308 return u_arg1 >> b_arg2;
309 }
310
311 static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
312 {
313 int32_t b_arg2 = BIT_POSITION(arg2, df);
314 return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
315 }
316
317 static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
318 int64_t arg2)
319 {
320 int32_t b_arg2 = BIT_POSITION(arg2, df);
321 return UNSIGNED(arg1 | (1LL << b_arg2), df);
322 }
323
324 static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
325 {
326 int32_t b_arg2 = BIT_POSITION(arg2, df);
327 return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
328 }
329
330 static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
331 int64_t arg2)
332 {
333 uint64_t u_arg1 = UNSIGNED(arg1, df);
334 uint64_t u_dest = UNSIGNED(dest, df);
335 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
336 int32_t sh_a = DF_BITS(df) - sh_d;
337 if (sh_d == DF_BITS(df)) {
338 return u_arg1;
339 } else {
340 return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
341 UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
342 }
343 }
344
345 static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
346 int64_t arg2)
347 {
348 uint64_t u_arg1 = UNSIGNED(arg1, df);
349 uint64_t u_dest = UNSIGNED(dest, df);
350 int32_t sh_d = BIT_POSITION(arg2, df) + 1;
351 int32_t sh_a = DF_BITS(df) - sh_d;
352 if (sh_d == DF_BITS(df)) {
353 return u_arg1;
354 } else {
355 return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
356 UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
357 }
358 }
359
360 static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
361 {
362 return arg < M_MIN_INT(m+1) ? M_MIN_INT(m+1) :
363 arg > M_MAX_INT(m+1) ? M_MAX_INT(m+1) :
364 arg;
365 }
366
367 static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
368 {
369 uint64_t u_arg = UNSIGNED(arg, df);
370 return u_arg < M_MAX_UINT(m+1) ? u_arg :
371 M_MAX_UINT(m+1);
372 }
373
374 static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
375 {
376 int32_t b_arg2 = BIT_POSITION(arg2, df);
377 if (b_arg2 == 0) {
378 return arg1;
379 } else {
380 int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
381 return (arg1 >> b_arg2) + r_bit;
382 }
383 }
384
385 static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
386 {
387 uint64_t u_arg1 = UNSIGNED(arg1, df);
388 int32_t b_arg2 = BIT_POSITION(arg2, df);
389 if (b_arg2 == 0) {
390 return u_arg1;
391 } else {
392 uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
393 return (u_arg1 >> b_arg2) + r_bit;
394 }
395 }
396
397 #define MSA_BINOP_IMMU_DF(helper, func) \
398 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
399 uint32_t ws, uint32_t u5) \
400 { \
401 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
402 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
403 uint32_t i; \
404 \
405 switch (df) { \
406 case DF_BYTE: \
407 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
408 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
409 } \
410 break; \
411 case DF_HALF: \
412 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
413 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
414 } \
415 break; \
416 case DF_WORD: \
417 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
418 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
419 } \
420 break; \
421 case DF_DOUBLE: \
422 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
423 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
424 } \
425 break; \
426 default: \
427 assert(0); \
428 } \
429 }
430
431 MSA_BINOP_IMMU_DF(slli, sll)
432 MSA_BINOP_IMMU_DF(srai, sra)
433 MSA_BINOP_IMMU_DF(srli, srl)
434 MSA_BINOP_IMMU_DF(bclri, bclr)
435 MSA_BINOP_IMMU_DF(bseti, bset)
436 MSA_BINOP_IMMU_DF(bnegi, bneg)
437 MSA_BINOP_IMMU_DF(sat_s, sat_s)
438 MSA_BINOP_IMMU_DF(sat_u, sat_u)
439 MSA_BINOP_IMMU_DF(srari, srar)
440 MSA_BINOP_IMMU_DF(srlri, srlr)
441 #undef MSA_BINOP_IMMU_DF
442
443 #define MSA_TEROP_IMMU_DF(helper, func) \
444 void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
445 uint32_t wd, uint32_t ws, uint32_t u5) \
446 { \
447 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
448 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
449 uint32_t i; \
450 \
451 switch (df) { \
452 case DF_BYTE: \
453 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
454 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
455 u5); \
456 } \
457 break; \
458 case DF_HALF: \
459 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
460 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
461 u5); \
462 } \
463 break; \
464 case DF_WORD: \
465 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
466 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
467 u5); \
468 } \
469 break; \
470 case DF_DOUBLE: \
471 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
472 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
473 u5); \
474 } \
475 break; \
476 default: \
477 assert(0); \
478 } \
479 }
480
481 MSA_TEROP_IMMU_DF(binsli, binsl)
482 MSA_TEROP_IMMU_DF(binsri, binsr)
483 #undef MSA_TEROP_IMMU_DF
484
485 static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
486 {
487 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
488 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
489 return abs_arg1 > abs_arg2 ? arg1 : arg2;
490 }
491
492 static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
493 {
494 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
495 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
496 return abs_arg1 < abs_arg2 ? arg1 : arg2;
497 }
498
499 static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
500 {
501 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
502 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
503 return abs_arg1 + abs_arg2;
504 }
505
506 static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
507 {
508 uint64_t max_int = (uint64_t)DF_MAX_INT(df);
509 uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
510 uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
511 if (abs_arg1 > max_int || abs_arg2 > max_int) {
512 return (int64_t)max_int;
513 } else {
514 return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
515 }
516 }
517
518 static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
519 {
520 int64_t max_int = DF_MAX_INT(df);
521 int64_t min_int = DF_MIN_INT(df);
522 if (arg1 < 0) {
523 return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
524 } else {
525 return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
526 }
527 }
528
529 static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
530 {
531 uint64_t max_uint = DF_MAX_UINT(df);
532 uint64_t u_arg1 = UNSIGNED(arg1, df);
533 uint64_t u_arg2 = UNSIGNED(arg2, df);
534 return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
535 }
536
537 static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2)
538 {
539 /* signed shift */
540 return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1);
541 }
542
543 static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
544 {
545 uint64_t u_arg1 = UNSIGNED(arg1, df);
546 uint64_t u_arg2 = UNSIGNED(arg2, df);
547 /* unsigned shift */
548 return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1);
549 }
550
551 static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2)
552 {
553 /* signed shift */
554 return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1);
555 }
556
557 static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
558 {
559 uint64_t u_arg1 = UNSIGNED(arg1, df);
560 uint64_t u_arg2 = UNSIGNED(arg2, df);
561 /* unsigned shift */
562 return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1);
563 }
564
565 static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
566 {
567 int64_t max_int = DF_MAX_INT(df);
568 int64_t min_int = DF_MIN_INT(df);
569 if (arg2 > 0) {
570 return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int;
571 } else {
572 return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int;
573 }
574 }
575
576 static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2)
577 {
578 uint64_t u_arg1 = UNSIGNED(arg1, df);
579 uint64_t u_arg2 = UNSIGNED(arg2, df);
580 return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0;
581 }
582
583 static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2)
584 {
585 uint64_t u_arg1 = UNSIGNED(arg1, df);
586 uint64_t max_uint = DF_MAX_UINT(df);
587 if (arg2 >= 0) {
588 uint64_t u_arg2 = (uint64_t)arg2;
589 return (u_arg1 > u_arg2) ?
590 (int64_t)(u_arg1 - u_arg2) :
591 0;
592 } else {
593 uint64_t u_arg2 = (uint64_t)(-arg2);
594 return (u_arg1 < max_uint - u_arg2) ?
595 (int64_t)(u_arg1 + u_arg2) :
596 (int64_t)max_uint;
597 }
598 }
599
600 static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
601 {
602 uint64_t u_arg1 = UNSIGNED(arg1, df);
603 uint64_t u_arg2 = UNSIGNED(arg2, df);
604 int64_t max_int = DF_MAX_INT(df);
605 int64_t min_int = DF_MIN_INT(df);
606 if (u_arg1 > u_arg2) {
607 return u_arg1 - u_arg2 < (uint64_t)max_int ?
608 (int64_t)(u_arg1 - u_arg2) :
609 max_int;
610 } else {
611 return u_arg2 - u_arg1 < (uint64_t)(-min_int) ?
612 (int64_t)(u_arg1 - u_arg2) :
613 min_int;
614 }
615 }
616
617 static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
618 {
619 /* signed compare */
620 return (arg1 < arg2) ?
621 (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
622 }
623
624 static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
625 {
626 uint64_t u_arg1 = UNSIGNED(arg1, df);
627 uint64_t u_arg2 = UNSIGNED(arg2, df);
628 /* unsigned compare */
629 return (u_arg1 < u_arg2) ?
630 (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
631 }
632
633 static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
634 {
635 return arg1 * arg2;
636 }
637
638 static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2)
639 {
640 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
641 return DF_MIN_INT(df);
642 }
643 return arg2 ? arg1 / arg2 : 0;
644 }
645
646 static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2)
647 {
648 uint64_t u_arg1 = UNSIGNED(arg1, df);
649 uint64_t u_arg2 = UNSIGNED(arg2, df);
650 return u_arg2 ? u_arg1 / u_arg2 : 0;
651 }
652
653 static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2)
654 {
655 if (arg1 == DF_MIN_INT(df) && arg2 == -1) {
656 return 0;
657 }
658 return arg2 ? arg1 % arg2 : 0;
659 }
660
661 static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2)
662 {
663 uint64_t u_arg1 = UNSIGNED(arg1, df);
664 uint64_t u_arg2 = UNSIGNED(arg2, df);
665 return u_arg2 ? u_arg1 % u_arg2 : 0;
666 }
667
668 #define SIGNED_EVEN(a, df) \
669 ((((int64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
670
671 #define UNSIGNED_EVEN(a, df) \
672 ((((uint64_t)(a)) << (64 - DF_BITS(df)/2)) >> (64 - DF_BITS(df)/2))
673
674 #define SIGNED_ODD(a, df) \
675 ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
676
677 #define UNSIGNED_ODD(a, df) \
678 ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)/2))
679
680 #define SIGNED_EXTRACT(e, o, a, df) \
681 do { \
682 e = SIGNED_EVEN(a, df); \
683 o = SIGNED_ODD(a, df); \
684 } while (0);
685
686 #define UNSIGNED_EXTRACT(e, o, a, df) \
687 do { \
688 e = UNSIGNED_EVEN(a, df); \
689 o = UNSIGNED_ODD(a, df); \
690 } while (0);
691
692 static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2)
693 {
694 int64_t even_arg1;
695 int64_t even_arg2;
696 int64_t odd_arg1;
697 int64_t odd_arg2;
698 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
699 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
700 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
701 }
702
703 static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2)
704 {
705 int64_t even_arg1;
706 int64_t even_arg2;
707 int64_t odd_arg1;
708 int64_t odd_arg2;
709 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
710 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
711 return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
712 }
713
714 #define CONCATENATE_AND_SLIDE(s, k) \
715 do { \
716 for (i = 0; i < s; i++) { \
717 v[i] = pws->b[s * k + i]; \
718 v[i + s] = pwd->b[s * k + i]; \
719 } \
720 for (i = 0; i < s; i++) { \
721 pwd->b[s * k + i] = v[i + n]; \
722 } \
723 } while (0)
724
725 static inline void msa_sld_df(uint32_t df, wr_t *pwd,
726 wr_t *pws, target_ulong rt)
727 {
728 uint32_t n = rt % DF_ELEMENTS(df);
729 uint8_t v[64];
730 uint32_t i, k;
731
732 switch (df) {
733 case DF_BYTE:
734 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0);
735 break;
736 case DF_HALF:
737 for (k = 0; k < 2; k++) {
738 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k);
739 }
740 break;
741 case DF_WORD:
742 for (k = 0; k < 4; k++) {
743 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k);
744 }
745 break;
746 case DF_DOUBLE:
747 for (k = 0; k < 8; k++) {
748 CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k);
749 }
750 break;
751 default:
752 assert(0);
753 }
754 }
755
756 static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
757 {
758 return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
759 }
760
761 static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
762 {
763 return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
764 }
765
766 static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
767 {
768 return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
769 }
770
771 static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
772 {
773 return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
774 }
775
776 static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
777 {
778 int64_t q_min = DF_MIN_INT(df);
779 int64_t q_max = DF_MAX_INT(df);
780
781 if (arg1 == q_min && arg2 == q_min) {
782 return q_max;
783 }
784 return (arg1 * arg2) >> (DF_BITS(df) - 1);
785 }
786
787 static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2)
788 {
789 int64_t q_min = DF_MIN_INT(df);
790 int64_t q_max = DF_MAX_INT(df);
791 int64_t r_bit = 1 << (DF_BITS(df) - 2);
792
793 if (arg1 == q_min && arg2 == q_min) {
794 return q_max;
795 }
796 return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1);
797 }
798
799 #define MSA_BINOP_DF(func) \
800 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
801 uint32_t wd, uint32_t ws, uint32_t wt) \
802 { \
803 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
804 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
805 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
806 uint32_t i; \
807 \
808 switch (df) { \
809 case DF_BYTE: \
810 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
811 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], pwt->b[i]); \
812 } \
813 break; \
814 case DF_HALF: \
815 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
816 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], pwt->h[i]); \
817 } \
818 break; \
819 case DF_WORD: \
820 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
821 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], pwt->w[i]); \
822 } \
823 break; \
824 case DF_DOUBLE: \
825 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
826 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], pwt->d[i]); \
827 } \
828 break; \
829 default: \
830 assert(0); \
831 } \
832 }
833
834 MSA_BINOP_DF(sll)
835 MSA_BINOP_DF(sra)
836 MSA_BINOP_DF(srl)
837 MSA_BINOP_DF(bclr)
838 MSA_BINOP_DF(bset)
839 MSA_BINOP_DF(bneg)
840 MSA_BINOP_DF(addv)
841 MSA_BINOP_DF(subv)
842 MSA_BINOP_DF(max_s)
843 MSA_BINOP_DF(max_u)
844 MSA_BINOP_DF(min_s)
845 MSA_BINOP_DF(min_u)
846 MSA_BINOP_DF(max_a)
847 MSA_BINOP_DF(min_a)
848 MSA_BINOP_DF(ceq)
849 MSA_BINOP_DF(clt_s)
850 MSA_BINOP_DF(clt_u)
851 MSA_BINOP_DF(cle_s)
852 MSA_BINOP_DF(cle_u)
853 MSA_BINOP_DF(add_a)
854 MSA_BINOP_DF(adds_a)
855 MSA_BINOP_DF(adds_s)
856 MSA_BINOP_DF(adds_u)
857 MSA_BINOP_DF(ave_s)
858 MSA_BINOP_DF(ave_u)
859 MSA_BINOP_DF(aver_s)
860 MSA_BINOP_DF(aver_u)
861 MSA_BINOP_DF(subs_s)
862 MSA_BINOP_DF(subs_u)
863 MSA_BINOP_DF(subsus_u)
864 MSA_BINOP_DF(subsuu_s)
865 MSA_BINOP_DF(asub_s)
866 MSA_BINOP_DF(asub_u)
867 MSA_BINOP_DF(mulv)
868 MSA_BINOP_DF(div_s)
869 MSA_BINOP_DF(div_u)
870 MSA_BINOP_DF(mod_s)
871 MSA_BINOP_DF(mod_u)
872 MSA_BINOP_DF(dotp_s)
873 MSA_BINOP_DF(dotp_u)
874 MSA_BINOP_DF(srar)
875 MSA_BINOP_DF(srlr)
876 MSA_BINOP_DF(hadd_s)
877 MSA_BINOP_DF(hadd_u)
878 MSA_BINOP_DF(hsub_s)
879 MSA_BINOP_DF(hsub_u)
880
881 MSA_BINOP_DF(mul_q)
882 MSA_BINOP_DF(mulr_q)
883 #undef MSA_BINOP_DF
884
885 void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
886 uint32_t ws, uint32_t rt)
887 {
888 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
889 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
890
891 msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]);
892 }
893
894 static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1,
895 int64_t arg2)
896 {
897 return dest + arg1 * arg2;
898 }
899
900 static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1,
901 int64_t arg2)
902 {
903 return dest - arg1 * arg2;
904 }
905
906 static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1,
907 int64_t arg2)
908 {
909 int64_t even_arg1;
910 int64_t even_arg2;
911 int64_t odd_arg1;
912 int64_t odd_arg2;
913 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
914 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
915 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
916 }
917
918 static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1,
919 int64_t arg2)
920 {
921 int64_t even_arg1;
922 int64_t even_arg2;
923 int64_t odd_arg1;
924 int64_t odd_arg2;
925 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
926 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
927 return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2);
928 }
929
930 static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1,
931 int64_t arg2)
932 {
933 int64_t even_arg1;
934 int64_t even_arg2;
935 int64_t odd_arg1;
936 int64_t odd_arg2;
937 SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
938 SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
939 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
940 }
941
942 static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1,
943 int64_t arg2)
944 {
945 int64_t even_arg1;
946 int64_t even_arg2;
947 int64_t odd_arg1;
948 int64_t odd_arg2;
949 UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df);
950 UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df);
951 return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2));
952 }
953
954 static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1,
955 int64_t arg2)
956 {
957 int64_t q_prod, q_ret;
958
959 int64_t q_max = DF_MAX_INT(df);
960 int64_t q_min = DF_MIN_INT(df);
961
962 q_prod = arg1 * arg2;
963 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1);
964
965 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
966 }
967
968 static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1,
969 int64_t arg2)
970 {
971 int64_t q_prod, q_ret;
972
973 int64_t q_max = DF_MAX_INT(df);
974 int64_t q_min = DF_MIN_INT(df);
975
976 q_prod = arg1 * arg2;
977 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1);
978
979 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
980 }
981
982 static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1,
983 int64_t arg2)
984 {
985 int64_t q_prod, q_ret;
986
987 int64_t q_max = DF_MAX_INT(df);
988 int64_t q_min = DF_MIN_INT(df);
989 int64_t r_bit = 1 << (DF_BITS(df) - 2);
990
991 q_prod = arg1 * arg2;
992 q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1);
993
994 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
995 }
996
997 static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1,
998 int64_t arg2)
999 {
1000 int64_t q_prod, q_ret;
1001
1002 int64_t q_max = DF_MAX_INT(df);
1003 int64_t q_min = DF_MIN_INT(df);
1004 int64_t r_bit = 1 << (DF_BITS(df) - 2);
1005
1006 q_prod = arg1 * arg2;
1007 q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1);
1008
1009 return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret;
1010 }
1011
1012 #define MSA_TEROP_DF(func) \
1013 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1014 uint32_t ws, uint32_t wt) \
1015 { \
1016 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1017 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1018 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1019 uint32_t i; \
1020 \
1021 switch (df) { \
1022 case DF_BYTE: \
1023 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1024 pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
1025 pwt->b[i]); \
1026 } \
1027 break; \
1028 case DF_HALF: \
1029 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1030 pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
1031 pwt->h[i]); \
1032 } \
1033 break; \
1034 case DF_WORD: \
1035 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1036 pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
1037 pwt->w[i]); \
1038 } \
1039 break; \
1040 case DF_DOUBLE: \
1041 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1042 pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
1043 pwt->d[i]); \
1044 } \
1045 break; \
1046 default: \
1047 assert(0); \
1048 } \
1049 }
1050
1051 MSA_TEROP_DF(maddv)
1052 MSA_TEROP_DF(msubv)
1053 MSA_TEROP_DF(dpadd_s)
1054 MSA_TEROP_DF(dpadd_u)
1055 MSA_TEROP_DF(dpsub_s)
1056 MSA_TEROP_DF(dpsub_u)
1057 MSA_TEROP_DF(binsl)
1058 MSA_TEROP_DF(binsr)
1059 MSA_TEROP_DF(madd_q)
1060 MSA_TEROP_DF(msub_q)
1061 MSA_TEROP_DF(maddr_q)
1062 MSA_TEROP_DF(msubr_q)
1063 #undef MSA_TEROP_DF
1064
1065 static inline void msa_splat_df(uint32_t df, wr_t *pwd,
1066 wr_t *pws, target_ulong rt)
1067 {
1068 uint32_t n = rt % DF_ELEMENTS(df);
1069 uint32_t i;
1070
1071 switch (df) {
1072 case DF_BYTE:
1073 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1074 pwd->b[i] = pws->b[n];
1075 }
1076 break;
1077 case DF_HALF:
1078 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1079 pwd->h[i] = pws->h[n];
1080 }
1081 break;
1082 case DF_WORD:
1083 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1084 pwd->w[i] = pws->w[n];
1085 }
1086 break;
1087 case DF_DOUBLE:
1088 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1089 pwd->d[i] = pws->d[n];
1090 }
1091 break;
1092 default:
1093 assert(0);
1094 }
1095 }
1096
1097 void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1098 uint32_t ws, uint32_t rt)
1099 {
1100 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1101 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1102
1103 msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]);
1104 }
1105
1106 #define MSA_DO_B MSA_DO(b)
1107 #define MSA_DO_H MSA_DO(h)
1108 #define MSA_DO_W MSA_DO(w)
1109 #define MSA_DO_D MSA_DO(d)
1110
1111 #define MSA_LOOP_B MSA_LOOP(B)
1112 #define MSA_LOOP_H MSA_LOOP(H)
1113 #define MSA_LOOP_W MSA_LOOP(W)
1114 #define MSA_LOOP_D MSA_LOOP(D)
1115
1116 #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE)
1117 #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF)
1118 #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD)
1119 #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE)
1120
1121 #define MSA_LOOP(DF) \
1122 for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \
1123 MSA_DO_ ## DF \
1124 }
1125
1126 #define MSA_FN_DF(FUNC) \
1127 void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \
1128 uint32_t ws, uint32_t wt) \
1129 { \
1130 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1131 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1132 wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
1133 wr_t wx, *pwx = &wx; \
1134 uint32_t i; \
1135 switch (df) { \
1136 case DF_BYTE: \
1137 MSA_LOOP_B \
1138 break; \
1139 case DF_HALF: \
1140 MSA_LOOP_H \
1141 break; \
1142 case DF_WORD: \
1143 MSA_LOOP_W \
1144 break; \
1145 case DF_DOUBLE: \
1146 MSA_LOOP_D \
1147 break; \
1148 default: \
1149 assert(0); \
1150 } \
1151 msa_move_v(pwd, pwx); \
1152 }
1153
1154 #define MSA_LOOP_COND(DF) \
1155 (DF_ELEMENTS(DF) / 2)
1156
1157 #define Rb(pwr, i) (pwr->b[i])
1158 #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE)/2])
1159 #define Rh(pwr, i) (pwr->h[i])
1160 #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF)/2])
1161 #define Rw(pwr, i) (pwr->w[i])
1162 #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD)/2])
1163 #define Rd(pwr, i) (pwr->d[i])
1164 #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE)/2])
1165
1166 #define MSA_DO(DF) \
1167 do { \
1168 R##DF(pwx, i) = pwt->DF[2*i]; \
1169 L##DF(pwx, i) = pws->DF[2*i]; \
1170 } while (0);
1171 MSA_FN_DF(pckev_df)
1172 #undef MSA_DO
1173
1174 #define MSA_DO(DF) \
1175 do { \
1176 R##DF(pwx, i) = pwt->DF[2*i+1]; \
1177 L##DF(pwx, i) = pws->DF[2*i+1]; \
1178 } while (0);
1179 MSA_FN_DF(pckod_df)
1180 #undef MSA_DO
1181
1182 #define MSA_DO(DF) \
1183 do { \
1184 pwx->DF[2*i] = L##DF(pwt, i); \
1185 pwx->DF[2*i+1] = L##DF(pws, i); \
1186 } while (0);
1187 MSA_FN_DF(ilvl_df)
1188 #undef MSA_DO
1189
1190 #define MSA_DO(DF) \
1191 do { \
1192 pwx->DF[2*i] = R##DF(pwt, i); \
1193 pwx->DF[2*i+1] = R##DF(pws, i); \
1194 } while (0);
1195 MSA_FN_DF(ilvr_df)
1196 #undef MSA_DO
1197
1198 #define MSA_DO(DF) \
1199 do { \
1200 pwx->DF[2*i] = pwt->DF[2*i]; \
1201 pwx->DF[2*i+1] = pws->DF[2*i]; \
1202 } while (0);
1203 MSA_FN_DF(ilvev_df)
1204 #undef MSA_DO
1205
1206 #define MSA_DO(DF) \
1207 do { \
1208 pwx->DF[2*i] = pwt->DF[2*i+1]; \
1209 pwx->DF[2*i+1] = pws->DF[2*i+1]; \
1210 } while (0);
1211 MSA_FN_DF(ilvod_df)
1212 #undef MSA_DO
1213 #undef MSA_LOOP_COND
1214
1215 #define MSA_LOOP_COND(DF) \
1216 (DF_ELEMENTS(DF))
1217
1218 #define MSA_DO(DF) \
1219 do { \
1220 uint32_t n = DF_ELEMENTS(df); \
1221 uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \
1222 pwx->DF[i] = \
1223 (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \
1224 } while (0);
1225 MSA_FN_DF(vshf_df)
1226 #undef MSA_DO
1227 #undef MSA_LOOP_COND
1228 #undef MSA_FN_DF
1229
1230 void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1231 uint32_t ws, uint32_t n)
1232 {
1233 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1234 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1235
1236 msa_sld_df(df, pwd, pws, n);
1237 }
1238
1239 void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1240 uint32_t ws, uint32_t n)
1241 {
1242 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1243 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1244
1245 msa_splat_df(df, pwd, pws, n);
1246 }
1247
1248 void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1249 uint32_t ws, uint32_t n)
1250 {
1251 n %= DF_ELEMENTS(df);
1252
1253 switch (df) {
1254 case DF_BYTE:
1255 env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
1256 break;
1257 case DF_HALF:
1258 env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
1259 break;
1260 case DF_WORD:
1261 env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
1262 break;
1263 #ifdef TARGET_MIPS64
1264 case DF_DOUBLE:
1265 env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
1266 break;
1267 #endif
1268 default:
1269 assert(0);
1270 }
1271 }
1272
1273 void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
1274 uint32_t ws, uint32_t n)
1275 {
1276 n %= DF_ELEMENTS(df);
1277
1278 switch (df) {
1279 case DF_BYTE:
1280 env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n];
1281 break;
1282 case DF_HALF:
1283 env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n];
1284 break;
1285 case DF_WORD:
1286 env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n];
1287 break;
1288 #ifdef TARGET_MIPS64
1289 case DF_DOUBLE:
1290 env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n];
1291 break;
1292 #endif
1293 default:
1294 assert(0);
1295 }
1296 }
1297
1298 void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1299 uint32_t rs_num, uint32_t n)
1300 {
1301 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1302 target_ulong rs = env->active_tc.gpr[rs_num];
1303
1304 switch (df) {
1305 case DF_BYTE:
1306 pwd->b[n] = (int8_t)rs;
1307 break;
1308 case DF_HALF:
1309 pwd->h[n] = (int16_t)rs;
1310 break;
1311 case DF_WORD:
1312 pwd->w[n] = (int32_t)rs;
1313 break;
1314 case DF_DOUBLE:
1315 pwd->d[n] = (int64_t)rs;
1316 break;
1317 default:
1318 assert(0);
1319 }
1320 }
1321
1322 void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1323 uint32_t ws, uint32_t n)
1324 {
1325 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1326 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1327
1328 switch (df) {
1329 case DF_BYTE:
1330 pwd->b[n] = (int8_t)pws->b[0];
1331 break;
1332 case DF_HALF:
1333 pwd->h[n] = (int16_t)pws->h[0];
1334 break;
1335 case DF_WORD:
1336 pwd->w[n] = (int32_t)pws->w[0];
1337 break;
1338 case DF_DOUBLE:
1339 pwd->d[n] = (int64_t)pws->d[0];
1340 break;
1341 default:
1342 assert(0);
1343 }
1344 }
1345
1346 void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd)
1347 {
1348 switch (cd) {
1349 case 0:
1350 break;
1351 case 1:
1352 env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK;
1353 restore_msa_fp_status(env);
1354 /* check exception */
1355 if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)
1356 & GET_FP_CAUSE(env->active_tc.msacsr)) {
1357 do_raise_exception(env, EXCP_MSAFPE, GETPC());
1358 }
1359 break;
1360 }
1361 }
1362
1363 target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs)
1364 {
1365 switch (cs) {
1366 case 0:
1367 return env->msair;
1368 case 1:
1369 return env->active_tc.msacsr & MSACSR_MASK;
1370 }
1371 return 0;
1372 }
1373
1374 void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
1375 {
1376 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1377 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
1378
1379 msa_move_v(pwd, pws);
1380 }
1381
1382 static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
1383 {
1384 uint64_t x;
1385
1386 x = UNSIGNED(arg, df);
1387
1388 x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
1389 x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
1390 x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
1391 x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
1392 x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
1393 x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
1394
1395 return x;
1396 }
1397
1398 static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
1399 {
1400 uint64_t x, y;
1401 int n, c;
1402
1403 x = UNSIGNED(arg, df);
1404 n = DF_BITS(df);
1405 c = DF_BITS(df) / 2;
1406
1407 do {
1408 y = x >> c;
1409 if (y != 0) {
1410 n = n - c;
1411 x = y;
1412 }
1413 c = c >> 1;
1414 } while (c != 0);
1415
1416 return n - x;
1417 }
1418
1419 static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
1420 {
1421 return msa_nlzc_df(df, UNSIGNED((~arg), df));
1422 }
1423
1424 void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
1425 uint32_t rs)
1426 {
1427 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
1428 uint32_t i;
1429
1430 switch (df) {
1431 case DF_BYTE:
1432 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
1433 pwd->b[i] = (int8_t)env->active_tc.gpr[rs];
1434 }
1435 break;
1436 case DF_HALF:
1437 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
1438 pwd->h[i] = (int16_t)env->active_tc.gpr[rs];
1439 }
1440 break;
1441 case DF_WORD:
1442 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1443 pwd->w[i] = (int32_t)env->active_tc.gpr[rs];
1444 }
1445 break;
1446 case DF_DOUBLE:
1447 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1448 pwd->d[i] = (int64_t)env->active_tc.gpr[rs];
1449 }
1450 break;
1451 default:
1452 assert(0);
1453 }
1454 }
1455
1456 #define MSA_UNOP_DF(func) \
1457 void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
1458 uint32_t wd, uint32_t ws) \
1459 { \
1460 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
1461 wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
1462 uint32_t i; \
1463 \
1464 switch (df) { \
1465 case DF_BYTE: \
1466 for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
1467 pwd->b[i] = msa_ ## func ## _df(df, pws->b[i]); \
1468 } \
1469 break; \
1470 case DF_HALF: \
1471 for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
1472 pwd->h[i] = msa_ ## func ## _df(df, pws->h[i]); \
1473 } \
1474 break; \
1475 case DF_WORD: \
1476 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
1477 pwd->w[i] = msa_ ## func ## _df(df, pws->w[i]); \
1478 } \
1479 break; \
1480 case DF_DOUBLE: \
1481 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
1482 pwd->d[i] = msa_ ## func ## _df(df, pws->d[i]); \
1483 } \
1484 break; \
1485 default: \
1486 assert(0); \
1487 } \
1488 }
1489
1490 MSA_UNOP_DF(nlzc)
1491 MSA_UNOP_DF(nloc)
1492 MSA_UNOP_DF(pcnt)
1493 #undef MSA_UNOP_DF
1494
1495 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1496 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1497
1498 #define FLOAT_SNAN16 (float16_default_nan ^ 0x0220)
1499 /* 0x7c20 */
1500 #define FLOAT_SNAN32 (float32_default_nan ^ 0x00400020)
1501 /* 0x7f800020 */
1502 #define FLOAT_SNAN64 (float64_default_nan ^ 0x0008000000000020ULL)
1503 /* 0x7ff0000000000020 */
1504
1505 static inline void clear_msacsr_cause(CPUMIPSState *env)
1506 {
1507 SET_FP_CAUSE(env->active_tc.msacsr, 0);
1508 }
1509
1510 static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
1511 {
1512 if ((GET_FP_CAUSE(env->active_tc.msacsr) &
1513 (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) {
1514 UPDATE_FP_FLAGS(env->active_tc.msacsr,
1515 GET_FP_CAUSE(env->active_tc.msacsr));
1516 } else {
1517 do_raise_exception(env, EXCP_MSAFPE, retaddr);
1518 }
1519 }
1520
1521 /* Flush-to-zero use cases for update_msacsr() */
1522 #define CLEAR_FS_UNDERFLOW 1
1523 #define CLEAR_IS_INEXACT 2
1524 #define RECIPROCAL_INEXACT 4
1525
1526 static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
1527 {
1528 int ieee_ex;
1529
1530 int c;
1531 int cause;
1532 int enable;
1533
1534 ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
1535
1536 /* QEMU softfloat does not signal all underflow cases */
1537 if (denormal) {
1538 ieee_ex |= float_flag_underflow;
1539 }
1540
1541 c = ieee_ex_to_mips(ieee_ex);
1542 enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1543
1544 /* Set Inexact (I) when flushing inputs to zero */
1545 if ((ieee_ex & float_flag_input_denormal) &&
1546 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1547 if (action & CLEAR_IS_INEXACT) {
1548 c &= ~FP_INEXACT;
1549 } else {
1550 c |= FP_INEXACT;
1551 }
1552 }
1553
1554 /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
1555 if ((ieee_ex & float_flag_output_denormal) &&
1556 (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
1557 c |= FP_INEXACT;
1558 if (action & CLEAR_FS_UNDERFLOW) {
1559 c &= ~FP_UNDERFLOW;
1560 } else {
1561 c |= FP_UNDERFLOW;
1562 }
1563 }
1564
1565 /* Set Inexact (I) when Overflow (O) is not enabled */
1566 if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
1567 c |= FP_INEXACT;
1568 }
1569
1570 /* Clear Exact Underflow when Underflow (U) is not enabled */
1571 if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
1572 (c & FP_INEXACT) == 0) {
1573 c &= ~FP_UNDERFLOW;
1574 }
1575
1576 /* Reciprocal operations set only Inexact when valid and not
1577 divide by zero */
1578 if ((action & RECIPROCAL_INEXACT) &&
1579 (c & (FP_INVALID | FP_DIV0)) == 0) {
1580 c = FP_INEXACT;
1581 }
1582
1583 cause = c & enable; /* all current enabled exceptions */
1584
1585 if (cause == 0) {
1586 /* No enabled exception, update the MSACSR Cause
1587 with all current exceptions */
1588 SET_FP_CAUSE(env->active_tc.msacsr,
1589 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1590 } else {
1591 /* Current exceptions are enabled */
1592 if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
1593 /* Exception(s) will trap, update MSACSR Cause
1594 with all enabled exceptions */
1595 SET_FP_CAUSE(env->active_tc.msacsr,
1596 (GET_FP_CAUSE(env->active_tc.msacsr) | c));
1597 }
1598 }
1599
1600 return c;
1601 }
1602
1603 static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
1604 {
1605 int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
1606 return c & enable;
1607 }
1608
1609 static inline float16 float16_from_float32(int32_t a, flag ieee,
1610 float_status *status)
1611 {
1612 float16 f_val;
1613
1614 f_val = float32_to_float16((float32)a, ieee, status);
1615 f_val = float16_maybe_silence_nan(f_val);
1616
1617 return a < 0 ? (f_val | (1 << 15)) : f_val;
1618 }
1619
1620 static inline float32 float32_from_float64(int64_t a, float_status *status)
1621 {
1622 float32 f_val;
1623
1624 f_val = float64_to_float32((float64)a, status);
1625 f_val = float32_maybe_silence_nan(f_val);
1626
1627 return a < 0 ? (f_val | (1 << 31)) : f_val;
1628 }
1629
1630 static inline float32 float32_from_float16(int16_t a, flag ieee,
1631 float_status *status)
1632 {
1633 float32 f_val;
1634
1635 f_val = float16_to_float32((float16)a, ieee, status);
1636 f_val = float32_maybe_silence_nan(f_val);
1637
1638 return a < 0 ? (f_val | (1 << 31)) : f_val;
1639 }
1640
1641 static inline float64 float64_from_float32(int32_t a, float_status *status)
1642 {
1643 float64 f_val;
1644
1645 f_val = float32_to_float64((float64)a, status);
1646 f_val = float64_maybe_silence_nan(f_val);
1647
1648 return a < 0 ? (f_val | (1ULL << 63)) : f_val;
1649 }
1650
1651 static inline float32 float32_from_q16(int16_t a, float_status *status)
1652 {
1653 float32 f_val;
1654
1655 /* conversion as integer and scaling */
1656 f_val = int32_to_float32(a, status);
1657 f_val = float32_scalbn(f_val, -15, status);
1658
1659 return f_val;
1660 }
1661
1662 static inline float64 float64_from_q32(int32_t a, float_status *status)
1663 {
1664 float64 f_val;
1665
1666 /* conversion as integer and scaling */
1667 f_val = int32_to_float64(a, status);
1668 f_val = float64_scalbn(f_val, -31, status);
1669
1670 return f_val;
1671 }
1672
1673 static inline int16_t float32_to_q16(float32 a, float_status *status)
1674 {
1675 int32_t q_val;
1676 int32_t q_min = 0xffff8000;
1677 int32_t q_max = 0x00007fff;
1678
1679 int ieee_ex;
1680
1681 if (float32_is_any_nan(a)) {
1682 float_raise(float_flag_invalid, status);
1683 return 0;
1684 }
1685
1686 /* scaling */
1687 a = float32_scalbn(a, 15, status);
1688
1689 ieee_ex = get_float_exception_flags(status);
1690 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1691 , status);
1692
1693 if (ieee_ex & float_flag_overflow) {
1694 float_raise(float_flag_inexact, status);
1695 return (int32_t)a < 0 ? q_min : q_max;
1696 }
1697
1698 /* conversion to int */
1699 q_val = float32_to_int32(a, status);
1700
1701 ieee_ex = get_float_exception_flags(status);
1702 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1703 , status);
1704
1705 if (ieee_ex & float_flag_invalid) {
1706 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1707 , status);
1708 float_raise(float_flag_overflow | float_flag_inexact, status);
1709 return (int32_t)a < 0 ? q_min : q_max;
1710 }
1711
1712 if (q_val < q_min) {
1713 float_raise(float_flag_overflow | float_flag_inexact, status);
1714 return (int16_t)q_min;
1715 }
1716
1717 if (q_max < q_val) {
1718 float_raise(float_flag_overflow | float_flag_inexact, status);
1719 return (int16_t)q_max;
1720 }
1721
1722 return (int16_t)q_val;
1723 }
1724
1725 static inline int32_t float64_to_q32(float64 a, float_status *status)
1726 {
1727 int64_t q_val;
1728 int64_t q_min = 0xffffffff80000000LL;
1729 int64_t q_max = 0x000000007fffffffLL;
1730
1731 int ieee_ex;
1732
1733 if (float64_is_any_nan(a)) {
1734 float_raise(float_flag_invalid, status);
1735 return 0;
1736 }
1737
1738 /* scaling */
1739 a = float64_scalbn(a, 31, status);
1740
1741 ieee_ex = get_float_exception_flags(status);
1742 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1743 , status);
1744
1745 if (ieee_ex & float_flag_overflow) {
1746 float_raise(float_flag_inexact, status);
1747 return (int64_t)a < 0 ? q_min : q_max;
1748 }
1749
1750 /* conversion to integer */
1751 q_val = float64_to_int64(a, status);
1752
1753 ieee_ex = get_float_exception_flags(status);
1754 set_float_exception_flags(ieee_ex & (~float_flag_underflow)
1755 , status);
1756
1757 if (ieee_ex & float_flag_invalid) {
1758 set_float_exception_flags(ieee_ex & (~float_flag_invalid)
1759 , status);
1760 float_raise(float_flag_overflow | float_flag_inexact, status);
1761 return (int64_t)a < 0 ? q_min : q_max;
1762 }
1763
1764 if (q_val < q_min) {
1765 float_raise(float_flag_overflow | float_flag_inexact, status);
1766 return (int32_t)q_min;
1767 }
1768
1769 if (q_max < q_val) {
1770 float_raise(float_flag_overflow | float_flag_inexact, status);
1771 return (int32_t)q_max;
1772 }
1773
1774 return (int32_t)q_val;
1775 }
1776
1777 #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \
1778 do { \
1779 float_status *status = &env->active_tc.msa_fp_status; \
1780 int c; \
1781 int64_t cond; \
1782 set_float_exception_flags(0, status); \
1783 if (!QUIET) { \
1784 cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
1785 } else { \
1786 cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \
1787 } \
1788 DEST = cond ? M_MAX_UINT(BITS) : 0; \
1789 c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \
1790 \
1791 if (get_enabled_exceptions(env, c)) { \
1792 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
1793 } \
1794 } while (0)
1795
1796 #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \
1797 do { \
1798 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1799 if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \
1800 DEST = 0; \
1801 } \
1802 } while (0)
1803
1804 #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \
1805 do { \
1806 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1807 if (DEST == 0) { \
1808 MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \
1809 } \
1810 } while (0)
1811
1812 #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \
1813 do { \
1814 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1815 if (DEST == 0) { \
1816 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1817 } \
1818 } while (0)
1819
1820 #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \
1821 do { \
1822 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1823 if (DEST == 0) { \
1824 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1825 if (DEST == 0) { \
1826 MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \
1827 } \
1828 } \
1829 } while (0)
1830
1831 #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \
1832 do { \
1833 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1834 if (DEST == 0) { \
1835 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1836 } \
1837 } while (0)
1838
1839 #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \
1840 do { \
1841 MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \
1842 if (DEST == 0) { \
1843 MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \
1844 } \
1845 } while (0)
1846
1847 #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \
1848 do { \
1849 MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \
1850 if (DEST == 0) { \
1851 MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \
1852 } \
1853 } while (0)
1854
1855 static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1856 wr_t *pwt, uint32_t df, int quiet,
1857 uintptr_t retaddr)
1858 {
1859 wr_t wx, *pwx = &wx;
1860 uint32_t i;
1861
1862 clear_msacsr_cause(env);
1863
1864 switch (df) {
1865 case DF_WORD:
1866 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1867 MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1868 }
1869 break;
1870 case DF_DOUBLE:
1871 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1872 MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1873 }
1874 break;
1875 default:
1876 assert(0);
1877 }
1878
1879 check_msacsr_cause(env, retaddr);
1880
1881 msa_move_v(pwd, pwx);
1882 }
1883
1884 static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1885 wr_t *pwt, uint32_t df, int quiet,
1886 uintptr_t retaddr)
1887 {
1888 wr_t wx, *pwx = &wx;
1889 uint32_t i;
1890
1891 clear_msacsr_cause(env);
1892
1893 switch (df) {
1894 case DF_WORD:
1895 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1896 MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32,
1897 quiet);
1898 }
1899 break;
1900 case DF_DOUBLE:
1901 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1902 MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64,
1903 quiet);
1904 }
1905 break;
1906 default:
1907 assert(0);
1908 }
1909
1910 check_msacsr_cause(env, retaddr);
1911
1912 msa_move_v(pwd, pwx);
1913 }
1914
1915 static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1916 wr_t *pwt, uint32_t df, int quiet,
1917 uintptr_t retaddr)
1918 {
1919 wr_t wx, *pwx = &wx;
1920 uint32_t i;
1921
1922 clear_msacsr_cause(env);
1923
1924 switch (df) {
1925 case DF_WORD:
1926 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1927 MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet);
1928 }
1929 break;
1930 case DF_DOUBLE:
1931 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1932 MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet);
1933 }
1934 break;
1935 default:
1936 assert(0);
1937 }
1938
1939 check_msacsr_cause(env, retaddr);
1940
1941 msa_move_v(pwd, pwx);
1942 }
1943
1944 static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1945 wr_t *pwt, uint32_t df, int quiet,
1946 uintptr_t retaddr)
1947 {
1948 wr_t wx, *pwx = &wx;
1949 uint32_t i;
1950
1951 clear_msacsr_cause(env);
1952
1953 switch (df) {
1954 case DF_WORD:
1955 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1956 MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
1957 }
1958 break;
1959 case DF_DOUBLE:
1960 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1961 MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
1962 }
1963 break;
1964 default:
1965 assert(0);
1966 }
1967
1968 check_msacsr_cause(env, retaddr);
1969
1970 msa_move_v(pwd, pwx);
1971 }
1972
1973 static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
1974 wr_t *pwt, uint32_t df, int quiet,
1975 uintptr_t retaddr)
1976 {
1977 wr_t wx, *pwx = &wx;
1978 uint32_t i;
1979
1980 clear_msacsr_cause(env);
1981
1982 switch (df) {
1983 case DF_WORD:
1984 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
1985 MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet);
1986 }
1987 break;
1988 case DF_DOUBLE:
1989 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
1990 MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet);
1991 }
1992 break;
1993 default:
1994 assert(0);
1995 }
1996
1997 check_msacsr_cause(env, retaddr);
1998
1999 msa_move_v(pwd, pwx);
2000 }
2001
2002 static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2003 wr_t *pwt, uint32_t df, int quiet,
2004 uintptr_t retaddr)
2005 {
2006 wr_t wx, *pwx = &wx;
2007 uint32_t i;
2008
2009 clear_msacsr_cause(env);
2010
2011 switch (df) {
2012 case DF_WORD:
2013 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2014 MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2015 }
2016 break;
2017 case DF_DOUBLE:
2018 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2019 MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2020 }
2021 break;
2022 default:
2023 assert(0);
2024 }
2025
2026 check_msacsr_cause(env, retaddr);
2027
2028 msa_move_v(pwd, pwx);
2029 }
2030
2031 static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2032 wr_t *pwt, uint32_t df, int quiet,
2033 uintptr_t retaddr)
2034 {
2035 wr_t wx, *pwx = &wx;
2036 uint32_t i;
2037
2038 clear_msacsr_cause(env);
2039
2040 switch (df) {
2041 case DF_WORD:
2042 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2043 MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet);
2044 }
2045 break;
2046 case DF_DOUBLE:
2047 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2048 MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet);
2049 }
2050 break;
2051 default:
2052 assert(0);
2053 }
2054
2055 check_msacsr_cause(env, retaddr);
2056
2057 msa_move_v(pwd, pwx);
2058 }
2059
2060 static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2061 wr_t *pwt, uint32_t df, int quiet,
2062 uintptr_t retaddr)
2063 {
2064 wr_t wx, *pwx = &wx;
2065 uint32_t i;
2066
2067 clear_msacsr_cause(env);
2068
2069 switch (df) {
2070 case DF_WORD:
2071 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2072 MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2073 }
2074 break;
2075 case DF_DOUBLE:
2076 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2077 MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2078 }
2079 break;
2080 default:
2081 assert(0);
2082 }
2083
2084 check_msacsr_cause(env, retaddr);
2085
2086 msa_move_v(pwd, pwx);
2087 }
2088
2089 static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2090 wr_t *pwt, uint32_t df, int quiet,
2091 uintptr_t retaddr)
2092 {
2093 wr_t wx, *pwx = &wx;
2094 uint32_t i;
2095
2096 clear_msacsr_cause(env);
2097
2098 switch (df) {
2099 case DF_WORD:
2100 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2101 MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2102 }
2103 break;
2104 case DF_DOUBLE:
2105 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2106 MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2107 }
2108 break;
2109 default:
2110 assert(0);
2111 }
2112
2113 check_msacsr_cause(env, retaddr);
2114
2115 msa_move_v(pwd, pwx);
2116 }
2117
2118 static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2119 wr_t *pwt, uint32_t df, int quiet,
2120 uintptr_t retaddr)
2121 {
2122 wr_t wx, *pwx = &wx;
2123 uint32_t i;
2124
2125 clear_msacsr_cause(env);
2126
2127 switch (df) {
2128 case DF_WORD:
2129 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2130 MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2131 }
2132 break;
2133 case DF_DOUBLE:
2134 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2135 MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2136 }
2137 break;
2138 default:
2139 assert(0);
2140 }
2141
2142 check_msacsr_cause(env, retaddr);
2143
2144 msa_move_v(pwd, pwx);
2145 }
2146
2147 static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws,
2148 wr_t *pwt, uint32_t df, int quiet,
2149 uintptr_t retaddr)
2150 {
2151 wr_t wx, *pwx = &wx;
2152 uint32_t i;
2153
2154 clear_msacsr_cause(env);
2155
2156 switch (df) {
2157 case DF_WORD:
2158 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2159 MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet);
2160 }
2161 break;
2162 case DF_DOUBLE:
2163 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2164 MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet);
2165 }
2166 break;
2167 default:
2168 assert(0);
2169 }
2170
2171 check_msacsr_cause(env, retaddr);
2172
2173 msa_move_v(pwd, pwx);
2174 }
2175
2176 void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2177 uint32_t ws, uint32_t wt)
2178 {
2179 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2180 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2181 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2182 compare_af(env, pwd, pws, pwt, df, 1, GETPC());
2183 }
2184
2185 void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2186 uint32_t ws, uint32_t wt)
2187 {
2188 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2189 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2190 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2191 compare_un(env, pwd, pws, pwt, df, 1, GETPC());
2192 }
2193
2194 void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2195 uint32_t ws, uint32_t wt)
2196 {
2197 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2198 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2199 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2200 compare_eq(env, pwd, pws, pwt, df, 1, GETPC());
2201 }
2202
2203 void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2204 uint32_t ws, uint32_t wt)
2205 {
2206 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2207 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2208 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2209 compare_ueq(env, pwd, pws, pwt, df, 1, GETPC());
2210 }
2211
2212 void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2213 uint32_t ws, uint32_t wt)
2214 {
2215 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2216 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2217 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2218 compare_lt(env, pwd, pws, pwt, df, 1, GETPC());
2219 }
2220
2221 void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2222 uint32_t ws, uint32_t wt)
2223 {
2224 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2225 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2226 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2227 compare_ult(env, pwd, pws, pwt, df, 1, GETPC());
2228 }
2229
2230 void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2231 uint32_t ws, uint32_t wt)
2232 {
2233 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2234 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2235 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2236 compare_le(env, pwd, pws, pwt, df, 1, GETPC());
2237 }
2238
2239 void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2240 uint32_t ws, uint32_t wt)
2241 {
2242 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2243 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2244 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2245 compare_ule(env, pwd, pws, pwt, df, 1, GETPC());
2246 }
2247
2248 void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2249 uint32_t ws, uint32_t wt)
2250 {
2251 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2252 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2253 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2254 compare_af(env, pwd, pws, pwt, df, 0, GETPC());
2255 }
2256
2257 void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2258 uint32_t ws, uint32_t wt)
2259 {
2260 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2261 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2262 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2263 compare_un(env, pwd, pws, pwt, df, 0, GETPC());
2264 }
2265
2266 void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2267 uint32_t ws, uint32_t wt)
2268 {
2269 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2270 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2271 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2272 compare_eq(env, pwd, pws, pwt, df, 0, GETPC());
2273 }
2274
2275 void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2276 uint32_t ws, uint32_t wt)
2277 {
2278 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2279 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2280 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2281 compare_ueq(env, pwd, pws, pwt, df, 0, GETPC());
2282 }
2283
2284 void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2285 uint32_t ws, uint32_t wt)
2286 {
2287 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2288 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2289 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2290 compare_lt(env, pwd, pws, pwt, df, 0, GETPC());
2291 }
2292
2293 void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2294 uint32_t ws, uint32_t wt)
2295 {
2296 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2297 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2298 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2299 compare_ult(env, pwd, pws, pwt, df, 0, GETPC());
2300 }
2301
2302 void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2303 uint32_t ws, uint32_t wt)
2304 {
2305 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2306 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2307 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2308 compare_le(env, pwd, pws, pwt, df, 0, GETPC());
2309 }
2310
2311 void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2312 uint32_t ws, uint32_t wt)
2313 {
2314 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2315 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2316 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2317 compare_ule(env, pwd, pws, pwt, df, 0, GETPC());
2318 }
2319
2320 void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2321 uint32_t ws, uint32_t wt)
2322 {
2323 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2324 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2325 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2326 compare_or(env, pwd, pws, pwt, df, 1, GETPC());
2327 }
2328
2329 void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2330 uint32_t ws, uint32_t wt)
2331 {
2332 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2333 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2334 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2335 compare_une(env, pwd, pws, pwt, df, 1, GETPC());
2336 }
2337
2338 void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2339 uint32_t ws, uint32_t wt)
2340 {
2341 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2342 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2343 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2344 compare_ne(env, pwd, pws, pwt, df, 1, GETPC());
2345 }
2346
2347 void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2348 uint32_t ws, uint32_t wt)
2349 {
2350 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2351 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2352 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2353 compare_or(env, pwd, pws, pwt, df, 0, GETPC());
2354 }
2355
2356 void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2357 uint32_t ws, uint32_t wt)
2358 {
2359 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2360 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2361 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2362 compare_une(env, pwd, pws, pwt, df, 0, GETPC());
2363 }
2364
2365 void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2366 uint32_t ws, uint32_t wt)
2367 {
2368 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2369 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2370 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2371 compare_ne(env, pwd, pws, pwt, df, 0, GETPC());
2372 }
2373
2374 #define float16_is_zero(ARG) 0
2375 #define float16_is_zero_or_denormal(ARG) 0
2376
2377 #define IS_DENORMAL(ARG, BITS) \
2378 (!float ## BITS ## _is_zero(ARG) \
2379 && float ## BITS ## _is_zero_or_denormal(ARG))
2380
2381 #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \
2382 do { \
2383 float_status *status = &env->active_tc.msa_fp_status; \
2384 int c; \
2385 \
2386 set_float_exception_flags(0, status); \
2387 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2388 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2389 \
2390 if (get_enabled_exceptions(env, c)) { \
2391 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2392 } \
2393 } while (0)
2394
2395 void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2396 uint32_t ws, uint32_t wt)
2397 {
2398 wr_t wx, *pwx = &wx;
2399 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2400 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2401 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2402 uint32_t i;
2403
2404 clear_msacsr_cause(env);
2405
2406 switch (df) {
2407 case DF_WORD:
2408 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2409 MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32);
2410 }
2411 break;
2412 case DF_DOUBLE:
2413 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2414 MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64);
2415 }
2416 break;
2417 default:
2418 assert(0);
2419 }
2420
2421 check_msacsr_cause(env, GETPC());
2422 msa_move_v(pwd, pwx);
2423 }
2424
2425 void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2426 uint32_t ws, uint32_t wt)
2427 {
2428 wr_t wx, *pwx = &wx;
2429 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2430 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2431 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2432 uint32_t i;
2433
2434 clear_msacsr_cause(env);
2435
2436 switch (df) {
2437 case DF_WORD:
2438 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2439 MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32);
2440 }
2441 break;
2442 case DF_DOUBLE:
2443 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2444 MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64);
2445 }
2446 break;
2447 default:
2448 assert(0);
2449 }
2450
2451 check_msacsr_cause(env, GETPC());
2452 msa_move_v(pwd, pwx);
2453 }
2454
2455 void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2456 uint32_t ws, uint32_t wt)
2457 {
2458 wr_t wx, *pwx = &wx;
2459 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2460 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2461 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2462 uint32_t i;
2463
2464 clear_msacsr_cause(env);
2465
2466 switch (df) {
2467 case DF_WORD:
2468 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2469 MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32);
2470 }
2471 break;
2472 case DF_DOUBLE:
2473 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2474 MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64);
2475 }
2476 break;
2477 default:
2478 assert(0);
2479 }
2480
2481 check_msacsr_cause(env, GETPC());
2482
2483 msa_move_v(pwd, pwx);
2484 }
2485
2486 void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2487 uint32_t ws, uint32_t wt)
2488 {
2489 wr_t wx, *pwx = &wx;
2490 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2491 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2492 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2493 uint32_t i;
2494
2495 clear_msacsr_cause(env);
2496
2497 switch (df) {
2498 case DF_WORD:
2499 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2500 MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32);
2501 }
2502 break;
2503 case DF_DOUBLE:
2504 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2505 MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64);
2506 }
2507 break;
2508 default:
2509 assert(0);
2510 }
2511
2512 check_msacsr_cause(env, GETPC());
2513
2514 msa_move_v(pwd, pwx);
2515 }
2516
2517 #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \
2518 do { \
2519 float_status *status = &env->active_tc.msa_fp_status; \
2520 int c; \
2521 \
2522 set_float_exception_flags(0, status); \
2523 DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \
2524 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2525 \
2526 if (get_enabled_exceptions(env, c)) { \
2527 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2528 } \
2529 } while (0)
2530
2531 void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2532 uint32_t ws, uint32_t wt)
2533 {
2534 wr_t wx, *pwx = &wx;
2535 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2536 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2537 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2538 uint32_t i;
2539
2540 clear_msacsr_cause(env);
2541
2542 switch (df) {
2543 case DF_WORD:
2544 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2545 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2546 pws->w[i], pwt->w[i], 0, 32);
2547 }
2548 break;
2549 case DF_DOUBLE:
2550 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2551 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2552 pws->d[i], pwt->d[i], 0, 64);
2553 }
2554 break;
2555 default:
2556 assert(0);
2557 }
2558
2559 check_msacsr_cause(env, GETPC());
2560
2561 msa_move_v(pwd, pwx);
2562 }
2563
2564 void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2565 uint32_t ws, uint32_t wt)
2566 {
2567 wr_t wx, *pwx = &wx;
2568 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2569 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2570 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2571 uint32_t i;
2572
2573 clear_msacsr_cause(env);
2574
2575 switch (df) {
2576 case DF_WORD:
2577 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2578 MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i],
2579 pws->w[i], pwt->w[i],
2580 float_muladd_negate_product, 32);
2581 }
2582 break;
2583 case DF_DOUBLE:
2584 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2585 MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i],
2586 pws->d[i], pwt->d[i],
2587 float_muladd_negate_product, 64);
2588 }
2589 break;
2590 default:
2591 assert(0);
2592 }
2593
2594 check_msacsr_cause(env, GETPC());
2595
2596 msa_move_v(pwd, pwx);
2597 }
2598
2599 void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2600 uint32_t ws, uint32_t wt)
2601 {
2602 wr_t wx, *pwx = &wx;
2603 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2604 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2605 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2606 uint32_t i;
2607
2608 clear_msacsr_cause(env);
2609
2610 switch (df) {
2611 case DF_WORD:
2612 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2613 MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i],
2614 pwt->w[i] > 0x200 ? 0x200 :
2615 pwt->w[i] < -0x200 ? -0x200 : pwt->w[i],
2616 32);
2617 }
2618 break;
2619 case DF_DOUBLE:
2620 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2621 MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i],
2622 pwt->d[i] > 0x1000 ? 0x1000 :
2623 pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i],
2624 64);
2625 }
2626 break;
2627 default:
2628 assert(0);
2629 }
2630
2631 check_msacsr_cause(env, GETPC());
2632
2633 msa_move_v(pwd, pwx);
2634 }
2635
2636 #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \
2637 do { \
2638 float_status *status = &env->active_tc.msa_fp_status; \
2639 int c; \
2640 \
2641 set_float_exception_flags(0, status); \
2642 DEST = float ## BITS ## _ ## OP(ARG, status); \
2643 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
2644 \
2645 if (get_enabled_exceptions(env, c)) { \
2646 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2647 } \
2648 } while (0)
2649
2650 void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2651 uint32_t ws, uint32_t wt)
2652 {
2653 wr_t wx, *pwx = &wx;
2654 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2655 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2656 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2657 uint32_t i;
2658
2659 clear_msacsr_cause(env);
2660
2661 switch (df) {
2662 case DF_WORD:
2663 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2664 /* Half precision floats come in two formats: standard
2665 IEEE and "ARM" format. The latter gains extra exponent
2666 range by omitting the NaN/Inf encodings. */
2667 flag ieee = 1;
2668
2669 MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16);
2670 MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16);
2671 }
2672 break;
2673 case DF_DOUBLE:
2674 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2675 MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32);
2676 MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32);
2677 }
2678 break;
2679 default:
2680 assert(0);
2681 }
2682
2683 check_msacsr_cause(env, GETPC());
2684 msa_move_v(pwd, pwx);
2685 }
2686
2687 #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \
2688 do { \
2689 float_status *status = &env->active_tc.msa_fp_status; \
2690 int c; \
2691 \
2692 set_float_exception_flags(0, status); \
2693 DEST = float ## BITS ## _ ## OP(ARG, status); \
2694 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2695 \
2696 if (get_enabled_exceptions(env, c)) { \
2697 DEST = ((FLOAT_SNAN ## XBITS >> 6) << 6) | c; \
2698 } \
2699 } while (0)
2700
2701 void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2702 uint32_t ws, uint32_t wt)
2703 {
2704 wr_t wx, *pwx = &wx;
2705 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2706 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2707 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2708 uint32_t i;
2709
2710 clear_msacsr_cause(env);
2711
2712 switch (df) {
2713 case DF_WORD:
2714 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2715 MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16);
2716 MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16);
2717 }
2718 break;
2719 case DF_DOUBLE:
2720 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2721 MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32);
2722 MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32);
2723 }
2724 break;
2725 default:
2726 assert(0);
2727 }
2728
2729 check_msacsr_cause(env, GETPC());
2730
2731 msa_move_v(pwd, pwx);
2732 }
2733
2734 #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS) \
2735 !float ## BITS ## _is_any_nan(ARG1) \
2736 && float ## BITS ## _is_quiet_nan(ARG2)
2737
2738 #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \
2739 do { \
2740 float_status *status = &env->active_tc.msa_fp_status; \
2741 int c; \
2742 \
2743 set_float_exception_flags(0, status); \
2744 DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \
2745 c = update_msacsr(env, 0, 0); \
2746 \
2747 if (get_enabled_exceptions(env, c)) { \
2748 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2749 } \
2750 } while (0)
2751
2752 #define FMAXMIN_A(F, G, X, _S, _T, BITS) \
2753 do { \
2754 uint## BITS ##_t S = _S, T = _T; \
2755 uint## BITS ##_t as, at, xs, xt, xd; \
2756 if (NUMBER_QNAN_PAIR(S, T, BITS)) { \
2757 T = S; \
2758 } \
2759 else if (NUMBER_QNAN_PAIR(T, S, BITS)) { \
2760 S = T; \
2761 } \
2762 as = float## BITS ##_abs(S); \
2763 at = float## BITS ##_abs(T); \
2764 MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \
2765 MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \
2766 MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \
2767 X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \
2768 } while (0)
2769
2770 void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2771 uint32_t ws, uint32_t wt)
2772 {
2773 wr_t wx, *pwx = &wx;
2774 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2775 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2776 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2777 uint32_t i;
2778
2779 clear_msacsr_cause(env);
2780
2781 switch (df) {
2782 case DF_WORD:
2783 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2784 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
2785 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pws->w[i], 32);
2786 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
2787 MSA_FLOAT_MAXOP(pwx->w[i], min, pwt->w[i], pwt->w[i], 32);
2788 } else {
2789 MSA_FLOAT_MAXOP(pwx->w[i], min, pws->w[i], pwt->w[i], 32);
2790 }
2791 }
2792 break;
2793 case DF_DOUBLE:
2794 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2795 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
2796 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pws->d[i], 64);
2797 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
2798 MSA_FLOAT_MAXOP(pwx->d[i], min, pwt->d[i], pwt->d[i], 64);
2799 } else {
2800 MSA_FLOAT_MAXOP(pwx->d[i], min, pws->d[i], pwt->d[i], 64);
2801 }
2802 }
2803 break;
2804 default:
2805 assert(0);
2806 }
2807
2808 check_msacsr_cause(env, GETPC());
2809
2810 msa_move_v(pwd, pwx);
2811 }
2812
2813 void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2814 uint32_t ws, uint32_t wt)
2815 {
2816 wr_t wx, *pwx = &wx;
2817 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2818 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2819 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2820 uint32_t i;
2821
2822 clear_msacsr_cause(env);
2823
2824 switch (df) {
2825 case DF_WORD:
2826 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2827 FMAXMIN_A(min, max, pwx->w[i], pws->w[i], pwt->w[i], 32);
2828 }
2829 break;
2830 case DF_DOUBLE:
2831 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2832 FMAXMIN_A(min, max, pwx->d[i], pws->d[i], pwt->d[i], 64);
2833 }
2834 break;
2835 default:
2836 assert(0);
2837 }
2838
2839 check_msacsr_cause(env, GETPC());
2840
2841 msa_move_v(pwd, pwx);
2842 }
2843
2844 void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2845 uint32_t ws, uint32_t wt)
2846 {
2847 wr_t wx, *pwx = &wx;
2848 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2849 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2850 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2851 uint32_t i;
2852
2853 clear_msacsr_cause(env);
2854
2855 switch (df) {
2856 case DF_WORD:
2857 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2858 if (NUMBER_QNAN_PAIR(pws->w[i], pwt->w[i], 32)) {
2859 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pws->w[i], 32);
2860 } else if (NUMBER_QNAN_PAIR(pwt->w[i], pws->w[i], 32)) {
2861 MSA_FLOAT_MAXOP(pwx->w[i], max, pwt->w[i], pwt->w[i], 32);
2862 } else {
2863 MSA_FLOAT_MAXOP(pwx->w[i], max, pws->w[i], pwt->w[i], 32);
2864 }
2865 }
2866 break;
2867 case DF_DOUBLE:
2868 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2869 if (NUMBER_QNAN_PAIR(pws->d[i], pwt->d[i], 64)) {
2870 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pws->d[i], 64);
2871 } else if (NUMBER_QNAN_PAIR(pwt->d[i], pws->d[i], 64)) {
2872 MSA_FLOAT_MAXOP(pwx->d[i], max, pwt->d[i], pwt->d[i], 64);
2873 } else {
2874 MSA_FLOAT_MAXOP(pwx->d[i], max, pws->d[i], pwt->d[i], 64);
2875 }
2876 }
2877 break;
2878 default:
2879 assert(0);
2880 }
2881
2882 check_msacsr_cause(env, GETPC());
2883
2884 msa_move_v(pwd, pwx);
2885 }
2886
2887 void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2888 uint32_t ws, uint32_t wt)
2889 {
2890 wr_t wx, *pwx = &wx;
2891 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2892 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2893 wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
2894 uint32_t i;
2895
2896 clear_msacsr_cause(env);
2897
2898 switch (df) {
2899 case DF_WORD:
2900 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2901 FMAXMIN_A(max, min, pwx->w[i], pws->w[i], pwt->w[i], 32);
2902 }
2903 break;
2904 case DF_DOUBLE:
2905 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2906 FMAXMIN_A(max, min, pwx->d[i], pws->d[i], pwt->d[i], 64);
2907 }
2908 break;
2909 default:
2910 assert(0);
2911 }
2912
2913 check_msacsr_cause(env, GETPC());
2914
2915 msa_move_v(pwd, pwx);
2916 }
2917
2918 void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df,
2919 uint32_t wd, uint32_t ws)
2920 {
2921 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2922 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2923 if (df == DF_WORD) {
2924 pwd->w[0] = helper_float_class_s(pws->w[0]);
2925 pwd->w[1] = helper_float_class_s(pws->w[1]);
2926 pwd->w[2] = helper_float_class_s(pws->w[2]);
2927 pwd->w[3] = helper_float_class_s(pws->w[3]);
2928 } else {
2929 pwd->d[0] = helper_float_class_d(pws->d[0]);
2930 pwd->d[1] = helper_float_class_d(pws->d[1]);
2931 }
2932 }
2933
2934 #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \
2935 do { \
2936 float_status *status = &env->active_tc.msa_fp_status; \
2937 int c; \
2938 \
2939 set_float_exception_flags(0, status); \
2940 DEST = float ## BITS ## _ ## OP(ARG, status); \
2941 c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \
2942 \
2943 if (get_enabled_exceptions(env, c)) { \
2944 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
2945 } else if (float ## BITS ## _is_any_nan(ARG)) { \
2946 DEST = 0; \
2947 } \
2948 } while (0)
2949
2950 void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2951 uint32_t ws)
2952 {
2953 wr_t wx, *pwx = &wx;
2954 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2955 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2956 uint32_t i;
2957
2958 clear_msacsr_cause(env);
2959
2960 switch (df) {
2961 case DF_WORD:
2962 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2963 MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32);
2964 }
2965 break;
2966 case DF_DOUBLE:
2967 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2968 MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64);
2969 }
2970 break;
2971 default:
2972 assert(0);
2973 }
2974
2975 check_msacsr_cause(env, GETPC());
2976
2977 msa_move_v(pwd, pwx);
2978 }
2979
2980 void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
2981 uint32_t ws)
2982 {
2983 wr_t wx, *pwx = &wx;
2984 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
2985 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
2986 uint32_t i;
2987
2988 clear_msacsr_cause(env);
2989
2990 switch (df) {
2991 case DF_WORD:
2992 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
2993 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32);
2994 }
2995 break;
2996 case DF_DOUBLE:
2997 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
2998 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64);
2999 }
3000 break;
3001 default:
3002 assert(0);
3003 }
3004
3005 check_msacsr_cause(env, GETPC());
3006
3007 msa_move_v(pwd, pwx);
3008 }
3009
3010 void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3011 uint32_t ws)
3012 {
3013 wr_t wx, *pwx = &wx;
3014 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3015 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3016 uint32_t i;
3017
3018 clear_msacsr_cause(env);
3019
3020 switch (df) {
3021 case DF_WORD:
3022 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3023 MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32);
3024 }
3025 break;
3026 case DF_DOUBLE:
3027 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3028 MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64);
3029 }
3030 break;
3031 default:
3032 assert(0);
3033 }
3034
3035 check_msacsr_cause(env, GETPC());
3036
3037 msa_move_v(pwd, pwx);
3038 }
3039
3040 #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \
3041 do { \
3042 float_status *status = &env->active_tc.msa_fp_status; \
3043 int c; \
3044 \
3045 set_float_exception_flags(0, status); \
3046 DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \
3047 c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \
3048 float ## BITS ## _is_quiet_nan(DEST) ? \
3049 0 : RECIPROCAL_INEXACT, \
3050 IS_DENORMAL(DEST, BITS)); \
3051 \
3052 if (get_enabled_exceptions(env, c)) { \
3053 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
3054 } \
3055 } while (0)
3056
3057 void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3058 uint32_t ws)
3059 {
3060 wr_t wx, *pwx = &wx;
3061 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3062 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3063 uint32_t i;
3064
3065 clear_msacsr_cause(env);
3066
3067 switch (df) {
3068 case DF_WORD:
3069 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3070 MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i],
3071 &env->active_tc.msa_fp_status), 32);
3072 }
3073 break;
3074 case DF_DOUBLE:
3075 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3076 MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i],
3077 &env->active_tc.msa_fp_status), 64);
3078 }
3079 break;
3080 default:
3081 assert(0);
3082 }
3083
3084 check_msacsr_cause(env, GETPC());
3085
3086 msa_move_v(pwd, pwx);
3087 }
3088
3089 void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3090 uint32_t ws)
3091 {
3092 wr_t wx, *pwx = &wx;
3093 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3094 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3095 uint32_t i;
3096
3097 clear_msacsr_cause(env);
3098
3099 switch (df) {
3100 case DF_WORD:
3101 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3102 MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32);
3103 }
3104 break;
3105 case DF_DOUBLE:
3106 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3107 MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64);
3108 }
3109 break;
3110 default:
3111 assert(0);
3112 }
3113
3114 check_msacsr_cause(env, GETPC());
3115
3116 msa_move_v(pwd, pwx);
3117 }
3118
3119 void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3120 uint32_t ws)
3121 {
3122 wr_t wx, *pwx = &wx;
3123 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3124 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3125 uint32_t i;
3126
3127 clear_msacsr_cause(env);
3128
3129 switch (df) {
3130 case DF_WORD:
3131 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3132 MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32);
3133 }
3134 break;
3135 case DF_DOUBLE:
3136 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3137 MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64);
3138 }
3139 break;
3140 default:
3141 assert(0);
3142 }
3143
3144 check_msacsr_cause(env, GETPC());
3145
3146 msa_move_v(pwd, pwx);
3147 }
3148
3149 #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \
3150 do { \
3151 float_status *status = &env->active_tc.msa_fp_status; \
3152 int c; \
3153 \
3154 set_float_exception_flags(0, status); \
3155 set_float_rounding_mode(float_round_down, status); \
3156 DEST = float ## BITS ## _ ## log2(ARG, status); \
3157 DEST = float ## BITS ## _ ## round_to_int(DEST, status); \
3158 set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \
3159 MSACSR_RM_MASK) >> MSACSR_RM], \
3160 status); \
3161 \
3162 set_float_exception_flags(get_float_exception_flags(status) & \
3163 (~float_flag_inexact), \
3164 status); \
3165 \
3166 c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \
3167 \
3168 if (get_enabled_exceptions(env, c)) { \
3169 DEST = ((FLOAT_SNAN ## BITS >> 6) << 6) | c; \
3170 } \
3171 } while (0)
3172
3173 void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3174 uint32_t ws)
3175 {
3176 wr_t wx, *pwx = &wx;
3177 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3178 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3179 uint32_t i;
3180
3181 clear_msacsr_cause(env);
3182
3183 switch (df) {
3184 case DF_WORD:
3185 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3186 MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32);
3187 }
3188 break;
3189 case DF_DOUBLE:
3190 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3191 MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64);
3192 }
3193 break;
3194 default:
3195 assert(0);
3196 }
3197
3198 check_msacsr_cause(env, GETPC());
3199
3200 msa_move_v(pwd, pwx);
3201 }
3202
3203 void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3204 uint32_t ws)
3205 {
3206 wr_t wx, *pwx = &wx;
3207 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3208 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3209 uint32_t i;
3210
3211 clear_msacsr_cause(env);
3212
3213 switch (df) {
3214 case DF_WORD:
3215 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3216 /* Half precision floats come in two formats: standard
3217 IEEE and "ARM" format. The latter gains extra exponent
3218 range by omitting the NaN/Inf encodings. */
3219 flag ieee = 1;
3220
3221 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32);
3222 }
3223 break;
3224 case DF_DOUBLE:
3225 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3226 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64);
3227 }
3228 break;
3229 default:
3230 assert(0);
3231 }
3232
3233 check_msacsr_cause(env, GETPC());
3234 msa_move_v(pwd, pwx);
3235 }
3236
3237 void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3238 uint32_t ws)
3239 {
3240 wr_t wx, *pwx = &wx;
3241 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3242 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3243 uint32_t i;
3244
3245 clear_msacsr_cause(env);
3246
3247 switch (df) {
3248 case DF_WORD:
3249 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3250 /* Half precision floats come in two formats: standard
3251 IEEE and "ARM" format. The latter gains extra exponent
3252 range by omitting the NaN/Inf encodings. */
3253 flag ieee = 1;
3254
3255 MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32);
3256 }
3257 break;
3258 case DF_DOUBLE:
3259 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3260 MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64);
3261 }
3262 break;
3263 default:
3264 assert(0);
3265 }
3266
3267 check_msacsr_cause(env, GETPC());
3268 msa_move_v(pwd, pwx);
3269 }
3270
3271 void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3272 uint32_t ws)
3273 {
3274 wr_t wx, *pwx = &wx;
3275 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3276 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3277 uint32_t i;
3278
3279 switch (df) {
3280 case DF_WORD:
3281 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3282 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32);
3283 }
3284 break;
3285 case DF_DOUBLE:
3286 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3287 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64);
3288 }
3289 break;
3290 default:
3291 assert(0);
3292 }
3293
3294 msa_move_v(pwd, pwx);
3295 }
3296
3297 void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3298 uint32_t ws)
3299 {
3300 wr_t wx, *pwx = &wx;
3301 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3302 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3303 uint32_t i;
3304
3305 switch (df) {
3306 case DF_WORD:
3307 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3308 MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32);
3309 }
3310 break;
3311 case DF_DOUBLE:
3312 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3313 MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64);
3314 }
3315 break;
3316 default:
3317 assert(0);
3318 }
3319
3320 msa_move_v(pwd, pwx);
3321 }
3322
3323 void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3324 uint32_t ws)
3325 {
3326 wr_t wx, *pwx = &wx;
3327 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3328 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3329 uint32_t i;
3330
3331 clear_msacsr_cause(env);
3332
3333 switch (df) {
3334 case DF_WORD:
3335 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3336 MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32);
3337 }
3338 break;
3339 case DF_DOUBLE:
3340 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3341 MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64);
3342 }
3343 break;
3344 default:
3345 assert(0);
3346 }
3347
3348 check_msacsr_cause(env, GETPC());
3349
3350 msa_move_v(pwd, pwx);
3351 }
3352
3353 void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3354 uint32_t ws)
3355 {
3356 wr_t wx, *pwx = &wx;
3357 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3358 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3359 uint32_t i;
3360
3361 clear_msacsr_cause(env);
3362
3363 switch (df) {
3364 case DF_WORD:
3365 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3366 MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32);
3367 }
3368 break;
3369 case DF_DOUBLE:
3370 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3371 MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64);
3372 }
3373 break;
3374 default:
3375 assert(0);
3376 }
3377
3378 check_msacsr_cause(env, GETPC());
3379
3380 msa_move_v(pwd, pwx);
3381 }
3382
3383 #define float32_from_int32 int32_to_float32
3384 #define float32_from_uint32 uint32_to_float32
3385
3386 #define float64_from_int64 int64_to_float64
3387 #define float64_from_uint64 uint64_to_float64
3388
3389 void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3390 uint32_t ws)
3391 {
3392 wr_t wx, *pwx = &wx;
3393 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3394 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3395 uint32_t i;
3396
3397 clear_msacsr_cause(env);
3398
3399 switch (df) {
3400 case DF_WORD:
3401 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3402 MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32);
3403 }
3404 break;
3405 case DF_DOUBLE:
3406 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3407 MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64);
3408 }
3409 break;
3410 default:
3411 assert(0);
3412 }
3413
3414 check_msacsr_cause(env, GETPC());
3415
3416 msa_move_v(pwd, pwx);
3417 }
3418
3419 void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
3420 uint32_t ws)
3421 {
3422 wr_t wx, *pwx = &wx;
3423 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3424 wr_t *pws = &(env->active_fpu.fpr[ws].wr);
3425 uint32_t i;
3426
3427 clear_msacsr_cause(env);
3428
3429 switch (df) {
3430 case DF_WORD:
3431 for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3432 MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32);
3433 }
3434 break;
3435 case DF_DOUBLE:
3436 for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3437 MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64);
3438 }
3439 break;
3440 default:
3441 assert(0);
3442 }
3443
3444 check_msacsr_cause(env, GETPC());
3445
3446 msa_move_v(pwd, pwx);
3447 }
QEmu