hw/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "qemu-common.h"
   5 #include "memory.h"
   6 #include "ioport.h"
   7 #include "isa.h"
   8 #include "fdc.h"
   9 #include "net.h"
  10 #include "memory.h"
  11
  12 /* PC-style peripherals (also used by other machines).  */
  13
  14 /* serial.c */
  15
  16 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
  17                          CharDriverState *chr);
  18 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
  19                              qemu_irq irq, int baudbase,
  20                              CharDriverState *chr, int ioregister,
  21                              int be);
  22 static inline bool serial_isa_init(int index, CharDriverState *chr)
  23 {
  24     ISADevice *dev;
  25
  26     dev = isa_try_create("isa-serial");
  27     if (!dev) {
  28         return false;
  29     }
  30     qdev_prop_set_uint32(&dev->qdev, "index", index);
  31     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
  32     if (qdev_init(&dev->qdev) < 0) {
  33         return false;
  34     }
  35     return true;
  36 }
  37
  38 void serial_set_frequency(SerialState *s, uint32_t frequency);
  39
  40 /* parallel.c */
  41 static inline bool parallel_init(int index, CharDriverState *chr)
  42 {
  43     ISADevice *dev;
  44
  45     dev = isa_try_create("isa-parallel");
  46     if (!dev) {
  47         return false;
  48     }
  49     qdev_prop_set_uint32(&dev->qdev, "index", index);
  50     qdev_prop_set_chr(&dev->qdev, "chardev", chr);
  51     if (qdev_init(&dev->qdev) < 0) {
  52         return false;
  53     }
  54     return true;
  55 }
  56
  57 bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
  58                       CharDriverState *chr);
  59
  60 /* i8259.c */
  61
  62 typedef struct PicState2 PicState2;
  63 extern PicState2 *isa_pic;
  64 void pic_set_irq(int irq, int level);
  65 void pic_set_irq_new(void *opaque, int irq, int level);
  66 qemu_irq *i8259_init(qemu_irq parent_irq);
  67 int pic_read_irq(PicState2 *s);
  68 void pic_update_irq(PicState2 *s);
  69 uint32_t pic_intack_read(PicState2 *s);
  70 void pic_info(Monitor *mon);
  71 void irq_info(Monitor *mon);
  72
  73 /* ISA */
  74 #define IOAPIC_NUM_PINS 0x18
  75
  76 typedef struct isa_irq_state {
  77     qemu_irq *i8259;
  78     qemu_irq ioapic[IOAPIC_NUM_PINS];
  79 } IsaIrqState;
  80
  81 void isa_irq_handler(void *opaque, int n, int level);
  82
  83 /* i8254.c */
  84
  85 #define PIT_FREQ 1193182
  86
  87 static inline ISADevice *pit_init(int base, int irq)
  88 {
  89     ISADevice *dev;
  90
  91     dev = isa_create("isa-pit");
  92     qdev_prop_set_uint32(&dev->qdev, "iobase", base);
  93     qdev_prop_set_uint32(&dev->qdev, "irq", irq);
  94     qdev_init_nofail(&dev->qdev);
  95
  96     return dev;
  97 }
  98
  99 void pit_set_gate(ISADevice *dev, int channel, int val);
 100 int pit_get_gate(ISADevice *dev, int channel);
 101 int pit_get_initial_count(ISADevice *dev, int channel);
 102 int pit_get_mode(ISADevice *dev, int channel);
 103 int pit_get_out(ISADevice *dev, int channel, int64_t current_time);
 104
 105 void hpet_pit_disable(void);
 106 void hpet_pit_enable(void);
 107
 108 /* vmport.c */
 109 static inline void vmport_init(void)
 110 {
 111     isa_create_simple("vmport");
 112 }
 113 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
 114 void vmmouse_get_data(uint32_t *data);
 115 void vmmouse_set_data(const uint32_t *data);
 116
 117 /* pckbd.c */
 118
 119 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
 120 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 121                    target_phys_addr_t base, ram_addr_t size,
 122                    target_phys_addr_t mask);
 123 void i8042_isa_mouse_fake_event(void *opaque);
 124 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
 125
 126 /* pc.c */
 127 extern int fd_bootchk;
 128
 129 void pc_register_ferr_irq(qemu_irq irq);
 130 void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
 131 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 132
 133 void pc_cpus_init(const char *cpu_model);
 134 void pc_memory_init(MemoryRegion *system_memory,
 135                     const char *kernel_filename,
 136                     const char *kernel_cmdline,
 137                     const char *initrd_filename,
 138                     ram_addr_t below_4g_mem_size,
 139                     ram_addr_t above_4g_mem_size,
 140                     MemoryRegion *pci_memory,
 141                     MemoryRegion **ram_memory);
 142 qemu_irq *pc_allocate_cpu_irq(void);
 143 void pc_vga_init(PCIBus *pci_bus);
 144 void pc_basic_device_init(qemu_irq *isa_irq,
 145                           ISADevice **rtc_state,
 146                           bool no_vmport);
 147 void pc_init_ne2k_isa(NICInfo *nd);
 148 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 149                   const char *boot_device,
 150                   BusState *ide0, BusState *ide1,
 151                   ISADevice *s);
 152 void pc_pci_device_init(PCIBus *pci_bus);
 153
 154 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 155 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
 156
 157 /* acpi.c */
 158 extern int acpi_enabled;
 159 extern char *acpi_tables;
 160 extern size_t acpi_tables_len;
 161
 162 void acpi_bios_init(void);
 163 int acpi_table_add(const char *table_desc);
 164
 165 /* acpi_piix.c */
 166
 167 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 168                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 169                        int kvm_enabled);
 170 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 171
 172 /* hpet.c */
 173 extern int no_hpet;
 174
 175 /* pcspk.c */
 176 void pcspk_init(ISADevice *pit);
 177 int pcspk_audio_init(qemu_irq *pic);
 178
 179 /* piix_pci.c */
 180 struct PCII440FXState;
 181 typedef struct PCII440FXState PCII440FXState;
 182
 183 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
 184                     qemu_irq *pic,
 185                     MemoryRegion *address_space_mem,
 186                     MemoryRegion *address_space_io,
 187                     ram_addr_t ram_size,
 188                     target_phys_addr_t pci_hole_start,
 189                     target_phys_addr_t pci_hole_size,
 190                     target_phys_addr_t pci_hole64_start,
 191                     target_phys_addr_t pci_hole64_size,
 192                     MemoryRegion *pci_memory,
 193                     MemoryRegion *ram_memory);
 194
 195 /* piix4.c */
 196 extern PCIDevice *piix4_dev;
 197 int piix4_init(PCIBus *bus, int devfn);
 198
 199 /* vga.c */
 200 enum vga_retrace_method {
 201     VGA_RETRACE_DUMB,
 202     VGA_RETRACE_PRECISE
 203 };
 204
 205 extern enum vga_retrace_method vga_retrace_method;
 206
 207 static inline int isa_vga_init(void)
 208 {
 209     ISADevice *dev;
 210
 211     dev = isa_try_create("isa-vga");
 212     if (!dev) {
 213         fprintf(stderr, "Warning: isa-vga not available\n");
 214         return 0;
 215     }
 216     qdev_init_nofail(&dev->qdev);
 217     return 1;
 218 }
 219
 220 int pci_vga_init(PCIBus *bus);
 221 int isa_vga_mm_init(target_phys_addr_t vram_base,
 222                     target_phys_addr_t ctrl_base, int it_shift,
 223                     MemoryRegion *address_space);
 224
 225 /* cirrus_vga.c */
 226 void pci_cirrus_vga_init(PCIBus *bus);
 227 void isa_cirrus_vga_init(MemoryRegion *address_space);
 228
 229 /* ne2000.c */
 230 static inline bool isa_ne2000_init(int base, int irq, NICInfo *nd)
 231 {
 232     ISADevice *dev;
 233
 234     qemu_check_nic_model(nd, "ne2k_isa");
 235
 236     dev = isa_try_create("ne2k_isa");
 237     if (!dev) {
 238         return false;
 239     }
 240     qdev_prop_set_uint32(&dev->qdev, "iobase", base);
 241     qdev_prop_set_uint32(&dev->qdev, "irq",    irq);
 242     qdev_set_nic_properties(&dev->qdev, nd);
 243     qdev_init_nofail(&dev->qdev);
 244     return true;
 245 }
 246
 247 /* e820 types */
 248 #define E820_RAM        1
 249 #define E820_RESERVED   2
 250 #define E820_ACPI       3
 251 #define E820_NVS        4
 252 #define E820_UNUSABLE   5
 253
 254 int e820_add_entry(uint64_t, uint64_t, uint32_t);
 255
 256 #endif