hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "acpi.h"
  24 #include "sysemu.h"
  25 #include "range.h"
  26
  27 //#define DEBUG
  28
  29 #ifdef DEBUG
  30 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  31 #else
  32 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  33 #endif
  34
  35 #define ACPI_DBG_IO_ADDR  0xb044
  36
  37 #define GPE_BASE 0xafe0
  38 #define GPE_LEN 4
  39 #define PCI_BASE 0xae00
  40 #define PCI_EJ_BASE 0xae08
  41 #define PCI_RMV_BASE 0xae0c
  42
  43 #define PIIX4_PCI_HOTPLUG_STATUS 2
  44
  45 struct pci_status {
  46     uint32_t up;
  47     uint32_t down;
  48 };
  49
  50 typedef struct PIIX4PMState {
  51     PCIDevice dev;
  52     IORange ioport;
  53     ACPIPM1EVT pm1a;
  54     ACPIPM1CNT pm1_cnt;
  55
  56     APMState apm;
  57
  58     ACPIPMTimer tmr;
  59
  60     PMSMBus smb;
  61     uint32_t smb_io_base;
  62
  63     qemu_irq irq;
  64     qemu_irq smi_irq;
  65     int kvm_enabled;
  66
  67     /* for pci hotplug */
  68     ACPIGPE gpe;
  69     struct pci_status pci0_status;
  70     uint32_t pci0_hotplug_enable;
  71 } PIIX4PMState;
  72
  73 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  74
  75 #define ACPI_ENABLE 0xf1
  76 #define ACPI_DISABLE 0xf0
  77
  78 static void pm_update_sci(PIIX4PMState *s)
  79 {
  80     int sci_level, pmsts;
  81
  82     pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
  83     sci_level = (((pmsts & s->pm1a.en) &
  84                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  85                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  86                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  87                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
  88         (((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
  89
  90     qemu_set_irq(s->irq, sci_level);
  91     /* schedule a timer interruption if needed */
  92     acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
  93                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
  94 }
  95
  96 static void pm_tmr_timer(ACPIPMTimer *tmr)
  97 {
  98     PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
  99     pm_update_sci(s);
 100 }
 101
 102 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 103                             uint64_t val)
 104 {
 105     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 106
 107     if (width != 2) {
 108         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 109                       (unsigned)addr, width, (unsigned)val);
 110     }
 111
 112     switch(addr) {
 113     case 0x00:
 114         acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
 115         pm_update_sci(s);
 116         break;
 117     case 0x02:
 118         s->pm1a.en = val;
 119         pm_update_sci(s);
 120         break;
 121     case 0x04:
 122         acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
 123         break;
 124     default:
 125         break;
 126     }
 127     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 128                   (unsigned int)val);
 129 }
 130
 131 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 132                             uint64_t *data)
 133 {
 134     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 135     uint32_t val;
 136
 137     switch(addr) {
 138     case 0x00:
 139         val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
 140         break;
 141     case 0x02:
 142         val = s->pm1a.en;
 143         break;
 144     case 0x04:
 145         val = s->pm1_cnt.cnt;
 146         break;
 147     case 0x08:
 148         val = acpi_pm_tmr_get(&s->tmr);
 149         break;
 150     default:
 151         val = 0;
 152         break;
 153     }
 154     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 155     *data = val;
 156 }
 157
 158 static const IORangeOps pm_iorange_ops = {
 159     .read = pm_ioport_read,
 160     .write = pm_ioport_write,
 161 };
 162
 163 static void apm_ctrl_changed(uint32_t val, void *arg)
 164 {
 165     PIIX4PMState *s = arg;
 166
 167     /* ACPI specs 3.0, 4.7.2.5 */
 168     acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
 169
 170     if (s->dev.config[0x5b] & (1 << 1)) {
 171         if (s->smi_irq) {
 172             qemu_irq_raise(s->smi_irq);
 173         }
 174     }
 175 }
 176
 177 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 178 {
 179     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 180 }
 181
 182 static void pm_io_space_update(PIIX4PMState *s)
 183 {
 184     uint32_t pm_io_base;
 185
 186     if (s->dev.config[0x80] & 1) {
 187         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 188         pm_io_base &= 0xffc0;
 189
 190         /* XXX: need to improve memory and ioport allocation */
 191         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 192         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 193         ioport_register(&s->ioport);
 194     }
 195 }
 196
 197 static void pm_write_config(PCIDevice *d,
 198                             uint32_t address, uint32_t val, int len)
 199 {
 200     pci_default_write_config(d, address, val, len);
 201     if (range_covers_byte(address, len, 0x80))
 202         pm_io_space_update((PIIX4PMState *)d);
 203 }
 204
 205 static int vmstate_acpi_post_load(void *opaque, int version_id)
 206 {
 207     PIIX4PMState *s = opaque;
 208
 209     pm_io_space_update(s);
 210     return 0;
 211 }
 212
 213 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 214  {                                                                   \
 215      .name       = (stringify(_field)),                              \
 216      .version_id = 0,                                                \
 217      .num        = GPE_LEN,                                          \
 218      .info       = &vmstate_info_uint16,                             \
 219      .size       = sizeof(uint16_t),                                 \
 220      .flags      = VMS_ARRAY | VMS_POINTER,                          \
 221      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 222  }
 223
 224 static const VMStateDescription vmstate_gpe = {
 225     .name = "gpe",
 226     .version_id = 1,
 227     .minimum_version_id = 1,
 228     .minimum_version_id_old = 1,
 229     .fields      = (VMStateField []) {
 230         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 231         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 232         VMSTATE_END_OF_LIST()
 233     }
 234 };
 235
 236 static const VMStateDescription vmstate_pci_status = {
 237     .name = "pci_status",
 238     .version_id = 1,
 239     .minimum_version_id = 1,
 240     .minimum_version_id_old = 1,
 241     .fields      = (VMStateField []) {
 242         VMSTATE_UINT32(up, struct pci_status),
 243         VMSTATE_UINT32(down, struct pci_status),
 244         VMSTATE_END_OF_LIST()
 245     }
 246 };
 247
 248 static const VMStateDescription vmstate_acpi = {
 249     .name = "piix4_pm",
 250     .version_id = 2,
 251     .minimum_version_id = 1,
 252     .minimum_version_id_old = 1,
 253     .post_load = vmstate_acpi_post_load,
 254     .fields      = (VMStateField []) {
 255         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 256         VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
 257         VMSTATE_UINT16(pm1a.en, PIIX4PMState),
 258         VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
 259         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 260         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
 261         VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
 262         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 263         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 264                        struct pci_status),
 265         VMSTATE_END_OF_LIST()
 266     }
 267 };
 268
 269 static void piix4_update_hotplug(PIIX4PMState *s)
 270 {
 271     PCIDevice *dev = &s->dev;
 272     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 273     DeviceState *qdev, *next;
 274
 275     s->pci0_hotplug_enable = ~0;
 276
 277     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 278         PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
 279         PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
 280         int slot = PCI_SLOT(pdev->devfn);
 281
 282         if (info->no_hotplug) {
 283             s->pci0_hotplug_enable &= ~(1 << slot);
 284         }
 285     }
 286 }
 287
 288 static void piix4_reset(void *opaque)
 289 {
 290     PIIX4PMState *s = opaque;
 291     uint8_t *pci_conf = s->dev.config;
 292
 293     pci_conf[0x58] = 0;
 294     pci_conf[0x59] = 0;
 295     pci_conf[0x5a] = 0;
 296     pci_conf[0x5b] = 0;
 297
 298     if (s->kvm_enabled) {
 299         /* Mark SMM as already inited (until KVM supports SMM). */
 300         pci_conf[0x5B] = 0x02;
 301     }
 302     piix4_update_hotplug(s);
 303 }
 304
 305 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 306 {
 307     PIIX4PMState *s = opaque;
 308     ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
 309     ACPIPMTimer *tmr = s? &s->tmr: NULL;
 310
 311     acpi_pm1_evt_power_down(pm1a, tmr);
 312 }
 313
 314 static int piix4_pm_initfn(PCIDevice *dev)
 315 {
 316     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 317     uint8_t *pci_conf;
 318
 319     pci_conf = s->dev.config;
 320     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 321     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 322     pci_conf[0x06] = 0x80;
 323     pci_conf[0x07] = 0x02;
 324     pci_conf[0x08] = 0x03; // revision number
 325     pci_conf[0x09] = 0x00;
 326     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 327     pci_conf[0x3d] = 0x01; // interrupt pin 1
 328
 329     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 330
 331     /* APM */
 332     apm_init(&s->apm, apm_ctrl_changed, s);
 333
 334     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 335
 336     if (s->kvm_enabled) {
 337         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 338          * support SMM mode. */
 339         pci_conf[0x5B] = 0x02;
 340     }
 341
 342     /* XXX: which specification is used ? The i82731AB has different
 343        mappings */
 344     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 345     pci_conf[0x63] = 0x60;
 346     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 347         (serial_hds[1] != NULL ? 0x90 : 0);
 348
 349     pci_conf[0x90] = s->smb_io_base | 1;
 350     pci_conf[0x91] = s->smb_io_base >> 8;
 351     pci_conf[0xd2] = 0x09;
 352     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 353     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 354
 355     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 356     acpi_gpe_init(&s->gpe, GPE_LEN);
 357
 358     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 359
 360     pm_smbus_init(&s->dev.qdev, &s->smb);
 361     qemu_register_reset(piix4_reset, s);
 362     piix4_acpi_system_hot_add_init(dev->bus, s);
 363
 364     return 0;
 365 }
 366
 367 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 368                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 369                        int kvm_enabled)
 370 {
 371     PCIDevice *dev;
 372     PIIX4PMState *s;
 373
 374     dev = pci_create(bus, devfn, "PIIX4_PM");
 375     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 376
 377     s = DO_UPCAST(PIIX4PMState, dev, dev);
 378     s->irq = sci_irq;
 379     acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
 380     s->smi_irq = smi_irq;
 381     s->kvm_enabled = kvm_enabled;
 382
 383     qdev_init_nofail(&dev->qdev);
 384
 385     return s->smb.smbus;
 386 }
 387
 388 static PCIDeviceInfo piix4_pm_info = {
 389     .qdev.name          = "PIIX4_PM",
 390     .qdev.desc          = "PM",
 391     .qdev.size          = sizeof(PIIX4PMState),
 392     .qdev.vmsd          = &vmstate_acpi,
 393     .qdev.no_user       = 1,
 394     .no_hotplug         = 1,
 395     .init               = piix4_pm_initfn,
 396     .config_write       = pm_write_config,
 397     .qdev.props         = (Property[]) {
 398         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 399         DEFINE_PROP_END_OF_LIST(),
 400     }
 401 };
 402
 403 static void piix4_pm_register(void)
 404 {
 405     pci_qdev_register(&piix4_pm_info);
 406 }
 407
 408 device_init(piix4_pm_register);
 409
 410 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 411 {
 412     PIIX4PMState *s = opaque;
 413     uint32_t val = acpi_gpe_ioport_readb(&s->gpe, addr);
 414
 415     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 416     return val;
 417 }
 418
 419 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 420 {
 421     PIIX4PMState *s = opaque;
 422
 423     acpi_gpe_ioport_writeb(&s->gpe, addr, val);
 424     pm_update_sci(s);
 425
 426     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 427 }
 428
 429 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 430 {
 431     uint32_t val = 0;
 432     struct pci_status *g = opaque;
 433     switch (addr) {
 434         case PCI_BASE:
 435             val = g->up;
 436             break;
 437         case PCI_BASE + 4:
 438             val = g->down;
 439             break;
 440         default:
 441             break;
 442     }
 443
 444     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 445     return val;
 446 }
 447
 448 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 449 {
 450     struct pci_status *g = opaque;
 451     switch (addr) {
 452         case PCI_BASE:
 453             g->up = val;
 454             break;
 455         case PCI_BASE + 4:
 456             g->down = val;
 457             break;
 458    }
 459
 460     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 461 }
 462
 463 static uint32_t pciej_read(void *opaque, uint32_t addr)
 464 {
 465     PIIX4_DPRINTF("pciej read %x\n", addr);
 466     return 0;
 467 }
 468
 469 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 470 {
 471     BusState *bus = opaque;
 472     DeviceState *qdev, *next;
 473     PCIDevice *dev;
 474     int slot = ffs(val) - 1;
 475
 476     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 477         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 478         if (PCI_SLOT(dev->devfn) == slot) {
 479             qdev_free(qdev);
 480         }
 481     }
 482
 483
 484     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 485 }
 486
 487 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 488 {
 489     PIIX4PMState *s = opaque;
 490
 491     return s->pci0_hotplug_enable;
 492 }
 493
 494 static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
 495 {
 496     return;
 497 }
 498
 499 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 500                                 PCIHotplugState state);
 501
 502 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 503 {
 504     struct pci_status *pci0_status = &s->pci0_status;
 505
 506     register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
 507     register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
 508     acpi_gpe_blk(&s->gpe, GPE_BASE);
 509
 510     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 511     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 512
 513     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 514     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 515
 516     register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
 517     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 518
 519     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 520 }
 521
 522 static void enable_device(PIIX4PMState *s, int slot)
 523 {
 524     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 525     s->pci0_status.up |= (1 << slot);
 526 }
 527
 528 static void disable_device(PIIX4PMState *s, int slot)
 529 {
 530     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 531     s->pci0_status.down |= (1 << slot);
 532 }
 533
 534 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 535                                 PCIHotplugState state)
 536 {
 537     int slot = PCI_SLOT(dev->devfn);
 538     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 539                                 DO_UPCAST(PCIDevice, qdev, qdev));
 540
 541     /* Don't send event when device is enabled during qemu machine creation:
 542      * it is present on boot, no hotplug event is necessary. We do send an
 543      * event when the device is disabled later. */
 544     if (state == PCI_COLDPLUG_ENABLED) {
 545         return 0;
 546     }
 547
 548     s->pci0_status.up = 0;
 549     s->pci0_status.down = 0;
 550     if (state == PCI_HOTPLUG_ENABLED) {
 551         enable_device(s, slot);
 552     } else {
 553         disable_device(s, slot);
 554     }
 555
 556     pm_update_sci(s);
 557
 558     return 0;
 559 }