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PPC: Add dcbtls emulation
[qemu.git] / target-ppc / translate_init.c
blob0f9dec753be3fe25a5693e28d000887610ecafec
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31
32 //#define PPC_DUMP_CPU
33 //#define PPC_DEBUG_SPR
34 //#define PPC_DUMP_SPR_ACCESSES
35
36 /* For user-mode emulation, we don't emulate any IRQ controller */
37 #if defined(CONFIG_USER_ONLY)
38 #define PPC_IRQ_INIT_FN(name) \
39 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
40 { \
41 }
42 #else
43 #define PPC_IRQ_INIT_FN(name) \
44 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
45 #endif
46
47 PPC_IRQ_INIT_FN(40x);
48 PPC_IRQ_INIT_FN(6xx);
49 PPC_IRQ_INIT_FN(970);
50 PPC_IRQ_INIT_FN(POWER7);
51 PPC_IRQ_INIT_FN(e500);
52
53 /* Generic callbacks:
54 * do nothing but store/retrieve spr value
55 */
56 static void spr_load_dump_spr(int sprn)
57 {
58 #ifdef PPC_DUMP_SPR_ACCESSES
59 TCGv_i32 t0 = tcg_const_i32(sprn);
60 gen_helper_load_dump_spr(cpu_env, t0);
61 tcg_temp_free_i32(t0);
62 #endif
63 }
64
65 static void spr_read_generic (void *opaque, int gprn, int sprn)
66 {
67 gen_load_spr(cpu_gpr[gprn], sprn);
68 spr_load_dump_spr(sprn);
69 }
70
71 static void spr_store_dump_spr(int sprn)
72 {
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 TCGv_i32 t0 = tcg_const_i32(sprn);
75 gen_helper_store_dump_spr(cpu_env, t0);
76 tcg_temp_free_i32(t0);
77 #endif
78 }
79
80 static void spr_write_generic (void *opaque, int sprn, int gprn)
81 {
82 gen_store_spr(sprn, cpu_gpr[gprn]);
83 spr_store_dump_spr(sprn);
84 }
85
86 #if !defined(CONFIG_USER_ONLY)
87 static void spr_write_generic32(void *opaque, int sprn, int gprn)
88 {
89 #ifdef TARGET_PPC64
90 TCGv t0 = tcg_temp_new();
91 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
92 gen_store_spr(sprn, t0);
93 tcg_temp_free(t0);
94 spr_store_dump_spr(sprn);
95 #else
96 spr_write_generic(opaque, sprn, gprn);
97 #endif
98 }
99
100 static void spr_write_clear (void *opaque, int sprn, int gprn)
101 {
102 TCGv t0 = tcg_temp_new();
103 TCGv t1 = tcg_temp_new();
104 gen_load_spr(t0, sprn);
105 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
106 tcg_gen_and_tl(t0, t0, t1);
107 gen_store_spr(sprn, t0);
108 tcg_temp_free(t0);
109 tcg_temp_free(t1);
110 }
111
112 static void spr_access_nop(void *opaque, int sprn, int gprn)
113 {
114 }
115
116 #endif
117
118 /* SPR common to all PowerPC */
119 /* XER */
120 static void spr_read_xer (void *opaque, int gprn, int sprn)
121 {
122 gen_read_xer(cpu_gpr[gprn]);
123 }
124
125 static void spr_write_xer (void *opaque, int sprn, int gprn)
126 {
127 gen_write_xer(cpu_gpr[gprn]);
128 }
129
130 /* LR */
131 static void spr_read_lr (void *opaque, int gprn, int sprn)
132 {
133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
134 }
135
136 static void spr_write_lr (void *opaque, int sprn, int gprn)
137 {
138 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
139 }
140
141 /* CFAR */
142 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
143 static void spr_read_cfar (void *opaque, int gprn, int sprn)
144 {
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
146 }
147
148 static void spr_write_cfar (void *opaque, int sprn, int gprn)
149 {
150 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
151 }
152 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
153
154 /* CTR */
155 static void spr_read_ctr (void *opaque, int gprn, int sprn)
156 {
157 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
158 }
159
160 static void spr_write_ctr (void *opaque, int sprn, int gprn)
161 {
162 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
163 }
164
165 /* User read access to SPR */
166 /* USPRx */
167 /* UMMCRx */
168 /* UPMCx */
169 /* USIA */
170 /* UDECR */
171 static void spr_read_ureg (void *opaque, int gprn, int sprn)
172 {
173 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
174 }
175
176 /* SPR common to all non-embedded PowerPC */
177 /* DECR */
178 #if !defined(CONFIG_USER_ONLY)
179 static void spr_read_decr (void *opaque, int gprn, int sprn)
180 {
181 if (use_icount) {
182 gen_io_start();
183 }
184 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
185 if (use_icount) {
186 gen_io_end();
187 gen_stop_exception(opaque);
188 }
189 }
190
191 static void spr_write_decr (void *opaque, int sprn, int gprn)
192 {
193 if (use_icount) {
194 gen_io_start();
195 }
196 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
197 if (use_icount) {
198 gen_io_end();
199 gen_stop_exception(opaque);
200 }
201 }
202 #endif
203
204 /* SPR common to all non-embedded PowerPC, except 601 */
205 /* Time base */
206 static void spr_read_tbl (void *opaque, int gprn, int sprn)
207 {
208 if (use_icount) {
209 gen_io_start();
210 }
211 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
212 if (use_icount) {
213 gen_io_end();
214 gen_stop_exception(opaque);
215 }
216 }
217
218 static void spr_read_tbu (void *opaque, int gprn, int sprn)
219 {
220 if (use_icount) {
221 gen_io_start();
222 }
223 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
224 if (use_icount) {
225 gen_io_end();
226 gen_stop_exception(opaque);
227 }
228 }
229
230 __attribute__ (( unused ))
231 static void spr_read_atbl (void *opaque, int gprn, int sprn)
232 {
233 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
234 }
235
236 __attribute__ (( unused ))
237 static void spr_read_atbu (void *opaque, int gprn, int sprn)
238 {
239 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
240 }
241
242 #if !defined(CONFIG_USER_ONLY)
243 static void spr_write_tbl (void *opaque, int sprn, int gprn)
244 {
245 if (use_icount) {
246 gen_io_start();
247 }
248 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
249 if (use_icount) {
250 gen_io_end();
251 gen_stop_exception(opaque);
252 }
253 }
254
255 static void spr_write_tbu (void *opaque, int sprn, int gprn)
256 {
257 if (use_icount) {
258 gen_io_start();
259 }
260 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
261 if (use_icount) {
262 gen_io_end();
263 gen_stop_exception(opaque);
264 }
265 }
266
267 __attribute__ (( unused ))
268 static void spr_write_atbl (void *opaque, int sprn, int gprn)
269 {
270 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
271 }
272
273 __attribute__ (( unused ))
274 static void spr_write_atbu (void *opaque, int sprn, int gprn)
275 {
276 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
277 }
278
279 #if defined(TARGET_PPC64)
280 __attribute__ (( unused ))
281 static void spr_read_purr (void *opaque, int gprn, int sprn)
282 {
283 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
284 }
285 #endif
286 #endif
287
288 #if !defined(CONFIG_USER_ONLY)
289 /* IBAT0U...IBAT0U */
290 /* IBAT0L...IBAT7L */
291 static void spr_read_ibat (void *opaque, int gprn, int sprn)
292 {
293 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
294 }
295
296 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
297 {
298 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
299 }
300
301 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
302 {
303 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
304 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
305 tcg_temp_free_i32(t0);
306 }
307
308 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
309 {
310 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
311 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
312 tcg_temp_free_i32(t0);
313 }
314
315 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
316 {
317 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
318 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
319 tcg_temp_free_i32(t0);
320 }
321
322 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
323 {
324 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
325 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
326 tcg_temp_free_i32(t0);
327 }
328
329 /* DBAT0U...DBAT7U */
330 /* DBAT0L...DBAT7L */
331 static void spr_read_dbat (void *opaque, int gprn, int sprn)
332 {
333 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
334 }
335
336 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
337 {
338 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
339 }
340
341 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
342 {
343 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
344 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
345 tcg_temp_free_i32(t0);
346 }
347
348 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
349 {
350 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
351 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
352 tcg_temp_free_i32(t0);
353 }
354
355 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
356 {
357 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
358 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
359 tcg_temp_free_i32(t0);
360 }
361
362 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
363 {
364 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
365 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
366 tcg_temp_free_i32(t0);
367 }
368
369 /* SDR1 */
370 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
371 {
372 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
373 }
374
375 /* 64 bits PowerPC specific SPRs */
376 #if defined(TARGET_PPC64)
377 static void spr_read_hior (void *opaque, int gprn, int sprn)
378 {
379 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
380 }
381
382 static void spr_write_hior (void *opaque, int sprn, int gprn)
383 {
384 TCGv t0 = tcg_temp_new();
385 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
386 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
387 tcg_temp_free(t0);
388 }
389 #endif
390 #endif
391
392 /* PowerPC 601 specific registers */
393 /* RTC */
394 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
395 {
396 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
397 }
398
399 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
400 {
401 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
402 }
403
404 #if !defined(CONFIG_USER_ONLY)
405 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
406 {
407 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
411 {
412 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
413 }
414
415 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
416 {
417 DisasContext *ctx = opaque;
418
419 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
420 /* Must stop the translation as endianness may have changed */
421 gen_stop_exception(ctx);
422 }
423 #endif
424
425 /* Unified bats */
426 #if !defined(CONFIG_USER_ONLY)
427 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
428 {
429 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
430 }
431
432 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
433 {
434 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
435 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
436 tcg_temp_free_i32(t0);
437 }
438
439 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
440 {
441 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
442 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
443 tcg_temp_free_i32(t0);
444 }
445 #endif
446
447 /* PowerPC 40x specific registers */
448 #if !defined(CONFIG_USER_ONLY)
449 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
450 {
451 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
452 }
453
454 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
455 {
456 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
457 }
458
459 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
460 {
461 DisasContext *ctx = opaque;
462
463 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
464 /* We must stop translation as we may have rebooted */
465 gen_stop_exception(ctx);
466 }
467
468 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
469 {
470 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
471 }
472
473 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
474 {
475 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
476 }
477
478 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
479 {
480 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
481 }
482 #endif
483
484 /* PowerPC 403 specific registers */
485 /* PBL1 / PBU1 / PBL2 / PBU2 */
486 #if !defined(CONFIG_USER_ONLY)
487 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
488 {
489 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
490 }
491
492 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
493 {
494 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
495 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
496 tcg_temp_free_i32(t0);
497 }
498
499 static void spr_write_pir (void *opaque, int sprn, int gprn)
500 {
501 TCGv t0 = tcg_temp_new();
502 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
503 gen_store_spr(SPR_PIR, t0);
504 tcg_temp_free(t0);
505 }
506 #endif
507
508 /* SPE specific registers */
509 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
510 {
511 TCGv_i32 t0 = tcg_temp_new_i32();
512 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
513 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
514 tcg_temp_free_i32(t0);
515 }
516
517 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
518 {
519 TCGv_i32 t0 = tcg_temp_new_i32();
520 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
521 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
522 tcg_temp_free_i32(t0);
523 }
524
525 #if !defined(CONFIG_USER_ONLY)
526 /* Callback used to write the exception vector base */
527 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
528 {
529 TCGv t0 = tcg_temp_new();
530 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
531 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
532 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
533 gen_store_spr(sprn, t0);
534 tcg_temp_free(t0);
535 }
536
537 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
538 {
539 DisasContext *ctx = opaque;
540 int sprn_offs;
541
542 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
543 sprn_offs = sprn - SPR_BOOKE_IVOR0;
544 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
545 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
546 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
547 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
548 } else {
549 printf("Trying to write an unknown exception vector %d %03x\n",
550 sprn, sprn);
551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
552 return;
553 }
554
555 TCGv t0 = tcg_temp_new();
556 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
557 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
558 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
559 gen_store_spr(sprn, t0);
560 tcg_temp_free(t0);
561 }
562 #endif
563
564 static inline void vscr_init (CPUPPCState *env, uint32_t val)
565 {
566 env->vscr = val;
567 /* Altivec always uses round-to-nearest */
568 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
569 set_flush_to_zero(vscr_nj, &env->vec_status);
570 }
571
572 #ifdef CONFIG_USER_ONLY
573 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
574 oea_read, oea_write, one_reg_id, initial_value) \
575 _spr_register(env, num, name, uea_read, uea_write, initial_value)
576 #else
577 #if !defined(CONFIG_KVM)
578 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
579 oea_read, oea_write, one_reg_id, initial_value) \
580 _spr_register(env, num, name, uea_read, uea_write, \
581 oea_read, oea_write, initial_value)
582 #else
583 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, one_reg_id, initial_value) \
585 _spr_register(env, num, name, uea_read, uea_write, \
586 oea_read, oea_write, one_reg_id, initial_value)
587 #endif
588 #endif
589
590 #define spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, initial_value) \
592 spr_register_kvm(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, 0, initial_value)
594
595 static inline void _spr_register(CPUPPCState *env, int num,
596 const char *name,
597 void (*uea_read)(void *opaque, int gprn, int sprn),
598 void (*uea_write)(void *opaque, int sprn, int gprn),
599 #if !defined(CONFIG_USER_ONLY)
600
601 void (*oea_read)(void *opaque, int gprn, int sprn),
602 void (*oea_write)(void *opaque, int sprn, int gprn),
603 #endif
604 #if defined(CONFIG_KVM)
605 uint64_t one_reg_id,
606 #endif
607 target_ulong initial_value)
608 {
609 ppc_spr_t *spr;
610
611 spr = &env->spr_cb[num];
612 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
613 #if !defined(CONFIG_USER_ONLY)
614 spr->oea_read != NULL || spr->oea_write != NULL ||
615 #endif
616 spr->uea_read != NULL || spr->uea_write != NULL) {
617 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
618 exit(1);
619 }
620 #if defined(PPC_DEBUG_SPR)
621 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
622 name, initial_value);
623 #endif
624 spr->name = name;
625 spr->uea_read = uea_read;
626 spr->uea_write = uea_write;
627 #if !defined(CONFIG_USER_ONLY)
628 spr->oea_read = oea_read;
629 spr->oea_write = oea_write;
630 #endif
631 #if defined(CONFIG_KVM)
632 spr->one_reg_id = one_reg_id,
633 #endif
634 env->spr[num] = spr->default_value = initial_value;
635 }
636
637 /* Generic PowerPC SPRs */
638 static void gen_spr_generic (CPUPPCState *env)
639 {
640 /* Integer processing */
641 spr_register(env, SPR_XER, "XER",
642 &spr_read_xer, &spr_write_xer,
643 &spr_read_xer, &spr_write_xer,
644 0x00000000);
645 /* Branch contol */
646 spr_register(env, SPR_LR, "LR",
647 &spr_read_lr, &spr_write_lr,
648 &spr_read_lr, &spr_write_lr,
649 0x00000000);
650 spr_register(env, SPR_CTR, "CTR",
651 &spr_read_ctr, &spr_write_ctr,
652 &spr_read_ctr, &spr_write_ctr,
653 0x00000000);
654 /* Interrupt processing */
655 spr_register(env, SPR_SRR0, "SRR0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SRR1, "SRR1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Processor control */
664 spr_register(env, SPR_SPRG0, "SPRG0",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, &spr_write_generic,
667 0x00000000);
668 spr_register(env, SPR_SPRG1, "SPRG1",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 spr_register(env, SPR_SPRG2, "SPRG2",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SPRG3, "SPRG3",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 }
681
682 /* SPR common to all non-embedded PowerPC, including 601 */
683 static void gen_spr_ne_601 (CPUPPCState *env)
684 {
685 /* Exception processing */
686 spr_register_kvm(env, SPR_DSISR, "DSISR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 KVM_REG_PPC_DSISR, 0x00000000);
690 spr_register_kvm(env, SPR_DAR, "DAR",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_generic, &spr_write_generic,
693 KVM_REG_PPC_DAR, 0x00000000);
694 /* Timer */
695 spr_register(env, SPR_DECR, "DECR",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_decr, &spr_write_decr,
698 0x00000000);
699 /* Memory management */
700 spr_register(env, SPR_SDR1, "SDR1",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, &spr_write_sdr1,
703 0x00000000);
704 }
705
706 /* BATs 0-3 */
707 static void gen_low_BATs (CPUPPCState *env)
708 {
709 #if !defined(CONFIG_USER_ONLY)
710 spr_register(env, SPR_IBAT0U, "IBAT0U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT0L, "IBAT0L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_IBAT1U, "IBAT1U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_ibat, &spr_write_ibatu,
721 0x00000000);
722 spr_register(env, SPR_IBAT1L, "IBAT1L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_ibat, &spr_write_ibatl,
725 0x00000000);
726 spr_register(env, SPR_IBAT2U, "IBAT2U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_ibat, &spr_write_ibatu,
729 0x00000000);
730 spr_register(env, SPR_IBAT2L, "IBAT2L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_ibat, &spr_write_ibatl,
733 0x00000000);
734 spr_register(env, SPR_IBAT3U, "IBAT3U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_ibat, &spr_write_ibatu,
737 0x00000000);
738 spr_register(env, SPR_IBAT3L, "IBAT3L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_ibat, &spr_write_ibatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT0U, "DBAT0U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT0L, "DBAT0L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 spr_register(env, SPR_DBAT1U, "DBAT1U",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_dbat, &spr_write_dbatu,
753 0x00000000);
754 spr_register(env, SPR_DBAT1L, "DBAT1L",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_dbat, &spr_write_dbatl,
757 0x00000000);
758 spr_register(env, SPR_DBAT2U, "DBAT2U",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_dbat, &spr_write_dbatu,
761 0x00000000);
762 spr_register(env, SPR_DBAT2L, "DBAT2L",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_dbat, &spr_write_dbatl,
765 0x00000000);
766 spr_register(env, SPR_DBAT3U, "DBAT3U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_dbat, &spr_write_dbatu,
769 0x00000000);
770 spr_register(env, SPR_DBAT3L, "DBAT3L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_dbat, &spr_write_dbatl,
773 0x00000000);
774 env->nb_BATs += 4;
775 #endif
776 }
777
778 /* BATs 4-7 */
779 static void gen_high_BATs (CPUPPCState *env)
780 {
781 #if !defined(CONFIG_USER_ONLY)
782 spr_register(env, SPR_IBAT4U, "IBAT4U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT4L, "IBAT4L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_IBAT5U, "IBAT5U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat_h, &spr_write_ibatu_h,
793 0x00000000);
794 spr_register(env, SPR_IBAT5L, "IBAT5L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat_h, &spr_write_ibatl_h,
797 0x00000000);
798 spr_register(env, SPR_IBAT6U, "IBAT6U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_ibat_h, &spr_write_ibatu_h,
801 0x00000000);
802 spr_register(env, SPR_IBAT6L, "IBAT6L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_ibat_h, &spr_write_ibatl_h,
805 0x00000000);
806 spr_register(env, SPR_IBAT7U, "IBAT7U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_ibat_h, &spr_write_ibatu_h,
809 0x00000000);
810 spr_register(env, SPR_IBAT7L, "IBAT7L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_ibat_h, &spr_write_ibatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT4U, "DBAT4U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT4L, "DBAT4L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 spr_register(env, SPR_DBAT5U, "DBAT5U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat_h, &spr_write_dbatu_h,
825 0x00000000);
826 spr_register(env, SPR_DBAT5L, "DBAT5L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat_h, &spr_write_dbatl_h,
829 0x00000000);
830 spr_register(env, SPR_DBAT6U, "DBAT6U",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_dbat_h, &spr_write_dbatu_h,
833 0x00000000);
834 spr_register(env, SPR_DBAT6L, "DBAT6L",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_dbat_h, &spr_write_dbatl_h,
837 0x00000000);
838 spr_register(env, SPR_DBAT7U, "DBAT7U",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_dbat_h, &spr_write_dbatu_h,
841 0x00000000);
842 spr_register(env, SPR_DBAT7L, "DBAT7L",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_dbat_h, &spr_write_dbatl_h,
845 0x00000000);
846 env->nb_BATs += 4;
847 #endif
848 }
849
850 /* Generic PowerPC time base */
851 static void gen_tbl (CPUPPCState *env)
852 {
853 spr_register(env, SPR_VTBL, "TBL",
854 &spr_read_tbl, SPR_NOACCESS,
855 &spr_read_tbl, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_TBL, "TBL",
858 &spr_read_tbl, SPR_NOACCESS,
859 &spr_read_tbl, &spr_write_tbl,
860 0x00000000);
861 spr_register(env, SPR_VTBU, "TBU",
862 &spr_read_tbu, SPR_NOACCESS,
863 &spr_read_tbu, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_TBU, "TBU",
866 &spr_read_tbu, SPR_NOACCESS,
867 &spr_read_tbu, &spr_write_tbu,
868 0x00000000);
869 }
870
871 /* Softare table search registers */
872 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
873 {
874 #if !defined(CONFIG_USER_ONLY)
875 env->nb_tlb = nb_tlbs;
876 env->nb_ways = nb_ways;
877 env->id_tlbs = 1;
878 env->tlb_type = TLB_6XX;
879 spr_register(env, SPR_DMISS, "DMISS",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, SPR_NOACCESS,
882 0x00000000);
883 spr_register(env, SPR_DCMP, "DCMP",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 0x00000000);
887 spr_register(env, SPR_HASH1, "HASH1",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
890 0x00000000);
891 spr_register(env, SPR_HASH2, "HASH2",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, SPR_NOACCESS,
894 0x00000000);
895 spr_register(env, SPR_IMISS, "IMISS",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 0x00000000);
899 spr_register(env, SPR_ICMP, "ICMP",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 0x00000000);
903 spr_register(env, SPR_RPA, "RPA",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 #endif
908 }
909
910 /* SPR common to MPC755 and G2 */
911 static void gen_spr_G2_755 (CPUPPCState *env)
912 {
913 /* SGPRs */
914 spr_register(env, SPR_SPRG4, "SPRG4",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 spr_register(env, SPR_SPRG5, "SPRG5",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 spr_register(env, SPR_SPRG6, "SPRG6",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 spr_register(env, SPR_SPRG7, "SPRG7",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930 }
931
932 /* SPR common to all 7xx PowerPC implementations */
933 static void gen_spr_7xx (CPUPPCState *env)
934 {
935 /* Breakpoints */
936 /* XXX : not implemented */
937 spr_register_kvm(env, SPR_DABR, "DABR",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 KVM_REG_PPC_DABR, 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_IABR, "IABR",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* Cache management */
947 /* XXX : not implemented */
948 spr_register(env, SPR_ICTC, "ICTC",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* Performance monitors */
953 /* XXX : not implemented */
954 spr_register(env, SPR_MMCR0, "MMCR0",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_MMCR1, "MMCR1",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_PMC1, "PMC1",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_PMC2, "PMC2",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_PMC3, "PMC3",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_PMC4, "PMC4",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983 /* XXX : not implemented */
984 spr_register(env, SPR_SIAR, "SIAR",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, SPR_NOACCESS,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_UMMCR0, "UMMCR0",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
993 /* XXX : not implemented */
994 spr_register(env, SPR_UMMCR1, "UMMCR1",
995 &spr_read_ureg, SPR_NOACCESS,
996 &spr_read_ureg, SPR_NOACCESS,
997 0x00000000);
998 /* XXX : not implemented */
999 spr_register(env, SPR_UPMC1, "UPMC1",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_UPMC2, "UPMC2",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_UPMC3, "UPMC3",
1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_UPMC4, "UPMC4",
1015 &spr_read_ureg, SPR_NOACCESS,
1016 &spr_read_ureg, SPR_NOACCESS,
1017 0x00000000);
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_USIAR, "USIAR",
1020 &spr_read_ureg, SPR_NOACCESS,
1021 &spr_read_ureg, SPR_NOACCESS,
1022 0x00000000);
1023 /* External access control */
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_EAR, "EAR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 }
1030
1031 #ifdef TARGET_PPC64
1032 #ifndef CONFIG_USER_ONLY
1033 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1034 {
1035 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1036 spr_load_dump_spr(SPR_AMR);
1037 }
1038
1039 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1040 {
1041 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1042 spr_store_dump_spr(SPR_AMR);
1043 }
1044
1045 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1046 {
1047 TCGv t0 = tcg_temp_new();
1048
1049 gen_load_spr(t0, SPR_UAMOR);
1050 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1051 gen_store_spr(SPR_AMR, t0);
1052 spr_store_dump_spr(SPR_AMR);
1053 }
1054 #endif /* CONFIG_USER_ONLY */
1055
1056 static void gen_spr_amr (CPUPPCState *env)
1057 {
1058 #ifndef CONFIG_USER_ONLY
1059 /* Virtual Page Class Key protection */
1060 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1061 * userspace accessible, 29 is privileged. So we only need to set
1062 * the kvm ONE_REG id on one of them, we use 29 */
1063 spr_register(env, SPR_UAMR, "UAMR",
1064 &spr_read_uamr, &spr_write_uamr_pr,
1065 &spr_read_uamr, &spr_write_uamr,
1066 0);
1067 spr_register_kvm(env, SPR_AMR, "AMR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 KVM_REG_PPC_AMR, 0);
1071 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_generic,
1074 KVM_REG_PPC_UAMOR, 0);
1075 #endif /* !CONFIG_USER_ONLY */
1076 }
1077 #endif /* TARGET_PPC64 */
1078
1079 static void gen_spr_thrm (CPUPPCState *env)
1080 {
1081 /* Thermal management */
1082 /* XXX : not implemented */
1083 spr_register(env, SPR_THRM1, "THRM1",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_generic, &spr_write_generic,
1086 0x00000000);
1087 /* XXX : not implemented */
1088 spr_register(env, SPR_THRM2, "THRM2",
1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_THRM3, "THRM3",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 }
1098
1099 /* SPR specific to PowerPC 604 implementation */
1100 static void gen_spr_604 (CPUPPCState *env)
1101 {
1102 /* Processor identification */
1103 spr_register(env, SPR_PIR, "PIR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_pir,
1106 0x00000000);
1107 /* Breakpoints */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_IABR, "IABR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register_kvm(env, SPR_DABR, "DABR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 KVM_REG_PPC_DABR, 0x00000000);
1118 /* Performance counters */
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_MMCR0, "MMCR0",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_PMC1, "PMC1",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_PMC2, "PMC2",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* XXX : not implemented */
1135 spr_register(env, SPR_SIAR, "SIAR",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, SPR_NOACCESS,
1138 0x00000000);
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_SDA, "SDA",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, SPR_NOACCESS,
1143 0x00000000);
1144 /* External access control */
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_EAR, "EAR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 }
1151
1152 /* SPR specific to PowerPC 603 implementation */
1153 static void gen_spr_603 (CPUPPCState *env)
1154 {
1155 /* External access control */
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_EAR, "EAR",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* Breakpoints */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_IABR, "IABR",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167
1168 }
1169
1170 /* SPR specific to PowerPC G2 implementation */
1171 static void gen_spr_G2 (CPUPPCState *env)
1172 {
1173 /* Memory base address */
1174 /* MBAR */
1175 /* XXX : not implemented */
1176 spr_register(env, SPR_MBAR, "MBAR",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180 /* Exception processing */
1181 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* Breakpoints */
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_DABR, "DABR",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_DABR2, "DABR2",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* XXX : not implemented */
1201 spr_register(env, SPR_IABR, "IABR",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
1205 /* XXX : not implemented */
1206 spr_register(env, SPR_IABR2, "IABR2",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_IBCR, "IBCR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* XXX : not implemented */
1216 spr_register(env, SPR_DBCR, "DBCR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220 }
1221
1222 /* SPR specific to PowerPC 602 implementation */
1223 static void gen_spr_602 (CPUPPCState *env)
1224 {
1225 /* ESA registers */
1226 /* XXX : not implemented */
1227 spr_register(env, SPR_SER, "SER",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_SEBR, "SEBR",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* XXX : not implemented */
1237 spr_register(env, SPR_ESASRR, "ESASRR",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_generic,
1240 0x00000000);
1241 /* Floating point status */
1242 /* XXX : not implemented */
1243 spr_register(env, SPR_SP, "SP",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 /* XXX : not implemented */
1248 spr_register(env, SPR_LT, "LT",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
1252 /* Watchdog timer */
1253 /* XXX : not implemented */
1254 spr_register(env, SPR_TCR, "TCR",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 /* Interrupt base */
1259 spr_register(env, SPR_IBR, "IBR",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_IABR, "IABR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 }
1269
1270 /* SPR specific to PowerPC 601 implementation */
1271 static void gen_spr_601 (CPUPPCState *env)
1272 {
1273 /* Multiplication/division register */
1274 /* MQ */
1275 spr_register(env, SPR_MQ, "MQ",
1276 &spr_read_generic, &spr_write_generic,
1277 &spr_read_generic, &spr_write_generic,
1278 0x00000000);
1279 /* RTC registers */
1280 spr_register(env, SPR_601_RTCU, "RTCU",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 SPR_NOACCESS, &spr_write_601_rtcu,
1283 0x00000000);
1284 spr_register(env, SPR_601_VRTCU, "RTCU",
1285 &spr_read_601_rtcu, SPR_NOACCESS,
1286 &spr_read_601_rtcu, SPR_NOACCESS,
1287 0x00000000);
1288 spr_register(env, SPR_601_RTCL, "RTCL",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 SPR_NOACCESS, &spr_write_601_rtcl,
1291 0x00000000);
1292 spr_register(env, SPR_601_VRTCL, "RTCL",
1293 &spr_read_601_rtcl, SPR_NOACCESS,
1294 &spr_read_601_rtcl, SPR_NOACCESS,
1295 0x00000000);
1296 /* Timer */
1297 #if 0 /* ? */
1298 spr_register(env, SPR_601_UDECR, "UDECR",
1299 &spr_read_decr, SPR_NOACCESS,
1300 &spr_read_decr, SPR_NOACCESS,
1301 0x00000000);
1302 #endif
1303 /* External access control */
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_EAR, "EAR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Memory management */
1310 #if !defined(CONFIG_USER_ONLY)
1311 spr_register(env, SPR_IBAT0U, "IBAT0U",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_601_ubat, &spr_write_601_ubatu,
1314 0x00000000);
1315 spr_register(env, SPR_IBAT0L, "IBAT0L",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_601_ubat, &spr_write_601_ubatl,
1318 0x00000000);
1319 spr_register(env, SPR_IBAT1U, "IBAT1U",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_601_ubat, &spr_write_601_ubatu,
1322 0x00000000);
1323 spr_register(env, SPR_IBAT1L, "IBAT1L",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_601_ubat, &spr_write_601_ubatl,
1326 0x00000000);
1327 spr_register(env, SPR_IBAT2U, "IBAT2U",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_601_ubat, &spr_write_601_ubatu,
1330 0x00000000);
1331 spr_register(env, SPR_IBAT2L, "IBAT2L",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_601_ubat, &spr_write_601_ubatl,
1334 0x00000000);
1335 spr_register(env, SPR_IBAT3U, "IBAT3U",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_601_ubat, &spr_write_601_ubatu,
1338 0x00000000);
1339 spr_register(env, SPR_IBAT3L, "IBAT3L",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_601_ubat, &spr_write_601_ubatl,
1342 0x00000000);
1343 env->nb_BATs = 4;
1344 #endif
1345 }
1346
1347 static void gen_spr_74xx (CPUPPCState *env)
1348 {
1349 /* Processor identification */
1350 spr_register(env, SPR_PIR, "PIR",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_pir,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_MMCR2, "MMCR2",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_UMMCR2, "UMMCR2",
1361 &spr_read_ureg, SPR_NOACCESS,
1362 &spr_read_ureg, SPR_NOACCESS,
1363 0x00000000);
1364 /* XXX: not implemented */
1365 spr_register(env, SPR_BAMR, "BAMR",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_MSSCR0, "MSSCR0",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* Hardware implementation registers */
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_HID0, "HID0",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 /* XXX : not implemented */
1381 spr_register(env, SPR_HID1, "HID1",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385 /* Altivec */
1386 spr_register(env, SPR_VRSAVE, "VRSAVE",
1387 &spr_read_generic, &spr_write_generic,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390 /* XXX : not implemented */
1391 spr_register(env, SPR_L2CR, "L2CR",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, spr_access_nop,
1394 0x00000000);
1395 /* Not strictly an SPR */
1396 vscr_init(env, 0x00010000);
1397 }
1398
1399 static void gen_l3_ctrl (CPUPPCState *env)
1400 {
1401 /* L3CR */
1402 /* XXX : not implemented */
1403 spr_register(env, SPR_L3CR, "L3CR",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407 /* L3ITCR0 */
1408 /* XXX : not implemented */
1409 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413 /* L3PM */
1414 /* XXX : not implemented */
1415 spr_register(env, SPR_L3PM, "L3PM",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419 }
1420
1421 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1422 {
1423 #if !defined(CONFIG_USER_ONLY)
1424 env->nb_tlb = nb_tlbs;
1425 env->nb_ways = nb_ways;
1426 env->id_tlbs = 1;
1427 env->tlb_type = TLB_6XX;
1428 /* XXX : not implemented */
1429 spr_register(env, SPR_PTEHI, "PTEHI",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433 /* XXX : not implemented */
1434 spr_register(env, SPR_PTELO, "PTELO",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438 /* XXX : not implemented */
1439 spr_register(env, SPR_TLBMISS, "TLBMISS",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 #endif
1444 }
1445
1446 #if !defined(CONFIG_USER_ONLY)
1447 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1448 {
1449 TCGv t0 = tcg_temp_new();
1450
1451 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1452 gen_store_spr(sprn, t0);
1453 tcg_temp_free(t0);
1454 }
1455
1456 static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn)
1457 {
1458 TCGv t0 = tcg_temp_new();
1459
1460 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1461 gen_store_spr(sprn, t0);
1462 tcg_temp_free(t0);
1463 }
1464
1465 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1466 {
1467 TCGv_i32 t0 = tcg_const_i32(sprn);
1468 gen_helper_booke206_tlbflush(cpu_env, t0);
1469 tcg_temp_free_i32(t0);
1470 }
1471
1472 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1473 {
1474 TCGv_i32 t0 = tcg_const_i32(sprn);
1475 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1476 tcg_temp_free_i32(t0);
1477 }
1478 #endif
1479
1480 static void gen_spr_usprgh (CPUPPCState *env)
1481 {
1482 spr_register(env, SPR_USPRG4, "USPRG4",
1483 &spr_read_ureg, SPR_NOACCESS,
1484 &spr_read_ureg, SPR_NOACCESS,
1485 0x00000000);
1486 spr_register(env, SPR_USPRG5, "USPRG5",
1487 &spr_read_ureg, SPR_NOACCESS,
1488 &spr_read_ureg, SPR_NOACCESS,
1489 0x00000000);
1490 spr_register(env, SPR_USPRG6, "USPRG6",
1491 &spr_read_ureg, SPR_NOACCESS,
1492 &spr_read_ureg, SPR_NOACCESS,
1493 0x00000000);
1494 spr_register(env, SPR_USPRG7, "USPRG7",
1495 &spr_read_ureg, SPR_NOACCESS,
1496 &spr_read_ureg, SPR_NOACCESS,
1497 0x00000000);
1498 }
1499
1500 /* PowerPC BookE SPR */
1501 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1502 {
1503 const char *ivor_names[64] = {
1504 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1505 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1506 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1507 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1508 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1509 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1510 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1511 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1512 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1513 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1514 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1515 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1516 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1517 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1518 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1519 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1520 };
1521 #define SPR_BOOKE_IVORxx (-1)
1522 int ivor_sprn[64] = {
1523 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1524 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1525 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1526 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1527 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1528 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1529 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1530 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1531 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1532 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1533 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1534 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1535 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1536 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1537 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1538 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1539 };
1540 int i;
1541
1542 /* Interrupt processing */
1543 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_generic,
1550 0x00000000);
1551 /* Debug */
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572 /* XXX : not implemented */
1573 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_40x_dbcr0,
1576 0x00000000);
1577 /* XXX : not implemented */
1578 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582 /* XXX : not implemented */
1583 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 /* XXX : not implemented */
1588 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_clear,
1591 0x00000000);
1592 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_generic,
1595 0x00000000);
1596 spr_register(env, SPR_BOOKE_ESR, "ESR",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_generic,
1599 0x00000000);
1600 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_excp_prefix,
1603 0x00000000);
1604 /* Exception vectors */
1605 for (i = 0; i < 64; i++) {
1606 if (ivor_mask & (1ULL << i)) {
1607 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1608 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1609 exit(1);
1610 }
1611 spr_register(env, ivor_sprn[i], ivor_names[i],
1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, &spr_write_excp_vector,
1614 0x00000000);
1615 }
1616 }
1617 spr_register(env, SPR_BOOKE_PID, "PID",
1618 SPR_NOACCESS, SPR_NOACCESS,
1619 &spr_read_generic, &spr_write_booke_pid,
1620 0x00000000);
1621 spr_register(env, SPR_BOOKE_TCR, "TCR",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_booke_tcr,
1624 0x00000000);
1625 spr_register(env, SPR_BOOKE_TSR, "TSR",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_booke_tsr,
1628 0x00000000);
1629 /* Timer */
1630 spr_register(env, SPR_DECR, "DECR",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_decr, &spr_write_decr,
1633 0x00000000);
1634 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 SPR_NOACCESS, &spr_write_generic,
1637 0x00000000);
1638 /* SPRGs */
1639 spr_register(env, SPR_USPRG0, "USPRG0",
1640 &spr_read_generic, &spr_write_generic,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 spr_register(env, SPR_SPRG4, "SPRG4",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 spr_register(env, SPR_SPRG5, "SPRG5",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 spr_register(env, SPR_SPRG6, "SPRG6",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_generic,
1654 0x00000000);
1655 spr_register(env, SPR_SPRG7, "SPRG7",
1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_generic,
1658 0x00000000);
1659 }
1660
1661 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1662 uint32_t maxsize, uint32_t flags,
1663 uint32_t nentries)
1664 {
1665 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1666 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1667 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1668 flags | nentries;
1669 }
1670
1671 /* BookE 2.06 storage control registers */
1672 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1673 uint32_t *tlbncfg)
1674 {
1675 #if !defined(CONFIG_USER_ONLY)
1676 const char *mas_names[8] = {
1677 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1678 };
1679 int mas_sprn[8] = {
1680 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1681 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1682 };
1683 int i;
1684
1685 /* TLB assist registers */
1686 /* XXX : not implemented */
1687 for (i = 0; i < 8; i++) {
1688 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1689 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1690 uea_write = &spr_write_generic;
1691 }
1692 if (mas_mask & (1 << i)) {
1693 spr_register(env, mas_sprn[i], mas_names[i],
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, uea_write,
1696 0x00000000);
1697 }
1698 }
1699 if (env->nb_pids > 1) {
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_BOOKE_PID1, "PID1",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_booke_pid,
1704 0x00000000);
1705 }
1706 if (env->nb_pids > 2) {
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_BOOKE_PID2, "PID2",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_booke_pid,
1711 0x00000000);
1712 }
1713 /* XXX : not implemented */
1714 spr_register(env, SPR_MMUCFG, "MMUCFG",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, SPR_NOACCESS,
1717 0x00000000); /* TOFIX */
1718 switch (env->nb_ways) {
1719 case 4:
1720 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, SPR_NOACCESS,
1723 tlbncfg[3]);
1724 /* Fallthru */
1725 case 3:
1726 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, SPR_NOACCESS,
1729 tlbncfg[2]);
1730 /* Fallthru */
1731 case 2:
1732 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1733 SPR_NOACCESS, SPR_NOACCESS,
1734 &spr_read_generic, SPR_NOACCESS,
1735 tlbncfg[1]);
1736 /* Fallthru */
1737 case 1:
1738 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, SPR_NOACCESS,
1741 tlbncfg[0]);
1742 /* Fallthru */
1743 case 0:
1744 default:
1745 break;
1746 }
1747 #endif
1748
1749 gen_spr_usprgh(env);
1750 }
1751
1752 /* SPR specific to PowerPC 440 implementation */
1753 static void gen_spr_440 (CPUPPCState *env)
1754 {
1755 /* Cache control */
1756 /* XXX : not implemented */
1757 spr_register(env, SPR_440_DNV0, "DNV0",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_440_DNV1, "DNV1",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, &spr_write_generic,
1765 0x00000000);
1766 /* XXX : not implemented */
1767 spr_register(env, SPR_440_DNV2, "DNV2",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_440_DNV3, "DNV3",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 /* XXX : not implemented */
1777 spr_register(env, SPR_440_DTV0, "DTV0",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 /* XXX : not implemented */
1782 spr_register(env, SPR_440_DTV1, "DTV1",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_generic,
1785 0x00000000);
1786 /* XXX : not implemented */
1787 spr_register(env, SPR_440_DTV2, "DTV2",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* XXX : not implemented */
1792 spr_register(env, SPR_440_DTV3, "DTV3",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 /* XXX : not implemented */
1797 spr_register(env, SPR_440_DVLIM, "DVLIM",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
1801 /* XXX : not implemented */
1802 spr_register(env, SPR_440_INV0, "INV0",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 /* XXX : not implemented */
1807 spr_register(env, SPR_440_INV1, "INV1",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1810 0x00000000);
1811 /* XXX : not implemented */
1812 spr_register(env, SPR_440_INV2, "INV2",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* XXX : not implemented */
1817 spr_register(env, SPR_440_INV3, "INV3",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* XXX : not implemented */
1822 spr_register(env, SPR_440_ITV0, "ITV0",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
1826 /* XXX : not implemented */
1827 spr_register(env, SPR_440_ITV1, "ITV1",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 /* XXX : not implemented */
1832 spr_register(env, SPR_440_ITV2, "ITV2",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_generic,
1835 0x00000000);
1836 /* XXX : not implemented */
1837 spr_register(env, SPR_440_ITV3, "ITV3",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_440_IVLIM, "IVLIM",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_generic,
1845 0x00000000);
1846 /* Cache debug */
1847 /* XXX : not implemented */
1848 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, SPR_NOACCESS,
1851 0x00000000);
1852 /* XXX : not implemented */
1853 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, SPR_NOACCESS,
1856 0x00000000);
1857 /* XXX : not implemented */
1858 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, SPR_NOACCESS,
1861 0x00000000);
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, SPR_NOACCESS,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, SPR_NOACCESS,
1871 0x00000000);
1872 /* XXX : not implemented */
1873 spr_register(env, SPR_440_DBDR, "DBDR",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_generic,
1876 0x00000000);
1877 /* Processor control */
1878 spr_register(env, SPR_4xx_CCR0, "CCR0",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, SPR_NOACCESS,
1885 0x00000000);
1886 /* Storage control */
1887 spr_register(env, SPR_440_MMUCR, "MMUCR",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_generic,
1890 0x00000000);
1891 }
1892
1893 /* SPR shared between PowerPC 40x implementations */
1894 static void gen_spr_40x (CPUPPCState *env)
1895 {
1896 /* Cache */
1897 /* not emulated, as QEMU do not emulate caches */
1898 spr_register(env, SPR_40x_DCCR, "DCCR",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 /* not emulated, as QEMU do not emulate caches */
1903 spr_register(env, SPR_40x_ICCR, "ICCR",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* not emulated, as QEMU do not emulate caches */
1908 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, SPR_NOACCESS,
1911 0x00000000);
1912 /* Exception */
1913 spr_register(env, SPR_40x_DEAR, "DEAR",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 spr_register(env, SPR_40x_ESR, "ESR",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 spr_register(env, SPR_40x_EVPR, "EVPR",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_excp_prefix,
1924 0x00000000);
1925 spr_register(env, SPR_40x_SRR2, "SRR2",
1926 &spr_read_generic, &spr_write_generic,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 spr_register(env, SPR_40x_SRR3, "SRR3",
1930 &spr_read_generic, &spr_write_generic,
1931 &spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 /* Timers */
1934 spr_register(env, SPR_40x_PIT, "PIT",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 &spr_read_40x_pit, &spr_write_40x_pit,
1937 0x00000000);
1938 spr_register(env, SPR_40x_TCR, "TCR",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_booke_tcr,
1941 0x00000000);
1942 spr_register(env, SPR_40x_TSR, "TSR",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_booke_tsr,
1945 0x00000000);
1946 }
1947
1948 /* SPR specific to PowerPC 405 implementation */
1949 static void gen_spr_405 (CPUPPCState *env)
1950 {
1951 /* MMU */
1952 spr_register(env, SPR_40x_PID, "PID",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956 spr_register(env, SPR_4xx_CCR0, "CCR0",
1957 SPR_NOACCESS, SPR_NOACCESS,
1958 &spr_read_generic, &spr_write_generic,
1959 0x00700000);
1960 /* Debug interface */
1961 /* XXX : not implemented */
1962 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_40x_dbcr0,
1965 0x00000000);
1966 /* XXX : not implemented */
1967 spr_register(env, SPR_405_DBCR1, "DBCR1",
1968 SPR_NOACCESS, SPR_NOACCESS,
1969 &spr_read_generic, &spr_write_generic,
1970 0x00000000);
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_40x_DBSR, "DBSR",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_clear,
1975 /* Last reset was system reset */
1976 0x00000300);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_40x_DAC1, "DAC1",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 spr_register(env, SPR_40x_DAC2, "DAC2",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_generic,
1985 0x00000000);
1986 /* XXX : not implemented */
1987 spr_register(env, SPR_405_DVC1, "DVC1",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
1991 /* XXX : not implemented */
1992 spr_register(env, SPR_405_DVC2, "DVC2",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_40x_IAC1, "IAC1",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 spr_register(env, SPR_40x_IAC2, "IAC2",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005 /* XXX : not implemented */
2006 spr_register(env, SPR_405_IAC3, "IAC3",
2007 SPR_NOACCESS, SPR_NOACCESS,
2008 &spr_read_generic, &spr_write_generic,
2009 0x00000000);
2010 /* XXX : not implemented */
2011 spr_register(env, SPR_405_IAC4, "IAC4",
2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, &spr_write_generic,
2014 0x00000000);
2015 /* Storage control */
2016 /* XXX: TODO: not implemented */
2017 spr_register(env, SPR_405_SLER, "SLER",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_40x_sler,
2020 0x00000000);
2021 spr_register(env, SPR_40x_ZPR, "ZPR",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_generic,
2024 0x00000000);
2025 /* XXX : not implemented */
2026 spr_register(env, SPR_405_SU0R, "SU0R",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 /* SPRG */
2031 spr_register(env, SPR_USPRG0, "USPRG0",
2032 &spr_read_ureg, SPR_NOACCESS,
2033 &spr_read_ureg, SPR_NOACCESS,
2034 0x00000000);
2035 spr_register(env, SPR_SPRG4, "SPRG4",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039 spr_register(env, SPR_SPRG5, "SPRG5",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 spr_register(env, SPR_SPRG6, "SPRG6",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 spr_read_generic, &spr_write_generic,
2046 0x00000000);
2047 spr_register(env, SPR_SPRG7, "SPRG7",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 spr_read_generic, &spr_write_generic,
2050 0x00000000);
2051 gen_spr_usprgh(env);
2052 }
2053
2054 /* SPR shared between PowerPC 401 & 403 implementations */
2055 static void gen_spr_401_403 (CPUPPCState *env)
2056 {
2057 /* Time base */
2058 spr_register(env, SPR_403_VTBL, "TBL",
2059 &spr_read_tbl, SPR_NOACCESS,
2060 &spr_read_tbl, SPR_NOACCESS,
2061 0x00000000);
2062 spr_register(env, SPR_403_TBL, "TBL",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 SPR_NOACCESS, &spr_write_tbl,
2065 0x00000000);
2066 spr_register(env, SPR_403_VTBU, "TBU",
2067 &spr_read_tbu, SPR_NOACCESS,
2068 &spr_read_tbu, SPR_NOACCESS,
2069 0x00000000);
2070 spr_register(env, SPR_403_TBU, "TBU",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 SPR_NOACCESS, &spr_write_tbu,
2073 0x00000000);
2074 /* Debug */
2075 /* not emulated, as QEMU do not emulate caches */
2076 spr_register(env, SPR_403_CDBCR, "CDBCR",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, &spr_write_generic,
2079 0x00000000);
2080 }
2081
2082 /* SPR specific to PowerPC 401 implementation */
2083 static void gen_spr_401 (CPUPPCState *env)
2084 {
2085 /* Debug interface */
2086 /* XXX : not implemented */
2087 spr_register(env, SPR_40x_DBCR0, "DBCR",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_40x_dbcr0,
2090 0x00000000);
2091 /* XXX : not implemented */
2092 spr_register(env, SPR_40x_DBSR, "DBSR",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_clear,
2095 /* Last reset was system reset */
2096 0x00000300);
2097 /* XXX : not implemented */
2098 spr_register(env, SPR_40x_DAC1, "DAC",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 /* XXX : not implemented */
2103 spr_register(env, SPR_40x_IAC1, "IAC",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 /* Storage control */
2108 /* XXX: TODO: not implemented */
2109 spr_register(env, SPR_405_SLER, "SLER",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_40x_sler,
2112 0x00000000);
2113 /* not emulated, as QEMU never does speculative access */
2114 spr_register(env, SPR_40x_SGR, "SGR",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0xFFFFFFFF);
2118 /* not emulated, as QEMU do not emulate caches */
2119 spr_register(env, SPR_40x_DCWR, "DCWR",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
2123 }
2124
2125 static void gen_spr_401x2 (CPUPPCState *env)
2126 {
2127 gen_spr_401(env);
2128 spr_register(env, SPR_40x_PID, "PID",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 spr_register(env, SPR_40x_ZPR, "ZPR",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 }
2137
2138 /* SPR specific to PowerPC 403 implementation */
2139 static void gen_spr_403 (CPUPPCState *env)
2140 {
2141 /* Debug interface */
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_40x_dbcr0,
2146 0x00000000);
2147 /* XXX : not implemented */
2148 spr_register(env, SPR_40x_DBSR, "DBSR",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_clear,
2151 /* Last reset was system reset */
2152 0x00000300);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_40x_DAC1, "DAC1",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_generic,
2157 0x00000000);
2158 /* XXX : not implemented */
2159 spr_register(env, SPR_40x_DAC2, "DAC2",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_40x_IAC1, "IAC1",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_40x_IAC2, "IAC2",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
2173 }
2174
2175 static void gen_spr_403_real (CPUPPCState *env)
2176 {
2177 spr_register(env, SPR_403_PBL1, "PBL1",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_403_pbr, &spr_write_403_pbr,
2180 0x00000000);
2181 spr_register(env, SPR_403_PBU1, "PBU1",
2182 SPR_NOACCESS, SPR_NOACCESS,
2183 &spr_read_403_pbr, &spr_write_403_pbr,
2184 0x00000000);
2185 spr_register(env, SPR_403_PBL2, "PBL2",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_403_pbr, &spr_write_403_pbr,
2188 0x00000000);
2189 spr_register(env, SPR_403_PBU2, "PBU2",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_403_pbr, &spr_write_403_pbr,
2192 0x00000000);
2193 }
2194
2195 static void gen_spr_403_mmu (CPUPPCState *env)
2196 {
2197 /* MMU */
2198 spr_register(env, SPR_40x_PID, "PID",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 spr_register(env, SPR_40x_ZPR, "ZPR",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_generic,
2205 0x00000000);
2206 }
2207
2208 /* SPR specific to PowerPC compression coprocessor extension */
2209 static void gen_spr_compress (CPUPPCState *env)
2210 {
2211 /* XXX : not implemented */
2212 spr_register(env, SPR_401_SKR, "SKR",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_generic, &spr_write_generic,
2215 0x00000000);
2216 }
2217
2218 static void gen_spr_5xx_8xx (CPUPPCState *env)
2219 {
2220 /* Exception processing */
2221 spr_register_kvm(env, SPR_DSISR, "DSISR",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_generic, &spr_write_generic,
2224 KVM_REG_PPC_DSISR, 0x00000000);
2225 spr_register_kvm(env, SPR_DAR, "DAR",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 KVM_REG_PPC_DAR, 0x00000000);
2229 /* Timer */
2230 spr_register(env, SPR_DECR, "DECR",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_decr, &spr_write_decr,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_MPC_EIE, "EIE",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_MPC_EID, "EID",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_MPC_NRI, "NRI",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_MPC_CMPA, "CMPA",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_MPC_CMPB, "CMPB",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_MPC_CMPC, "CMPC",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_MPC_CMPD, "CMPD",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_MPC_ECR, "ECR",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_MPC_DER, "DER",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_MPC_CMPE, "CMPE",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_MPC_CMPF, "CMPF",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_MPC_CMPG, "CMPG",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_MPC_CMPH, "CMPH",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 /* XXX : not implemented */
2310 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2311 SPR_NOACCESS, SPR_NOACCESS,
2312 &spr_read_generic, &spr_write_generic,
2313 0x00000000);
2314 /* XXX : not implemented */
2315 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 /* XXX : not implemented */
2320 spr_register(env, SPR_MPC_BAR, "BAR",
2321 SPR_NOACCESS, SPR_NOACCESS,
2322 &spr_read_generic, &spr_write_generic,
2323 0x00000000);
2324 /* XXX : not implemented */
2325 spr_register(env, SPR_MPC_DPDR, "DPDR",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_generic,
2328 0x00000000);
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_MPC_IMMR, "IMMR",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 }
2335
2336 static void gen_spr_5xx (CPUPPCState *env)
2337 {
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 /* XXX : not implemented */
2429 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2430 SPR_NOACCESS, SPR_NOACCESS,
2431 &spr_read_generic, &spr_write_generic,
2432 0x00000000);
2433 /* XXX : not implemented */
2434 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2435 SPR_NOACCESS, SPR_NOACCESS,
2436 &spr_read_generic, &spr_write_generic,
2437 0x00000000);
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 }
2444
2445 static void gen_spr_8xx (CPUPPCState *env)
2446 {
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 /* XXX : not implemented */
2538 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2539 SPR_NOACCESS, SPR_NOACCESS,
2540 &spr_read_generic, &spr_write_generic,
2541 0x00000000);
2542 /* XXX : not implemented */
2543 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2544 SPR_NOACCESS, SPR_NOACCESS,
2545 &spr_read_generic, &spr_write_generic,
2546 0x00000000);
2547 /* XXX : not implemented */
2548 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2549 SPR_NOACCESS, SPR_NOACCESS,
2550 &spr_read_generic, &spr_write_generic,
2551 0x00000000);
2552 /* XXX : not implemented */
2553 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2554 SPR_NOACCESS, SPR_NOACCESS,
2555 &spr_read_generic, &spr_write_generic,
2556 0x00000000);
2557 /* XXX : not implemented */
2558 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2559 SPR_NOACCESS, SPR_NOACCESS,
2560 &spr_read_generic, &spr_write_generic,
2561 0x00000000);
2562 /* XXX : not implemented */
2563 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2564 SPR_NOACCESS, SPR_NOACCESS,
2565 &spr_read_generic, &spr_write_generic,
2566 0x00000000);
2567 /* XXX : not implemented */
2568 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2569 SPR_NOACCESS, SPR_NOACCESS,
2570 &spr_read_generic, &spr_write_generic,
2571 0x00000000);
2572 }
2573
2574 // XXX: TODO
2575 /*
2576 * AMR => SPR 29 (Power 2.04)
2577 * CTRL => SPR 136 (Power 2.04)
2578 * CTRL => SPR 152 (Power 2.04)
2579 * SCOMC => SPR 276 (64 bits ?)
2580 * SCOMD => SPR 277 (64 bits ?)
2581 * TBU40 => SPR 286 (Power 2.04 hypv)
2582 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2583 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2584 * HDSISR => SPR 306 (Power 2.04 hypv)
2585 * HDAR => SPR 307 (Power 2.04 hypv)
2586 * PURR => SPR 309 (Power 2.04 hypv)
2587 * HDEC => SPR 310 (Power 2.04 hypv)
2588 * HIOR => SPR 311 (hypv)
2589 * RMOR => SPR 312 (970)
2590 * HRMOR => SPR 313 (Power 2.04 hypv)
2591 * HSRR0 => SPR 314 (Power 2.04 hypv)
2592 * HSRR1 => SPR 315 (Power 2.04 hypv)
2593 * LPIDR => SPR 317 (970)
2594 * EPR => SPR 702 (Power 2.04 emb)
2595 * perf => 768-783 (Power 2.04)
2596 * perf => 784-799 (Power 2.04)
2597 * PPR => SPR 896 (Power 2.04)
2598 * EPLC => SPR 947 (Power 2.04 emb)
2599 * EPSC => SPR 948 (Power 2.04 emb)
2600 * DABRX => 1015 (Power 2.04 hypv)
2601 * FPECR => SPR 1022 (?)
2602 * ... and more (thermal management, performance counters, ...)
2603 */
2604
2605 /*****************************************************************************/
2606 /* Exception vectors models */
2607 static void init_excp_4xx_real (CPUPPCState *env)
2608 {
2609 #if !defined(CONFIG_USER_ONLY)
2610 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2611 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2612 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2613 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2614 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2615 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2616 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2617 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2618 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2619 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2620 env->ivor_mask = 0x0000FFF0UL;
2621 env->ivpr_mask = 0xFFFF0000UL;
2622 /* Hardware reset vector */
2623 env->hreset_vector = 0xFFFFFFFCUL;
2624 #endif
2625 }
2626
2627 static void init_excp_4xx_softmmu (CPUPPCState *env)
2628 {
2629 #if !defined(CONFIG_USER_ONLY)
2630 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2631 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2632 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2633 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2634 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2635 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2636 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2637 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2638 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2639 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2640 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2641 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2642 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2643 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2644 env->ivor_mask = 0x0000FFF0UL;
2645 env->ivpr_mask = 0xFFFF0000UL;
2646 /* Hardware reset vector */
2647 env->hreset_vector = 0xFFFFFFFCUL;
2648 #endif
2649 }
2650
2651 static void init_excp_MPC5xx (CPUPPCState *env)
2652 {
2653 #if !defined(CONFIG_USER_ONLY)
2654 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2655 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2656 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2657 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2658 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2659 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2660 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2661 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2662 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2663 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2664 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2665 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2666 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2667 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2668 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2669 env->ivor_mask = 0x0000FFF0UL;
2670 env->ivpr_mask = 0xFFFF0000UL;
2671 /* Hardware reset vector */
2672 env->hreset_vector = 0x00000100UL;
2673 #endif
2674 }
2675
2676 static void init_excp_MPC8xx (CPUPPCState *env)
2677 {
2678 #if !defined(CONFIG_USER_ONLY)
2679 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2680 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2681 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2682 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2683 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2684 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2685 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2686 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2687 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2688 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2689 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2690 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2691 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2692 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2693 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2694 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2695 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2696 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2697 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2698 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2699 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2700 env->ivor_mask = 0x0000FFF0UL;
2701 env->ivpr_mask = 0xFFFF0000UL;
2702 /* Hardware reset vector */
2703 env->hreset_vector = 0x00000100UL;
2704 #endif
2705 }
2706
2707 static void init_excp_G2 (CPUPPCState *env)
2708 {
2709 #if !defined(CONFIG_USER_ONLY)
2710 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2711 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2712 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2713 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2714 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2715 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2716 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2717 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2718 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2719 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2720 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2721 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2722 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2723 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2724 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2725 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2726 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2727 /* Hardware reset vector */
2728 env->hreset_vector = 0x00000100UL;
2729 #endif
2730 }
2731
2732 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2733 {
2734 #if !defined(CONFIG_USER_ONLY)
2735 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2736 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2739 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2740 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2755 env->ivor_mask = 0x0000FFF7UL;
2756 env->ivpr_mask = ivpr_mask;
2757 /* Hardware reset vector */
2758 env->hreset_vector = 0xFFFFFFFCUL;
2759 #endif
2760 }
2761
2762 static void init_excp_BookE (CPUPPCState *env)
2763 {
2764 #if !defined(CONFIG_USER_ONLY)
2765 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2766 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2767 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2768 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2769 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2770 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2771 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2772 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2773 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2774 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2775 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2776 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2777 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2778 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2779 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2780 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2781 env->ivor_mask = 0x0000FFE0UL;
2782 env->ivpr_mask = 0xFFFF0000UL;
2783 /* Hardware reset vector */
2784 env->hreset_vector = 0xFFFFFFFCUL;
2785 #endif
2786 }
2787
2788 static void init_excp_601 (CPUPPCState *env)
2789 {
2790 #if !defined(CONFIG_USER_ONLY)
2791 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2792 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2793 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2794 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2795 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2796 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2797 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2798 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2799 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2800 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2801 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2802 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2803 /* Hardware reset vector */
2804 env->hreset_vector = 0x00000100UL;
2805 #endif
2806 }
2807
2808 static void init_excp_602 (CPUPPCState *env)
2809 {
2810 #if !defined(CONFIG_USER_ONLY)
2811 /* XXX: exception prefix has a special behavior on 602 */
2812 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2813 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2814 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2815 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2816 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2817 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2818 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2819 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2820 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2821 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2822 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2823 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2824 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2825 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2826 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2827 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2828 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2829 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2830 /* Hardware reset vector */
2831 env->hreset_vector = 0x00000100UL;
2832 #endif
2833 }
2834
2835 static void init_excp_603 (CPUPPCState *env)
2836 {
2837 #if !defined(CONFIG_USER_ONLY)
2838 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2839 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2840 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2841 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2842 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2843 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2844 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2845 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2847 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2848 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2849 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2850 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2851 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2852 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2853 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2854 /* Hardware reset vector */
2855 env->hreset_vector = 0x00000100UL;
2856 #endif
2857 }
2858
2859 static void init_excp_604 (CPUPPCState *env)
2860 {
2861 #if !defined(CONFIG_USER_ONLY)
2862 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2863 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2864 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2865 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2866 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2867 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2868 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2869 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2870 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2871 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2872 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2873 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2874 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2875 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2876 /* Hardware reset vector */
2877 env->hreset_vector = 0x00000100UL;
2878 #endif
2879 }
2880
2881 static void init_excp_7x0 (CPUPPCState *env)
2882 {
2883 #if !defined(CONFIG_USER_ONLY)
2884 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2885 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2886 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2887 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2888 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2889 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2890 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2891 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2892 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2893 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2894 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2895 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2896 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2897 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2898 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2899 /* Hardware reset vector */
2900 env->hreset_vector = 0x00000100UL;
2901 #endif
2902 }
2903
2904 static void init_excp_750cl (CPUPPCState *env)
2905 {
2906 #if !defined(CONFIG_USER_ONLY)
2907 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2908 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2909 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2910 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2911 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2912 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2913 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2914 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2915 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2916 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2917 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2918 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2919 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2920 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2921 /* Hardware reset vector */
2922 env->hreset_vector = 0x00000100UL;
2923 #endif
2924 }
2925
2926 static void init_excp_750cx (CPUPPCState *env)
2927 {
2928 #if !defined(CONFIG_USER_ONLY)
2929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2940 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2941 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2942 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2943 /* Hardware reset vector */
2944 env->hreset_vector = 0x00000100UL;
2945 #endif
2946 }
2947
2948 /* XXX: Check if this is correct */
2949 static void init_excp_7x5 (CPUPPCState *env)
2950 {
2951 #if !defined(CONFIG_USER_ONLY)
2952 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2953 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2954 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2955 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2956 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2957 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2958 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2959 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2960 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2961 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2962 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2963 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2964 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2965 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2966 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2967 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2968 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2969 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2970 /* Hardware reset vector */
2971 env->hreset_vector = 0x00000100UL;
2972 #endif
2973 }
2974
2975 static void init_excp_7400 (CPUPPCState *env)
2976 {
2977 #if !defined(CONFIG_USER_ONLY)
2978 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2979 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2980 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2981 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2982 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2983 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2984 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2985 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2986 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2987 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2988 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2989 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2990 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2991 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2992 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2993 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2994 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2995 /* Hardware reset vector */
2996 env->hreset_vector = 0x00000100UL;
2997 #endif
2998 }
2999
3000 static void init_excp_7450 (CPUPPCState *env)
3001 {
3002 #if !defined(CONFIG_USER_ONLY)
3003 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3004 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3005 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3006 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3007 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3008 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3009 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3010 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3011 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3012 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3013 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3014 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3015 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3016 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3017 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3018 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3019 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3020 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3021 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3022 /* Hardware reset vector */
3023 env->hreset_vector = 0x00000100UL;
3024 #endif
3025 }
3026
3027 #if defined (TARGET_PPC64)
3028 static void init_excp_970 (CPUPPCState *env)
3029 {
3030 #if !defined(CONFIG_USER_ONLY)
3031 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3032 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3033 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3034 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3035 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3036 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3037 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3038 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3039 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3040 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3041 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3042 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3043 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3044 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3045 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3046 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3047 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3048 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3049 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3050 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3051 /* Hardware reset vector */
3052 env->hreset_vector = 0x0000000000000100ULL;
3053 #endif
3054 }
3055
3056 static void init_excp_POWER7 (CPUPPCState *env)
3057 {
3058 #if !defined(CONFIG_USER_ONLY)
3059 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3060 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3061 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3062 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3063 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3064 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3065 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3066 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3067 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3068 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3069 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3070 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3071 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3072 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3073 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3074 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3075 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3076 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3077 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3078 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3079 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3080 /* Hardware reset vector */
3081 env->hreset_vector = 0x0000000000000100ULL;
3082 #endif
3083 }
3084 #endif
3085
3086 /*****************************************************************************/
3087 /* Power management enable checks */
3088 static int check_pow_none (CPUPPCState *env)
3089 {
3090 return 0;
3091 }
3092
3093 static int check_pow_nocheck (CPUPPCState *env)
3094 {
3095 return 1;
3096 }
3097
3098 static int check_pow_hid0 (CPUPPCState *env)
3099 {
3100 if (env->spr[SPR_HID0] & 0x00E00000)
3101 return 1;
3102
3103 return 0;
3104 }
3105
3106 static int check_pow_hid0_74xx (CPUPPCState *env)
3107 {
3108 if (env->spr[SPR_HID0] & 0x00600000)
3109 return 1;
3110
3111 return 0;
3112 }
3113
3114 /*****************************************************************************/
3115 /* PowerPC implementations definitions */
3116
3117 #define POWERPC_FAMILY(_name) \
3118 static void \
3119 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3120 \
3121 static const TypeInfo \
3122 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3123 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3124 .parent = TYPE_POWERPC_CPU, \
3125 .abstract = true, \
3126 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3127 }; \
3128 \
3129 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3130 { \
3131 type_register_static( \
3132 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3133 } \
3134 \
3135 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3136 \
3137 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3138
3139 static void init_proc_401 (CPUPPCState *env)
3140 {
3141 gen_spr_40x(env);
3142 gen_spr_401_403(env);
3143 gen_spr_401(env);
3144 init_excp_4xx_real(env);
3145 env->dcache_line_size = 32;
3146 env->icache_line_size = 32;
3147 /* Allocate hardware IRQ controller */
3148 ppc40x_irq_init(env);
3149
3150 SET_FIT_PERIOD(12, 16, 20, 24);
3151 SET_WDT_PERIOD(16, 20, 24, 28);
3152 }
3153
3154 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3155 {
3156 DeviceClass *dc = DEVICE_CLASS(oc);
3157 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3158
3159 dc->desc = "PowerPC 401";
3160 pcc->init_proc = init_proc_401;
3161 pcc->check_pow = check_pow_nocheck;
3162 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3163 PPC_WRTEE | PPC_DCR |
3164 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3165 PPC_CACHE_DCBZ |
3166 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3167 PPC_4xx_COMMON | PPC_40x_EXCP;
3168 pcc->msr_mask = (1ull << MSR_KEY) |
3169 (1ull << MSR_POW) |
3170 (1ull << MSR_CE) |
3171 (1ull << MSR_ILE) |
3172 (1ull << MSR_EE) |
3173 (1ull << MSR_PR) |
3174 (1ull << MSR_ME) |
3175 (1ull << MSR_DE) |
3176 (1ull << MSR_LE);
3177 pcc->mmu_model = POWERPC_MMU_REAL;
3178 pcc->excp_model = POWERPC_EXCP_40x;
3179 pcc->bus_model = PPC_FLAGS_INPUT_401;
3180 pcc->bfd_mach = bfd_mach_ppc_403;
3181 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3182 POWERPC_FLAG_BUS_CLK;
3183 }
3184
3185 static void init_proc_401x2 (CPUPPCState *env)
3186 {
3187 gen_spr_40x(env);
3188 gen_spr_401_403(env);
3189 gen_spr_401x2(env);
3190 gen_spr_compress(env);
3191 /* Memory management */
3192 #if !defined(CONFIG_USER_ONLY)
3193 env->nb_tlb = 64;
3194 env->nb_ways = 1;
3195 env->id_tlbs = 0;
3196 env->tlb_type = TLB_EMB;
3197 #endif
3198 init_excp_4xx_softmmu(env);
3199 env->dcache_line_size = 32;
3200 env->icache_line_size = 32;
3201 /* Allocate hardware IRQ controller */
3202 ppc40x_irq_init(env);
3203
3204 SET_FIT_PERIOD(12, 16, 20, 24);
3205 SET_WDT_PERIOD(16, 20, 24, 28);
3206 }
3207
3208 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3209 {
3210 DeviceClass *dc = DEVICE_CLASS(oc);
3211 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3212
3213 dc->desc = "PowerPC 401x2";
3214 pcc->init_proc = init_proc_401x2;
3215 pcc->check_pow = check_pow_nocheck;
3216 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3217 PPC_DCR | PPC_WRTEE |
3218 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3219 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3220 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3221 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3222 PPC_4xx_COMMON | PPC_40x_EXCP;
3223 pcc->msr_mask = (1ull << 20) |
3224 (1ull << MSR_KEY) |
3225 (1ull << MSR_POW) |
3226 (1ull << MSR_CE) |
3227 (1ull << MSR_ILE) |
3228 (1ull << MSR_EE) |
3229 (1ull << MSR_PR) |
3230 (1ull << MSR_ME) |
3231 (1ull << MSR_DE) |
3232 (1ull << MSR_IR) |
3233 (1ull << MSR_DR) |
3234 (1ull << MSR_LE);
3235 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3236 pcc->excp_model = POWERPC_EXCP_40x;
3237 pcc->bus_model = PPC_FLAGS_INPUT_401;
3238 pcc->bfd_mach = bfd_mach_ppc_403;
3239 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3240 POWERPC_FLAG_BUS_CLK;
3241 }
3242
3243 static void init_proc_401x3 (CPUPPCState *env)
3244 {
3245 gen_spr_40x(env);
3246 gen_spr_401_403(env);
3247 gen_spr_401(env);
3248 gen_spr_401x2(env);
3249 gen_spr_compress(env);
3250 init_excp_4xx_softmmu(env);
3251 env->dcache_line_size = 32;
3252 env->icache_line_size = 32;
3253 /* Allocate hardware IRQ controller */
3254 ppc40x_irq_init(env);
3255
3256 SET_FIT_PERIOD(12, 16, 20, 24);
3257 SET_WDT_PERIOD(16, 20, 24, 28);
3258 }
3259
3260 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3261 {
3262 DeviceClass *dc = DEVICE_CLASS(oc);
3263 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3264
3265 dc->desc = "PowerPC 401x3";
3266 pcc->init_proc = init_proc_401x3;
3267 pcc->check_pow = check_pow_nocheck;
3268 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3269 PPC_DCR | PPC_WRTEE |
3270 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3271 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3272 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3273 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3274 PPC_4xx_COMMON | PPC_40x_EXCP;
3275 pcc->msr_mask = (1ull << 20) |
3276 (1ull << MSR_KEY) |
3277 (1ull << MSR_POW) |
3278 (1ull << MSR_CE) |
3279 (1ull << MSR_ILE) |
3280 (1ull << MSR_EE) |
3281 (1ull << MSR_PR) |
3282 (1ull << MSR_ME) |
3283 (1ull << MSR_DWE) |
3284 (1ull << MSR_DE) |
3285 (1ull << MSR_IR) |
3286 (1ull << MSR_DR) |
3287 (1ull << MSR_LE);
3288 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3289 pcc->excp_model = POWERPC_EXCP_40x;
3290 pcc->bus_model = PPC_FLAGS_INPUT_401;
3291 pcc->bfd_mach = bfd_mach_ppc_403;
3292 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3293 POWERPC_FLAG_BUS_CLK;
3294 }
3295
3296 static void init_proc_IOP480 (CPUPPCState *env)
3297 {
3298 gen_spr_40x(env);
3299 gen_spr_401_403(env);
3300 gen_spr_401x2(env);
3301 gen_spr_compress(env);
3302 /* Memory management */
3303 #if !defined(CONFIG_USER_ONLY)
3304 env->nb_tlb = 64;
3305 env->nb_ways = 1;
3306 env->id_tlbs = 0;
3307 env->tlb_type = TLB_EMB;
3308 #endif
3309 init_excp_4xx_softmmu(env);
3310 env->dcache_line_size = 32;
3311 env->icache_line_size = 32;
3312 /* Allocate hardware IRQ controller */
3313 ppc40x_irq_init(env);
3314
3315 SET_FIT_PERIOD(8, 12, 16, 20);
3316 SET_WDT_PERIOD(16, 20, 24, 28);
3317 }
3318
3319 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3320 {
3321 DeviceClass *dc = DEVICE_CLASS(oc);
3322 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3323
3324 dc->desc = "IOP480";
3325 pcc->init_proc = init_proc_IOP480;
3326 pcc->check_pow = check_pow_nocheck;
3327 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3328 PPC_DCR | PPC_WRTEE |
3329 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3330 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3331 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3332 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3333 PPC_4xx_COMMON | PPC_40x_EXCP;
3334 pcc->msr_mask = (1ull << 20) |
3335 (1ull << MSR_KEY) |
3336 (1ull << MSR_POW) |
3337 (1ull << MSR_CE) |
3338 (1ull << MSR_ILE) |
3339 (1ull << MSR_EE) |
3340 (1ull << MSR_PR) |
3341 (1ull << MSR_ME) |
3342 (1ull << MSR_DE) |
3343 (1ull << MSR_IR) |
3344 (1ull << MSR_DR) |
3345 (1ull << MSR_LE);
3346 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3347 pcc->excp_model = POWERPC_EXCP_40x;
3348 pcc->bus_model = PPC_FLAGS_INPUT_401;
3349 pcc->bfd_mach = bfd_mach_ppc_403;
3350 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3351 POWERPC_FLAG_BUS_CLK;
3352 }
3353
3354 static void init_proc_403 (CPUPPCState *env)
3355 {
3356 gen_spr_40x(env);
3357 gen_spr_401_403(env);
3358 gen_spr_403(env);
3359 gen_spr_403_real(env);
3360 init_excp_4xx_real(env);
3361 env->dcache_line_size = 32;
3362 env->icache_line_size = 32;
3363 /* Allocate hardware IRQ controller */
3364 ppc40x_irq_init(env);
3365
3366 SET_FIT_PERIOD(8, 12, 16, 20);
3367 SET_WDT_PERIOD(16, 20, 24, 28);
3368 }
3369
3370 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3371 {
3372 DeviceClass *dc = DEVICE_CLASS(oc);
3373 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3374
3375 dc->desc = "PowerPC 403";
3376 pcc->init_proc = init_proc_403;
3377 pcc->check_pow = check_pow_nocheck;
3378 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3379 PPC_DCR | PPC_WRTEE |
3380 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3381 PPC_CACHE_DCBZ |
3382 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3383 PPC_4xx_COMMON | PPC_40x_EXCP;
3384 pcc->msr_mask = (1ull << MSR_POW) |
3385 (1ull << MSR_CE) |
3386 (1ull << MSR_ILE) |
3387 (1ull << MSR_EE) |
3388 (1ull << MSR_PR) |
3389 (1ull << MSR_ME) |
3390 (1ull << MSR_PE) |
3391 (1ull << MSR_PX) |
3392 (1ull << MSR_LE);
3393 pcc->mmu_model = POWERPC_MMU_REAL;
3394 pcc->excp_model = POWERPC_EXCP_40x;
3395 pcc->bus_model = PPC_FLAGS_INPUT_401;
3396 pcc->bfd_mach = bfd_mach_ppc_403;
3397 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3398 POWERPC_FLAG_BUS_CLK;
3399 }
3400
3401 static void init_proc_403GCX (CPUPPCState *env)
3402 {
3403 gen_spr_40x(env);
3404 gen_spr_401_403(env);
3405 gen_spr_403(env);
3406 gen_spr_403_real(env);
3407 gen_spr_403_mmu(env);
3408 /* Bus access control */
3409 /* not emulated, as QEMU never does speculative access */
3410 spr_register(env, SPR_40x_SGR, "SGR",
3411 SPR_NOACCESS, SPR_NOACCESS,
3412 &spr_read_generic, &spr_write_generic,
3413 0xFFFFFFFF);
3414 /* not emulated, as QEMU do not emulate caches */
3415 spr_register(env, SPR_40x_DCWR, "DCWR",
3416 SPR_NOACCESS, SPR_NOACCESS,
3417 &spr_read_generic, &spr_write_generic,
3418 0x00000000);
3419 /* Memory management */
3420 #if !defined(CONFIG_USER_ONLY)
3421 env->nb_tlb = 64;
3422 env->nb_ways = 1;
3423 env->id_tlbs = 0;
3424 env->tlb_type = TLB_EMB;
3425 #endif
3426 init_excp_4xx_softmmu(env);
3427 env->dcache_line_size = 32;
3428 env->icache_line_size = 32;
3429 /* Allocate hardware IRQ controller */
3430 ppc40x_irq_init(env);
3431
3432 SET_FIT_PERIOD(8, 12, 16, 20);
3433 SET_WDT_PERIOD(16, 20, 24, 28);
3434 }
3435
3436 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3437 {
3438 DeviceClass *dc = DEVICE_CLASS(oc);
3439 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3440
3441 dc->desc = "PowerPC 403 GCX";
3442 pcc->init_proc = init_proc_403GCX;
3443 pcc->check_pow = check_pow_nocheck;
3444 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3445 PPC_DCR | PPC_WRTEE |
3446 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3447 PPC_CACHE_DCBZ |
3448 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3449 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3450 PPC_4xx_COMMON | PPC_40x_EXCP;
3451 pcc->msr_mask = (1ull << MSR_POW) |
3452 (1ull << MSR_CE) |
3453 (1ull << MSR_ILE) |
3454 (1ull << MSR_EE) |
3455 (1ull << MSR_PR) |
3456 (1ull << MSR_ME) |
3457 (1ull << MSR_PE) |
3458 (1ull << MSR_PX) |
3459 (1ull << MSR_LE);
3460 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3461 pcc->excp_model = POWERPC_EXCP_40x;
3462 pcc->bus_model = PPC_FLAGS_INPUT_401;
3463 pcc->bfd_mach = bfd_mach_ppc_403;
3464 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3465 POWERPC_FLAG_BUS_CLK;
3466 }
3467
3468 static void init_proc_405 (CPUPPCState *env)
3469 {
3470 /* Time base */
3471 gen_tbl(env);
3472 gen_spr_40x(env);
3473 gen_spr_405(env);
3474 /* Bus access control */
3475 /* not emulated, as QEMU never does speculative access */
3476 spr_register(env, SPR_40x_SGR, "SGR",
3477 SPR_NOACCESS, SPR_NOACCESS,
3478 &spr_read_generic, &spr_write_generic,
3479 0xFFFFFFFF);
3480 /* not emulated, as QEMU do not emulate caches */
3481 spr_register(env, SPR_40x_DCWR, "DCWR",
3482 SPR_NOACCESS, SPR_NOACCESS,
3483 &spr_read_generic, &spr_write_generic,
3484 0x00000000);
3485 /* Memory management */
3486 #if !defined(CONFIG_USER_ONLY)
3487 env->nb_tlb = 64;
3488 env->nb_ways = 1;
3489 env->id_tlbs = 0;
3490 env->tlb_type = TLB_EMB;
3491 #endif
3492 init_excp_4xx_softmmu(env);
3493 env->dcache_line_size = 32;
3494 env->icache_line_size = 32;
3495 /* Allocate hardware IRQ controller */
3496 ppc40x_irq_init(env);
3497
3498 SET_FIT_PERIOD(8, 12, 16, 20);
3499 SET_WDT_PERIOD(16, 20, 24, 28);
3500 }
3501
3502 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3503 {
3504 DeviceClass *dc = DEVICE_CLASS(oc);
3505 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3506
3507 dc->desc = "PowerPC 405";
3508 pcc->init_proc = init_proc_405;
3509 pcc->check_pow = check_pow_nocheck;
3510 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3511 PPC_DCR | PPC_WRTEE |
3512 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3513 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3514 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3515 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3516 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3517 pcc->msr_mask = (1ull << MSR_POW) |
3518 (1ull << MSR_CE) |
3519 (1ull << MSR_EE) |
3520 (1ull << MSR_PR) |
3521 (1ull << MSR_FP) |
3522 (1ull << MSR_DWE) |
3523 (1ull << MSR_DE) |
3524 (1ull << MSR_IR) |
3525 (1ull << MSR_DR);
3526 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3527 pcc->excp_model = POWERPC_EXCP_40x;
3528 pcc->bus_model = PPC_FLAGS_INPUT_405;
3529 pcc->bfd_mach = bfd_mach_ppc_403;
3530 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3531 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3532 }
3533
3534 static void init_proc_440EP (CPUPPCState *env)
3535 {
3536 /* Time base */
3537 gen_tbl(env);
3538 gen_spr_BookE(env, 0x000000000000FFFFULL);
3539 gen_spr_440(env);
3540 gen_spr_usprgh(env);
3541 /* Processor identification */
3542 spr_register(env, SPR_BOOKE_PIR, "PIR",
3543 SPR_NOACCESS, SPR_NOACCESS,
3544 &spr_read_generic, &spr_write_pir,
3545 0x00000000);
3546 /* XXX : not implemented */
3547 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3548 SPR_NOACCESS, SPR_NOACCESS,
3549 &spr_read_generic, &spr_write_generic,
3550 0x00000000);
3551 /* XXX : not implemented */
3552 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3553 SPR_NOACCESS, SPR_NOACCESS,
3554 &spr_read_generic, &spr_write_generic,
3555 0x00000000);
3556 /* XXX : not implemented */
3557 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3558 SPR_NOACCESS, SPR_NOACCESS,
3559 &spr_read_generic, &spr_write_generic,
3560 0x00000000);
3561 /* XXX : not implemented */
3562 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3563 SPR_NOACCESS, SPR_NOACCESS,
3564 &spr_read_generic, &spr_write_generic,
3565 0x00000000);
3566 /* XXX : not implemented */
3567 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3568 SPR_NOACCESS, SPR_NOACCESS,
3569 &spr_read_generic, &spr_write_generic,
3570 0x00000000);
3571 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3572 SPR_NOACCESS, SPR_NOACCESS,
3573 &spr_read_generic, &spr_write_generic,
3574 0x00000000);
3575 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3576 SPR_NOACCESS, SPR_NOACCESS,
3577 &spr_read_generic, &spr_write_generic,
3578 0x00000000);
3579 /* XXX : not implemented */
3580 spr_register(env, SPR_440_CCR1, "CCR1",
3581 SPR_NOACCESS, SPR_NOACCESS,
3582 &spr_read_generic, &spr_write_generic,
3583 0x00000000);
3584 /* Memory management */
3585 #if !defined(CONFIG_USER_ONLY)
3586 env->nb_tlb = 64;
3587 env->nb_ways = 1;
3588 env->id_tlbs = 0;
3589 env->tlb_type = TLB_EMB;
3590 #endif
3591 init_excp_BookE(env);
3592 env->dcache_line_size = 32;
3593 env->icache_line_size = 32;
3594 ppc40x_irq_init(env);
3595
3596 SET_FIT_PERIOD(12, 16, 20, 24);
3597 SET_WDT_PERIOD(20, 24, 28, 32);
3598 }
3599
3600 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3601 {
3602 DeviceClass *dc = DEVICE_CLASS(oc);
3603 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3604
3605 dc->desc = "PowerPC 440 EP";
3606 pcc->init_proc = init_proc_440EP;
3607 pcc->check_pow = check_pow_nocheck;
3608 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3609 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3610 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3611 PPC_FLOAT_STFIWX |
3612 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3613 PPC_CACHE | PPC_CACHE_ICBI |
3614 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3615 PPC_MEM_TLBSYNC | PPC_MFTB |
3616 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3617 PPC_440_SPEC;
3618 pcc->msr_mask = (1ull << MSR_POW) |
3619 (1ull << MSR_CE) |
3620 (1ull << MSR_EE) |
3621 (1ull << MSR_PR) |
3622 (1ull << MSR_FP) |
3623 (1ull << MSR_ME) |
3624 (1ull << MSR_FE0) |
3625 (1ull << MSR_DWE) |
3626 (1ull << MSR_DE) |
3627 (1ull << MSR_FE1) |
3628 (1ull << MSR_IR) |
3629 (1ull << MSR_DR);
3630 pcc->mmu_model = POWERPC_MMU_BOOKE;
3631 pcc->excp_model = POWERPC_EXCP_BOOKE;
3632 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3633 pcc->bfd_mach = bfd_mach_ppc_403;
3634 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3635 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3636 }
3637
3638 static void init_proc_440GP (CPUPPCState *env)
3639 {
3640 /* Time base */
3641 gen_tbl(env);
3642 gen_spr_BookE(env, 0x000000000000FFFFULL);
3643 gen_spr_440(env);
3644 gen_spr_usprgh(env);
3645 /* Processor identification */
3646 spr_register(env, SPR_BOOKE_PIR, "PIR",
3647 SPR_NOACCESS, SPR_NOACCESS,
3648 &spr_read_generic, &spr_write_pir,
3649 0x00000000);
3650 /* XXX : not implemented */
3651 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3652 SPR_NOACCESS, SPR_NOACCESS,
3653 &spr_read_generic, &spr_write_generic,
3654 0x00000000);
3655 /* XXX : not implemented */
3656 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_generic,
3659 0x00000000);
3660 /* XXX : not implemented */
3661 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_generic,
3664 0x00000000);
3665 /* XXX : not implemented */
3666 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
3670 /* Memory management */
3671 #if !defined(CONFIG_USER_ONLY)
3672 env->nb_tlb = 64;
3673 env->nb_ways = 1;
3674 env->id_tlbs = 0;
3675 env->tlb_type = TLB_EMB;
3676 #endif
3677 init_excp_BookE(env);
3678 env->dcache_line_size = 32;
3679 env->icache_line_size = 32;
3680 /* XXX: TODO: allocate internal IRQ controller */
3681
3682 SET_FIT_PERIOD(12, 16, 20, 24);
3683 SET_WDT_PERIOD(20, 24, 28, 32);
3684 }
3685
3686 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3687 {
3688 DeviceClass *dc = DEVICE_CLASS(oc);
3689 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3690
3691 dc->desc = "PowerPC 440 GP";
3692 pcc->init_proc = init_proc_440GP;
3693 pcc->check_pow = check_pow_nocheck;
3694 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3695 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3696 PPC_CACHE | PPC_CACHE_ICBI |
3697 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3698 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3699 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3700 PPC_440_SPEC;
3701 pcc->msr_mask = (1ull << MSR_POW) |
3702 (1ull << MSR_CE) |
3703 (1ull << MSR_EE) |
3704 (1ull << MSR_PR) |
3705 (1ull << MSR_FP) |
3706 (1ull << MSR_ME) |
3707 (1ull << MSR_FE0) |
3708 (1ull << MSR_DWE) |
3709 (1ull << MSR_DE) |
3710 (1ull << MSR_FE1) |
3711 (1ull << MSR_IR) |
3712 (1ull << MSR_DR);
3713 pcc->mmu_model = POWERPC_MMU_BOOKE;
3714 pcc->excp_model = POWERPC_EXCP_BOOKE;
3715 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3716 pcc->bfd_mach = bfd_mach_ppc_403;
3717 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3718 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3719 }
3720
3721 static void init_proc_440x4 (CPUPPCState *env)
3722 {
3723 /* Time base */
3724 gen_tbl(env);
3725 gen_spr_BookE(env, 0x000000000000FFFFULL);
3726 gen_spr_440(env);
3727 gen_spr_usprgh(env);
3728 /* Processor identification */
3729 spr_register(env, SPR_BOOKE_PIR, "PIR",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_pir,
3732 0x00000000);
3733 /* XXX : not implemented */
3734 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3735 SPR_NOACCESS, SPR_NOACCESS,
3736 &spr_read_generic, &spr_write_generic,
3737 0x00000000);
3738 /* XXX : not implemented */
3739 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3740 SPR_NOACCESS, SPR_NOACCESS,
3741 &spr_read_generic, &spr_write_generic,
3742 0x00000000);
3743 /* XXX : not implemented */
3744 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3745 SPR_NOACCESS, SPR_NOACCESS,
3746 &spr_read_generic, &spr_write_generic,
3747 0x00000000);
3748 /* XXX : not implemented */
3749 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3750 SPR_NOACCESS, SPR_NOACCESS,
3751 &spr_read_generic, &spr_write_generic,
3752 0x00000000);
3753 /* Memory management */
3754 #if !defined(CONFIG_USER_ONLY)
3755 env->nb_tlb = 64;
3756 env->nb_ways = 1;
3757 env->id_tlbs = 0;
3758 env->tlb_type = TLB_EMB;
3759 #endif
3760 init_excp_BookE(env);
3761 env->dcache_line_size = 32;
3762 env->icache_line_size = 32;
3763 /* XXX: TODO: allocate internal IRQ controller */
3764
3765 SET_FIT_PERIOD(12, 16, 20, 24);
3766 SET_WDT_PERIOD(20, 24, 28, 32);
3767 }
3768
3769 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3770 {
3771 DeviceClass *dc = DEVICE_CLASS(oc);
3772 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3773
3774 dc->desc = "PowerPC 440x4";
3775 pcc->init_proc = init_proc_440x4;
3776 pcc->check_pow = check_pow_nocheck;
3777 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3778 PPC_DCR | PPC_WRTEE |
3779 PPC_CACHE | PPC_CACHE_ICBI |
3780 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3781 PPC_MEM_TLBSYNC | PPC_MFTB |
3782 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3783 PPC_440_SPEC;
3784 pcc->msr_mask = (1ull << MSR_POW) |
3785 (1ull << MSR_CE) |
3786 (1ull << MSR_EE) |
3787 (1ull << MSR_PR) |
3788 (1ull << MSR_FP) |
3789 (1ull << MSR_ME) |
3790 (1ull << MSR_FE0) |
3791 (1ull << MSR_DWE) |
3792 (1ull << MSR_DE) |
3793 (1ull << MSR_FE1) |
3794 (1ull << MSR_IR) |
3795 (1ull << MSR_DR);
3796 pcc->mmu_model = POWERPC_MMU_BOOKE;
3797 pcc->excp_model = POWERPC_EXCP_BOOKE;
3798 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3799 pcc->bfd_mach = bfd_mach_ppc_403;
3800 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3801 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3802 }
3803
3804 static void init_proc_440x5 (CPUPPCState *env)
3805 {
3806 /* Time base */
3807 gen_tbl(env);
3808 gen_spr_BookE(env, 0x000000000000FFFFULL);
3809 gen_spr_440(env);
3810 gen_spr_usprgh(env);
3811 /* Processor identification */
3812 spr_register(env, SPR_BOOKE_PIR, "PIR",
3813 SPR_NOACCESS, SPR_NOACCESS,
3814 &spr_read_generic, &spr_write_pir,
3815 0x00000000);
3816 /* XXX : not implemented */
3817 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3818 SPR_NOACCESS, SPR_NOACCESS,
3819 &spr_read_generic, &spr_write_generic,
3820 0x00000000);
3821 /* XXX : not implemented */
3822 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3823 SPR_NOACCESS, SPR_NOACCESS,
3824 &spr_read_generic, &spr_write_generic,
3825 0x00000000);
3826 /* XXX : not implemented */
3827 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_generic,
3830 0x00000000);
3831 /* XXX : not implemented */
3832 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3833 SPR_NOACCESS, SPR_NOACCESS,
3834 &spr_read_generic, &spr_write_generic,
3835 0x00000000);
3836 /* XXX : not implemented */
3837 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3838 SPR_NOACCESS, SPR_NOACCESS,
3839 &spr_read_generic, &spr_write_generic,
3840 0x00000000);
3841 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3842 SPR_NOACCESS, SPR_NOACCESS,
3843 &spr_read_generic, &spr_write_generic,
3844 0x00000000);
3845 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3846 SPR_NOACCESS, SPR_NOACCESS,
3847 &spr_read_generic, &spr_write_generic,
3848 0x00000000);
3849 /* XXX : not implemented */
3850 spr_register(env, SPR_440_CCR1, "CCR1",
3851 SPR_NOACCESS, SPR_NOACCESS,
3852 &spr_read_generic, &spr_write_generic,
3853 0x00000000);
3854 /* Memory management */
3855 #if !defined(CONFIG_USER_ONLY)
3856 env->nb_tlb = 64;
3857 env->nb_ways = 1;
3858 env->id_tlbs = 0;
3859 env->tlb_type = TLB_EMB;
3860 #endif
3861 init_excp_BookE(env);
3862 env->dcache_line_size = 32;
3863 env->icache_line_size = 32;
3864 ppc40x_irq_init(env);
3865
3866 SET_FIT_PERIOD(12, 16, 20, 24);
3867 SET_WDT_PERIOD(20, 24, 28, 32);
3868 }
3869
3870 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3871 {
3872 DeviceClass *dc = DEVICE_CLASS(oc);
3873 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3874
3875 dc->desc = "PowerPC 440x5";
3876 pcc->init_proc = init_proc_440x5;
3877 pcc->check_pow = check_pow_nocheck;
3878 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3879 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3880 PPC_CACHE | PPC_CACHE_ICBI |
3881 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3882 PPC_MEM_TLBSYNC | PPC_MFTB |
3883 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3884 PPC_440_SPEC;
3885 pcc->msr_mask = (1ull << MSR_POW) |
3886 (1ull << MSR_CE) |
3887 (1ull << MSR_EE) |
3888 (1ull << MSR_PR) |
3889 (1ull << MSR_FP) |
3890 (1ull << MSR_ME) |
3891 (1ull << MSR_FE0) |
3892 (1ull << MSR_DWE) |
3893 (1ull << MSR_DE) |
3894 (1ull << MSR_FE1) |
3895 (1ull << MSR_IR) |
3896 (1ull << MSR_DR);
3897 pcc->mmu_model = POWERPC_MMU_BOOKE;
3898 pcc->excp_model = POWERPC_EXCP_BOOKE;
3899 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3900 pcc->bfd_mach = bfd_mach_ppc_403;
3901 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3902 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3903 }
3904
3905 static void init_proc_460 (CPUPPCState *env)
3906 {
3907 /* Time base */
3908 gen_tbl(env);
3909 gen_spr_BookE(env, 0x000000000000FFFFULL);
3910 gen_spr_440(env);
3911 gen_spr_usprgh(env);
3912 /* Processor identification */
3913 spr_register(env, SPR_BOOKE_PIR, "PIR",
3914 SPR_NOACCESS, SPR_NOACCESS,
3915 &spr_read_generic, &spr_write_pir,
3916 0x00000000);
3917 /* XXX : not implemented */
3918 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3919 SPR_NOACCESS, SPR_NOACCESS,
3920 &spr_read_generic, &spr_write_generic,
3921 0x00000000);
3922 /* XXX : not implemented */
3923 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3924 SPR_NOACCESS, SPR_NOACCESS,
3925 &spr_read_generic, &spr_write_generic,
3926 0x00000000);
3927 /* XXX : not implemented */
3928 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3929 SPR_NOACCESS, SPR_NOACCESS,
3930 &spr_read_generic, &spr_write_generic,
3931 0x00000000);
3932 /* XXX : not implemented */
3933 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3934 SPR_NOACCESS, SPR_NOACCESS,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
3937 /* XXX : not implemented */
3938 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3939 SPR_NOACCESS, SPR_NOACCESS,
3940 &spr_read_generic, &spr_write_generic,
3941 0x00000000);
3942 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3943 SPR_NOACCESS, SPR_NOACCESS,
3944 &spr_read_generic, &spr_write_generic,
3945 0x00000000);
3946 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3947 SPR_NOACCESS, SPR_NOACCESS,
3948 &spr_read_generic, &spr_write_generic,
3949 0x00000000);
3950 /* XXX : not implemented */
3951 spr_register(env, SPR_440_CCR1, "CCR1",
3952 SPR_NOACCESS, SPR_NOACCESS,
3953 &spr_read_generic, &spr_write_generic,
3954 0x00000000);
3955 /* XXX : not implemented */
3956 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3957 &spr_read_generic, &spr_write_generic,
3958 &spr_read_generic, &spr_write_generic,
3959 0x00000000);
3960 /* Memory management */
3961 #if !defined(CONFIG_USER_ONLY)
3962 env->nb_tlb = 64;
3963 env->nb_ways = 1;
3964 env->id_tlbs = 0;
3965 env->tlb_type = TLB_EMB;
3966 #endif
3967 init_excp_BookE(env);
3968 env->dcache_line_size = 32;
3969 env->icache_line_size = 32;
3970 /* XXX: TODO: allocate internal IRQ controller */
3971
3972 SET_FIT_PERIOD(12, 16, 20, 24);
3973 SET_WDT_PERIOD(20, 24, 28, 32);
3974 }
3975
3976 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3977 {
3978 DeviceClass *dc = DEVICE_CLASS(oc);
3979 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3980
3981 dc->desc = "PowerPC 460 (guessed)";
3982 pcc->init_proc = init_proc_460;
3983 pcc->check_pow = check_pow_nocheck;
3984 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3985 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3986 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3987 PPC_CACHE | PPC_CACHE_ICBI |
3988 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3989 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3990 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3991 PPC_440_SPEC;
3992 pcc->msr_mask = (1ull << MSR_POW) |
3993 (1ull << MSR_CE) |
3994 (1ull << MSR_EE) |
3995 (1ull << MSR_PR) |
3996 (1ull << MSR_FP) |
3997 (1ull << MSR_ME) |
3998 (1ull << MSR_FE0) |
3999 (1ull << MSR_DWE) |
4000 (1ull << MSR_DE) |
4001 (1ull << MSR_FE1) |
4002 (1ull << MSR_IR) |
4003 (1ull << MSR_DR);
4004 pcc->mmu_model = POWERPC_MMU_BOOKE;
4005 pcc->excp_model = POWERPC_EXCP_BOOKE;
4006 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4007 pcc->bfd_mach = bfd_mach_ppc_403;
4008 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4009 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4010 }
4011
4012 static void init_proc_460F (CPUPPCState *env)
4013 {
4014 /* Time base */
4015 gen_tbl(env);
4016 gen_spr_BookE(env, 0x000000000000FFFFULL);
4017 gen_spr_440(env);
4018 gen_spr_usprgh(env);
4019 /* Processor identification */
4020 spr_register(env, SPR_BOOKE_PIR, "PIR",
4021 SPR_NOACCESS, SPR_NOACCESS,
4022 &spr_read_generic, &spr_write_pir,
4023 0x00000000);
4024 /* XXX : not implemented */
4025 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4026 SPR_NOACCESS, SPR_NOACCESS,
4027 &spr_read_generic, &spr_write_generic,
4028 0x00000000);
4029 /* XXX : not implemented */
4030 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4031 SPR_NOACCESS, SPR_NOACCESS,
4032 &spr_read_generic, &spr_write_generic,
4033 0x00000000);
4034 /* XXX : not implemented */
4035 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4036 SPR_NOACCESS, SPR_NOACCESS,
4037 &spr_read_generic, &spr_write_generic,
4038 0x00000000);
4039 /* XXX : not implemented */
4040 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4041 SPR_NOACCESS, SPR_NOACCESS,
4042 &spr_read_generic, &spr_write_generic,
4043 0x00000000);
4044 /* XXX : not implemented */
4045 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4046 SPR_NOACCESS, SPR_NOACCESS,
4047 &spr_read_generic, &spr_write_generic,
4048 0x00000000);
4049 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4050 SPR_NOACCESS, SPR_NOACCESS,
4051 &spr_read_generic, &spr_write_generic,
4052 0x00000000);
4053 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4054 SPR_NOACCESS, SPR_NOACCESS,
4055 &spr_read_generic, &spr_write_generic,
4056 0x00000000);
4057 /* XXX : not implemented */
4058 spr_register(env, SPR_440_CCR1, "CCR1",
4059 SPR_NOACCESS, SPR_NOACCESS,
4060 &spr_read_generic, &spr_write_generic,
4061 0x00000000);
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4064 &spr_read_generic, &spr_write_generic,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* Memory management */
4068 #if !defined(CONFIG_USER_ONLY)
4069 env->nb_tlb = 64;
4070 env->nb_ways = 1;
4071 env->id_tlbs = 0;
4072 env->tlb_type = TLB_EMB;
4073 #endif
4074 init_excp_BookE(env);
4075 env->dcache_line_size = 32;
4076 env->icache_line_size = 32;
4077 /* XXX: TODO: allocate internal IRQ controller */
4078
4079 SET_FIT_PERIOD(12, 16, 20, 24);
4080 SET_WDT_PERIOD(20, 24, 28, 32);
4081 }
4082
4083 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4084 {
4085 DeviceClass *dc = DEVICE_CLASS(oc);
4086 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4087
4088 dc->desc = "PowerPC 460F (guessed)";
4089 pcc->init_proc = init_proc_460F;
4090 pcc->check_pow = check_pow_nocheck;
4091 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4092 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4093 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4094 PPC_FLOAT_STFIWX | PPC_MFTB |
4095 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4096 PPC_WRTEE | PPC_MFAPIDI |
4097 PPC_CACHE | PPC_CACHE_ICBI |
4098 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4099 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4100 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4101 PPC_440_SPEC;
4102 pcc->msr_mask = (1ull << MSR_POW) |
4103 (1ull << MSR_CE) |
4104 (1ull << MSR_EE) |
4105 (1ull << MSR_PR) |
4106 (1ull << MSR_FP) |
4107 (1ull << MSR_ME) |
4108 (1ull << MSR_FE0) |
4109 (1ull << MSR_DWE) |
4110 (1ull << MSR_DE) |
4111 (1ull << MSR_FE1) |
4112 (1ull << MSR_IR) |
4113 (1ull << MSR_DR);
4114 pcc->mmu_model = POWERPC_MMU_BOOKE;
4115 pcc->excp_model = POWERPC_EXCP_BOOKE;
4116 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4117 pcc->bfd_mach = bfd_mach_ppc_403;
4118 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4119 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4120 }
4121
4122 static void init_proc_MPC5xx (CPUPPCState *env)
4123 {
4124 /* Time base */
4125 gen_tbl(env);
4126 gen_spr_5xx_8xx(env);
4127 gen_spr_5xx(env);
4128 init_excp_MPC5xx(env);
4129 env->dcache_line_size = 32;
4130 env->icache_line_size = 32;
4131 /* XXX: TODO: allocate internal IRQ controller */
4132 }
4133
4134 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4135 {
4136 DeviceClass *dc = DEVICE_CLASS(oc);
4137 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4138
4139 dc->desc = "Freescale 5xx cores (aka RCPU)";
4140 pcc->init_proc = init_proc_MPC5xx;
4141 pcc->check_pow = check_pow_none;
4142 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4143 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4144 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4145 PPC_MFTB;
4146 pcc->msr_mask = (1ull << MSR_ILE) |
4147 (1ull << MSR_EE) |
4148 (1ull << MSR_PR) |
4149 (1ull << MSR_FP) |
4150 (1ull << MSR_ME) |
4151 (1ull << MSR_FE0) |
4152 (1ull << MSR_SE) |
4153 (1ull << MSR_DE) |
4154 (1ull << MSR_FE1) |
4155 (1ull << MSR_EP) |
4156 (1ull << MSR_RI) |
4157 (1ull << MSR_LE);
4158 pcc->mmu_model = POWERPC_MMU_REAL;
4159 pcc->excp_model = POWERPC_EXCP_603;
4160 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4161 pcc->bfd_mach = bfd_mach_ppc_505;
4162 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4163 POWERPC_FLAG_BUS_CLK;
4164 }
4165
4166 static void init_proc_MPC8xx (CPUPPCState *env)
4167 {
4168 /* Time base */
4169 gen_tbl(env);
4170 gen_spr_5xx_8xx(env);
4171 gen_spr_8xx(env);
4172 init_excp_MPC8xx(env);
4173 env->dcache_line_size = 32;
4174 env->icache_line_size = 32;
4175 /* XXX: TODO: allocate internal IRQ controller */
4176 }
4177
4178 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4179 {
4180 DeviceClass *dc = DEVICE_CLASS(oc);
4181 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4182
4183 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4184 pcc->init_proc = init_proc_MPC8xx;
4185 pcc->check_pow = check_pow_none;
4186 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4187 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4188 PPC_CACHE_ICBI | PPC_MFTB;
4189 pcc->msr_mask = (1ull << MSR_ILE) |
4190 (1ull << MSR_EE) |
4191 (1ull << MSR_PR) |
4192 (1ull << MSR_FP) |
4193 (1ull << MSR_ME) |
4194 (1ull << MSR_SE) |
4195 (1ull << MSR_DE) |
4196 (1ull << MSR_EP) |
4197 (1ull << MSR_IR) |
4198 (1ull << MSR_DR) |
4199 (1ull << MSR_RI) |
4200 (1ull << MSR_LE);
4201 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4202 pcc->excp_model = POWERPC_EXCP_603;
4203 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4204 pcc->bfd_mach = bfd_mach_ppc_860;
4205 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4206 POWERPC_FLAG_BUS_CLK;
4207 }
4208
4209 /* Freescale 82xx cores (aka PowerQUICC-II) */
4210
4211 static void init_proc_G2 (CPUPPCState *env)
4212 {
4213 gen_spr_ne_601(env);
4214 gen_spr_G2_755(env);
4215 gen_spr_G2(env);
4216 /* Time base */
4217 gen_tbl(env);
4218 /* External access control */
4219 /* XXX : not implemented */
4220 spr_register(env, SPR_EAR, "EAR",
4221 SPR_NOACCESS, SPR_NOACCESS,
4222 &spr_read_generic, &spr_write_generic,
4223 0x00000000);
4224 /* Hardware implementation register */
4225 /* XXX : not implemented */
4226 spr_register(env, SPR_HID0, "HID0",
4227 SPR_NOACCESS, SPR_NOACCESS,
4228 &spr_read_generic, &spr_write_generic,
4229 0x00000000);
4230 /* XXX : not implemented */
4231 spr_register(env, SPR_HID1, "HID1",
4232 SPR_NOACCESS, SPR_NOACCESS,
4233 &spr_read_generic, &spr_write_generic,
4234 0x00000000);
4235 /* XXX : not implemented */
4236 spr_register(env, SPR_HID2, "HID2",
4237 SPR_NOACCESS, SPR_NOACCESS,
4238 &spr_read_generic, &spr_write_generic,
4239 0x00000000);
4240 /* Memory management */
4241 gen_low_BATs(env);
4242 gen_high_BATs(env);
4243 gen_6xx_7xx_soft_tlb(env, 64, 2);
4244 init_excp_G2(env);
4245 env->dcache_line_size = 32;
4246 env->icache_line_size = 32;
4247 /* Allocate hardware IRQ controller */
4248 ppc6xx_irq_init(env);
4249 }
4250
4251 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4252 {
4253 DeviceClass *dc = DEVICE_CLASS(oc);
4254 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4255
4256 dc->desc = "PowerPC G2";
4257 pcc->init_proc = init_proc_G2;
4258 pcc->check_pow = check_pow_hid0;
4259 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4260 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4261 PPC_FLOAT_STFIWX |
4262 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4263 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4264 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4265 PPC_SEGMENT | PPC_EXTERN;
4266 pcc->msr_mask = (1ull << MSR_POW) |
4267 (1ull << MSR_TGPR) |
4268 (1ull << MSR_EE) |
4269 (1ull << MSR_PR) |
4270 (1ull << MSR_FP) |
4271 (1ull << MSR_ME) |
4272 (1ull << MSR_FE0) |
4273 (1ull << MSR_SE) |
4274 (1ull << MSR_DE) |
4275 (1ull << MSR_FE1) |
4276 (1ull << MSR_AL) |
4277 (1ull << MSR_EP) |
4278 (1ull << MSR_IR) |
4279 (1ull << MSR_DR) |
4280 (1ull << MSR_RI);
4281 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4282 pcc->excp_model = POWERPC_EXCP_G2;
4283 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4284 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4285 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4286 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4287 }
4288
4289 static void init_proc_G2LE (CPUPPCState *env)
4290 {
4291 gen_spr_ne_601(env);
4292 gen_spr_G2_755(env);
4293 gen_spr_G2(env);
4294 /* Time base */
4295 gen_tbl(env);
4296 /* External access control */
4297 /* XXX : not implemented */
4298 spr_register(env, SPR_EAR, "EAR",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
4302 /* Hardware implementation register */
4303 /* XXX : not implemented */
4304 spr_register(env, SPR_HID0, "HID0",
4305 SPR_NOACCESS, SPR_NOACCESS,
4306 &spr_read_generic, &spr_write_generic,
4307 0x00000000);
4308 /* XXX : not implemented */
4309 spr_register(env, SPR_HID1, "HID1",
4310 SPR_NOACCESS, SPR_NOACCESS,
4311 &spr_read_generic, &spr_write_generic,
4312 0x00000000);
4313 /* XXX : not implemented */
4314 spr_register(env, SPR_HID2, "HID2",
4315 SPR_NOACCESS, SPR_NOACCESS,
4316 &spr_read_generic, &spr_write_generic,
4317 0x00000000);
4318 /* Breakpoints */
4319 /* XXX : not implemented */
4320 spr_register(env, SPR_DABR, "DABR",
4321 SPR_NOACCESS, SPR_NOACCESS,
4322 &spr_read_generic, &spr_write_generic,
4323 0x00000000);
4324 /* XXX : not implemented */
4325 spr_register(env, SPR_DABR2, "DABR2",
4326 SPR_NOACCESS, SPR_NOACCESS,
4327 &spr_read_generic, &spr_write_generic,
4328 0x00000000);
4329 /* XXX : not implemented */
4330 spr_register(env, SPR_IABR2, "IABR2",
4331 SPR_NOACCESS, SPR_NOACCESS,
4332 &spr_read_generic, &spr_write_generic,
4333 0x00000000);
4334 /* XXX : not implemented */
4335 spr_register(env, SPR_IBCR, "IBCR",
4336 SPR_NOACCESS, SPR_NOACCESS,
4337 &spr_read_generic, &spr_write_generic,
4338 0x00000000);
4339 /* XXX : not implemented */
4340 spr_register(env, SPR_DBCR, "DBCR",
4341 SPR_NOACCESS, SPR_NOACCESS,
4342 &spr_read_generic, &spr_write_generic,
4343 0x00000000);
4344
4345 /* Memory management */
4346 gen_low_BATs(env);
4347 gen_high_BATs(env);
4348 gen_6xx_7xx_soft_tlb(env, 64, 2);
4349 init_excp_G2(env);
4350 env->dcache_line_size = 32;
4351 env->icache_line_size = 32;
4352 /* Allocate hardware IRQ controller */
4353 ppc6xx_irq_init(env);
4354 }
4355
4356 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4357 {
4358 DeviceClass *dc = DEVICE_CLASS(oc);
4359 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4360
4361 dc->desc = "PowerPC G2LE";
4362 pcc->init_proc = init_proc_G2LE;
4363 pcc->check_pow = check_pow_hid0;
4364 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4365 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4366 PPC_FLOAT_STFIWX |
4367 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4368 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4369 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4370 PPC_SEGMENT | PPC_EXTERN;
4371 pcc->msr_mask = (1ull << MSR_POW) |
4372 (1ull << MSR_TGPR) |
4373 (1ull << MSR_ILE) |
4374 (1ull << MSR_EE) |
4375 (1ull << MSR_PR) |
4376 (1ull << MSR_FP) |
4377 (1ull << MSR_ME) |
4378 (1ull << MSR_FE0) |
4379 (1ull << MSR_SE) |
4380 (1ull << MSR_DE) |
4381 (1ull << MSR_FE1) |
4382 (1ull << MSR_AL) |
4383 (1ull << MSR_EP) |
4384 (1ull << MSR_IR) |
4385 (1ull << MSR_DR) |
4386 (1ull << MSR_RI) |
4387 (1ull << MSR_LE);
4388 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4389 pcc->excp_model = POWERPC_EXCP_G2;
4390 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4391 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4392 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4393 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4394 }
4395
4396 static void init_proc_e200 (CPUPPCState *env)
4397 {
4398 /* Time base */
4399 gen_tbl(env);
4400 gen_spr_BookE(env, 0x000000070000FFFFULL);
4401 /* XXX : not implemented */
4402 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4403 &spr_read_spefscr, &spr_write_spefscr,
4404 &spr_read_spefscr, &spr_write_spefscr,
4405 0x00000000);
4406 /* Memory management */
4407 gen_spr_BookE206(env, 0x0000005D, NULL);
4408 /* XXX : not implemented */
4409 spr_register(env, SPR_HID0, "HID0",
4410 SPR_NOACCESS, SPR_NOACCESS,
4411 &spr_read_generic, &spr_write_generic,
4412 0x00000000);
4413 /* XXX : not implemented */
4414 spr_register(env, SPR_HID1, "HID1",
4415 SPR_NOACCESS, SPR_NOACCESS,
4416 &spr_read_generic, &spr_write_generic,
4417 0x00000000);
4418 /* XXX : not implemented */
4419 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4420 SPR_NOACCESS, SPR_NOACCESS,
4421 &spr_read_generic, &spr_write_generic,
4422 0x00000000);
4423 /* XXX : not implemented */
4424 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4425 SPR_NOACCESS, SPR_NOACCESS,
4426 &spr_read_generic, &spr_write_generic,
4427 0x00000000);
4428 /* XXX : not implemented */
4429 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4430 SPR_NOACCESS, SPR_NOACCESS,
4431 &spr_read_generic, &spr_write_generic,
4432 0x00000000);
4433 /* XXX : not implemented */
4434 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4435 SPR_NOACCESS, SPR_NOACCESS,
4436 &spr_read_generic, &spr_write_generic,
4437 0x00000000);
4438 /* XXX : not implemented */
4439 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4440 SPR_NOACCESS, SPR_NOACCESS,
4441 &spr_read_generic, &spr_write_generic,
4442 0x00000000);
4443 /* XXX : not implemented */
4444 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4445 &spr_read_generic, SPR_NOACCESS,
4446 &spr_read_generic, SPR_NOACCESS,
4447 0x00000000);
4448 /* XXX : not implemented */
4449 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4450 SPR_NOACCESS, SPR_NOACCESS,
4451 &spr_read_generic, &spr_write_generic,
4452 0x00000000);
4453 /* XXX : not implemented */
4454 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4455 SPR_NOACCESS, SPR_NOACCESS,
4456 &spr_read_generic, &spr_write_generic,
4457 0x00000000);
4458 /* XXX : not implemented */
4459 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4460 SPR_NOACCESS, SPR_NOACCESS,
4461 &spr_read_generic, &spr_write_generic,
4462 0x00000000);
4463 /* XXX : not implemented */
4464 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4465 SPR_NOACCESS, SPR_NOACCESS,
4466 &spr_read_generic, &spr_write_generic,
4467 0x00000000);
4468 /* XXX : not implemented */
4469 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4470 SPR_NOACCESS, SPR_NOACCESS,
4471 &spr_read_generic, &spr_write_generic,
4472 0x00000000);
4473 /* XXX : not implemented */
4474 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4475 SPR_NOACCESS, SPR_NOACCESS,
4476 &spr_read_generic, &spr_write_generic,
4477 0x00000000);
4478 /* XXX : not implemented */
4479 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4480 SPR_NOACCESS, SPR_NOACCESS,
4481 &spr_read_generic, &spr_write_generic,
4482 0x00000000); /* TOFIX */
4483 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4484 SPR_NOACCESS, SPR_NOACCESS,
4485 &spr_read_generic, &spr_write_generic,
4486 0x00000000);
4487 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4488 SPR_NOACCESS, SPR_NOACCESS,
4489 &spr_read_generic, &spr_write_generic,
4490 0x00000000);
4491 #if !defined(CONFIG_USER_ONLY)
4492 env->nb_tlb = 64;
4493 env->nb_ways = 1;
4494 env->id_tlbs = 0;
4495 env->tlb_type = TLB_EMB;
4496 #endif
4497 init_excp_e200(env, 0xFFFF0000UL);
4498 env->dcache_line_size = 32;
4499 env->icache_line_size = 32;
4500 /* XXX: TODO: allocate internal IRQ controller */
4501 }
4502
4503 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4504 {
4505 DeviceClass *dc = DEVICE_CLASS(oc);
4506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4507
4508 dc->desc = "e200 core";
4509 pcc->init_proc = init_proc_e200;
4510 pcc->check_pow = check_pow_hid0;
4511 /* XXX: unimplemented instructions:
4512 * dcblc
4513 * dcbtlst
4514 * dcbtstls
4515 * icblc
4516 * icbtls
4517 * tlbivax
4518 * all SPE multiply-accumulate instructions
4519 */
4520 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4521 PPC_SPE | PPC_SPE_SINGLE |
4522 PPC_WRTEE | PPC_RFDI |
4523 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4524 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4525 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4526 PPC_BOOKE;
4527 pcc->msr_mask = (1ull << MSR_UCLE) |
4528 (1ull << MSR_SPE) |
4529 (1ull << MSR_POW) |
4530 (1ull << MSR_CE) |
4531 (1ull << MSR_EE) |
4532 (1ull << MSR_PR) |
4533 (1ull << MSR_FP) |
4534 (1ull << MSR_ME) |
4535 (1ull << MSR_FE0) |
4536 (1ull << MSR_DWE) |
4537 (1ull << MSR_DE) |
4538 (1ull << MSR_FE1) |
4539 (1ull << MSR_IR) |
4540 (1ull << MSR_DR);
4541 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4542 pcc->excp_model = POWERPC_EXCP_BOOKE;
4543 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4544 pcc->bfd_mach = bfd_mach_ppc_860;
4545 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4546 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4547 POWERPC_FLAG_BUS_CLK;
4548 }
4549
4550 static void init_proc_e300 (CPUPPCState *env)
4551 {
4552 gen_spr_ne_601(env);
4553 gen_spr_603(env);
4554 /* Time base */
4555 gen_tbl(env);
4556 /* hardware implementation registers */
4557 /* XXX : not implemented */
4558 spr_register(env, SPR_HID0, "HID0",
4559 SPR_NOACCESS, SPR_NOACCESS,
4560 &spr_read_generic, &spr_write_generic,
4561 0x00000000);
4562 /* XXX : not implemented */
4563 spr_register(env, SPR_HID1, "HID1",
4564 SPR_NOACCESS, SPR_NOACCESS,
4565 &spr_read_generic, &spr_write_generic,
4566 0x00000000);
4567 /* XXX : not implemented */
4568 spr_register(env, SPR_HID2, "HID2",
4569 SPR_NOACCESS, SPR_NOACCESS,
4570 &spr_read_generic, &spr_write_generic,
4571 0x00000000);
4572 /* Memory management */
4573 gen_low_BATs(env);
4574 gen_high_BATs(env);
4575 gen_6xx_7xx_soft_tlb(env, 64, 2);
4576 init_excp_603(env);
4577 env->dcache_line_size = 32;
4578 env->icache_line_size = 32;
4579 /* Allocate hardware IRQ controller */
4580 ppc6xx_irq_init(env);
4581 }
4582
4583 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4584 {
4585 DeviceClass *dc = DEVICE_CLASS(oc);
4586 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4587
4588 dc->desc = "e300 core";
4589 pcc->init_proc = init_proc_e300;
4590 pcc->check_pow = check_pow_hid0;
4591 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4592 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4593 PPC_FLOAT_STFIWX |
4594 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4595 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4596 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4597 PPC_SEGMENT | PPC_EXTERN;
4598 pcc->msr_mask = (1ull << MSR_POW) |
4599 (1ull << MSR_TGPR) |
4600 (1ull << MSR_ILE) |
4601 (1ull << MSR_EE) |
4602 (1ull << MSR_PR) |
4603 (1ull << MSR_FP) |
4604 (1ull << MSR_ME) |
4605 (1ull << MSR_FE0) |
4606 (1ull << MSR_SE) |
4607 (1ull << MSR_DE) |
4608 (1ull << MSR_FE1) |
4609 (1ull << MSR_AL) |
4610 (1ull << MSR_EP) |
4611 (1ull << MSR_IR) |
4612 (1ull << MSR_DR) |
4613 (1ull << MSR_RI) |
4614 (1ull << MSR_LE);
4615 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4616 pcc->excp_model = POWERPC_EXCP_603;
4617 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4618 pcc->bfd_mach = bfd_mach_ppc_603;
4619 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4620 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4621 }
4622
4623 #if !defined(CONFIG_USER_ONLY)
4624 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4625 {
4626 TCGv val = tcg_temp_new();
4627 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4628 gen_store_spr(SPR_BOOKE_MAS3, val);
4629 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4630 gen_store_spr(SPR_BOOKE_MAS7, val);
4631 tcg_temp_free(val);
4632 }
4633
4634 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4635 {
4636 TCGv mas7 = tcg_temp_new();
4637 TCGv mas3 = tcg_temp_new();
4638 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4639 tcg_gen_shli_tl(mas7, mas7, 32);
4640 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4641 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4642 tcg_temp_free(mas3);
4643 tcg_temp_free(mas7);
4644 }
4645
4646 #endif
4647
4648 enum fsl_e500_version {
4649 fsl_e500v1,
4650 fsl_e500v2,
4651 fsl_e500mc,
4652 fsl_e5500,
4653 };
4654
4655 static void init_proc_e500 (CPUPPCState *env, int version)
4656 {
4657 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4658 uint32_t tlbncfg[2];
4659 uint64_t ivor_mask;
4660 uint64_t ivpr_mask = 0xFFFF0000ULL;
4661 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4662 | 0x0020; /* 32 kb */
4663 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4664 | 0x0020; /* 32 kb */
4665 #if !defined(CONFIG_USER_ONLY)
4666 int i;
4667 #endif
4668
4669 /* Time base */
4670 gen_tbl(env);
4671 /*
4672 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4673 * complain when accessing them.
4674 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4675 */
4676 switch (version) {
4677 case fsl_e500v1:
4678 case fsl_e500v2:
4679 default:
4680 ivor_mask = 0x0000000F0000FFFFULL;
4681 break;
4682 case fsl_e500mc:
4683 case fsl_e5500:
4684 ivor_mask = 0x000003FE0000FFFFULL;
4685 break;
4686 }
4687 gen_spr_BookE(env, ivor_mask);
4688 /* Processor identification */
4689 spr_register(env, SPR_BOOKE_PIR, "PIR",
4690 SPR_NOACCESS, SPR_NOACCESS,
4691 &spr_read_generic, &spr_write_pir,
4692 0x00000000);
4693 /* XXX : not implemented */
4694 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4695 &spr_read_spefscr, &spr_write_spefscr,
4696 &spr_read_spefscr, &spr_write_spefscr,
4697 0x00000000);
4698 #if !defined(CONFIG_USER_ONLY)
4699 /* Memory management */
4700 env->nb_pids = 3;
4701 env->nb_ways = 2;
4702 env->id_tlbs = 0;
4703 switch (version) {
4704 case fsl_e500v1:
4705 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4706 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4707 break;
4708 case fsl_e500v2:
4709 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4710 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4711 break;
4712 case fsl_e500mc:
4713 case fsl_e5500:
4714 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4715 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4716 break;
4717 default:
4718 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4719 }
4720 #endif
4721 /* Cache sizes */
4722 switch (version) {
4723 case fsl_e500v1:
4724 case fsl_e500v2:
4725 env->dcache_line_size = 32;
4726 env->icache_line_size = 32;
4727 break;
4728 case fsl_e500mc:
4729 case fsl_e5500:
4730 env->dcache_line_size = 64;
4731 env->icache_line_size = 64;
4732 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4733 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4734 break;
4735 default:
4736 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4737 }
4738 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4739 /* XXX : not implemented */
4740 spr_register(env, SPR_HID0, "HID0",
4741 SPR_NOACCESS, SPR_NOACCESS,
4742 &spr_read_generic, &spr_write_generic,
4743 0x00000000);
4744 /* XXX : not implemented */
4745 spr_register(env, SPR_HID1, "HID1",
4746 SPR_NOACCESS, SPR_NOACCESS,
4747 &spr_read_generic, &spr_write_generic,
4748 0x00000000);
4749 /* XXX : not implemented */
4750 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4751 SPR_NOACCESS, SPR_NOACCESS,
4752 &spr_read_generic, &spr_write_generic,
4753 0x00000000);
4754 /* XXX : not implemented */
4755 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4756 SPR_NOACCESS, SPR_NOACCESS,
4757 &spr_read_generic, &spr_write_generic,
4758 0x00000000);
4759 /* XXX : not implemented */
4760 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4761 SPR_NOACCESS, SPR_NOACCESS,
4762 &spr_read_generic, &spr_write_generic,
4763 0x00000000);
4764 /* XXX : not implemented */
4765 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4766 SPR_NOACCESS, SPR_NOACCESS,
4767 &spr_read_generic, &spr_write_generic,
4768 0x00000000);
4769 /* XXX : not implemented */
4770 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4771 SPR_NOACCESS, SPR_NOACCESS,
4772 &spr_read_generic, &spr_write_generic,
4773 0x00000000);
4774 /* XXX : not implemented */
4775 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4776 SPR_NOACCESS, SPR_NOACCESS,
4777 &spr_read_generic, &spr_write_generic,
4778 0x00000000);
4779 /* XXX : not implemented */
4780 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4781 &spr_read_generic, SPR_NOACCESS,
4782 &spr_read_generic, SPR_NOACCESS,
4783 l1cfg0);
4784 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4785 &spr_read_generic, SPR_NOACCESS,
4786 &spr_read_generic, SPR_NOACCESS,
4787 l1cfg1);
4788 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4789 SPR_NOACCESS, SPR_NOACCESS,
4790 &spr_read_generic, &spr_write_e500_l1csr0,
4791 0x00000000);
4792 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4793 SPR_NOACCESS, SPR_NOACCESS,
4794 &spr_read_generic, &spr_write_e500_l1csr1,
4795 0x00000000);
4796 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4797 SPR_NOACCESS, SPR_NOACCESS,
4798 &spr_read_generic, &spr_write_generic,
4799 0x00000000);
4800 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4801 SPR_NOACCESS, SPR_NOACCESS,
4802 &spr_read_generic, &spr_write_generic,
4803 0x00000000);
4804 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4805 SPR_NOACCESS, SPR_NOACCESS,
4806 &spr_read_generic, &spr_write_booke206_mmucsr0,
4807 0x00000000);
4808 spr_register(env, SPR_BOOKE_EPR, "EPR",
4809 SPR_NOACCESS, SPR_NOACCESS,
4810 &spr_read_generic, SPR_NOACCESS,
4811 0x00000000);
4812 /* XXX better abstract into Emb.xxx features */
4813 if (version == fsl_e5500) {
4814 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4815 SPR_NOACCESS, SPR_NOACCESS,
4816 &spr_read_generic, &spr_write_generic,
4817 0x00000000);
4818 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4819 SPR_NOACCESS, SPR_NOACCESS,
4820 &spr_read_mas73, &spr_write_mas73,
4821 0x00000000);
4822 ivpr_mask = (target_ulong)~0xFFFFULL;
4823 }
4824
4825 #if !defined(CONFIG_USER_ONLY)
4826 env->nb_tlb = 0;
4827 env->tlb_type = TLB_MAS;
4828 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4829 env->nb_tlb += booke206_tlb_size(env, i);
4830 }
4831 #endif
4832
4833 init_excp_e200(env, ivpr_mask);
4834 /* Allocate hardware IRQ controller */
4835 ppce500_irq_init(env);
4836 }
4837
4838 static void init_proc_e500v1(CPUPPCState *env)
4839 {
4840 init_proc_e500(env, fsl_e500v1);
4841 }
4842
4843 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4844 {
4845 DeviceClass *dc = DEVICE_CLASS(oc);
4846 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4847
4848 dc->desc = "e500v1 core";
4849 pcc->init_proc = init_proc_e500v1;
4850 pcc->check_pow = check_pow_hid0;
4851 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4852 PPC_SPE | PPC_SPE_SINGLE |
4853 PPC_WRTEE | PPC_RFDI |
4854 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4855 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4856 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4857 pcc->insns_flags2 = PPC2_BOOKE206;
4858 pcc->msr_mask = (1ull << MSR_UCLE) |
4859 (1ull << MSR_SPE) |
4860 (1ull << MSR_POW) |
4861 (1ull << MSR_CE) |
4862 (1ull << MSR_EE) |
4863 (1ull << MSR_PR) |
4864 (1ull << MSR_FP) |
4865 (1ull << MSR_ME) |
4866 (1ull << MSR_FE0) |
4867 (1ull << MSR_DWE) |
4868 (1ull << MSR_DE) |
4869 (1ull << MSR_FE1) |
4870 (1ull << MSR_IR) |
4871 (1ull << MSR_DR);
4872 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4873 pcc->excp_model = POWERPC_EXCP_BOOKE;
4874 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4875 pcc->bfd_mach = bfd_mach_ppc_860;
4876 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4877 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4878 POWERPC_FLAG_BUS_CLK;
4879 }
4880
4881 static void init_proc_e500v2(CPUPPCState *env)
4882 {
4883 init_proc_e500(env, fsl_e500v2);
4884 }
4885
4886 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4887 {
4888 DeviceClass *dc = DEVICE_CLASS(oc);
4889 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4890
4891 dc->desc = "e500v2 core";
4892 pcc->init_proc = init_proc_e500v2;
4893 pcc->check_pow = check_pow_hid0;
4894 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4895 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4896 PPC_WRTEE | PPC_RFDI |
4897 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4898 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4899 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4900 pcc->insns_flags2 = PPC2_BOOKE206;
4901 pcc->msr_mask = (1ull << MSR_UCLE) |
4902 (1ull << MSR_SPE) |
4903 (1ull << MSR_POW) |
4904 (1ull << MSR_CE) |
4905 (1ull << MSR_EE) |
4906 (1ull << MSR_PR) |
4907 (1ull << MSR_FP) |
4908 (1ull << MSR_ME) |
4909 (1ull << MSR_FE0) |
4910 (1ull << MSR_DWE) |
4911 (1ull << MSR_DE) |
4912 (1ull << MSR_FE1) |
4913 (1ull << MSR_IR) |
4914 (1ull << MSR_DR);
4915 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4916 pcc->excp_model = POWERPC_EXCP_BOOKE;
4917 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4918 pcc->bfd_mach = bfd_mach_ppc_860;
4919 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4920 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4921 POWERPC_FLAG_BUS_CLK;
4922 }
4923
4924 static void init_proc_e500mc(CPUPPCState *env)
4925 {
4926 init_proc_e500(env, fsl_e500mc);
4927 }
4928
4929 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4930 {
4931 DeviceClass *dc = DEVICE_CLASS(oc);
4932 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4933
4934 dc->desc = "e500mc core";
4935 pcc->init_proc = init_proc_e500mc;
4936 pcc->check_pow = check_pow_none;
4937 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4938 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4939 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4940 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4941 PPC_FLOAT | PPC_FLOAT_FRES |
4942 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4943 PPC_FLOAT_STFIWX | PPC_WAIT |
4944 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4945 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4946 pcc->msr_mask = (1ull << MSR_GS) |
4947 (1ull << MSR_UCLE) |
4948 (1ull << MSR_CE) |
4949 (1ull << MSR_EE) |
4950 (1ull << MSR_PR) |
4951 (1ull << MSR_FP) |
4952 (1ull << MSR_ME) |
4953 (1ull << MSR_FE0) |
4954 (1ull << MSR_DE) |
4955 (1ull << MSR_FE1) |
4956 (1ull << MSR_IR) |
4957 (1ull << MSR_DR) |
4958 (1ull << MSR_PX) |
4959 (1ull << MSR_RI);
4960 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4961 pcc->excp_model = POWERPC_EXCP_BOOKE;
4962 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4963 /* FIXME: figure out the correct flag for e500mc */
4964 pcc->bfd_mach = bfd_mach_ppc_e500;
4965 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4966 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4967 }
4968
4969 #ifdef TARGET_PPC64
4970 static void init_proc_e5500(CPUPPCState *env)
4971 {
4972 init_proc_e500(env, fsl_e5500);
4973 }
4974
4975 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4976 {
4977 DeviceClass *dc = DEVICE_CLASS(oc);
4978 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4979
4980 dc->desc = "e5500 core";
4981 pcc->init_proc = init_proc_e5500;
4982 pcc->check_pow = check_pow_none;
4983 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4984 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4985 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4986 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4987 PPC_FLOAT | PPC_FLOAT_FRES |
4988 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4989 PPC_FLOAT_STFIWX | PPC_WAIT |
4990 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4991 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4992 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206;
4993 pcc->msr_mask = (1ull << MSR_CM) |
4994 (1ull << MSR_GS) |
4995 (1ull << MSR_UCLE) |
4996 (1ull << MSR_CE) |
4997 (1ull << MSR_EE) |
4998 (1ull << MSR_PR) |
4999 (1ull << MSR_FP) |
5000 (1ull << MSR_ME) |
5001 (1ull << MSR_FE0) |
5002 (1ull << MSR_DE) |
5003 (1ull << MSR_FE1) |
5004 (1ull << MSR_IR) |
5005 (1ull << MSR_DR) |
5006 (1ull << MSR_PX) |
5007 (1ull << MSR_RI);
5008 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5009 pcc->excp_model = POWERPC_EXCP_BOOKE;
5010 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5011 /* FIXME: figure out the correct flag for e5500 */
5012 pcc->bfd_mach = bfd_mach_ppc_e500;
5013 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5014 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5015 }
5016 #endif
5017
5018 /* Non-embedded PowerPC */
5019
5020 /* POWER : same as 601, without mfmsr, mfsr */
5021 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
5022 {
5023 DeviceClass *dc = DEVICE_CLASS(oc);
5024 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5025
5026 dc->desc = "POWER";
5027 /* pcc->insns_flags = XXX_TODO; */
5028 /* POWER RSC (from RAD6000) */
5029 pcc->msr_mask = (1ull << MSR_EE) |
5030 (1ull << MSR_PR) |
5031 (1ull << MSR_FP) |
5032 (1ull << MSR_ME) |
5033 (1ull << MSR_FE0) |
5034 (1ull << MSR_SE) |
5035 (1ull << MSR_DE) |
5036 (1ull << MSR_AL) |
5037 (1ull << MSR_EP) |
5038 (1ull << MSR_IR) |
5039 (1ull << MSR_DR);
5040 }
5041
5042 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5043
5044 static void init_proc_601 (CPUPPCState *env)
5045 {
5046 gen_spr_ne_601(env);
5047 gen_spr_601(env);
5048 /* Hardware implementation registers */
5049 /* XXX : not implemented */
5050 spr_register(env, SPR_HID0, "HID0",
5051 SPR_NOACCESS, SPR_NOACCESS,
5052 &spr_read_generic, &spr_write_hid0_601,
5053 0x80010080);
5054 /* XXX : not implemented */
5055 spr_register(env, SPR_HID1, "HID1",
5056 SPR_NOACCESS, SPR_NOACCESS,
5057 &spr_read_generic, &spr_write_generic,
5058 0x00000000);
5059 /* XXX : not implemented */
5060 spr_register(env, SPR_601_HID2, "HID2",
5061 SPR_NOACCESS, SPR_NOACCESS,
5062 &spr_read_generic, &spr_write_generic,
5063 0x00000000);
5064 /* XXX : not implemented */
5065 spr_register(env, SPR_601_HID5, "HID5",
5066 SPR_NOACCESS, SPR_NOACCESS,
5067 &spr_read_generic, &spr_write_generic,
5068 0x00000000);
5069 /* Memory management */
5070 init_excp_601(env);
5071 /* XXX: beware that dcache line size is 64
5072 * but dcbz uses 32 bytes "sectors"
5073 * XXX: this breaks clcs instruction !
5074 */
5075 env->dcache_line_size = 32;
5076 env->icache_line_size = 64;
5077 /* Allocate hardware IRQ controller */
5078 ppc6xx_irq_init(env);
5079 }
5080
5081 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5082 {
5083 DeviceClass *dc = DEVICE_CLASS(oc);
5084 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5085
5086 dc->desc = "PowerPC 601";
5087 pcc->init_proc = init_proc_601;
5088 pcc->check_pow = check_pow_none;
5089 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5090 PPC_FLOAT |
5091 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5092 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5093 PPC_SEGMENT | PPC_EXTERN;
5094 pcc->msr_mask = (1ull << MSR_EE) |
5095 (1ull << MSR_PR) |
5096 (1ull << MSR_FP) |
5097 (1ull << MSR_ME) |
5098 (1ull << MSR_FE0) |
5099 (1ull << MSR_SE) |
5100 (1ull << MSR_FE1) |
5101 (1ull << MSR_EP) |
5102 (1ull << MSR_IR) |
5103 (1ull << MSR_DR);
5104 pcc->mmu_model = POWERPC_MMU_601;
5105 #if defined(CONFIG_SOFTMMU)
5106 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5107 #endif
5108 pcc->excp_model = POWERPC_EXCP_601;
5109 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5110 pcc->bfd_mach = bfd_mach_ppc_601;
5111 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5112 }
5113
5114 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5115
5116 static void init_proc_601v (CPUPPCState *env)
5117 {
5118 init_proc_601(env);
5119 /* XXX : not implemented */
5120 spr_register(env, SPR_601_HID15, "HID15",
5121 SPR_NOACCESS, SPR_NOACCESS,
5122 &spr_read_generic, &spr_write_generic,
5123 0x00000000);
5124 }
5125
5126 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5127 {
5128 DeviceClass *dc = DEVICE_CLASS(oc);
5129 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5130
5131 dc->desc = "PowerPC 601v";
5132 pcc->init_proc = init_proc_601v;
5133 pcc->check_pow = check_pow_none;
5134 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5135 PPC_FLOAT |
5136 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5137 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5138 PPC_SEGMENT | PPC_EXTERN;
5139 pcc->msr_mask = (1ull << MSR_EE) |
5140 (1ull << MSR_PR) |
5141 (1ull << MSR_FP) |
5142 (1ull << MSR_ME) |
5143 (1ull << MSR_FE0) |
5144 (1ull << MSR_SE) |
5145 (1ull << MSR_FE1) |
5146 (1ull << MSR_EP) |
5147 (1ull << MSR_IR) |
5148 (1ull << MSR_DR);
5149 pcc->mmu_model = POWERPC_MMU_601;
5150 #if defined(CONFIG_SOFTMMU)
5151 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5152 #endif
5153 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5154 pcc->bfd_mach = bfd_mach_ppc_601;
5155 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5156 }
5157
5158 static void init_proc_602 (CPUPPCState *env)
5159 {
5160 gen_spr_ne_601(env);
5161 gen_spr_602(env);
5162 /* Time base */
5163 gen_tbl(env);
5164 /* hardware implementation registers */
5165 /* XXX : not implemented */
5166 spr_register(env, SPR_HID0, "HID0",
5167 SPR_NOACCESS, SPR_NOACCESS,
5168 &spr_read_generic, &spr_write_generic,
5169 0x00000000);
5170 /* XXX : not implemented */
5171 spr_register(env, SPR_HID1, "HID1",
5172 SPR_NOACCESS, SPR_NOACCESS,
5173 &spr_read_generic, &spr_write_generic,
5174 0x00000000);
5175 /* Memory management */
5176 gen_low_BATs(env);
5177 gen_6xx_7xx_soft_tlb(env, 64, 2);
5178 init_excp_602(env);
5179 env->dcache_line_size = 32;
5180 env->icache_line_size = 32;
5181 /* Allocate hardware IRQ controller */
5182 ppc6xx_irq_init(env);
5183 }
5184
5185 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5186 {
5187 DeviceClass *dc = DEVICE_CLASS(oc);
5188 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5189
5190 dc->desc = "PowerPC 602";
5191 pcc->init_proc = init_proc_602;
5192 pcc->check_pow = check_pow_hid0;
5193 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5194 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5195 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5196 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5197 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5198 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5199 PPC_SEGMENT | PPC_602_SPEC;
5200 pcc->msr_mask = (1ull << MSR_VSX) |
5201 (1ull << MSR_SA) |
5202 (1ull << MSR_POW) |
5203 (1ull << MSR_TGPR) |
5204 (1ull << MSR_ILE) |
5205 (1ull << MSR_EE) |
5206 (1ull << MSR_PR) |
5207 (1ull << MSR_FP) |
5208 (1ull << MSR_ME) |
5209 (1ull << MSR_FE0) |
5210 (1ull << MSR_SE) |
5211 (1ull << MSR_DE) |
5212 (1ull << MSR_FE1) |
5213 (1ull << MSR_EP) |
5214 (1ull << MSR_IR) |
5215 (1ull << MSR_DR) |
5216 (1ull << MSR_RI) |
5217 (1ull << MSR_LE);
5218 /* XXX: 602 MMU is quite specific. Should add a special case */
5219 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5220 pcc->excp_model = POWERPC_EXCP_602;
5221 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5222 pcc->bfd_mach = bfd_mach_ppc_602;
5223 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5224 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5225 }
5226
5227 static void init_proc_603 (CPUPPCState *env)
5228 {
5229 gen_spr_ne_601(env);
5230 gen_spr_603(env);
5231 /* Time base */
5232 gen_tbl(env);
5233 /* hardware implementation registers */
5234 /* XXX : not implemented */
5235 spr_register(env, SPR_HID0, "HID0",
5236 SPR_NOACCESS, SPR_NOACCESS,
5237 &spr_read_generic, &spr_write_generic,
5238 0x00000000);
5239 /* XXX : not implemented */
5240 spr_register(env, SPR_HID1, "HID1",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 0x00000000);
5244 /* Memory management */
5245 gen_low_BATs(env);
5246 gen_6xx_7xx_soft_tlb(env, 64, 2);
5247 init_excp_603(env);
5248 env->dcache_line_size = 32;
5249 env->icache_line_size = 32;
5250 /* Allocate hardware IRQ controller */
5251 ppc6xx_irq_init(env);
5252 }
5253
5254 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5255 {
5256 DeviceClass *dc = DEVICE_CLASS(oc);
5257 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5258
5259 dc->desc = "PowerPC 603";
5260 pcc->init_proc = init_proc_603;
5261 pcc->check_pow = check_pow_hid0;
5262 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5263 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5264 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5265 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5266 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5267 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5268 PPC_SEGMENT | PPC_EXTERN;
5269 pcc->msr_mask = (1ull << MSR_POW) |
5270 (1ull << MSR_TGPR) |
5271 (1ull << MSR_ILE) |
5272 (1ull << MSR_EE) |
5273 (1ull << MSR_PR) |
5274 (1ull << MSR_FP) |
5275 (1ull << MSR_ME) |
5276 (1ull << MSR_FE0) |
5277 (1ull << MSR_SE) |
5278 (1ull << MSR_DE) |
5279 (1ull << MSR_FE1) |
5280 (1ull << MSR_EP) |
5281 (1ull << MSR_IR) |
5282 (1ull << MSR_DR) |
5283 (1ull << MSR_RI) |
5284 (1ull << MSR_LE);
5285 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5286 pcc->excp_model = POWERPC_EXCP_603;
5287 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5288 pcc->bfd_mach = bfd_mach_ppc_603;
5289 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5290 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5291 }
5292
5293 static void init_proc_603E (CPUPPCState *env)
5294 {
5295 gen_spr_ne_601(env);
5296 gen_spr_603(env);
5297 /* Time base */
5298 gen_tbl(env);
5299 /* hardware implementation registers */
5300 /* XXX : not implemented */
5301 spr_register(env, SPR_HID0, "HID0",
5302 SPR_NOACCESS, SPR_NOACCESS,
5303 &spr_read_generic, &spr_write_generic,
5304 0x00000000);
5305 /* XXX : not implemented */
5306 spr_register(env, SPR_HID1, "HID1",
5307 SPR_NOACCESS, SPR_NOACCESS,
5308 &spr_read_generic, &spr_write_generic,
5309 0x00000000);
5310 /* Memory management */
5311 gen_low_BATs(env);
5312 gen_6xx_7xx_soft_tlb(env, 64, 2);
5313 init_excp_603(env);
5314 env->dcache_line_size = 32;
5315 env->icache_line_size = 32;
5316 /* Allocate hardware IRQ controller */
5317 ppc6xx_irq_init(env);
5318 }
5319
5320 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5321 {
5322 DeviceClass *dc = DEVICE_CLASS(oc);
5323 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5324
5325 dc->desc = "PowerPC 603e";
5326 pcc->init_proc = init_proc_603E;
5327 pcc->check_pow = check_pow_hid0;
5328 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5329 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5330 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5331 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5332 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5333 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5334 PPC_SEGMENT | PPC_EXTERN;
5335 pcc->msr_mask = (1ull << MSR_POW) |
5336 (1ull << MSR_TGPR) |
5337 (1ull << MSR_ILE) |
5338 (1ull << MSR_EE) |
5339 (1ull << MSR_PR) |
5340 (1ull << MSR_FP) |
5341 (1ull << MSR_ME) |
5342 (1ull << MSR_FE0) |
5343 (1ull << MSR_SE) |
5344 (1ull << MSR_DE) |
5345 (1ull << MSR_FE1) |
5346 (1ull << MSR_EP) |
5347 (1ull << MSR_IR) |
5348 (1ull << MSR_DR) |
5349 (1ull << MSR_RI) |
5350 (1ull << MSR_LE);
5351 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5352 pcc->excp_model = POWERPC_EXCP_603E;
5353 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5354 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5355 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5356 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5357 }
5358
5359 static void init_proc_604 (CPUPPCState *env)
5360 {
5361 gen_spr_ne_601(env);
5362 gen_spr_604(env);
5363 /* Time base */
5364 gen_tbl(env);
5365 /* Hardware implementation registers */
5366 /* XXX : not implemented */
5367 spr_register(env, SPR_HID0, "HID0",
5368 SPR_NOACCESS, SPR_NOACCESS,
5369 &spr_read_generic, &spr_write_generic,
5370 0x00000000);
5371 /* Memory management */
5372 gen_low_BATs(env);
5373 init_excp_604(env);
5374 env->dcache_line_size = 32;
5375 env->icache_line_size = 32;
5376 /* Allocate hardware IRQ controller */
5377 ppc6xx_irq_init(env);
5378 }
5379
5380 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5381 {
5382 DeviceClass *dc = DEVICE_CLASS(oc);
5383 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5384
5385 dc->desc = "PowerPC 604";
5386 pcc->init_proc = init_proc_604;
5387 pcc->check_pow = check_pow_nocheck;
5388 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5389 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5390 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5391 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5392 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5393 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5394 PPC_SEGMENT | PPC_EXTERN;
5395 pcc->msr_mask = (1ull << MSR_POW) |
5396 (1ull << MSR_ILE) |
5397 (1ull << MSR_EE) |
5398 (1ull << MSR_PR) |
5399 (1ull << MSR_FP) |
5400 (1ull << MSR_ME) |
5401 (1ull << MSR_FE0) |
5402 (1ull << MSR_SE) |
5403 (1ull << MSR_DE) |
5404 (1ull << MSR_FE1) |
5405 (1ull << MSR_EP) |
5406 (1ull << MSR_IR) |
5407 (1ull << MSR_DR) |
5408 (1ull << MSR_PMM) |
5409 (1ull << MSR_RI) |
5410 (1ull << MSR_LE);
5411 pcc->mmu_model = POWERPC_MMU_32B;
5412 #if defined(CONFIG_SOFTMMU)
5413 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5414 #endif
5415 pcc->excp_model = POWERPC_EXCP_604;
5416 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5417 pcc->bfd_mach = bfd_mach_ppc_604;
5418 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5419 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5420 }
5421
5422 static void init_proc_604E (CPUPPCState *env)
5423 {
5424 gen_spr_ne_601(env);
5425 gen_spr_604(env);
5426 /* XXX : not implemented */
5427 spr_register(env, SPR_MMCR1, "MMCR1",
5428 SPR_NOACCESS, SPR_NOACCESS,
5429 &spr_read_generic, &spr_write_generic,
5430 0x00000000);
5431 /* XXX : not implemented */
5432 spr_register(env, SPR_PMC3, "PMC3",
5433 SPR_NOACCESS, SPR_NOACCESS,
5434 &spr_read_generic, &spr_write_generic,
5435 0x00000000);
5436 /* XXX : not implemented */
5437 spr_register(env, SPR_PMC4, "PMC4",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* Time base */
5442 gen_tbl(env);
5443 /* Hardware implementation registers */
5444 /* XXX : not implemented */
5445 spr_register(env, SPR_HID0, "HID0",
5446 SPR_NOACCESS, SPR_NOACCESS,
5447 &spr_read_generic, &spr_write_generic,
5448 0x00000000);
5449 /* XXX : not implemented */
5450 spr_register(env, SPR_HID1, "HID1",
5451 SPR_NOACCESS, SPR_NOACCESS,
5452 &spr_read_generic, &spr_write_generic,
5453 0x00000000);
5454 /* Memory management */
5455 gen_low_BATs(env);
5456 init_excp_604(env);
5457 env->dcache_line_size = 32;
5458 env->icache_line_size = 32;
5459 /* Allocate hardware IRQ controller */
5460 ppc6xx_irq_init(env);
5461 }
5462
5463 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5464 {
5465 DeviceClass *dc = DEVICE_CLASS(oc);
5466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5467
5468 dc->desc = "PowerPC 604E";
5469 pcc->init_proc = init_proc_604E;
5470 pcc->check_pow = check_pow_nocheck;
5471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5473 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5474 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5475 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5476 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5477 PPC_SEGMENT | PPC_EXTERN;
5478 pcc->msr_mask = (1ull << MSR_POW) |
5479 (1ull << MSR_ILE) |
5480 (1ull << MSR_EE) |
5481 (1ull << MSR_PR) |
5482 (1ull << MSR_FP) |
5483 (1ull << MSR_ME) |
5484 (1ull << MSR_FE0) |
5485 (1ull << MSR_SE) |
5486 (1ull << MSR_DE) |
5487 (1ull << MSR_FE1) |
5488 (1ull << MSR_EP) |
5489 (1ull << MSR_IR) |
5490 (1ull << MSR_DR) |
5491 (1ull << MSR_PMM) |
5492 (1ull << MSR_RI) |
5493 (1ull << MSR_LE);
5494 pcc->mmu_model = POWERPC_MMU_32B;
5495 #if defined(CONFIG_SOFTMMU)
5496 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5497 #endif
5498 pcc->excp_model = POWERPC_EXCP_604;
5499 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5500 pcc->bfd_mach = bfd_mach_ppc_604;
5501 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5502 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5503 }
5504
5505 static void init_proc_740 (CPUPPCState *env)
5506 {
5507 gen_spr_ne_601(env);
5508 gen_spr_7xx(env);
5509 /* Time base */
5510 gen_tbl(env);
5511 /* Thermal management */
5512 gen_spr_thrm(env);
5513 /* Hardware implementation registers */
5514 /* XXX : not implemented */
5515 spr_register(env, SPR_HID0, "HID0",
5516 SPR_NOACCESS, SPR_NOACCESS,
5517 &spr_read_generic, &spr_write_generic,
5518 0x00000000);
5519 /* XXX : not implemented */
5520 spr_register(env, SPR_HID1, "HID1",
5521 SPR_NOACCESS, SPR_NOACCESS,
5522 &spr_read_generic, &spr_write_generic,
5523 0x00000000);
5524 /* Memory management */
5525 gen_low_BATs(env);
5526 init_excp_7x0(env);
5527 env->dcache_line_size = 32;
5528 env->icache_line_size = 32;
5529 /* Allocate hardware IRQ controller */
5530 ppc6xx_irq_init(env);
5531 }
5532
5533 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5534 {
5535 DeviceClass *dc = DEVICE_CLASS(oc);
5536 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5537
5538 dc->desc = "PowerPC 740";
5539 pcc->init_proc = init_proc_740;
5540 pcc->check_pow = check_pow_hid0;
5541 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5542 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5543 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5544 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5545 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5546 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5547 PPC_SEGMENT | PPC_EXTERN;
5548 pcc->msr_mask = (1ull << MSR_POW) |
5549 (1ull << MSR_ILE) |
5550 (1ull << MSR_EE) |
5551 (1ull << MSR_PR) |
5552 (1ull << MSR_FP) |
5553 (1ull << MSR_ME) |
5554 (1ull << MSR_FE0) |
5555 (1ull << MSR_SE) |
5556 (1ull << MSR_DE) |
5557 (1ull << MSR_FE1) |
5558 (1ull << MSR_EP) |
5559 (1ull << MSR_IR) |
5560 (1ull << MSR_DR) |
5561 (1ull << MSR_PMM) |
5562 (1ull << MSR_RI) |
5563 (1ull << MSR_LE);
5564 pcc->mmu_model = POWERPC_MMU_32B;
5565 #if defined(CONFIG_SOFTMMU)
5566 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5567 #endif
5568 pcc->excp_model = POWERPC_EXCP_7x0;
5569 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5570 pcc->bfd_mach = bfd_mach_ppc_750;
5571 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5572 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5573 }
5574
5575 static void init_proc_750 (CPUPPCState *env)
5576 {
5577 gen_spr_ne_601(env);
5578 gen_spr_7xx(env);
5579 /* XXX : not implemented */
5580 spr_register(env, SPR_L2CR, "L2CR",
5581 SPR_NOACCESS, SPR_NOACCESS,
5582 &spr_read_generic, spr_access_nop,
5583 0x00000000);
5584 /* Time base */
5585 gen_tbl(env);
5586 /* Thermal management */
5587 gen_spr_thrm(env);
5588 /* Hardware implementation registers */
5589 /* XXX : not implemented */
5590 spr_register(env, SPR_HID0, "HID0",
5591 SPR_NOACCESS, SPR_NOACCESS,
5592 &spr_read_generic, &spr_write_generic,
5593 0x00000000);
5594 /* XXX : not implemented */
5595 spr_register(env, SPR_HID1, "HID1",
5596 SPR_NOACCESS, SPR_NOACCESS,
5597 &spr_read_generic, &spr_write_generic,
5598 0x00000000);
5599 /* Memory management */
5600 gen_low_BATs(env);
5601 /* XXX: high BATs are also present but are known to be bugged on
5602 * die version 1.x
5603 */
5604 init_excp_7x0(env);
5605 env->dcache_line_size = 32;
5606 env->icache_line_size = 32;
5607 /* Allocate hardware IRQ controller */
5608 ppc6xx_irq_init(env);
5609 }
5610
5611 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5612 {
5613 DeviceClass *dc = DEVICE_CLASS(oc);
5614 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5615
5616 dc->desc = "PowerPC 750";
5617 pcc->init_proc = init_proc_750;
5618 pcc->check_pow = check_pow_hid0;
5619 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5620 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5621 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5622 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5623 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5624 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5625 PPC_SEGMENT | PPC_EXTERN;
5626 pcc->msr_mask = (1ull << MSR_POW) |
5627 (1ull << MSR_ILE) |
5628 (1ull << MSR_EE) |
5629 (1ull << MSR_PR) |
5630 (1ull << MSR_FP) |
5631 (1ull << MSR_ME) |
5632 (1ull << MSR_FE0) |
5633 (1ull << MSR_SE) |
5634 (1ull << MSR_DE) |
5635 (1ull << MSR_FE1) |
5636 (1ull << MSR_EP) |
5637 (1ull << MSR_IR) |
5638 (1ull << MSR_DR) |
5639 (1ull << MSR_PMM) |
5640 (1ull << MSR_RI) |
5641 (1ull << MSR_LE);
5642 pcc->mmu_model = POWERPC_MMU_32B;
5643 #if defined(CONFIG_SOFTMMU)
5644 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5645 #endif
5646 pcc->excp_model = POWERPC_EXCP_7x0;
5647 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5648 pcc->bfd_mach = bfd_mach_ppc_750;
5649 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5650 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5651 }
5652
5653 static void init_proc_750cl (CPUPPCState *env)
5654 {
5655 gen_spr_ne_601(env);
5656 gen_spr_7xx(env);
5657 /* XXX : not implemented */
5658 spr_register(env, SPR_L2CR, "L2CR",
5659 SPR_NOACCESS, SPR_NOACCESS,
5660 &spr_read_generic, spr_access_nop,
5661 0x00000000);
5662 /* Time base */
5663 gen_tbl(env);
5664 /* Thermal management */
5665 /* Those registers are fake on 750CL */
5666 spr_register(env, SPR_THRM1, "THRM1",
5667 SPR_NOACCESS, SPR_NOACCESS,
5668 &spr_read_generic, &spr_write_generic,
5669 0x00000000);
5670 spr_register(env, SPR_THRM2, "THRM2",
5671 SPR_NOACCESS, SPR_NOACCESS,
5672 &spr_read_generic, &spr_write_generic,
5673 0x00000000);
5674 spr_register(env, SPR_THRM3, "THRM3",
5675 SPR_NOACCESS, SPR_NOACCESS,
5676 &spr_read_generic, &spr_write_generic,
5677 0x00000000);
5678 /* XXX: not implemented */
5679 spr_register(env, SPR_750_TDCL, "TDCL",
5680 SPR_NOACCESS, SPR_NOACCESS,
5681 &spr_read_generic, &spr_write_generic,
5682 0x00000000);
5683 spr_register(env, SPR_750_TDCH, "TDCH",
5684 SPR_NOACCESS, SPR_NOACCESS,
5685 &spr_read_generic, &spr_write_generic,
5686 0x00000000);
5687 /* DMA */
5688 /* XXX : not implemented */
5689 spr_register(env, SPR_750_WPAR, "WPAR",
5690 SPR_NOACCESS, SPR_NOACCESS,
5691 &spr_read_generic, &spr_write_generic,
5692 0x00000000);
5693 spr_register(env, SPR_750_DMAL, "DMAL",
5694 SPR_NOACCESS, SPR_NOACCESS,
5695 &spr_read_generic, &spr_write_generic,
5696 0x00000000);
5697 spr_register(env, SPR_750_DMAU, "DMAU",
5698 SPR_NOACCESS, SPR_NOACCESS,
5699 &spr_read_generic, &spr_write_generic,
5700 0x00000000);
5701 /* Hardware implementation registers */
5702 /* XXX : not implemented */
5703 spr_register(env, SPR_HID0, "HID0",
5704 SPR_NOACCESS, SPR_NOACCESS,
5705 &spr_read_generic, &spr_write_generic,
5706 0x00000000);
5707 /* XXX : not implemented */
5708 spr_register(env, SPR_HID1, "HID1",
5709 SPR_NOACCESS, SPR_NOACCESS,
5710 &spr_read_generic, &spr_write_generic,
5711 0x00000000);
5712 /* XXX : not implemented */
5713 spr_register(env, SPR_750CL_HID2, "HID2",
5714 SPR_NOACCESS, SPR_NOACCESS,
5715 &spr_read_generic, &spr_write_generic,
5716 0x00000000);
5717 /* XXX : not implemented */
5718 spr_register(env, SPR_750CL_HID4, "HID4",
5719 SPR_NOACCESS, SPR_NOACCESS,
5720 &spr_read_generic, &spr_write_generic,
5721 0x00000000);
5722 /* Quantization registers */
5723 /* XXX : not implemented */
5724 spr_register(env, SPR_750_GQR0, "GQR0",
5725 SPR_NOACCESS, SPR_NOACCESS,
5726 &spr_read_generic, &spr_write_generic,
5727 0x00000000);
5728 /* XXX : not implemented */
5729 spr_register(env, SPR_750_GQR1, "GQR1",
5730 SPR_NOACCESS, SPR_NOACCESS,
5731 &spr_read_generic, &spr_write_generic,
5732 0x00000000);
5733 /* XXX : not implemented */
5734 spr_register(env, SPR_750_GQR2, "GQR2",
5735 SPR_NOACCESS, SPR_NOACCESS,
5736 &spr_read_generic, &spr_write_generic,
5737 0x00000000);
5738 /* XXX : not implemented */
5739 spr_register(env, SPR_750_GQR3, "GQR3",
5740 SPR_NOACCESS, SPR_NOACCESS,
5741 &spr_read_generic, &spr_write_generic,
5742 0x00000000);
5743 /* XXX : not implemented */
5744 spr_register(env, SPR_750_GQR4, "GQR4",
5745 SPR_NOACCESS, SPR_NOACCESS,
5746 &spr_read_generic, &spr_write_generic,
5747 0x00000000);
5748 /* XXX : not implemented */
5749 spr_register(env, SPR_750_GQR5, "GQR5",
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_read_generic, &spr_write_generic,
5752 0x00000000);
5753 /* XXX : not implemented */
5754 spr_register(env, SPR_750_GQR6, "GQR6",
5755 SPR_NOACCESS, SPR_NOACCESS,
5756 &spr_read_generic, &spr_write_generic,
5757 0x00000000);
5758 /* XXX : not implemented */
5759 spr_register(env, SPR_750_GQR7, "GQR7",
5760 SPR_NOACCESS, SPR_NOACCESS,
5761 &spr_read_generic, &spr_write_generic,
5762 0x00000000);
5763 /* Memory management */
5764 gen_low_BATs(env);
5765 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5766 gen_high_BATs(env);
5767 init_excp_750cl(env);
5768 env->dcache_line_size = 32;
5769 env->icache_line_size = 32;
5770 /* Allocate hardware IRQ controller */
5771 ppc6xx_irq_init(env);
5772 }
5773
5774 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5775 {
5776 DeviceClass *dc = DEVICE_CLASS(oc);
5777 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5778
5779 dc->desc = "PowerPC 750 CL";
5780 pcc->init_proc = init_proc_750cl;
5781 pcc->check_pow = check_pow_hid0;
5782 /* XXX: not implemented:
5783 * cache lock instructions:
5784 * dcbz_l
5785 * floating point paired instructions
5786 * psq_lux
5787 * psq_lx
5788 * psq_stux
5789 * psq_stx
5790 * ps_abs
5791 * ps_add
5792 * ps_cmpo0
5793 * ps_cmpo1
5794 * ps_cmpu0
5795 * ps_cmpu1
5796 * ps_div
5797 * ps_madd
5798 * ps_madds0
5799 * ps_madds1
5800 * ps_merge00
5801 * ps_merge01
5802 * ps_merge10
5803 * ps_merge11
5804 * ps_mr
5805 * ps_msub
5806 * ps_mul
5807 * ps_muls0
5808 * ps_muls1
5809 * ps_nabs
5810 * ps_neg
5811 * ps_nmadd
5812 * ps_nmsub
5813 * ps_res
5814 * ps_rsqrte
5815 * ps_sel
5816 * ps_sub
5817 * ps_sum0
5818 * ps_sum1
5819 */
5820 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5821 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5822 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5823 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5824 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5825 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5826 PPC_SEGMENT | PPC_EXTERN;
5827 pcc->msr_mask = (1ull << MSR_POW) |
5828 (1ull << MSR_ILE) |
5829 (1ull << MSR_EE) |
5830 (1ull << MSR_PR) |
5831 (1ull << MSR_FP) |
5832 (1ull << MSR_ME) |
5833 (1ull << MSR_FE0) |
5834 (1ull << MSR_SE) |
5835 (1ull << MSR_DE) |
5836 (1ull << MSR_FE1) |
5837 (1ull << MSR_EP) |
5838 (1ull << MSR_IR) |
5839 (1ull << MSR_DR) |
5840 (1ull << MSR_PMM) |
5841 (1ull << MSR_RI) |
5842 (1ull << MSR_LE);
5843 pcc->mmu_model = POWERPC_MMU_32B;
5844 #if defined(CONFIG_SOFTMMU)
5845 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5846 #endif
5847 pcc->excp_model = POWERPC_EXCP_7x0;
5848 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5849 pcc->bfd_mach = bfd_mach_ppc_750;
5850 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5851 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5852 }
5853
5854 static void init_proc_750cx (CPUPPCState *env)
5855 {
5856 gen_spr_ne_601(env);
5857 gen_spr_7xx(env);
5858 /* XXX : not implemented */
5859 spr_register(env, SPR_L2CR, "L2CR",
5860 SPR_NOACCESS, SPR_NOACCESS,
5861 &spr_read_generic, spr_access_nop,
5862 0x00000000);
5863 /* Time base */
5864 gen_tbl(env);
5865 /* Thermal management */
5866 gen_spr_thrm(env);
5867 /* This register is not implemented but is present for compatibility */
5868 spr_register(env, SPR_SDA, "SDA",
5869 SPR_NOACCESS, SPR_NOACCESS,
5870 &spr_read_generic, &spr_write_generic,
5871 0x00000000);
5872 /* Hardware implementation registers */
5873 /* XXX : not implemented */
5874 spr_register(env, SPR_HID0, "HID0",
5875 SPR_NOACCESS, SPR_NOACCESS,
5876 &spr_read_generic, &spr_write_generic,
5877 0x00000000);
5878 /* XXX : not implemented */
5879 spr_register(env, SPR_HID1, "HID1",
5880 SPR_NOACCESS, SPR_NOACCESS,
5881 &spr_read_generic, &spr_write_generic,
5882 0x00000000);
5883 /* Memory management */
5884 gen_low_BATs(env);
5885 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5886 gen_high_BATs(env);
5887 init_excp_750cx(env);
5888 env->dcache_line_size = 32;
5889 env->icache_line_size = 32;
5890 /* Allocate hardware IRQ controller */
5891 ppc6xx_irq_init(env);
5892 }
5893
5894 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5895 {
5896 DeviceClass *dc = DEVICE_CLASS(oc);
5897 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5898
5899 dc->desc = "PowerPC 750CX";
5900 pcc->init_proc = init_proc_750cx;
5901 pcc->check_pow = check_pow_hid0;
5902 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5903 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5904 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5905 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5906 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5907 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5908 PPC_SEGMENT | PPC_EXTERN;
5909 pcc->msr_mask = (1ull << MSR_POW) |
5910 (1ull << MSR_ILE) |
5911 (1ull << MSR_EE) |
5912 (1ull << MSR_PR) |
5913 (1ull << MSR_FP) |
5914 (1ull << MSR_ME) |
5915 (1ull << MSR_FE0) |
5916 (1ull << MSR_SE) |
5917 (1ull << MSR_DE) |
5918 (1ull << MSR_FE1) |
5919 (1ull << MSR_EP) |
5920 (1ull << MSR_IR) |
5921 (1ull << MSR_DR) |
5922 (1ull << MSR_PMM) |
5923 (1ull << MSR_RI) |
5924 (1ull << MSR_LE);
5925 pcc->mmu_model = POWERPC_MMU_32B;
5926 #if defined(CONFIG_SOFTMMU)
5927 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5928 #endif
5929 pcc->excp_model = POWERPC_EXCP_7x0;
5930 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5931 pcc->bfd_mach = bfd_mach_ppc_750;
5932 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5933 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5934 }
5935
5936 static void init_proc_750fx (CPUPPCState *env)
5937 {
5938 gen_spr_ne_601(env);
5939 gen_spr_7xx(env);
5940 /* XXX : not implemented */
5941 spr_register(env, SPR_L2CR, "L2CR",
5942 SPR_NOACCESS, SPR_NOACCESS,
5943 &spr_read_generic, spr_access_nop,
5944 0x00000000);
5945 /* Time base */
5946 gen_tbl(env);
5947 /* Thermal management */
5948 gen_spr_thrm(env);
5949 /* XXX : not implemented */
5950 spr_register(env, SPR_750_THRM4, "THRM4",
5951 SPR_NOACCESS, SPR_NOACCESS,
5952 &spr_read_generic, &spr_write_generic,
5953 0x00000000);
5954 /* Hardware implementation registers */
5955 /* XXX : not implemented */
5956 spr_register(env, SPR_HID0, "HID0",
5957 SPR_NOACCESS, SPR_NOACCESS,
5958 &spr_read_generic, &spr_write_generic,
5959 0x00000000);
5960 /* XXX : not implemented */
5961 spr_register(env, SPR_HID1, "HID1",
5962 SPR_NOACCESS, SPR_NOACCESS,
5963 &spr_read_generic, &spr_write_generic,
5964 0x00000000);
5965 /* XXX : not implemented */
5966 spr_register(env, SPR_750FX_HID2, "HID2",
5967 SPR_NOACCESS, SPR_NOACCESS,
5968 &spr_read_generic, &spr_write_generic,
5969 0x00000000);
5970 /* Memory management */
5971 gen_low_BATs(env);
5972 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5973 gen_high_BATs(env);
5974 init_excp_7x0(env);
5975 env->dcache_line_size = 32;
5976 env->icache_line_size = 32;
5977 /* Allocate hardware IRQ controller */
5978 ppc6xx_irq_init(env);
5979 }
5980
5981 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5982 {
5983 DeviceClass *dc = DEVICE_CLASS(oc);
5984 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5985
5986 dc->desc = "PowerPC 750FX";
5987 pcc->init_proc = init_proc_750fx;
5988 pcc->check_pow = check_pow_hid0;
5989 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5990 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5991 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5992 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5993 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5995 PPC_SEGMENT | PPC_EXTERN;
5996 pcc->msr_mask = (1ull << MSR_POW) |
5997 (1ull << MSR_ILE) |
5998 (1ull << MSR_EE) |
5999 (1ull << MSR_PR) |
6000 (1ull << MSR_FP) |
6001 (1ull << MSR_ME) |
6002 (1ull << MSR_FE0) |
6003 (1ull << MSR_SE) |
6004 (1ull << MSR_DE) |
6005 (1ull << MSR_FE1) |
6006 (1ull << MSR_EP) |
6007 (1ull << MSR_IR) |
6008 (1ull << MSR_DR) |
6009 (1ull << MSR_PMM) |
6010 (1ull << MSR_RI) |
6011 (1ull << MSR_LE);
6012 pcc->mmu_model = POWERPC_MMU_32B;
6013 #if defined(CONFIG_SOFTMMU)
6014 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6015 #endif
6016 pcc->excp_model = POWERPC_EXCP_7x0;
6017 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6018 pcc->bfd_mach = bfd_mach_ppc_750;
6019 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6020 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6021 }
6022
6023 static void init_proc_750gx (CPUPPCState *env)
6024 {
6025 gen_spr_ne_601(env);
6026 gen_spr_7xx(env);
6027 /* XXX : not implemented (XXX: different from 750fx) */
6028 spr_register(env, SPR_L2CR, "L2CR",
6029 SPR_NOACCESS, SPR_NOACCESS,
6030 &spr_read_generic, spr_access_nop,
6031 0x00000000);
6032 /* Time base */
6033 gen_tbl(env);
6034 /* Thermal management */
6035 gen_spr_thrm(env);
6036 /* XXX : not implemented */
6037 spr_register(env, SPR_750_THRM4, "THRM4",
6038 SPR_NOACCESS, SPR_NOACCESS,
6039 &spr_read_generic, &spr_write_generic,
6040 0x00000000);
6041 /* Hardware implementation registers */
6042 /* XXX : not implemented (XXX: different from 750fx) */
6043 spr_register(env, SPR_HID0, "HID0",
6044 SPR_NOACCESS, SPR_NOACCESS,
6045 &spr_read_generic, &spr_write_generic,
6046 0x00000000);
6047 /* XXX : not implemented */
6048 spr_register(env, SPR_HID1, "HID1",
6049 SPR_NOACCESS, SPR_NOACCESS,
6050 &spr_read_generic, &spr_write_generic,
6051 0x00000000);
6052 /* XXX : not implemented (XXX: different from 750fx) */
6053 spr_register(env, SPR_750FX_HID2, "HID2",
6054 SPR_NOACCESS, SPR_NOACCESS,
6055 &spr_read_generic, &spr_write_generic,
6056 0x00000000);
6057 /* Memory management */
6058 gen_low_BATs(env);
6059 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6060 gen_high_BATs(env);
6061 init_excp_7x0(env);
6062 env->dcache_line_size = 32;
6063 env->icache_line_size = 32;
6064 /* Allocate hardware IRQ controller */
6065 ppc6xx_irq_init(env);
6066 }
6067
6068 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6069 {
6070 DeviceClass *dc = DEVICE_CLASS(oc);
6071 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6072
6073 dc->desc = "PowerPC 750GX";
6074 pcc->init_proc = init_proc_750gx;
6075 pcc->check_pow = check_pow_hid0;
6076 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6077 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6078 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6079 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6080 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6081 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6082 PPC_SEGMENT | PPC_EXTERN;
6083 pcc->msr_mask = (1ull << MSR_POW) |
6084 (1ull << MSR_ILE) |
6085 (1ull << MSR_EE) |
6086 (1ull << MSR_PR) |
6087 (1ull << MSR_FP) |
6088 (1ull << MSR_ME) |
6089 (1ull << MSR_FE0) |
6090 (1ull << MSR_SE) |
6091 (1ull << MSR_DE) |
6092 (1ull << MSR_FE1) |
6093 (1ull << MSR_EP) |
6094 (1ull << MSR_IR) |
6095 (1ull << MSR_DR) |
6096 (1ull << MSR_PMM) |
6097 (1ull << MSR_RI) |
6098 (1ull << MSR_LE);
6099 pcc->mmu_model = POWERPC_MMU_32B;
6100 #if defined(CONFIG_SOFTMMU)
6101 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6102 #endif
6103 pcc->excp_model = POWERPC_EXCP_7x0;
6104 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6105 pcc->bfd_mach = bfd_mach_ppc_750;
6106 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6107 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6108 }
6109
6110 static void init_proc_745 (CPUPPCState *env)
6111 {
6112 gen_spr_ne_601(env);
6113 gen_spr_7xx(env);
6114 gen_spr_G2_755(env);
6115 /* Time base */
6116 gen_tbl(env);
6117 /* Thermal management */
6118 gen_spr_thrm(env);
6119 /* Hardware implementation registers */
6120 /* XXX : not implemented */
6121 spr_register(env, SPR_HID0, "HID0",
6122 SPR_NOACCESS, SPR_NOACCESS,
6123 &spr_read_generic, &spr_write_generic,
6124 0x00000000);
6125 /* XXX : not implemented */
6126 spr_register(env, SPR_HID1, "HID1",
6127 SPR_NOACCESS, SPR_NOACCESS,
6128 &spr_read_generic, &spr_write_generic,
6129 0x00000000);
6130 /* XXX : not implemented */
6131 spr_register(env, SPR_HID2, "HID2",
6132 SPR_NOACCESS, SPR_NOACCESS,
6133 &spr_read_generic, &spr_write_generic,
6134 0x00000000);
6135 /* Memory management */
6136 gen_low_BATs(env);
6137 gen_high_BATs(env);
6138 gen_6xx_7xx_soft_tlb(env, 64, 2);
6139 init_excp_7x5(env);
6140 env->dcache_line_size = 32;
6141 env->icache_line_size = 32;
6142 /* Allocate hardware IRQ controller */
6143 ppc6xx_irq_init(env);
6144 }
6145
6146 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6147 {
6148 DeviceClass *dc = DEVICE_CLASS(oc);
6149 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6150
6151 dc->desc = "PowerPC 745";
6152 pcc->init_proc = init_proc_745;
6153 pcc->check_pow = check_pow_hid0;
6154 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6155 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6156 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6157 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6158 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6159 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6160 PPC_SEGMENT | PPC_EXTERN;
6161 pcc->msr_mask = (1ull << MSR_POW) |
6162 (1ull << MSR_ILE) |
6163 (1ull << MSR_EE) |
6164 (1ull << MSR_PR) |
6165 (1ull << MSR_FP) |
6166 (1ull << MSR_ME) |
6167 (1ull << MSR_FE0) |
6168 (1ull << MSR_SE) |
6169 (1ull << MSR_DE) |
6170 (1ull << MSR_FE1) |
6171 (1ull << MSR_EP) |
6172 (1ull << MSR_IR) |
6173 (1ull << MSR_DR) |
6174 (1ull << MSR_PMM) |
6175 (1ull << MSR_RI) |
6176 (1ull << MSR_LE);
6177 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6178 pcc->excp_model = POWERPC_EXCP_7x5;
6179 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6180 pcc->bfd_mach = bfd_mach_ppc_750;
6181 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6182 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6183 }
6184
6185 static void init_proc_755 (CPUPPCState *env)
6186 {
6187 gen_spr_ne_601(env);
6188 gen_spr_7xx(env);
6189 gen_spr_G2_755(env);
6190 /* Time base */
6191 gen_tbl(env);
6192 /* L2 cache control */
6193 /* XXX : not implemented */
6194 spr_register(env, SPR_L2CR, "L2CR",
6195 SPR_NOACCESS, SPR_NOACCESS,
6196 &spr_read_generic, spr_access_nop,
6197 0x00000000);
6198 /* XXX : not implemented */
6199 spr_register(env, SPR_L2PMCR, "L2PMCR",
6200 SPR_NOACCESS, SPR_NOACCESS,
6201 &spr_read_generic, &spr_write_generic,
6202 0x00000000);
6203 /* Thermal management */
6204 gen_spr_thrm(env);
6205 /* Hardware implementation registers */
6206 /* XXX : not implemented */
6207 spr_register(env, SPR_HID0, "HID0",
6208 SPR_NOACCESS, SPR_NOACCESS,
6209 &spr_read_generic, &spr_write_generic,
6210 0x00000000);
6211 /* XXX : not implemented */
6212 spr_register(env, SPR_HID1, "HID1",
6213 SPR_NOACCESS, SPR_NOACCESS,
6214 &spr_read_generic, &spr_write_generic,
6215 0x00000000);
6216 /* XXX : not implemented */
6217 spr_register(env, SPR_HID2, "HID2",
6218 SPR_NOACCESS, SPR_NOACCESS,
6219 &spr_read_generic, &spr_write_generic,
6220 0x00000000);
6221 /* Memory management */
6222 gen_low_BATs(env);
6223 gen_high_BATs(env);
6224 gen_6xx_7xx_soft_tlb(env, 64, 2);
6225 init_excp_7x5(env);
6226 env->dcache_line_size = 32;
6227 env->icache_line_size = 32;
6228 /* Allocate hardware IRQ controller */
6229 ppc6xx_irq_init(env);
6230 }
6231
6232 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6233 {
6234 DeviceClass *dc = DEVICE_CLASS(oc);
6235 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6236
6237 dc->desc = "PowerPC 755";
6238 pcc->init_proc = init_proc_755;
6239 pcc->check_pow = check_pow_hid0;
6240 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6241 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6242 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6243 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6244 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6245 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6246 PPC_SEGMENT | PPC_EXTERN;
6247 pcc->msr_mask = (1ull << MSR_POW) |
6248 (1ull << MSR_ILE) |
6249 (1ull << MSR_EE) |
6250 (1ull << MSR_PR) |
6251 (1ull << MSR_FP) |
6252 (1ull << MSR_ME) |
6253 (1ull << MSR_FE0) |
6254 (1ull << MSR_SE) |
6255 (1ull << MSR_DE) |
6256 (1ull << MSR_FE1) |
6257 (1ull << MSR_EP) |
6258 (1ull << MSR_IR) |
6259 (1ull << MSR_DR) |
6260 (1ull << MSR_PMM) |
6261 (1ull << MSR_RI) |
6262 (1ull << MSR_LE);
6263 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6264 pcc->excp_model = POWERPC_EXCP_7x5;
6265 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6266 pcc->bfd_mach = bfd_mach_ppc_750;
6267 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6268 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6269 }
6270
6271 static void init_proc_7400 (CPUPPCState *env)
6272 {
6273 gen_spr_ne_601(env);
6274 gen_spr_7xx(env);
6275 /* Time base */
6276 gen_tbl(env);
6277 /* 74xx specific SPR */
6278 gen_spr_74xx(env);
6279 /* XXX : not implemented */
6280 spr_register(env, SPR_UBAMR, "UBAMR",
6281 &spr_read_ureg, SPR_NOACCESS,
6282 &spr_read_ureg, SPR_NOACCESS,
6283 0x00000000);
6284 /* XXX: this seems not implemented on all revisions. */
6285 /* XXX : not implemented */
6286 spr_register(env, SPR_MSSCR1, "MSSCR1",
6287 SPR_NOACCESS, SPR_NOACCESS,
6288 &spr_read_generic, &spr_write_generic,
6289 0x00000000);
6290 /* Thermal management */
6291 gen_spr_thrm(env);
6292 /* Memory management */
6293 gen_low_BATs(env);
6294 init_excp_7400(env);
6295 env->dcache_line_size = 32;
6296 env->icache_line_size = 32;
6297 /* Allocate hardware IRQ controller */
6298 ppc6xx_irq_init(env);
6299 }
6300
6301 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6302 {
6303 DeviceClass *dc = DEVICE_CLASS(oc);
6304 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6305
6306 dc->desc = "PowerPC 7400 (aka G4)";
6307 pcc->init_proc = init_proc_7400;
6308 pcc->check_pow = check_pow_hid0;
6309 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6310 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6311 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6312 PPC_FLOAT_STFIWX |
6313 PPC_CACHE | PPC_CACHE_ICBI |
6314 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6315 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6316 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6317 PPC_MEM_TLBIA |
6318 PPC_SEGMENT | PPC_EXTERN |
6319 PPC_ALTIVEC;
6320 pcc->msr_mask = (1ull << MSR_VR) |
6321 (1ull << MSR_POW) |
6322 (1ull << MSR_ILE) |
6323 (1ull << MSR_EE) |
6324 (1ull << MSR_PR) |
6325 (1ull << MSR_FP) |
6326 (1ull << MSR_ME) |
6327 (1ull << MSR_FE0) |
6328 (1ull << MSR_SE) |
6329 (1ull << MSR_DE) |
6330 (1ull << MSR_FE1) |
6331 (1ull << MSR_EP) |
6332 (1ull << MSR_IR) |
6333 (1ull << MSR_DR) |
6334 (1ull << MSR_PMM) |
6335 (1ull << MSR_RI) |
6336 (1ull << MSR_LE);
6337 pcc->mmu_model = POWERPC_MMU_32B;
6338 #if defined(CONFIG_SOFTMMU)
6339 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6340 #endif
6341 pcc->excp_model = POWERPC_EXCP_74xx;
6342 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6343 pcc->bfd_mach = bfd_mach_ppc_7400;
6344 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6345 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6346 POWERPC_FLAG_BUS_CLK;
6347 }
6348
6349 static void init_proc_7410 (CPUPPCState *env)
6350 {
6351 gen_spr_ne_601(env);
6352 gen_spr_7xx(env);
6353 /* Time base */
6354 gen_tbl(env);
6355 /* 74xx specific SPR */
6356 gen_spr_74xx(env);
6357 /* XXX : not implemented */
6358 spr_register(env, SPR_UBAMR, "UBAMR",
6359 &spr_read_ureg, SPR_NOACCESS,
6360 &spr_read_ureg, SPR_NOACCESS,
6361 0x00000000);
6362 /* Thermal management */
6363 gen_spr_thrm(env);
6364 /* L2PMCR */
6365 /* XXX : not implemented */
6366 spr_register(env, SPR_L2PMCR, "L2PMCR",
6367 SPR_NOACCESS, SPR_NOACCESS,
6368 &spr_read_generic, &spr_write_generic,
6369 0x00000000);
6370 /* LDSTDB */
6371 /* XXX : not implemented */
6372 spr_register(env, SPR_LDSTDB, "LDSTDB",
6373 SPR_NOACCESS, SPR_NOACCESS,
6374 &spr_read_generic, &spr_write_generic,
6375 0x00000000);
6376 /* Memory management */
6377 gen_low_BATs(env);
6378 init_excp_7400(env);
6379 env->dcache_line_size = 32;
6380 env->icache_line_size = 32;
6381 /* Allocate hardware IRQ controller */
6382 ppc6xx_irq_init(env);
6383 }
6384
6385 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6386 {
6387 DeviceClass *dc = DEVICE_CLASS(oc);
6388 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6389
6390 dc->desc = "PowerPC 7410 (aka G4)";
6391 pcc->init_proc = init_proc_7410;
6392 pcc->check_pow = check_pow_hid0;
6393 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6394 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6395 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6396 PPC_FLOAT_STFIWX |
6397 PPC_CACHE | PPC_CACHE_ICBI |
6398 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6399 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6400 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6401 PPC_MEM_TLBIA |
6402 PPC_SEGMENT | PPC_EXTERN |
6403 PPC_ALTIVEC;
6404 pcc->msr_mask = (1ull << MSR_VR) |
6405 (1ull << MSR_POW) |
6406 (1ull << MSR_ILE) |
6407 (1ull << MSR_EE) |
6408 (1ull << MSR_PR) |
6409 (1ull << MSR_FP) |
6410 (1ull << MSR_ME) |
6411 (1ull << MSR_FE0) |
6412 (1ull << MSR_SE) |
6413 (1ull << MSR_DE) |
6414 (1ull << MSR_FE1) |
6415 (1ull << MSR_EP) |
6416 (1ull << MSR_IR) |
6417 (1ull << MSR_DR) |
6418 (1ull << MSR_PMM) |
6419 (1ull << MSR_RI) |
6420 (1ull << MSR_LE);
6421 pcc->mmu_model = POWERPC_MMU_32B;
6422 #if defined(CONFIG_SOFTMMU)
6423 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6424 #endif
6425 pcc->excp_model = POWERPC_EXCP_74xx;
6426 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6427 pcc->bfd_mach = bfd_mach_ppc_7400;
6428 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6429 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6430 POWERPC_FLAG_BUS_CLK;
6431 }
6432
6433 static void init_proc_7440 (CPUPPCState *env)
6434 {
6435 gen_spr_ne_601(env);
6436 gen_spr_7xx(env);
6437 /* Time base */
6438 gen_tbl(env);
6439 /* 74xx specific SPR */
6440 gen_spr_74xx(env);
6441 /* XXX : not implemented */
6442 spr_register(env, SPR_UBAMR, "UBAMR",
6443 &spr_read_ureg, SPR_NOACCESS,
6444 &spr_read_ureg, SPR_NOACCESS,
6445 0x00000000);
6446 /* LDSTCR */
6447 /* XXX : not implemented */
6448 spr_register(env, SPR_LDSTCR, "LDSTCR",
6449 SPR_NOACCESS, SPR_NOACCESS,
6450 &spr_read_generic, &spr_write_generic,
6451 0x00000000);
6452 /* ICTRL */
6453 /* XXX : not implemented */
6454 spr_register(env, SPR_ICTRL, "ICTRL",
6455 SPR_NOACCESS, SPR_NOACCESS,
6456 &spr_read_generic, &spr_write_generic,
6457 0x00000000);
6458 /* MSSSR0 */
6459 /* XXX : not implemented */
6460 spr_register(env, SPR_MSSSR0, "MSSSR0",
6461 SPR_NOACCESS, SPR_NOACCESS,
6462 &spr_read_generic, &spr_write_generic,
6463 0x00000000);
6464 /* PMC */
6465 /* XXX : not implemented */
6466 spr_register(env, SPR_PMC5, "PMC5",
6467 SPR_NOACCESS, SPR_NOACCESS,
6468 &spr_read_generic, &spr_write_generic,
6469 0x00000000);
6470 /* XXX : not implemented */
6471 spr_register(env, SPR_UPMC5, "UPMC5",
6472 &spr_read_ureg, SPR_NOACCESS,
6473 &spr_read_ureg, SPR_NOACCESS,
6474 0x00000000);
6475 /* XXX : not implemented */
6476 spr_register(env, SPR_PMC6, "PMC6",
6477 SPR_NOACCESS, SPR_NOACCESS,
6478 &spr_read_generic, &spr_write_generic,
6479 0x00000000);
6480 /* XXX : not implemented */
6481 spr_register(env, SPR_UPMC6, "UPMC6",
6482 &spr_read_ureg, SPR_NOACCESS,
6483 &spr_read_ureg, SPR_NOACCESS,
6484 0x00000000);
6485 /* Memory management */
6486 gen_low_BATs(env);
6487 gen_74xx_soft_tlb(env, 128, 2);
6488 init_excp_7450(env);
6489 env->dcache_line_size = 32;
6490 env->icache_line_size = 32;
6491 /* Allocate hardware IRQ controller */
6492 ppc6xx_irq_init(env);
6493 }
6494
6495 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6496 {
6497 DeviceClass *dc = DEVICE_CLASS(oc);
6498 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6499
6500 dc->desc = "PowerPC 7440 (aka G4)";
6501 pcc->init_proc = init_proc_7440;
6502 pcc->check_pow = check_pow_hid0_74xx;
6503 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6504 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6505 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6506 PPC_FLOAT_STFIWX |
6507 PPC_CACHE | PPC_CACHE_ICBI |
6508 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6509 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6510 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6511 PPC_MEM_TLBIA | PPC_74xx_TLB |
6512 PPC_SEGMENT | PPC_EXTERN |
6513 PPC_ALTIVEC;
6514 pcc->msr_mask = (1ull << MSR_VR) |
6515 (1ull << MSR_POW) |
6516 (1ull << MSR_ILE) |
6517 (1ull << MSR_EE) |
6518 (1ull << MSR_PR) |
6519 (1ull << MSR_FP) |
6520 (1ull << MSR_ME) |
6521 (1ull << MSR_FE0) |
6522 (1ull << MSR_SE) |
6523 (1ull << MSR_DE) |
6524 (1ull << MSR_FE1) |
6525 (1ull << MSR_EP) |
6526 (1ull << MSR_IR) |
6527 (1ull << MSR_DR) |
6528 (1ull << MSR_PMM) |
6529 (1ull << MSR_RI) |
6530 (1ull << MSR_LE);
6531 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6532 pcc->excp_model = POWERPC_EXCP_74xx;
6533 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6534 pcc->bfd_mach = bfd_mach_ppc_7400;
6535 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6536 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6537 POWERPC_FLAG_BUS_CLK;
6538 }
6539
6540 static void init_proc_7450 (CPUPPCState *env)
6541 {
6542 gen_spr_ne_601(env);
6543 gen_spr_7xx(env);
6544 /* Time base */
6545 gen_tbl(env);
6546 /* 74xx specific SPR */
6547 gen_spr_74xx(env);
6548 /* Level 3 cache control */
6549 gen_l3_ctrl(env);
6550 /* L3ITCR1 */
6551 /* XXX : not implemented */
6552 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6553 SPR_NOACCESS, SPR_NOACCESS,
6554 &spr_read_generic, &spr_write_generic,
6555 0x00000000);
6556 /* L3ITCR2 */
6557 /* XXX : not implemented */
6558 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6559 SPR_NOACCESS, SPR_NOACCESS,
6560 &spr_read_generic, &spr_write_generic,
6561 0x00000000);
6562 /* L3ITCR3 */
6563 /* XXX : not implemented */
6564 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6565 SPR_NOACCESS, SPR_NOACCESS,
6566 &spr_read_generic, &spr_write_generic,
6567 0x00000000);
6568 /* L3OHCR */
6569 /* XXX : not implemented */
6570 spr_register(env, SPR_L3OHCR, "L3OHCR",
6571 SPR_NOACCESS, SPR_NOACCESS,
6572 &spr_read_generic, &spr_write_generic,
6573 0x00000000);
6574 /* XXX : not implemented */
6575 spr_register(env, SPR_UBAMR, "UBAMR",
6576 &spr_read_ureg, SPR_NOACCESS,
6577 &spr_read_ureg, SPR_NOACCESS,
6578 0x00000000);
6579 /* LDSTCR */
6580 /* XXX : not implemented */
6581 spr_register(env, SPR_LDSTCR, "LDSTCR",
6582 SPR_NOACCESS, SPR_NOACCESS,
6583 &spr_read_generic, &spr_write_generic,
6584 0x00000000);
6585 /* ICTRL */
6586 /* XXX : not implemented */
6587 spr_register(env, SPR_ICTRL, "ICTRL",
6588 SPR_NOACCESS, SPR_NOACCESS,
6589 &spr_read_generic, &spr_write_generic,
6590 0x00000000);
6591 /* MSSSR0 */
6592 /* XXX : not implemented */
6593 spr_register(env, SPR_MSSSR0, "MSSSR0",
6594 SPR_NOACCESS, SPR_NOACCESS,
6595 &spr_read_generic, &spr_write_generic,
6596 0x00000000);
6597 /* PMC */
6598 /* XXX : not implemented */
6599 spr_register(env, SPR_PMC5, "PMC5",
6600 SPR_NOACCESS, SPR_NOACCESS,
6601 &spr_read_generic, &spr_write_generic,
6602 0x00000000);
6603 /* XXX : not implemented */
6604 spr_register(env, SPR_UPMC5, "UPMC5",
6605 &spr_read_ureg, SPR_NOACCESS,
6606 &spr_read_ureg, SPR_NOACCESS,
6607 0x00000000);
6608 /* XXX : not implemented */
6609 spr_register(env, SPR_PMC6, "PMC6",
6610 SPR_NOACCESS, SPR_NOACCESS,
6611 &spr_read_generic, &spr_write_generic,
6612 0x00000000);
6613 /* XXX : not implemented */
6614 spr_register(env, SPR_UPMC6, "UPMC6",
6615 &spr_read_ureg, SPR_NOACCESS,
6616 &spr_read_ureg, SPR_NOACCESS,
6617 0x00000000);
6618 /* Memory management */
6619 gen_low_BATs(env);
6620 gen_74xx_soft_tlb(env, 128, 2);
6621 init_excp_7450(env);
6622 env->dcache_line_size = 32;
6623 env->icache_line_size = 32;
6624 /* Allocate hardware IRQ controller */
6625 ppc6xx_irq_init(env);
6626 }
6627
6628 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6629 {
6630 DeviceClass *dc = DEVICE_CLASS(oc);
6631 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6632
6633 dc->desc = "PowerPC 7450 (aka G4)";
6634 pcc->init_proc = init_proc_7450;
6635 pcc->check_pow = check_pow_hid0_74xx;
6636 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6637 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6638 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6639 PPC_FLOAT_STFIWX |
6640 PPC_CACHE | PPC_CACHE_ICBI |
6641 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6642 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6643 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6644 PPC_MEM_TLBIA | PPC_74xx_TLB |
6645 PPC_SEGMENT | PPC_EXTERN |
6646 PPC_ALTIVEC;
6647 pcc->msr_mask = (1ull << MSR_VR) |
6648 (1ull << MSR_POW) |
6649 (1ull << MSR_ILE) |
6650 (1ull << MSR_EE) |
6651 (1ull << MSR_PR) |
6652 (1ull << MSR_FP) |
6653 (1ull << MSR_ME) |
6654 (1ull << MSR_FE0) |
6655 (1ull << MSR_SE) |
6656 (1ull << MSR_DE) |
6657 (1ull << MSR_FE1) |
6658 (1ull << MSR_EP) |
6659 (1ull << MSR_IR) |
6660 (1ull << MSR_DR) |
6661 (1ull << MSR_PMM) |
6662 (1ull << MSR_RI) |
6663 (1ull << MSR_LE);
6664 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6665 pcc->excp_model = POWERPC_EXCP_74xx;
6666 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6667 pcc->bfd_mach = bfd_mach_ppc_7400;
6668 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6669 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6670 POWERPC_FLAG_BUS_CLK;
6671 }
6672
6673 static void init_proc_7445 (CPUPPCState *env)
6674 {
6675 gen_spr_ne_601(env);
6676 gen_spr_7xx(env);
6677 /* Time base */
6678 gen_tbl(env);
6679 /* 74xx specific SPR */
6680 gen_spr_74xx(env);
6681 /* LDSTCR */
6682 /* XXX : not implemented */
6683 spr_register(env, SPR_LDSTCR, "LDSTCR",
6684 SPR_NOACCESS, SPR_NOACCESS,
6685 &spr_read_generic, &spr_write_generic,
6686 0x00000000);
6687 /* ICTRL */
6688 /* XXX : not implemented */
6689 spr_register(env, SPR_ICTRL, "ICTRL",
6690 SPR_NOACCESS, SPR_NOACCESS,
6691 &spr_read_generic, &spr_write_generic,
6692 0x00000000);
6693 /* MSSSR0 */
6694 /* XXX : not implemented */
6695 spr_register(env, SPR_MSSSR0, "MSSSR0",
6696 SPR_NOACCESS, SPR_NOACCESS,
6697 &spr_read_generic, &spr_write_generic,
6698 0x00000000);
6699 /* PMC */
6700 /* XXX : not implemented */
6701 spr_register(env, SPR_PMC5, "PMC5",
6702 SPR_NOACCESS, SPR_NOACCESS,
6703 &spr_read_generic, &spr_write_generic,
6704 0x00000000);
6705 /* XXX : not implemented */
6706 spr_register(env, SPR_UPMC5, "UPMC5",
6707 &spr_read_ureg, SPR_NOACCESS,
6708 &spr_read_ureg, SPR_NOACCESS,
6709 0x00000000);
6710 /* XXX : not implemented */
6711 spr_register(env, SPR_PMC6, "PMC6",
6712 SPR_NOACCESS, SPR_NOACCESS,
6713 &spr_read_generic, &spr_write_generic,
6714 0x00000000);
6715 /* XXX : not implemented */
6716 spr_register(env, SPR_UPMC6, "UPMC6",
6717 &spr_read_ureg, SPR_NOACCESS,
6718 &spr_read_ureg, SPR_NOACCESS,
6719 0x00000000);
6720 /* SPRGs */
6721 spr_register(env, SPR_SPRG4, "SPRG4",
6722 SPR_NOACCESS, SPR_NOACCESS,
6723 &spr_read_generic, &spr_write_generic,
6724 0x00000000);
6725 spr_register(env, SPR_USPRG4, "USPRG4",
6726 &spr_read_ureg, SPR_NOACCESS,
6727 &spr_read_ureg, SPR_NOACCESS,
6728 0x00000000);
6729 spr_register(env, SPR_SPRG5, "SPRG5",
6730 SPR_NOACCESS, SPR_NOACCESS,
6731 &spr_read_generic, &spr_write_generic,
6732 0x00000000);
6733 spr_register(env, SPR_USPRG5, "USPRG5",
6734 &spr_read_ureg, SPR_NOACCESS,
6735 &spr_read_ureg, SPR_NOACCESS,
6736 0x00000000);
6737 spr_register(env, SPR_SPRG6, "SPRG6",
6738 SPR_NOACCESS, SPR_NOACCESS,
6739 &spr_read_generic, &spr_write_generic,
6740 0x00000000);
6741 spr_register(env, SPR_USPRG6, "USPRG6",
6742 &spr_read_ureg, SPR_NOACCESS,
6743 &spr_read_ureg, SPR_NOACCESS,
6744 0x00000000);
6745 spr_register(env, SPR_SPRG7, "SPRG7",
6746 SPR_NOACCESS, SPR_NOACCESS,
6747 &spr_read_generic, &spr_write_generic,
6748 0x00000000);
6749 spr_register(env, SPR_USPRG7, "USPRG7",
6750 &spr_read_ureg, SPR_NOACCESS,
6751 &spr_read_ureg, SPR_NOACCESS,
6752 0x00000000);
6753 /* Memory management */
6754 gen_low_BATs(env);
6755 gen_high_BATs(env);
6756 gen_74xx_soft_tlb(env, 128, 2);
6757 init_excp_7450(env);
6758 env->dcache_line_size = 32;
6759 env->icache_line_size = 32;
6760 /* Allocate hardware IRQ controller */
6761 ppc6xx_irq_init(env);
6762 }
6763
6764 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6765 {
6766 DeviceClass *dc = DEVICE_CLASS(oc);
6767 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6768
6769 dc->desc = "PowerPC 7445 (aka G4)";
6770 pcc->init_proc = init_proc_7445;
6771 pcc->check_pow = check_pow_hid0_74xx;
6772 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6773 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6774 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6775 PPC_FLOAT_STFIWX |
6776 PPC_CACHE | PPC_CACHE_ICBI |
6777 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6778 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6779 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6780 PPC_MEM_TLBIA | PPC_74xx_TLB |
6781 PPC_SEGMENT | PPC_EXTERN |
6782 PPC_ALTIVEC;
6783 pcc->msr_mask = (1ull << MSR_VR) |
6784 (1ull << MSR_POW) |
6785 (1ull << MSR_ILE) |
6786 (1ull << MSR_EE) |
6787 (1ull << MSR_PR) |
6788 (1ull << MSR_FP) |
6789 (1ull << MSR_ME) |
6790 (1ull << MSR_FE0) |
6791 (1ull << MSR_SE) |
6792 (1ull << MSR_DE) |
6793 (1ull << MSR_FE1) |
6794 (1ull << MSR_EP) |
6795 (1ull << MSR_IR) |
6796 (1ull << MSR_DR) |
6797 (1ull << MSR_PMM) |
6798 (1ull << MSR_RI) |
6799 (1ull << MSR_LE);
6800 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6801 pcc->excp_model = POWERPC_EXCP_74xx;
6802 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6803 pcc->bfd_mach = bfd_mach_ppc_7400;
6804 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6805 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6806 POWERPC_FLAG_BUS_CLK;
6807 }
6808
6809 static void init_proc_7455 (CPUPPCState *env)
6810 {
6811 gen_spr_ne_601(env);
6812 gen_spr_7xx(env);
6813 /* Time base */
6814 gen_tbl(env);
6815 /* 74xx specific SPR */
6816 gen_spr_74xx(env);
6817 /* Level 3 cache control */
6818 gen_l3_ctrl(env);
6819 /* LDSTCR */
6820 /* XXX : not implemented */
6821 spr_register(env, SPR_LDSTCR, "LDSTCR",
6822 SPR_NOACCESS, SPR_NOACCESS,
6823 &spr_read_generic, &spr_write_generic,
6824 0x00000000);
6825 /* ICTRL */
6826 /* XXX : not implemented */
6827 spr_register(env, SPR_ICTRL, "ICTRL",
6828 SPR_NOACCESS, SPR_NOACCESS,
6829 &spr_read_generic, &spr_write_generic,
6830 0x00000000);
6831 /* MSSSR0 */
6832 /* XXX : not implemented */
6833 spr_register(env, SPR_MSSSR0, "MSSSR0",
6834 SPR_NOACCESS, SPR_NOACCESS,
6835 &spr_read_generic, &spr_write_generic,
6836 0x00000000);
6837 /* PMC */
6838 /* XXX : not implemented */
6839 spr_register(env, SPR_PMC5, "PMC5",
6840 SPR_NOACCESS, SPR_NOACCESS,
6841 &spr_read_generic, &spr_write_generic,
6842 0x00000000);
6843 /* XXX : not implemented */
6844 spr_register(env, SPR_UPMC5, "UPMC5",
6845 &spr_read_ureg, SPR_NOACCESS,
6846 &spr_read_ureg, SPR_NOACCESS,
6847 0x00000000);
6848 /* XXX : not implemented */
6849 spr_register(env, SPR_PMC6, "PMC6",
6850 SPR_NOACCESS, SPR_NOACCESS,
6851 &spr_read_generic, &spr_write_generic,
6852 0x00000000);
6853 /* XXX : not implemented */
6854 spr_register(env, SPR_UPMC6, "UPMC6",
6855 &spr_read_ureg, SPR_NOACCESS,
6856 &spr_read_ureg, SPR_NOACCESS,
6857 0x00000000);
6858 /* SPRGs */
6859 spr_register(env, SPR_SPRG4, "SPRG4",
6860 SPR_NOACCESS, SPR_NOACCESS,
6861 &spr_read_generic, &spr_write_generic,
6862 0x00000000);
6863 spr_register(env, SPR_USPRG4, "USPRG4",
6864 &spr_read_ureg, SPR_NOACCESS,
6865 &spr_read_ureg, SPR_NOACCESS,
6866 0x00000000);
6867 spr_register(env, SPR_SPRG5, "SPRG5",
6868 SPR_NOACCESS, SPR_NOACCESS,
6869 &spr_read_generic, &spr_write_generic,
6870 0x00000000);
6871 spr_register(env, SPR_USPRG5, "USPRG5",
6872 &spr_read_ureg, SPR_NOACCESS,
6873 &spr_read_ureg, SPR_NOACCESS,
6874 0x00000000);
6875 spr_register(env, SPR_SPRG6, "SPRG6",
6876 SPR_NOACCESS, SPR_NOACCESS,
6877 &spr_read_generic, &spr_write_generic,
6878 0x00000000);
6879 spr_register(env, SPR_USPRG6, "USPRG6",
6880 &spr_read_ureg, SPR_NOACCESS,
6881 &spr_read_ureg, SPR_NOACCESS,
6882 0x00000000);
6883 spr_register(env, SPR_SPRG7, "SPRG7",
6884 SPR_NOACCESS, SPR_NOACCESS,
6885 &spr_read_generic, &spr_write_generic,
6886 0x00000000);
6887 spr_register(env, SPR_USPRG7, "USPRG7",
6888 &spr_read_ureg, SPR_NOACCESS,
6889 &spr_read_ureg, SPR_NOACCESS,
6890 0x00000000);
6891 /* Memory management */
6892 gen_low_BATs(env);
6893 gen_high_BATs(env);
6894 gen_74xx_soft_tlb(env, 128, 2);
6895 init_excp_7450(env);
6896 env->dcache_line_size = 32;
6897 env->icache_line_size = 32;
6898 /* Allocate hardware IRQ controller */
6899 ppc6xx_irq_init(env);
6900 }
6901
6902 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6903 {
6904 DeviceClass *dc = DEVICE_CLASS(oc);
6905 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6906
6907 dc->desc = "PowerPC 7455 (aka G4)";
6908 pcc->init_proc = init_proc_7455;
6909 pcc->check_pow = check_pow_hid0_74xx;
6910 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6911 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6912 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6913 PPC_FLOAT_STFIWX |
6914 PPC_CACHE | PPC_CACHE_ICBI |
6915 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6916 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6917 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6918 PPC_MEM_TLBIA | PPC_74xx_TLB |
6919 PPC_SEGMENT | PPC_EXTERN |
6920 PPC_ALTIVEC;
6921 pcc->msr_mask = (1ull << MSR_VR) |
6922 (1ull << MSR_POW) |
6923 (1ull << MSR_ILE) |
6924 (1ull << MSR_EE) |
6925 (1ull << MSR_PR) |
6926 (1ull << MSR_FP) |
6927 (1ull << MSR_ME) |
6928 (1ull << MSR_FE0) |
6929 (1ull << MSR_SE) |
6930 (1ull << MSR_DE) |
6931 (1ull << MSR_FE1) |
6932 (1ull << MSR_EP) |
6933 (1ull << MSR_IR) |
6934 (1ull << MSR_DR) |
6935 (1ull << MSR_PMM) |
6936 (1ull << MSR_RI) |
6937 (1ull << MSR_LE);
6938 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6939 pcc->excp_model = POWERPC_EXCP_74xx;
6940 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6941 pcc->bfd_mach = bfd_mach_ppc_7400;
6942 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6943 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6944 POWERPC_FLAG_BUS_CLK;
6945 }
6946
6947 static void init_proc_7457 (CPUPPCState *env)
6948 {
6949 gen_spr_ne_601(env);
6950 gen_spr_7xx(env);
6951 /* Time base */
6952 gen_tbl(env);
6953 /* 74xx specific SPR */
6954 gen_spr_74xx(env);
6955 /* Level 3 cache control */
6956 gen_l3_ctrl(env);
6957 /* L3ITCR1 */
6958 /* XXX : not implemented */
6959 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6960 SPR_NOACCESS, SPR_NOACCESS,
6961 &spr_read_generic, &spr_write_generic,
6962 0x00000000);
6963 /* L3ITCR2 */
6964 /* XXX : not implemented */
6965 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6966 SPR_NOACCESS, SPR_NOACCESS,
6967 &spr_read_generic, &spr_write_generic,
6968 0x00000000);
6969 /* L3ITCR3 */
6970 /* XXX : not implemented */
6971 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6972 SPR_NOACCESS, SPR_NOACCESS,
6973 &spr_read_generic, &spr_write_generic,
6974 0x00000000);
6975 /* L3OHCR */
6976 /* XXX : not implemented */
6977 spr_register(env, SPR_L3OHCR, "L3OHCR",
6978 SPR_NOACCESS, SPR_NOACCESS,
6979 &spr_read_generic, &spr_write_generic,
6980 0x00000000);
6981 /* LDSTCR */
6982 /* XXX : not implemented */
6983 spr_register(env, SPR_LDSTCR, "LDSTCR",
6984 SPR_NOACCESS, SPR_NOACCESS,
6985 &spr_read_generic, &spr_write_generic,
6986 0x00000000);
6987 /* ICTRL */
6988 /* XXX : not implemented */
6989 spr_register(env, SPR_ICTRL, "ICTRL",
6990 SPR_NOACCESS, SPR_NOACCESS,
6991 &spr_read_generic, &spr_write_generic,
6992 0x00000000);
6993 /* MSSSR0 */
6994 /* XXX : not implemented */
6995 spr_register(env, SPR_MSSSR0, "MSSSR0",
6996 SPR_NOACCESS, SPR_NOACCESS,
6997 &spr_read_generic, &spr_write_generic,
6998 0x00000000);
6999 /* PMC */
7000 /* XXX : not implemented */
7001 spr_register(env, SPR_PMC5, "PMC5",
7002 SPR_NOACCESS, SPR_NOACCESS,
7003 &spr_read_generic, &spr_write_generic,
7004 0x00000000);
7005 /* XXX : not implemented */
7006 spr_register(env, SPR_UPMC5, "UPMC5",
7007 &spr_read_ureg, SPR_NOACCESS,
7008 &spr_read_ureg, SPR_NOACCESS,
7009 0x00000000);
7010 /* XXX : not implemented */
7011 spr_register(env, SPR_PMC6, "PMC6",
7012 SPR_NOACCESS, SPR_NOACCESS,
7013 &spr_read_generic, &spr_write_generic,
7014 0x00000000);
7015 /* XXX : not implemented */
7016 spr_register(env, SPR_UPMC6, "UPMC6",
7017 &spr_read_ureg, SPR_NOACCESS,
7018 &spr_read_ureg, SPR_NOACCESS,
7019 0x00000000);
7020 /* SPRGs */
7021 spr_register(env, SPR_SPRG4, "SPRG4",
7022 SPR_NOACCESS, SPR_NOACCESS,
7023 &spr_read_generic, &spr_write_generic,
7024 0x00000000);
7025 spr_register(env, SPR_USPRG4, "USPRG4",
7026 &spr_read_ureg, SPR_NOACCESS,
7027 &spr_read_ureg, SPR_NOACCESS,
7028 0x00000000);
7029 spr_register(env, SPR_SPRG5, "SPRG5",
7030 SPR_NOACCESS, SPR_NOACCESS,
7031 &spr_read_generic, &spr_write_generic,
7032 0x00000000);
7033 spr_register(env, SPR_USPRG5, "USPRG5",
7034 &spr_read_ureg, SPR_NOACCESS,
7035 &spr_read_ureg, SPR_NOACCESS,
7036 0x00000000);
7037 spr_register(env, SPR_SPRG6, "SPRG6",
7038 SPR_NOACCESS, SPR_NOACCESS,
7039 &spr_read_generic, &spr_write_generic,
7040 0x00000000);
7041 spr_register(env, SPR_USPRG6, "USPRG6",
7042 &spr_read_ureg, SPR_NOACCESS,
7043 &spr_read_ureg, SPR_NOACCESS,
7044 0x00000000);
7045 spr_register(env, SPR_SPRG7, "SPRG7",
7046 SPR_NOACCESS, SPR_NOACCESS,
7047 &spr_read_generic, &spr_write_generic,
7048 0x00000000);
7049 spr_register(env, SPR_USPRG7, "USPRG7",
7050 &spr_read_ureg, SPR_NOACCESS,
7051 &spr_read_ureg, SPR_NOACCESS,
7052 0x00000000);
7053 /* Memory management */
7054 gen_low_BATs(env);
7055 gen_high_BATs(env);
7056 gen_74xx_soft_tlb(env, 128, 2);
7057 init_excp_7450(env);
7058 env->dcache_line_size = 32;
7059 env->icache_line_size = 32;
7060 /* Allocate hardware IRQ controller */
7061 ppc6xx_irq_init(env);
7062 }
7063
7064 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7065 {
7066 DeviceClass *dc = DEVICE_CLASS(oc);
7067 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7068
7069 dc->desc = "PowerPC 7457 (aka G4)";
7070 pcc->init_proc = init_proc_7457;
7071 pcc->check_pow = check_pow_hid0_74xx;
7072 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7073 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7074 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7075 PPC_FLOAT_STFIWX |
7076 PPC_CACHE | PPC_CACHE_ICBI |
7077 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7078 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7079 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7080 PPC_MEM_TLBIA | PPC_74xx_TLB |
7081 PPC_SEGMENT | PPC_EXTERN |
7082 PPC_ALTIVEC;
7083 pcc->msr_mask = (1ull << MSR_VR) |
7084 (1ull << MSR_POW) |
7085 (1ull << MSR_ILE) |
7086 (1ull << MSR_EE) |
7087 (1ull << MSR_PR) |
7088 (1ull << MSR_FP) |
7089 (1ull << MSR_ME) |
7090 (1ull << MSR_FE0) |
7091 (1ull << MSR_SE) |
7092 (1ull << MSR_DE) |
7093 (1ull << MSR_FE1) |
7094 (1ull << MSR_EP) |
7095 (1ull << MSR_IR) |
7096 (1ull << MSR_DR) |
7097 (1ull << MSR_PMM) |
7098 (1ull << MSR_RI) |
7099 (1ull << MSR_LE);
7100 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7101 pcc->excp_model = POWERPC_EXCP_74xx;
7102 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7103 pcc->bfd_mach = bfd_mach_ppc_7400;
7104 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7105 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7106 POWERPC_FLAG_BUS_CLK;
7107 }
7108
7109 static void init_proc_e600 (CPUPPCState *env)
7110 {
7111 gen_spr_ne_601(env);
7112 gen_spr_7xx(env);
7113 /* Time base */
7114 gen_tbl(env);
7115 /* 74xx specific SPR */
7116 gen_spr_74xx(env);
7117 /* XXX : not implemented */
7118 spr_register(env, SPR_UBAMR, "UBAMR",
7119 &spr_read_ureg, SPR_NOACCESS,
7120 &spr_read_ureg, SPR_NOACCESS,
7121 0x00000000);
7122 /* XXX : not implemented */
7123 spr_register(env, SPR_LDSTCR, "LDSTCR",
7124 SPR_NOACCESS, SPR_NOACCESS,
7125 &spr_read_generic, &spr_write_generic,
7126 0x00000000);
7127 /* XXX : not implemented */
7128 spr_register(env, SPR_ICTRL, "ICTRL",
7129 SPR_NOACCESS, SPR_NOACCESS,
7130 &spr_read_generic, &spr_write_generic,
7131 0x00000000);
7132 /* XXX : not implemented */
7133 spr_register(env, SPR_MSSSR0, "MSSSR0",
7134 SPR_NOACCESS, SPR_NOACCESS,
7135 &spr_read_generic, &spr_write_generic,
7136 0x00000000);
7137 /* XXX : not implemented */
7138 spr_register(env, SPR_PMC5, "PMC5",
7139 SPR_NOACCESS, SPR_NOACCESS,
7140 &spr_read_generic, &spr_write_generic,
7141 0x00000000);
7142 /* XXX : not implemented */
7143 spr_register(env, SPR_UPMC5, "UPMC5",
7144 &spr_read_ureg, SPR_NOACCESS,
7145 &spr_read_ureg, SPR_NOACCESS,
7146 0x00000000);
7147 /* XXX : not implemented */
7148 spr_register(env, SPR_PMC6, "PMC6",
7149 SPR_NOACCESS, SPR_NOACCESS,
7150 &spr_read_generic, &spr_write_generic,
7151 0x00000000);
7152 /* XXX : not implemented */
7153 spr_register(env, SPR_UPMC6, "UPMC6",
7154 &spr_read_ureg, SPR_NOACCESS,
7155 &spr_read_ureg, SPR_NOACCESS,
7156 0x00000000);
7157 /* SPRGs */
7158 spr_register(env, SPR_SPRG4, "SPRG4",
7159 SPR_NOACCESS, SPR_NOACCESS,
7160 &spr_read_generic, &spr_write_generic,
7161 0x00000000);
7162 spr_register(env, SPR_USPRG4, "USPRG4",
7163 &spr_read_ureg, SPR_NOACCESS,
7164 &spr_read_ureg, SPR_NOACCESS,
7165 0x00000000);
7166 spr_register(env, SPR_SPRG5, "SPRG5",
7167 SPR_NOACCESS, SPR_NOACCESS,
7168 &spr_read_generic, &spr_write_generic,
7169 0x00000000);
7170 spr_register(env, SPR_USPRG5, "USPRG5",
7171 &spr_read_ureg, SPR_NOACCESS,
7172 &spr_read_ureg, SPR_NOACCESS,
7173 0x00000000);
7174 spr_register(env, SPR_SPRG6, "SPRG6",
7175 SPR_NOACCESS, SPR_NOACCESS,
7176 &spr_read_generic, &spr_write_generic,
7177 0x00000000);
7178 spr_register(env, SPR_USPRG6, "USPRG6",
7179 &spr_read_ureg, SPR_NOACCESS,
7180 &spr_read_ureg, SPR_NOACCESS,
7181 0x00000000);
7182 spr_register(env, SPR_SPRG7, "SPRG7",
7183 SPR_NOACCESS, SPR_NOACCESS,
7184 &spr_read_generic, &spr_write_generic,
7185 0x00000000);
7186 spr_register(env, SPR_USPRG7, "USPRG7",
7187 &spr_read_ureg, SPR_NOACCESS,
7188 &spr_read_ureg, SPR_NOACCESS,
7189 0x00000000);
7190 /* Memory management */
7191 gen_low_BATs(env);
7192 gen_high_BATs(env);
7193 gen_74xx_soft_tlb(env, 128, 2);
7194 init_excp_7450(env);
7195 env->dcache_line_size = 32;
7196 env->icache_line_size = 32;
7197 /* Allocate hardware IRQ controller */
7198 ppc6xx_irq_init(env);
7199 }
7200
7201 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7202 {
7203 DeviceClass *dc = DEVICE_CLASS(oc);
7204 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7205
7206 dc->desc = "PowerPC e600";
7207 pcc->init_proc = init_proc_e600;
7208 pcc->check_pow = check_pow_hid0_74xx;
7209 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7210 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7211 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7212 PPC_FLOAT_STFIWX |
7213 PPC_CACHE | PPC_CACHE_ICBI |
7214 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7215 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7216 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7217 PPC_MEM_TLBIA | PPC_74xx_TLB |
7218 PPC_SEGMENT | PPC_EXTERN |
7219 PPC_ALTIVEC;
7220 pcc->insns_flags2 = PPC_NONE;
7221 pcc->msr_mask = (1ull << MSR_VR) |
7222 (1ull << MSR_POW) |
7223 (1ull << MSR_ILE) |
7224 (1ull << MSR_EE) |
7225 (1ull << MSR_PR) |
7226 (1ull << MSR_FP) |
7227 (1ull << MSR_ME) |
7228 (1ull << MSR_FE0) |
7229 (1ull << MSR_SE) |
7230 (1ull << MSR_DE) |
7231 (1ull << MSR_FE1) |
7232 (1ull << MSR_EP) |
7233 (1ull << MSR_IR) |
7234 (1ull << MSR_DR) |
7235 (1ull << MSR_PMM) |
7236 (1ull << MSR_RI) |
7237 (1ull << MSR_LE);
7238 pcc->mmu_model = POWERPC_MMU_32B;
7239 #if defined(CONFIG_SOFTMMU)
7240 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7241 #endif
7242 pcc->excp_model = POWERPC_EXCP_74xx;
7243 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7244 pcc->bfd_mach = bfd_mach_ppc_7400;
7245 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7246 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7247 POWERPC_FLAG_BUS_CLK;
7248 }
7249
7250 #if defined (TARGET_PPC64)
7251 #if defined(CONFIG_USER_ONLY)
7252 #define POWERPC970_HID5_INIT 0x00000080
7253 #else
7254 #define POWERPC970_HID5_INIT 0x00000000
7255 #endif
7256
7257 static int check_pow_970 (CPUPPCState *env)
7258 {
7259 if (env->spr[SPR_HID0] & 0x00600000)
7260 return 1;
7261
7262 return 0;
7263 }
7264
7265 static void init_proc_970 (CPUPPCState *env)
7266 {
7267 gen_spr_ne_601(env);
7268 gen_spr_7xx(env);
7269 /* Time base */
7270 gen_tbl(env);
7271 /* Hardware implementation registers */
7272 /* XXX : not implemented */
7273 spr_register(env, SPR_HID0, "HID0",
7274 SPR_NOACCESS, SPR_NOACCESS,
7275 &spr_read_generic, &spr_write_clear,
7276 0x60000000);
7277 /* XXX : not implemented */
7278 spr_register(env, SPR_HID1, "HID1",
7279 SPR_NOACCESS, SPR_NOACCESS,
7280 &spr_read_generic, &spr_write_generic,
7281 0x00000000);
7282 /* XXX : not implemented */
7283 spr_register(env, SPR_970_HID5, "HID5",
7284 SPR_NOACCESS, SPR_NOACCESS,
7285 &spr_read_generic, &spr_write_generic,
7286 POWERPC970_HID5_INIT);
7287 /* Memory management */
7288 /* XXX: not correct */
7289 gen_low_BATs(env);
7290 spr_register(env, SPR_HIOR, "SPR_HIOR",
7291 SPR_NOACCESS, SPR_NOACCESS,
7292 &spr_read_hior, &spr_write_hior,
7293 0x00000000);
7294 #if !defined(CONFIG_USER_ONLY)
7295 env->slb_nr = 32;
7296 #endif
7297 init_excp_970(env);
7298 env->dcache_line_size = 128;
7299 env->icache_line_size = 128;
7300 /* Allocate hardware IRQ controller */
7301 ppc970_irq_init(env);
7302 /* Can't find information on what this should be on reset. This
7303 * value is the one used by 74xx processors. */
7304 vscr_init(env, 0x00010000);
7305 }
7306
7307 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7308 {
7309 DeviceClass *dc = DEVICE_CLASS(oc);
7310 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7311
7312 dc->desc = "PowerPC 970";
7313 pcc->init_proc = init_proc_970;
7314 pcc->check_pow = check_pow_970;
7315 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7316 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7317 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7318 PPC_FLOAT_STFIWX |
7319 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7320 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7321 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7322 PPC_64B | PPC_ALTIVEC |
7323 PPC_SEGMENT_64B | PPC_SLBI;
7324 pcc->msr_mask = (1ull << MSR_SF) |
7325 (1ull << MSR_SHV) |
7326 (1ull << MSR_VR) |
7327 (1ull << MSR_POW) |
7328 (1ull << MSR_EE) |
7329 (1ull << MSR_PR) |
7330 (1ull << MSR_FP) |
7331 (1ull << MSR_ME) |
7332 (1ull << MSR_FE0) |
7333 (1ull << MSR_SE) |
7334 (1ull << MSR_DE) |
7335 (1ull << MSR_FE1) |
7336 (1ull << MSR_IR) |
7337 (1ull << MSR_DR) |
7338 (1ull << MSR_PMM) |
7339 (1ull << MSR_RI);
7340 pcc->mmu_model = POWERPC_MMU_64B;
7341 #if defined(CONFIG_SOFTMMU)
7342 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7343 #endif
7344 pcc->excp_model = POWERPC_EXCP_970;
7345 pcc->bus_model = PPC_FLAGS_INPUT_970;
7346 pcc->bfd_mach = bfd_mach_ppc64;
7347 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7348 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7349 POWERPC_FLAG_BUS_CLK;
7350 pcc->l1_dcache_size = 0x8000;
7351 pcc->l1_icache_size = 0x10000;
7352 }
7353
7354 static int check_pow_970FX (CPUPPCState *env)
7355 {
7356 if (env->spr[SPR_HID0] & 0x00600000)
7357 return 1;
7358
7359 return 0;
7360 }
7361
7362 static void init_proc_970FX (CPUPPCState *env)
7363 {
7364 gen_spr_ne_601(env);
7365 gen_spr_7xx(env);
7366 /* Time base */
7367 gen_tbl(env);
7368 /* Hardware implementation registers */
7369 /* XXX : not implemented */
7370 spr_register(env, SPR_HID0, "HID0",
7371 SPR_NOACCESS, SPR_NOACCESS,
7372 &spr_read_generic, &spr_write_clear,
7373 0x60000000);
7374 /* XXX : not implemented */
7375 spr_register(env, SPR_HID1, "HID1",
7376 SPR_NOACCESS, SPR_NOACCESS,
7377 &spr_read_generic, &spr_write_generic,
7378 0x00000000);
7379 /* XXX : not implemented */
7380 spr_register(env, SPR_970_HID5, "HID5",
7381 SPR_NOACCESS, SPR_NOACCESS,
7382 &spr_read_generic, &spr_write_generic,
7383 POWERPC970_HID5_INIT);
7384 /* Memory management */
7385 /* XXX: not correct */
7386 gen_low_BATs(env);
7387 spr_register(env, SPR_HIOR, "SPR_HIOR",
7388 SPR_NOACCESS, SPR_NOACCESS,
7389 &spr_read_hior, &spr_write_hior,
7390 0x00000000);
7391 spr_register(env, SPR_CTRL, "SPR_CTRL",
7392 SPR_NOACCESS, SPR_NOACCESS,
7393 SPR_NOACCESS, &spr_write_generic,
7394 0x00000000);
7395 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7396 SPR_NOACCESS, SPR_NOACCESS,
7397 &spr_read_generic, SPR_NOACCESS,
7398 0x00000000);
7399 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7400 &spr_read_generic, &spr_write_generic,
7401 &spr_read_generic, &spr_write_generic,
7402 0x00000000);
7403 #if !defined(CONFIG_USER_ONLY)
7404 env->slb_nr = 64;
7405 #endif
7406 init_excp_970(env);
7407 env->dcache_line_size = 128;
7408 env->icache_line_size = 128;
7409 /* Allocate hardware IRQ controller */
7410 ppc970_irq_init(env);
7411 /* Can't find information on what this should be on reset. This
7412 * value is the one used by 74xx processors. */
7413 vscr_init(env, 0x00010000);
7414 }
7415
7416 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
7417 {
7418 DeviceClass *dc = DEVICE_CLASS(oc);
7419 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7420
7421 dc->desc = "PowerPC 970FX (aka G5)";
7422 pcc->init_proc = init_proc_970FX;
7423 pcc->check_pow = check_pow_970FX;
7424 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7425 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7426 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7427 PPC_FLOAT_STFIWX |
7428 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7429 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7430 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7431 PPC_64B | PPC_ALTIVEC |
7432 PPC_SEGMENT_64B | PPC_SLBI;
7433 pcc->msr_mask = (1ull << MSR_SF) |
7434 (1ull << MSR_VR) |
7435 (1ull << MSR_POW) |
7436 (1ull << MSR_EE) |
7437 (1ull << MSR_PR) |
7438 (1ull << MSR_FP) |
7439 (1ull << MSR_ME) |
7440 (1ull << MSR_FE0) |
7441 (1ull << MSR_SE) |
7442 (1ull << MSR_DE) |
7443 (1ull << MSR_FE1) |
7444 (1ull << MSR_IR) |
7445 (1ull << MSR_DR) |
7446 (1ull << MSR_PMM) |
7447 (1ull << MSR_RI);
7448 pcc->mmu_model = POWERPC_MMU_64B;
7449 #if defined(CONFIG_SOFTMMU)
7450 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7451 #endif
7452 pcc->excp_model = POWERPC_EXCP_970;
7453 pcc->bus_model = PPC_FLAGS_INPUT_970;
7454 pcc->bfd_mach = bfd_mach_ppc64;
7455 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7456 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7457 POWERPC_FLAG_BUS_CLK;
7458 pcc->l1_dcache_size = 0x8000;
7459 pcc->l1_icache_size = 0x10000;
7460 }
7461
7462 static int check_pow_970MP (CPUPPCState *env)
7463 {
7464 if (env->spr[SPR_HID0] & 0x01C00000)
7465 return 1;
7466
7467 return 0;
7468 }
7469
7470 static void init_proc_970MP (CPUPPCState *env)
7471 {
7472 gen_spr_ne_601(env);
7473 gen_spr_7xx(env);
7474 /* Time base */
7475 gen_tbl(env);
7476 /* Hardware implementation registers */
7477 /* XXX : not implemented */
7478 spr_register(env, SPR_HID0, "HID0",
7479 SPR_NOACCESS, SPR_NOACCESS,
7480 &spr_read_generic, &spr_write_clear,
7481 0x60000000);
7482 /* XXX : not implemented */
7483 spr_register(env, SPR_HID1, "HID1",
7484 SPR_NOACCESS, SPR_NOACCESS,
7485 &spr_read_generic, &spr_write_generic,
7486 0x00000000);
7487 /* XXX : not implemented */
7488 spr_register(env, SPR_970_HID5, "HID5",
7489 SPR_NOACCESS, SPR_NOACCESS,
7490 &spr_read_generic, &spr_write_generic,
7491 POWERPC970_HID5_INIT);
7492 /* XXX : not implemented */
7493 /* Memory management */
7494 /* XXX: not correct */
7495 gen_low_BATs(env);
7496 spr_register(env, SPR_HIOR, "SPR_HIOR",
7497 SPR_NOACCESS, SPR_NOACCESS,
7498 &spr_read_hior, &spr_write_hior,
7499 0x00000000);
7500 /* Logical partitionning */
7501 spr_register_kvm(env, SPR_LPCR, "LPCR",
7502 SPR_NOACCESS, SPR_NOACCESS,
7503 &spr_read_generic, &spr_write_generic,
7504 KVM_REG_PPC_LPCR, 0x00000000);
7505 #if !defined(CONFIG_USER_ONLY)
7506 env->slb_nr = 32;
7507 #endif
7508 init_excp_970(env);
7509 env->dcache_line_size = 128;
7510 env->icache_line_size = 128;
7511 /* Allocate hardware IRQ controller */
7512 ppc970_irq_init(env);
7513 /* Can't find information on what this should be on reset. This
7514 * value is the one used by 74xx processors. */
7515 vscr_init(env, 0x00010000);
7516 }
7517
7518 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
7519 {
7520 DeviceClass *dc = DEVICE_CLASS(oc);
7521 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7522
7523 dc->desc = "PowerPC 970 MP";
7524 pcc->init_proc = init_proc_970MP;
7525 pcc->check_pow = check_pow_970MP;
7526 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7527 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7528 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7529 PPC_FLOAT_STFIWX |
7530 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7531 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7532 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7533 PPC_64B | PPC_ALTIVEC |
7534 PPC_SEGMENT_64B | PPC_SLBI;
7535 pcc->msr_mask = (1ull << MSR_SF) |
7536 (1ull << MSR_SHV) |
7537 (1ull << MSR_VR) |
7538 (1ull << MSR_POW) |
7539 (1ull << MSR_EE) |
7540 (1ull << MSR_PR) |
7541 (1ull << MSR_FP) |
7542 (1ull << MSR_ME) |
7543 (1ull << MSR_FE0) |
7544 (1ull << MSR_SE) |
7545 (1ull << MSR_DE) |
7546 (1ull << MSR_FE1) |
7547 (1ull << MSR_IR) |
7548 (1ull << MSR_DR) |
7549 (1ull << MSR_PMM) |
7550 (1ull << MSR_RI);
7551 pcc->mmu_model = POWERPC_MMU_64B;
7552 #if defined(CONFIG_SOFTMMU)
7553 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7554 #endif
7555 pcc->excp_model = POWERPC_EXCP_970;
7556 pcc->bus_model = PPC_FLAGS_INPUT_970;
7557 pcc->bfd_mach = bfd_mach_ppc64;
7558 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7559 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7560 POWERPC_FLAG_BUS_CLK;
7561 pcc->l1_dcache_size = 0x8000;
7562 pcc->l1_icache_size = 0x10000;
7563 }
7564
7565 static void init_proc_power5plus(CPUPPCState *env)
7566 {
7567 gen_spr_ne_601(env);
7568 gen_spr_7xx(env);
7569 /* Time base */
7570 gen_tbl(env);
7571 /* Hardware implementation registers */
7572 /* XXX : not implemented */
7573 spr_register(env, SPR_HID0, "HID0",
7574 SPR_NOACCESS, SPR_NOACCESS,
7575 &spr_read_generic, &spr_write_clear,
7576 0x60000000);
7577 /* XXX : not implemented */
7578 spr_register(env, SPR_HID1, "HID1",
7579 SPR_NOACCESS, SPR_NOACCESS,
7580 &spr_read_generic, &spr_write_generic,
7581 0x00000000);
7582 /* XXX : not implemented */
7583 spr_register(env, SPR_970_HID5, "HID5",
7584 SPR_NOACCESS, SPR_NOACCESS,
7585 &spr_read_generic, &spr_write_generic,
7586 POWERPC970_HID5_INIT);
7587 /* Memory management */
7588 /* XXX: not correct */
7589 gen_low_BATs(env);
7590 spr_register(env, SPR_HIOR, "SPR_HIOR",
7591 SPR_NOACCESS, SPR_NOACCESS,
7592 &spr_read_hior, &spr_write_hior,
7593 0x00000000);
7594 spr_register(env, SPR_CTRL, "SPR_CTRL",
7595 SPR_NOACCESS, SPR_NOACCESS,
7596 SPR_NOACCESS, &spr_write_generic,
7597 0x00000000);
7598 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7599 SPR_NOACCESS, SPR_NOACCESS,
7600 &spr_read_generic, SPR_NOACCESS,
7601 0x00000000);
7602 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7603 &spr_read_generic, &spr_write_generic,
7604 &spr_read_generic, &spr_write_generic,
7605 0x00000000);
7606 /* Logical partitionning */
7607 spr_register_kvm(env, SPR_LPCR, "LPCR",
7608 SPR_NOACCESS, SPR_NOACCESS,
7609 &spr_read_generic, &spr_write_generic,
7610 KVM_REG_PPC_LPCR, 0x00000000);
7611 #if !defined(CONFIG_USER_ONLY)
7612 env->slb_nr = 64;
7613 #endif
7614 init_excp_970(env);
7615 env->dcache_line_size = 128;
7616 env->icache_line_size = 128;
7617 /* Allocate hardware IRQ controller */
7618 ppc970_irq_init(env);
7619 /* Can't find information on what this should be on reset. This
7620 * value is the one used by 74xx processors. */
7621 vscr_init(env, 0x00010000);
7622 }
7623
7624 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7625 {
7626 DeviceClass *dc = DEVICE_CLASS(oc);
7627 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7628
7629 dc->fw_name = "PowerPC,POWER5";
7630 dc->desc = "POWER5+";
7631 pcc->init_proc = init_proc_power5plus;
7632 pcc->check_pow = check_pow_970FX;
7633 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7634 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7635 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7636 PPC_FLOAT_STFIWX |
7637 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7638 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7639 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7640 PPC_64B |
7641 PPC_SEGMENT_64B | PPC_SLBI;
7642 pcc->msr_mask = (1ull << MSR_SF) |
7643 (1ull << MSR_VR) |
7644 (1ull << MSR_POW) |
7645 (1ull << MSR_EE) |
7646 (1ull << MSR_PR) |
7647 (1ull << MSR_FP) |
7648 (1ull << MSR_ME) |
7649 (1ull << MSR_FE0) |
7650 (1ull << MSR_SE) |
7651 (1ull << MSR_DE) |
7652 (1ull << MSR_FE1) |
7653 (1ull << MSR_IR) |
7654 (1ull << MSR_DR) |
7655 (1ull << MSR_PMM) |
7656 (1ull << MSR_RI);
7657 pcc->mmu_model = POWERPC_MMU_64B;
7658 #if defined(CONFIG_SOFTMMU)
7659 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7660 #endif
7661 pcc->excp_model = POWERPC_EXCP_970;
7662 pcc->bus_model = PPC_FLAGS_INPUT_970;
7663 pcc->bfd_mach = bfd_mach_ppc64;
7664 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7665 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7666 POWERPC_FLAG_BUS_CLK;
7667 pcc->l1_dcache_size = 0x8000;
7668 pcc->l1_icache_size = 0x10000;
7669 }
7670
7671 static void init_proc_POWER7 (CPUPPCState *env)
7672 {
7673 gen_spr_ne_601(env);
7674 gen_spr_7xx(env);
7675 /* Time base */
7676 gen_tbl(env);
7677 /* Processor identification */
7678 spr_register(env, SPR_PIR, "PIR",
7679 SPR_NOACCESS, SPR_NOACCESS,
7680 &spr_read_generic, &spr_write_pir,
7681 0x00000000);
7682 #if !defined(CONFIG_USER_ONLY)
7683 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7684 spr_register_kvm(env, SPR_PURR, "PURR",
7685 &spr_read_purr, SPR_NOACCESS,
7686 &spr_read_purr, SPR_NOACCESS,
7687 KVM_REG_PPC_PURR, 0x00000000);
7688 spr_register_kvm(env, SPR_SPURR, "SPURR",
7689 &spr_read_purr, SPR_NOACCESS,
7690 &spr_read_purr, SPR_NOACCESS,
7691 KVM_REG_PPC_SPURR, 0x00000000);
7692 spr_register(env, SPR_CFAR, "SPR_CFAR",
7693 SPR_NOACCESS, SPR_NOACCESS,
7694 &spr_read_cfar, &spr_write_cfar,
7695 0x00000000);
7696 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7697 SPR_NOACCESS, SPR_NOACCESS,
7698 &spr_read_generic, &spr_write_generic,
7699 KVM_REG_PPC_DSCR, 0x00000000);
7700 spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
7701 SPR_NOACCESS, SPR_NOACCESS,
7702 &spr_read_generic, &spr_write_generic,
7703 KVM_REG_PPC_MMCRA, 0x00000000);
7704 spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
7705 SPR_NOACCESS, SPR_NOACCESS,
7706 &spr_read_generic, &spr_write_generic,
7707 KVM_REG_PPC_PMC5, 0x00000000);
7708 spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
7709 SPR_NOACCESS, SPR_NOACCESS,
7710 &spr_read_generic, &spr_write_generic,
7711 KVM_REG_PPC_PMC6, 0x00000000);
7712 #endif /* !CONFIG_USER_ONLY */
7713 gen_spr_amr(env);
7714 /* XXX : not implemented */
7715 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7716 SPR_NOACCESS, SPR_NOACCESS,
7717 SPR_NOACCESS, &spr_write_generic,
7718 0x80800000);
7719 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7720 SPR_NOACCESS, SPR_NOACCESS,
7721 &spr_read_generic, SPR_NOACCESS,
7722 0x80800000);
7723 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7724 &spr_read_generic, &spr_write_generic,
7725 &spr_read_generic, &spr_write_generic,
7726 0x00000000);
7727 spr_register(env, SPR_PPR, "PPR",
7728 &spr_read_generic, &spr_write_generic,
7729 &spr_read_generic, &spr_write_generic,
7730 0x00000000);
7731 /* Logical partitionning */
7732 spr_register_kvm(env, SPR_LPCR, "LPCR",
7733 SPR_NOACCESS, SPR_NOACCESS,
7734 &spr_read_generic, &spr_write_generic,
7735 KVM_REG_PPC_LPCR, 0x00000000);
7736 #if !defined(CONFIG_USER_ONLY)
7737 env->slb_nr = 32;
7738 #endif
7739 init_excp_POWER7(env);
7740 env->dcache_line_size = 128;
7741 env->icache_line_size = 128;
7742
7743 /* Allocate hardware IRQ controller */
7744 ppcPOWER7_irq_init(env);
7745 /* Can't find information on what this should be on reset. This
7746 * value is the one used by 74xx processors. */
7747 vscr_init(env, 0x00010000);
7748 }
7749
7750 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7751 {
7752 DeviceClass *dc = DEVICE_CLASS(oc);
7753 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7754
7755 dc->fw_name = "PowerPC,POWER7";
7756 dc->desc = "POWER7";
7757 pcc->pvr = CPU_POWERPC_POWER7_BASE;
7758 pcc->pvr_mask = CPU_POWERPC_POWER7_MASK;
7759 pcc->init_proc = init_proc_POWER7;
7760 pcc->check_pow = check_pow_nocheck;
7761 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7762 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7763 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7764 PPC_FLOAT_FRSQRTES |
7765 PPC_FLOAT_STFIWX |
7766 PPC_FLOAT_EXT |
7767 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7768 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7769 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7770 PPC_64B | PPC_ALTIVEC |
7771 PPC_SEGMENT_64B | PPC_SLBI |
7772 PPC_POPCNTB | PPC_POPCNTWD;
7773 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7774 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7775 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7776 PPC2_FP_TST_ISA206;
7777 pcc->msr_mask = (1ull << MSR_SF) |
7778 (1ull << MSR_VR) |
7779 (1ull << MSR_VSX) |
7780 (1ull << MSR_EE) |
7781 (1ull << MSR_PR) |
7782 (1ull << MSR_FP) |
7783 (1ull << MSR_ME) |
7784 (1ull << MSR_FE0) |
7785 (1ull << MSR_SE) |
7786 (1ull << MSR_DE) |
7787 (1ull << MSR_FE1) |
7788 (1ull << MSR_IR) |
7789 (1ull << MSR_DR) |
7790 (1ull << MSR_PMM) |
7791 (1ull << MSR_RI) |
7792 (1ull << MSR_LE);
7793 pcc->mmu_model = POWERPC_MMU_2_06;
7794 #if defined(CONFIG_SOFTMMU)
7795 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7796 #endif
7797 pcc->excp_model = POWERPC_EXCP_POWER7;
7798 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7799 pcc->bfd_mach = bfd_mach_ppc64;
7800 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7801 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7802 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7803 POWERPC_FLAG_VSX;
7804 pcc->l1_dcache_size = 0x8000;
7805 pcc->l1_icache_size = 0x8000;
7806 }
7807
7808 POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
7809 {
7810 DeviceClass *dc = DEVICE_CLASS(oc);
7811 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7812
7813 dc->fw_name = "PowerPC,POWER7+";
7814 dc->desc = "POWER7+";
7815 pcc->pvr = CPU_POWERPC_POWER7P_BASE;
7816 pcc->pvr_mask = CPU_POWERPC_POWER7P_MASK;
7817 pcc->init_proc = init_proc_POWER7;
7818 pcc->check_pow = check_pow_nocheck;
7819 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7820 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7821 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7822 PPC_FLOAT_FRSQRTES |
7823 PPC_FLOAT_STFIWX |
7824 PPC_FLOAT_EXT |
7825 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7826 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7827 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7828 PPC_64B | PPC_ALTIVEC |
7829 PPC_SEGMENT_64B | PPC_SLBI |
7830 PPC_POPCNTB | PPC_POPCNTWD;
7831 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7832 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7833 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7834 PPC2_FP_TST_ISA206;
7835 pcc->msr_mask = (1ull << MSR_SF) |
7836 (1ull << MSR_VR) |
7837 (1ull << MSR_VSX) |
7838 (1ull << MSR_EE) |
7839 (1ull << MSR_PR) |
7840 (1ull << MSR_FP) |
7841 (1ull << MSR_ME) |
7842 (1ull << MSR_FE0) |
7843 (1ull << MSR_SE) |
7844 (1ull << MSR_DE) |
7845 (1ull << MSR_FE1) |
7846 (1ull << MSR_IR) |
7847 (1ull << MSR_DR) |
7848 (1ull << MSR_PMM) |
7849 (1ull << MSR_RI) |
7850 (1ull << MSR_LE);
7851 pcc->mmu_model = POWERPC_MMU_2_06;
7852 #if defined(CONFIG_SOFTMMU)
7853 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7854 #endif
7855 pcc->excp_model = POWERPC_EXCP_POWER7;
7856 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7857 pcc->bfd_mach = bfd_mach_ppc64;
7858 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7859 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7860 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7861 POWERPC_FLAG_VSX;
7862 pcc->l1_dcache_size = 0x8000;
7863 pcc->l1_icache_size = 0x8000;
7864 }
7865
7866 static void init_proc_POWER8(CPUPPCState *env)
7867 {
7868 /* inherit P7 */
7869 init_proc_POWER7(env);
7870
7871 /* P8 supports the TAR */
7872 spr_register(env, SPR_TAR, "TAR",
7873 &spr_read_generic, &spr_write_generic,
7874 &spr_read_generic, &spr_write_generic,
7875 0x00000000);
7876 }
7877
7878 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7879 {
7880 DeviceClass *dc = DEVICE_CLASS(oc);
7881 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7882
7883 dc->fw_name = "PowerPC,POWER8";
7884 dc->desc = "POWER8";
7885 pcc->pvr = CPU_POWERPC_POWER8_BASE;
7886 pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
7887 pcc->init_proc = init_proc_POWER8;
7888 pcc->check_pow = check_pow_nocheck;
7889 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7890 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7891 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7892 PPC_FLOAT_FRSQRTES |
7893 PPC_FLOAT_STFIWX |
7894 PPC_FLOAT_EXT |
7895 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7896 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7897 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7898 PPC_64B | PPC_64BX | PPC_ALTIVEC |
7899 PPC_SEGMENT_64B | PPC_SLBI |
7900 PPC_POPCNTB | PPC_POPCNTWD;
7901 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7902 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7903 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7904 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7905 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7906 PPC2_ISA205 | PPC2_ISA207S;
7907 pcc->msr_mask = (1ull << MSR_SF) |
7908 (1ull << MSR_VR) |
7909 (1ull << MSR_VSX) |
7910 (1ull << MSR_EE) |
7911 (1ull << MSR_PR) |
7912 (1ull << MSR_FP) |
7913 (1ull << MSR_ME) |
7914 (1ull << MSR_FE0) |
7915 (1ull << MSR_SE) |
7916 (1ull << MSR_DE) |
7917 (1ull << MSR_FE1) |
7918 (1ull << MSR_IR) |
7919 (1ull << MSR_DR) |
7920 (1ull << MSR_PMM) |
7921 (1ull << MSR_RI) |
7922 (1ull << MSR_LE);
7923 pcc->mmu_model = POWERPC_MMU_2_06;
7924 #if defined(CONFIG_SOFTMMU)
7925 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7926 #endif
7927 pcc->excp_model = POWERPC_EXCP_POWER7;
7928 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7929 pcc->bfd_mach = bfd_mach_ppc64;
7930 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7931 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7932 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7933 POWERPC_FLAG_VSX;
7934 pcc->l1_dcache_size = 0x8000;
7935 pcc->l1_icache_size = 0x8000;
7936 }
7937 #endif /* defined (TARGET_PPC64) */
7938
7939
7940 /*****************************************************************************/
7941 /* Generic CPU instantiation routine */
7942 static void init_ppc_proc(PowerPCCPU *cpu)
7943 {
7944 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7945 CPUPPCState *env = &cpu->env;
7946 #if !defined(CONFIG_USER_ONLY)
7947 int i;
7948
7949 env->irq_inputs = NULL;
7950 /* Set all exception vectors to an invalid address */
7951 for (i = 0; i < POWERPC_EXCP_NB; i++)
7952 env->excp_vectors[i] = (target_ulong)(-1ULL);
7953 env->ivor_mask = 0x00000000;
7954 env->ivpr_mask = 0x00000000;
7955 /* Default MMU definitions */
7956 env->nb_BATs = 0;
7957 env->nb_tlb = 0;
7958 env->nb_ways = 0;
7959 env->tlb_type = TLB_NONE;
7960 #endif
7961 /* Register SPR common to all PowerPC implementations */
7962 gen_spr_generic(env);
7963 spr_register(env, SPR_PVR, "PVR",
7964 /* Linux permits userspace to read PVR */
7965 #if defined(CONFIG_LINUX_USER)
7966 &spr_read_generic,
7967 #else
7968 SPR_NOACCESS,
7969 #endif
7970 SPR_NOACCESS,
7971 &spr_read_generic, SPR_NOACCESS,
7972 pcc->pvr);
7973 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7974 if (pcc->svr != POWERPC_SVR_NONE) {
7975 if (pcc->svr & POWERPC_SVR_E500) {
7976 spr_register(env, SPR_E500_SVR, "SVR",
7977 SPR_NOACCESS, SPR_NOACCESS,
7978 &spr_read_generic, SPR_NOACCESS,
7979 pcc->svr & ~POWERPC_SVR_E500);
7980 } else {
7981 spr_register(env, SPR_SVR, "SVR",
7982 SPR_NOACCESS, SPR_NOACCESS,
7983 &spr_read_generic, SPR_NOACCESS,
7984 pcc->svr);
7985 }
7986 }
7987 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7988 (*pcc->init_proc)(env);
7989
7990 /* MSR bits & flags consistency checks */
7991 if (env->msr_mask & (1 << 25)) {
7992 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7993 case POWERPC_FLAG_SPE:
7994 case POWERPC_FLAG_VRE:
7995 break;
7996 default:
7997 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7998 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7999 exit(1);
8000 }
8001 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8002 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8003 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8004 exit(1);
8005 }
8006 if (env->msr_mask & (1 << 17)) {
8007 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8008 case POWERPC_FLAG_TGPR:
8009 case POWERPC_FLAG_CE:
8010 break;
8011 default:
8012 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8013 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8014 exit(1);
8015 }
8016 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8017 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8018 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8019 exit(1);
8020 }
8021 if (env->msr_mask & (1 << 10)) {
8022 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8023 POWERPC_FLAG_UBLE)) {
8024 case POWERPC_FLAG_SE:
8025 case POWERPC_FLAG_DWE:
8026 case POWERPC_FLAG_UBLE:
8027 break;
8028 default:
8029 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8030 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8031 "POWERPC_FLAG_UBLE\n");
8032 exit(1);
8033 }
8034 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8035 POWERPC_FLAG_UBLE)) {
8036 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8037 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8038 "POWERPC_FLAG_UBLE\n");
8039 exit(1);
8040 }
8041 if (env->msr_mask & (1 << 9)) {
8042 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8043 case POWERPC_FLAG_BE:
8044 case POWERPC_FLAG_DE:
8045 break;
8046 default:
8047 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8048 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8049 exit(1);
8050 }
8051 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8052 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8053 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8054 exit(1);
8055 }
8056 if (env->msr_mask & (1 << 2)) {
8057 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8058 case POWERPC_FLAG_PX:
8059 case POWERPC_FLAG_PMM:
8060 break;
8061 default:
8062 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8063 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8064 exit(1);
8065 }
8066 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8067 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8068 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8069 exit(1);
8070 }
8071 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8072 fprintf(stderr, "PowerPC flags inconsistency\n"
8073 "Should define the time-base and decrementer clock source\n");
8074 exit(1);
8075 }
8076 /* Allocate TLBs buffer when needed */
8077 #if !defined(CONFIG_USER_ONLY)
8078 if (env->nb_tlb != 0) {
8079 int nb_tlb = env->nb_tlb;
8080 if (env->id_tlbs != 0)
8081 nb_tlb *= 2;
8082 switch (env->tlb_type) {
8083 case TLB_6XX:
8084 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
8085 break;
8086 case TLB_EMB:
8087 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
8088 break;
8089 case TLB_MAS:
8090 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
8091 break;
8092 }
8093 /* Pre-compute some useful values */
8094 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8095 }
8096 if (env->irq_inputs == NULL) {
8097 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8098 " Attempt QEMU to crash very soon !\n");
8099 }
8100 #endif
8101 if (env->check_pow == NULL) {
8102 fprintf(stderr, "WARNING: no power management check handler "
8103 "registered.\n"
8104 " Attempt QEMU to crash very soon !\n");
8105 }
8106 }
8107
8108 #if defined(PPC_DUMP_CPU)
8109 static void dump_ppc_sprs (CPUPPCState *env)
8110 {
8111 ppc_spr_t *spr;
8112 #if !defined(CONFIG_USER_ONLY)
8113 uint32_t sr, sw;
8114 #endif
8115 uint32_t ur, uw;
8116 int i, j, n;
8117
8118 printf("Special purpose registers:\n");
8119 for (i = 0; i < 32; i++) {
8120 for (j = 0; j < 32; j++) {
8121 n = (i << 5) | j;
8122 spr = &env->spr_cb[n];
8123 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8124 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8125 #if !defined(CONFIG_USER_ONLY)
8126 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8127 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8128 if (sw || sr || uw || ur) {
8129 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8130 (i << 5) | j, (i << 5) | j, spr->name,
8131 sw ? 'w' : '-', sr ? 'r' : '-',
8132 uw ? 'w' : '-', ur ? 'r' : '-');
8133 }
8134 #else
8135 if (uw || ur) {
8136 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8137 (i << 5) | j, (i << 5) | j, spr->name,
8138 uw ? 'w' : '-', ur ? 'r' : '-');
8139 }
8140 #endif
8141 }
8142 }
8143 fflush(stdout);
8144 fflush(stderr);
8145 }
8146 #endif
8147
8148 /*****************************************************************************/
8149 #include <stdlib.h>
8150 #include <string.h>
8151
8152 /* Opcode types */
8153 enum {
8154 PPC_DIRECT = 0, /* Opcode routine */
8155 PPC_INDIRECT = 1, /* Indirect opcode table */
8156 };
8157
8158 static inline int is_indirect_opcode (void *handler)
8159 {
8160 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
8161 }
8162
8163 static inline opc_handler_t **ind_table(void *handler)
8164 {
8165 return (opc_handler_t **)((uintptr_t)handler & ~3);
8166 }
8167
8168 /* Instruction table creation */
8169 /* Opcodes tables creation */
8170 static void fill_new_table (opc_handler_t **table, int len)
8171 {
8172 int i;
8173
8174 for (i = 0; i < len; i++)
8175 table[i] = &invalid_handler;
8176 }
8177
8178 static int create_new_table (opc_handler_t **table, unsigned char idx)
8179 {
8180 opc_handler_t **tmp;
8181
8182 tmp = g_new(opc_handler_t *, 0x20);
8183 fill_new_table(tmp, 0x20);
8184 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8185
8186 return 0;
8187 }
8188
8189 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8190 opc_handler_t *handler)
8191 {
8192 if (table[idx] != &invalid_handler)
8193 return -1;
8194 table[idx] = handler;
8195
8196 return 0;
8197 }
8198
8199 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8200 unsigned char idx, opc_handler_t *handler)
8201 {
8202 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8203 printf("*** ERROR: opcode %02x already assigned in main "
8204 "opcode table\n", idx);
8205 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8206 printf(" Registered handler '%s' - new handler '%s'\n",
8207 ppc_opcodes[idx]->oname, handler->oname);
8208 #endif
8209 return -1;
8210 }
8211
8212 return 0;
8213 }
8214
8215 static int register_ind_in_table (opc_handler_t **table,
8216 unsigned char idx1, unsigned char idx2,
8217 opc_handler_t *handler)
8218 {
8219 if (table[idx1] == &invalid_handler) {
8220 if (create_new_table(table, idx1) < 0) {
8221 printf("*** ERROR: unable to create indirect table "
8222 "idx=%02x\n", idx1);
8223 return -1;
8224 }
8225 } else {
8226 if (!is_indirect_opcode(table[idx1])) {
8227 printf("*** ERROR: idx %02x already assigned to a direct "
8228 "opcode\n", idx1);
8229 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8230 printf(" Registered handler '%s' - new handler '%s'\n",
8231 ind_table(table[idx1])[idx2]->oname, handler->oname);
8232 #endif
8233 return -1;
8234 }
8235 }
8236 if (handler != NULL &&
8237 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8238 printf("*** ERROR: opcode %02x already assigned in "
8239 "opcode table %02x\n", idx2, idx1);
8240 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8241 printf(" Registered handler '%s' - new handler '%s'\n",
8242 ind_table(table[idx1])[idx2]->oname, handler->oname);
8243 #endif
8244 return -1;
8245 }
8246
8247 return 0;
8248 }
8249
8250 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8251 unsigned char idx1, unsigned char idx2,
8252 opc_handler_t *handler)
8253 {
8254 int ret;
8255
8256 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8257
8258 return ret;
8259 }
8260
8261 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8262 unsigned char idx1, unsigned char idx2,
8263 unsigned char idx3, opc_handler_t *handler)
8264 {
8265 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8266 printf("*** ERROR: unable to join indirect table idx "
8267 "[%02x-%02x]\n", idx1, idx2);
8268 return -1;
8269 }
8270 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8271 handler) < 0) {
8272 printf("*** ERROR: unable to insert opcode "
8273 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8274 return -1;
8275 }
8276
8277 return 0;
8278 }
8279
8280 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8281 {
8282 if (insn->opc2 != 0xFF) {
8283 if (insn->opc3 != 0xFF) {
8284 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8285 insn->opc3, &insn->handler) < 0)
8286 return -1;
8287 } else {
8288 if (register_ind_insn(ppc_opcodes, insn->opc1,
8289 insn->opc2, &insn->handler) < 0)
8290 return -1;
8291 }
8292 } else {
8293 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8294 return -1;
8295 }
8296
8297 return 0;
8298 }
8299
8300 static int test_opcode_table (opc_handler_t **table, int len)
8301 {
8302 int i, count, tmp;
8303
8304 for (i = 0, count = 0; i < len; i++) {
8305 /* Consistency fixup */
8306 if (table[i] == NULL)
8307 table[i] = &invalid_handler;
8308 if (table[i] != &invalid_handler) {
8309 if (is_indirect_opcode(table[i])) {
8310 tmp = test_opcode_table(ind_table(table[i]), 0x20);
8311 if (tmp == 0) {
8312 free(table[i]);
8313 table[i] = &invalid_handler;
8314 } else {
8315 count++;
8316 }
8317 } else {
8318 count++;
8319 }
8320 }
8321 }
8322
8323 return count;
8324 }
8325
8326 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8327 {
8328 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
8329 printf("*** WARNING: no opcode defined !\n");
8330 }
8331
8332 /*****************************************************************************/
8333 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8334 {
8335 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8336 CPUPPCState *env = &cpu->env;
8337 opcode_t *opc;
8338
8339 fill_new_table(env->opcodes, 0x40);
8340 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8341 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8342 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8343 if (register_insn(env->opcodes, opc) < 0) {
8344 error_setg(errp, "ERROR initializing PowerPC instruction "
8345 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8346 opc->opc3);
8347 return;
8348 }
8349 }
8350 }
8351 fix_opcode_tables(env->opcodes);
8352 fflush(stdout);
8353 fflush(stderr);
8354 }
8355
8356 #if defined(PPC_DUMP_CPU)
8357 static void dump_ppc_insns (CPUPPCState *env)
8358 {
8359 opc_handler_t **table, *handler;
8360 const char *p, *q;
8361 uint8_t opc1, opc2, opc3;
8362
8363 printf("Instructions set:\n");
8364 /* opc1 is 6 bits long */
8365 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
8366 table = env->opcodes;
8367 handler = table[opc1];
8368 if (is_indirect_opcode(handler)) {
8369 /* opc2 is 5 bits long */
8370 for (opc2 = 0; opc2 < 0x20; opc2++) {
8371 table = env->opcodes;
8372 handler = env->opcodes[opc1];
8373 table = ind_table(handler);
8374 handler = table[opc2];
8375 if (is_indirect_opcode(handler)) {
8376 table = ind_table(handler);
8377 /* opc3 is 5 bits long */
8378 for (opc3 = 0; opc3 < 0x20; opc3++) {
8379 handler = table[opc3];
8380 if (handler->handler != &gen_invalid) {
8381 /* Special hack to properly dump SPE insns */
8382 p = strchr(handler->oname, '_');
8383 if (p == NULL) {
8384 printf("INSN: %02x %02x %02x (%02d %04d) : "
8385 "%s\n",
8386 opc1, opc2, opc3, opc1,
8387 (opc3 << 5) | opc2,
8388 handler->oname);
8389 } else {
8390 q = "speundef";
8391 if ((p - handler->oname) != strlen(q) ||
8392 memcmp(handler->oname, q, strlen(q)) != 0) {
8393 /* First instruction */
8394 printf("INSN: %02x %02x %02x (%02d %04d) : "
8395 "%.*s\n",
8396 opc1, opc2 << 1, opc3, opc1,
8397 (opc3 << 6) | (opc2 << 1),
8398 (int)(p - handler->oname),
8399 handler->oname);
8400 }
8401 if (strcmp(p + 1, q) != 0) {
8402 /* Second instruction */
8403 printf("INSN: %02x %02x %02x (%02d %04d) : "
8404 "%s\n",
8405 opc1, (opc2 << 1) | 1, opc3, opc1,
8406 (opc3 << 6) | (opc2 << 1) | 1,
8407 p + 1);
8408 }
8409 }
8410 }
8411 }
8412 } else {
8413 if (handler->handler != &gen_invalid) {
8414 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8415 opc1, opc2, opc1, opc2, handler->oname);
8416 }
8417 }
8418 }
8419 } else {
8420 if (handler->handler != &gen_invalid) {
8421 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8422 opc1, opc1, handler->oname);
8423 }
8424 }
8425 }
8426 }
8427 #endif
8428
8429 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8430 {
8431 if (n < 32) {
8432 stfq_p(mem_buf, env->fpr[n]);
8433 return 8;
8434 }
8435 if (n == 32) {
8436 stl_p(mem_buf, env->fpscr);
8437 return 4;
8438 }
8439 return 0;
8440 }
8441
8442 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8443 {
8444 if (n < 32) {
8445 env->fpr[n] = ldfq_p(mem_buf);
8446 return 8;
8447 }
8448 if (n == 32) {
8449 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
8450 return 4;
8451 }
8452 return 0;
8453 }
8454
8455 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8456 {
8457 if (n < 32) {
8458 #ifdef HOST_WORDS_BIGENDIAN
8459 stq_p(mem_buf, env->avr[n].u64[0]);
8460 stq_p(mem_buf+8, env->avr[n].u64[1]);
8461 #else
8462 stq_p(mem_buf, env->avr[n].u64[1]);
8463 stq_p(mem_buf+8, env->avr[n].u64[0]);
8464 #endif
8465 return 16;
8466 }
8467 if (n == 32) {
8468 stl_p(mem_buf, env->vscr);
8469 return 4;
8470 }
8471 if (n == 33) {
8472 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
8473 return 4;
8474 }
8475 return 0;
8476 }
8477
8478 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8479 {
8480 if (n < 32) {
8481 #ifdef HOST_WORDS_BIGENDIAN
8482 env->avr[n].u64[0] = ldq_p(mem_buf);
8483 env->avr[n].u64[1] = ldq_p(mem_buf+8);
8484 #else
8485 env->avr[n].u64[1] = ldq_p(mem_buf);
8486 env->avr[n].u64[0] = ldq_p(mem_buf+8);
8487 #endif
8488 return 16;
8489 }
8490 if (n == 32) {
8491 env->vscr = ldl_p(mem_buf);
8492 return 4;
8493 }
8494 if (n == 33) {
8495 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
8496 return 4;
8497 }
8498 return 0;
8499 }
8500
8501 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8502 {
8503 if (n < 32) {
8504 #if defined(TARGET_PPC64)
8505 stl_p(mem_buf, env->gpr[n] >> 32);
8506 #else
8507 stl_p(mem_buf, env->gprh[n]);
8508 #endif
8509 return 4;
8510 }
8511 if (n == 32) {
8512 stq_p(mem_buf, env->spe_acc);
8513 return 8;
8514 }
8515 if (n == 33) {
8516 stl_p(mem_buf, env->spe_fscr);
8517 return 4;
8518 }
8519 return 0;
8520 }
8521
8522 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8523 {
8524 if (n < 32) {
8525 #if defined(TARGET_PPC64)
8526 target_ulong lo = (uint32_t)env->gpr[n];
8527 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
8528 env->gpr[n] = lo | hi;
8529 #else
8530 env->gprh[n] = ldl_p(mem_buf);
8531 #endif
8532 return 4;
8533 }
8534 if (n == 32) {
8535 env->spe_acc = ldq_p(mem_buf);
8536 return 8;
8537 }
8538 if (n == 33) {
8539 env->spe_fscr = ldl_p(mem_buf);
8540 return 4;
8541 }
8542 return 0;
8543 }
8544
8545 static int ppc_fixup_cpu(PowerPCCPU *cpu)
8546 {
8547 CPUPPCState *env = &cpu->env;
8548
8549 /* TCG doesn't (yet) emulate some groups of instructions that
8550 * are implemented on some otherwise supported CPUs (e.g. VSX
8551 * and decimal floating point instructions on POWER7). We
8552 * remove unsupported instruction groups from the cpu state's
8553 * instruction masks and hope the guest can cope. For at
8554 * least the pseries machine, the unavailability of these
8555 * instructions can be advertised to the guest via the device
8556 * tree. */
8557 if ((env->insns_flags & ~PPC_TCG_INSNS)
8558 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
8559 fprintf(stderr, "Warning: Disabling some instructions which are not "
8560 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
8561 env->insns_flags & ~PPC_TCG_INSNS,
8562 env->insns_flags2 & ~PPC_TCG_INSNS2);
8563 }
8564 env->insns_flags &= PPC_TCG_INSNS;
8565 env->insns_flags2 &= PPC_TCG_INSNS2;
8566 return 0;
8567 }
8568
8569 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
8570 {
8571 #ifdef TARGET_PPCEMB
8572 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
8573 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
8574 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
8575 #else
8576 return true;
8577 #endif
8578 }
8579
8580 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
8581 {
8582 CPUState *cs = CPU(dev);
8583 PowerPCCPU *cpu = POWERPC_CPU(dev);
8584 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8585 Error *local_err = NULL;
8586 #if !defined(CONFIG_USER_ONLY)
8587 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
8588 #endif
8589
8590 #if !defined(CONFIG_USER_ONLY)
8591 if (smp_threads > max_smt) {
8592 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
8593 max_smt, kvm_enabled() ? "KVM" : "TCG");
8594 return;
8595 }
8596 if (!is_power_of_2(smp_threads)) {
8597 error_setg(errp, "Cannot support %d threads on PPC with %s, "
8598 "threads count must be a power of 2.",
8599 smp_threads, kvm_enabled() ? "KVM" : "TCG");
8600 return;
8601 }
8602
8603 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
8604 + (cs->cpu_index % smp_threads);
8605 #endif
8606
8607 if (tcg_enabled()) {
8608 if (ppc_fixup_cpu(cpu) != 0) {
8609 error_setg(errp, "Unable to emulate selected CPU with TCG");
8610 return;
8611 }
8612 }
8613
8614 #if defined(TARGET_PPCEMB)
8615 if (!ppc_cpu_is_valid(pcc)) {
8616 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
8617 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
8618 "or choose another CPU model.");
8619 return;
8620 }
8621 #endif
8622
8623 create_ppc_opcodes(cpu, &local_err);
8624 if (local_err != NULL) {
8625 error_propagate(errp, local_err);
8626 return;
8627 }
8628 init_ppc_proc(cpu);
8629
8630 if (pcc->insns_flags & PPC_FLOAT) {
8631 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
8632 33, "power-fpu.xml", 0);
8633 }
8634 if (pcc->insns_flags & PPC_ALTIVEC) {
8635 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
8636 34, "power-altivec.xml", 0);
8637 }
8638 if (pcc->insns_flags & PPC_SPE) {
8639 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
8640 34, "power-spe.xml", 0);
8641 }
8642
8643 qemu_init_vcpu(cs);
8644
8645 pcc->parent_realize(dev, errp);
8646
8647 #if defined(PPC_DUMP_CPU)
8648 {
8649 CPUPPCState *env = &cpu->env;
8650 const char *mmu_model, *excp_model, *bus_model;
8651 switch (env->mmu_model) {
8652 case POWERPC_MMU_32B:
8653 mmu_model = "PowerPC 32";
8654 break;
8655 case POWERPC_MMU_SOFT_6xx:
8656 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8657 break;
8658 case POWERPC_MMU_SOFT_74xx:
8659 mmu_model = "PowerPC 74xx with software driven TLBs";
8660 break;
8661 case POWERPC_MMU_SOFT_4xx:
8662 mmu_model = "PowerPC 4xx with software driven TLBs";
8663 break;
8664 case POWERPC_MMU_SOFT_4xx_Z:
8665 mmu_model = "PowerPC 4xx with software driven TLBs "
8666 "and zones protections";
8667 break;
8668 case POWERPC_MMU_REAL:
8669 mmu_model = "PowerPC real mode only";
8670 break;
8671 case POWERPC_MMU_MPC8xx:
8672 mmu_model = "PowerPC MPC8xx";
8673 break;
8674 case POWERPC_MMU_BOOKE:
8675 mmu_model = "PowerPC BookE";
8676 break;
8677 case POWERPC_MMU_BOOKE206:
8678 mmu_model = "PowerPC BookE 2.06";
8679 break;
8680 case POWERPC_MMU_601:
8681 mmu_model = "PowerPC 601";
8682 break;
8683 #if defined (TARGET_PPC64)
8684 case POWERPC_MMU_64B:
8685 mmu_model = "PowerPC 64";
8686 break;
8687 #endif
8688 default:
8689 mmu_model = "Unknown or invalid";
8690 break;
8691 }
8692 switch (env->excp_model) {
8693 case POWERPC_EXCP_STD:
8694 excp_model = "PowerPC";
8695 break;
8696 case POWERPC_EXCP_40x:
8697 excp_model = "PowerPC 40x";
8698 break;
8699 case POWERPC_EXCP_601:
8700 excp_model = "PowerPC 601";
8701 break;
8702 case POWERPC_EXCP_602:
8703 excp_model = "PowerPC 602";
8704 break;
8705 case POWERPC_EXCP_603:
8706 excp_model = "PowerPC 603";
8707 break;
8708 case POWERPC_EXCP_603E:
8709 excp_model = "PowerPC 603e";
8710 break;
8711 case POWERPC_EXCP_604:
8712 excp_model = "PowerPC 604";
8713 break;
8714 case POWERPC_EXCP_7x0:
8715 excp_model = "PowerPC 740/750";
8716 break;
8717 case POWERPC_EXCP_7x5:
8718 excp_model = "PowerPC 745/755";
8719 break;
8720 case POWERPC_EXCP_74xx:
8721 excp_model = "PowerPC 74xx";
8722 break;
8723 case POWERPC_EXCP_BOOKE:
8724 excp_model = "PowerPC BookE";
8725 break;
8726 #if defined (TARGET_PPC64)
8727 case POWERPC_EXCP_970:
8728 excp_model = "PowerPC 970";
8729 break;
8730 #endif
8731 default:
8732 excp_model = "Unknown or invalid";
8733 break;
8734 }
8735 switch (env->bus_model) {
8736 case PPC_FLAGS_INPUT_6xx:
8737 bus_model = "PowerPC 6xx";
8738 break;
8739 case PPC_FLAGS_INPUT_BookE:
8740 bus_model = "PowerPC BookE";
8741 break;
8742 case PPC_FLAGS_INPUT_405:
8743 bus_model = "PowerPC 405";
8744 break;
8745 case PPC_FLAGS_INPUT_401:
8746 bus_model = "PowerPC 401/403";
8747 break;
8748 case PPC_FLAGS_INPUT_RCPU:
8749 bus_model = "RCPU / MPC8xx";
8750 break;
8751 #if defined (TARGET_PPC64)
8752 case PPC_FLAGS_INPUT_970:
8753 bus_model = "PowerPC 970";
8754 break;
8755 #endif
8756 default:
8757 bus_model = "Unknown or invalid";
8758 break;
8759 }
8760 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8761 " MMU model : %s\n",
8762 object_class_get_name(OBJECT_CLASS(pcc)),
8763 pcc->pvr, pcc->msr_mask, mmu_model);
8764 #if !defined(CONFIG_USER_ONLY)
8765 if (env->tlb.tlb6) {
8766 printf(" %d %s TLB in %d ways\n",
8767 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8768 env->nb_ways);
8769 }
8770 #endif
8771 printf(" Exceptions model : %s\n"
8772 " Bus model : %s\n",
8773 excp_model, bus_model);
8774 printf(" MSR features :\n");
8775 if (env->flags & POWERPC_FLAG_SPE)
8776 printf(" signal processing engine enable"
8777 "\n");
8778 else if (env->flags & POWERPC_FLAG_VRE)
8779 printf(" vector processor enable\n");
8780 if (env->flags & POWERPC_FLAG_TGPR)
8781 printf(" temporary GPRs\n");
8782 else if (env->flags & POWERPC_FLAG_CE)
8783 printf(" critical input enable\n");
8784 if (env->flags & POWERPC_FLAG_SE)
8785 printf(" single-step trace mode\n");
8786 else if (env->flags & POWERPC_FLAG_DWE)
8787 printf(" debug wait enable\n");
8788 else if (env->flags & POWERPC_FLAG_UBLE)
8789 printf(" user BTB lock enable\n");
8790 if (env->flags & POWERPC_FLAG_BE)
8791 printf(" branch-step trace mode\n");
8792 else if (env->flags & POWERPC_FLAG_DE)
8793 printf(" debug interrupt enable\n");
8794 if (env->flags & POWERPC_FLAG_PX)
8795 printf(" inclusive protection\n");
8796 else if (env->flags & POWERPC_FLAG_PMM)
8797 printf(" performance monitor mark\n");
8798 if (env->flags == POWERPC_FLAG_NONE)
8799 printf(" none\n");
8800 printf(" Time-base/decrementer clock source: %s\n",
8801 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
8802 dump_ppc_insns(env);
8803 dump_ppc_sprs(env);
8804 fflush(stdout);
8805 }
8806 #endif
8807 }
8808
8809 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
8810 {
8811 PowerPCCPU *cpu = POWERPC_CPU(dev);
8812 CPUPPCState *env = &cpu->env;
8813 int i;
8814
8815 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
8816 if (env->opcodes[i] != &invalid_handler) {
8817 g_free(env->opcodes[i]);
8818 }
8819 }
8820 }
8821
8822 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8823 {
8824 ObjectClass *oc = (ObjectClass *)a;
8825 uint32_t pvr = *(uint32_t *)b;
8826 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8827
8828 /* -cpu host does a PVR lookup during construction */
8829 if (unlikely(strcmp(object_class_get_name(oc),
8830 TYPE_HOST_POWERPC_CPU) == 0)) {
8831 return -1;
8832 }
8833
8834 if (!ppc_cpu_is_valid(pcc)) {
8835 return -1;
8836 }
8837
8838 return pcc->pvr == pvr ? 0 : -1;
8839 }
8840
8841 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8842 {
8843 GSList *list, *item;
8844 PowerPCCPUClass *pcc = NULL;
8845
8846 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8847 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8848 if (item != NULL) {
8849 pcc = POWERPC_CPU_CLASS(item->data);
8850 }
8851 g_slist_free(list);
8852
8853 return pcc;
8854 }
8855
8856 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
8857 {
8858 ObjectClass *oc = (ObjectClass *)a;
8859 uint32_t pvr = *(uint32_t *)b;
8860 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8861 gint ret;
8862
8863 /* -cpu host does a PVR lookup during construction */
8864 if (unlikely(strcmp(object_class_get_name(oc),
8865 TYPE_HOST_POWERPC_CPU) == 0)) {
8866 return -1;
8867 }
8868
8869 if (!ppc_cpu_is_valid(pcc)) {
8870 return -1;
8871 }
8872
8873 ret = (((pcc->pvr & pcc->pvr_mask) == (pvr & pcc->pvr_mask)) ? 0 : -1);
8874
8875 return ret;
8876 }
8877
8878 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8879 {
8880 GSList *list, *item;
8881 PowerPCCPUClass *pcc = NULL;
8882
8883 list = object_class_get_list(TYPE_POWERPC_CPU, true);
8884 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8885 if (item != NULL) {
8886 pcc = POWERPC_CPU_CLASS(item->data);
8887 }
8888 g_slist_free(list);
8889
8890 return pcc;
8891 }
8892
8893 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
8894 {
8895 ObjectClass *oc = (ObjectClass *)a;
8896 const char *name = b;
8897 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8898
8899 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
8900 ppc_cpu_is_valid(pcc) &&
8901 strcmp(object_class_get_name(oc) + strlen(name),
8902 "-" TYPE_POWERPC_CPU) == 0) {
8903 return 0;
8904 }
8905 return -1;
8906 }
8907
8908 #include <ctype.h>
8909
8910 static ObjectClass *ppc_cpu_class_by_name(const char *name);
8911
8912 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
8913 {
8914 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
8915
8916 /* Cache target class lookups in the alias table */
8917 if (!alias->oc) {
8918 alias->oc = ppc_cpu_class_by_name(alias->model);
8919 if (!alias->oc) {
8920 /* Fast check for non-existing aliases */
8921 alias->oc = invalid_class;
8922 }
8923 }
8924
8925 if (alias->oc == invalid_class) {
8926 return NULL;
8927 } else {
8928 return alias->oc;
8929 }
8930 }
8931
8932 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8933 {
8934 GSList *list, *item;
8935 ObjectClass *ret = NULL;
8936 const char *p;
8937 int i, len;
8938
8939 /* Check if the given name is a PVR */
8940 len = strlen(name);
8941 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8942 p = name + 2;
8943 goto check_pvr;
8944 } else if (len == 8) {
8945 p = name;
8946 check_pvr:
8947 for (i = 0; i < 8; i++) {
8948 if (!qemu_isxdigit(*p++))
8949 break;
8950 }
8951 if (i == 8) {
8952 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
8953 return ret;
8954 }
8955 }
8956
8957 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8958 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
8959 if (item != NULL) {
8960 ret = OBJECT_CLASS(item->data);
8961 }
8962 g_slist_free(list);
8963
8964 if (ret) {
8965 return ret;
8966 }
8967
8968 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8969 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
8970 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
8971 }
8972 }
8973
8974 return NULL;
8975 }
8976
8977 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
8978 {
8979 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
8980 }
8981
8982 /* Sort by PVR, ordering special case "host" last. */
8983 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8984 {
8985 ObjectClass *oc_a = (ObjectClass *)a;
8986 ObjectClass *oc_b = (ObjectClass *)b;
8987 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8988 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8989 const char *name_a = object_class_get_name(oc_a);
8990 const char *name_b = object_class_get_name(oc_b);
8991
8992 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8993 return 1;
8994 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8995 return -1;
8996 } else {
8997 /* Avoid an integer overflow during subtraction */
8998 if (pcc_a->pvr < pcc_b->pvr) {
8999 return -1;
9000 } else if (pcc_a->pvr > pcc_b->pvr) {
9001 return 1;
9002 } else {
9003 return 0;
9004 }
9005 }
9006 }
9007
9008 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
9009 {
9010 ObjectClass *oc = data;
9011 CPUListState *s = user_data;
9012 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9013 const char *typename = object_class_get_name(oc);
9014 char *name;
9015 int i;
9016
9017 if (!ppc_cpu_is_valid(pcc)) {
9018 return;
9019 }
9020 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
9021 return;
9022 }
9023
9024 name = g_strndup(typename,
9025 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9026 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
9027 name, pcc->pvr);
9028 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9029 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9030 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
9031
9032 if (alias_oc != oc) {
9033 continue;
9034 }
9035 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
9036 alias->alias, name);
9037 }
9038 g_free(name);
9039 }
9040
9041 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
9042 {
9043 CPUListState s = {
9044 .file = f,
9045 .cpu_fprintf = cpu_fprintf,
9046 };
9047 GSList *list;
9048
9049 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9050 list = g_slist_sort(list, ppc_cpu_list_compare);
9051 g_slist_foreach(list, ppc_cpu_list_entry, &s);
9052 g_slist_free(list);
9053
9054 #ifdef CONFIG_KVM
9055 cpu_fprintf(f, "\n");
9056 cpu_fprintf(f, "PowerPC %-16s\n", "host");
9057 #endif
9058 }
9059
9060 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9061 {
9062 ObjectClass *oc = data;
9063 CpuDefinitionInfoList **first = user_data;
9064 const char *typename;
9065 CpuDefinitionInfoList *entry;
9066 CpuDefinitionInfo *info;
9067 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9068
9069 if (!ppc_cpu_is_valid(pcc)) {
9070 return;
9071 }
9072
9073 typename = object_class_get_name(oc);
9074 info = g_malloc0(sizeof(*info));
9075 info->name = g_strndup(typename,
9076 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9077
9078 entry = g_malloc0(sizeof(*entry));
9079 entry->value = info;
9080 entry->next = *first;
9081 *first = entry;
9082 }
9083
9084 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
9085 {
9086 CpuDefinitionInfoList *cpu_list = NULL;
9087 GSList *list;
9088 int i;
9089
9090 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9091 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9092 g_slist_free(list);
9093
9094 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9095 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9096 ObjectClass *oc;
9097 CpuDefinitionInfoList *entry;
9098 CpuDefinitionInfo *info;
9099
9100 oc = ppc_cpu_class_by_alias(alias);
9101 if (oc == NULL) {
9102 continue;
9103 }
9104
9105 info = g_malloc0(sizeof(*info));
9106 info->name = g_strdup(alias->alias);
9107
9108 entry = g_malloc0(sizeof(*entry));
9109 entry->value = info;
9110 entry->next = cpu_list;
9111 cpu_list = entry;
9112 }
9113
9114 return cpu_list;
9115 }
9116
9117 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9118 {
9119 PowerPCCPU *cpu = POWERPC_CPU(cs);
9120
9121 cpu->env.nip = value;
9122 }
9123
9124 static bool ppc_cpu_has_work(CPUState *cs)
9125 {
9126 PowerPCCPU *cpu = POWERPC_CPU(cs);
9127 CPUPPCState *env = &cpu->env;
9128
9129 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9130 }
9131
9132 /* CPUClass::reset() */
9133 static void ppc_cpu_reset(CPUState *s)
9134 {
9135 PowerPCCPU *cpu = POWERPC_CPU(s);
9136 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9137 CPUPPCState *env = &cpu->env;
9138 target_ulong msr;
9139 int i;
9140
9141 pcc->parent_reset(s);
9142
9143 msr = (target_ulong)0;
9144 if (0) {
9145 /* XXX: find a suitable condition to enable the hypervisor mode */
9146 msr |= (target_ulong)MSR_HVB;
9147 }
9148 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9149 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9150 msr |= (target_ulong)1 << MSR_EP;
9151 #if defined(DO_SINGLE_STEP) && 0
9152 /* Single step trace mode */
9153 msr |= (target_ulong)1 << MSR_SE;
9154 msr |= (target_ulong)1 << MSR_BE;
9155 #endif
9156 #if defined(CONFIG_USER_ONLY)
9157 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9158 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9159 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9160 msr |= (target_ulong)1 << MSR_PR;
9161 #endif
9162
9163 #if defined(TARGET_PPC64)
9164 if (env->mmu_model & POWERPC_MMU_64) {
9165 env->msr |= (1ULL << MSR_SF);
9166 }
9167 #endif
9168
9169 hreg_store_msr(env, msr, 1);
9170
9171 #if !defined(CONFIG_USER_ONLY)
9172 env->nip = env->hreset_vector | env->excp_prefix;
9173 if (env->mmu_model != POWERPC_MMU_REAL) {
9174 ppc_tlb_invalidate_all(env);
9175 }
9176 #endif
9177
9178 hreg_compute_hflags(env);
9179 env->reserve_addr = (target_ulong)-1ULL;
9180 /* Be sure no exception or interrupt is pending */
9181 env->pending_interrupts = 0;
9182 s->exception_index = POWERPC_EXCP_NONE;
9183 env->error_code = 0;
9184
9185 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9186 env->vpa_addr = 0;
9187 env->slb_shadow_addr = 0;
9188 env->slb_shadow_size = 0;
9189 env->dtl_addr = 0;
9190 env->dtl_size = 0;
9191 #endif /* TARGET_PPC64 */
9192
9193 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9194 ppc_spr_t *spr = &env->spr_cb[i];
9195
9196 if (!spr->name) {
9197 continue;
9198 }
9199 env->spr[i] = spr->default_value;
9200 }
9201
9202 /* Flush all TLBs */
9203 tlb_flush(s, 1);
9204 }
9205
9206 static void ppc_cpu_initfn(Object *obj)
9207 {
9208 CPUState *cs = CPU(obj);
9209 PowerPCCPU *cpu = POWERPC_CPU(obj);
9210 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9211 CPUPPCState *env = &cpu->env;
9212
9213 cs->env_ptr = env;
9214 cpu_exec_init(env);
9215 cpu->cpu_dt_id = cs->cpu_index;
9216
9217 env->msr_mask = pcc->msr_mask;
9218 env->mmu_model = pcc->mmu_model;
9219 env->excp_model = pcc->excp_model;
9220 env->bus_model = pcc->bus_model;
9221 env->insns_flags = pcc->insns_flags;
9222 env->insns_flags2 = pcc->insns_flags2;
9223 env->flags = pcc->flags;
9224 env->bfd_mach = pcc->bfd_mach;
9225 env->check_pow = pcc->check_pow;
9226
9227 #if defined(TARGET_PPC64)
9228 if (pcc->sps) {
9229 env->sps = *pcc->sps;
9230 } else if (env->mmu_model & POWERPC_MMU_64) {
9231 /* Use default sets of page sizes */
9232 static const struct ppc_segment_page_sizes defsps = {
9233 .sps = {
9234 { .page_shift = 12, /* 4K */
9235 .slb_enc = 0,
9236 .enc = { { .page_shift = 12, .pte_enc = 0 } }
9237 },
9238 { .page_shift = 24, /* 16M */
9239 .slb_enc = 0x100,
9240 .enc = { { .page_shift = 24, .pte_enc = 0 } }
9241 },
9242 },
9243 };
9244 env->sps = defsps;
9245 }
9246 #endif /* defined(TARGET_PPC64) */
9247
9248 if (tcg_enabled()) {
9249 ppc_translate_init();
9250 }
9251 }
9252
9253 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9254 {
9255 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9256 CPUClass *cc = CPU_CLASS(oc);
9257 DeviceClass *dc = DEVICE_CLASS(oc);
9258
9259 pcc->parent_realize = dc->realize;
9260 pcc->pvr = CPU_POWERPC_DEFAULT_MASK;
9261 pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK;
9262 dc->realize = ppc_cpu_realizefn;
9263 dc->unrealize = ppc_cpu_unrealizefn;
9264
9265 pcc->parent_reset = cc->reset;
9266 cc->reset = ppc_cpu_reset;
9267
9268 cc->class_by_name = ppc_cpu_class_by_name;
9269 cc->has_work = ppc_cpu_has_work;
9270 cc->do_interrupt = ppc_cpu_do_interrupt;
9271 cc->dump_state = ppc_cpu_dump_state;
9272 cc->dump_statistics = ppc_cpu_dump_statistics;
9273 cc->set_pc = ppc_cpu_set_pc;
9274 cc->gdb_read_register = ppc_cpu_gdb_read_register;
9275 cc->gdb_write_register = ppc_cpu_gdb_write_register;
9276 #ifdef CONFIG_USER_ONLY
9277 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
9278 #else
9279 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
9280 cc->vmsd = &vmstate_ppc_cpu;
9281 #if defined(TARGET_PPC64)
9282 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
9283 cc->write_elf64_qemunote = ppc64_cpu_write_elf64_qemunote;
9284 #endif
9285 #endif
9286
9287 cc->gdb_num_core_regs = 71;
9288 #if defined(TARGET_PPC64)
9289 cc->gdb_core_xml_file = "power64-core.xml";
9290 #else
9291 cc->gdb_core_xml_file = "power-core.xml";
9292 #endif
9293
9294 dc->fw_name = "PowerPC,UNKNOWN";
9295 }
9296
9297 static const TypeInfo ppc_cpu_type_info = {
9298 .name = TYPE_POWERPC_CPU,
9299 .parent = TYPE_CPU,
9300 .instance_size = sizeof(PowerPCCPU),
9301 .instance_init = ppc_cpu_initfn,
9302 .abstract = true,
9303 .class_size = sizeof(PowerPCCPUClass),
9304 .class_init = ppc_cpu_class_init,
9305 };
9306
9307 static void ppc_cpu_register_types(void)
9308 {
9309 type_register_static(&ppc_cpu_type_info);
9310 }
9311
9312 type_init(ppc_cpu_register_types)
QEmu