target-ppc/fpu_helper.c

   1 /*
   2  *  PowerPC floating point and SPE emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "cpu.h"
  20 #include "exec/helper-proto.h"
  21
  22 /*****************************************************************************/
  23 /* Floating point operations helpers */
  24 uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
  25 {
  26     CPU_FloatU f;
  27     CPU_DoubleU d;
  28
  29     f.l = arg;
  30     d.d = float32_to_float64(f.f, &env->fp_status);
  31     return d.ll;
  32 }
  33
  34 uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
  35 {
  36     CPU_FloatU f;
  37     CPU_DoubleU d;
  38
  39     d.ll = arg;
  40     f.f = float64_to_float32(d.d, &env->fp_status);
  41     return f.l;
  42 }
  43
  44 static inline int isden(float64 d)
  45 {
  46     CPU_DoubleU u;
  47
  48     u.d = d;
  49
  50     return ((u.ll >> 52) & 0x7FF) == 0;
  51 }
  52
  53 static inline int ppc_float32_get_unbiased_exp(float32 f)
  54 {
  55     return ((f >> 23) & 0xFF) - 127;
  56 }
  57
  58 static inline int ppc_float64_get_unbiased_exp(float64 f)
  59 {
  60     return ((f >> 52) & 0x7FF) - 1023;
  61 }
  62
  63 uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
  64 {
  65     CPU_DoubleU farg;
  66     int isneg;
  67     int ret;
  68
  69     farg.ll = arg;
  70     isneg = float64_is_neg(farg.d);
  71     if (unlikely(float64_is_any_nan(farg.d))) {
  72         if (float64_is_signaling_nan(farg.d)) {
  73             /* Signaling NaN: flags are undefined */
  74             ret = 0x00;
  75         } else {
  76             /* Quiet NaN */
  77             ret = 0x11;
  78         }
  79     } else if (unlikely(float64_is_infinity(farg.d))) {
  80         /* +/- infinity */
  81         if (isneg) {
  82             ret = 0x09;
  83         } else {
  84             ret = 0x05;
  85         }
  86     } else {
  87         if (float64_is_zero(farg.d)) {
  88             /* +/- zero */
  89             if (isneg) {
  90                 ret = 0x12;
  91             } else {
  92                 ret = 0x02;
  93             }
  94         } else {
  95             if (isden(farg.d)) {
  96                 /* Denormalized numbers */
  97                 ret = 0x10;
  98             } else {
  99                 /* Normalized numbers */
 100                 ret = 0x00;
 101             }
 102             if (isneg) {
 103                 ret |= 0x08;
 104             } else {
 105                 ret |= 0x04;
 106             }
 107         }
 108     }
 109     if (set_fprf) {
 110         /* We update FPSCR_FPRF */
 111         env->fpscr &= ~(0x1F << FPSCR_FPRF);
 112         env->fpscr |= ret << FPSCR_FPRF;
 113     }
 114     /* We just need fpcc to update Rc1 */
 115     return ret & 0xF;
 116 }
 117
 118 /* Floating-point invalid operations exception */
 119 static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,
 120                                              int set_fpcc)
 121 {
 122     CPUState *cs = CPU(ppc_env_get_cpu(env));
 123     uint64_t ret = 0;
 124     int ve;
 125
 126     ve = fpscr_ve;
 127     switch (op) {
 128     case POWERPC_EXCP_FP_VXSNAN:
 129         env->fpscr |= 1 << FPSCR_VXSNAN;
 130         break;
 131     case POWERPC_EXCP_FP_VXSOFT:
 132         env->fpscr |= 1 << FPSCR_VXSOFT;
 133         break;
 134     case POWERPC_EXCP_FP_VXISI:
 135         /* Magnitude subtraction of infinities */
 136         env->fpscr |= 1 << FPSCR_VXISI;
 137         goto update_arith;
 138     case POWERPC_EXCP_FP_VXIDI:
 139         /* Division of infinity by infinity */
 140         env->fpscr |= 1 << FPSCR_VXIDI;
 141         goto update_arith;
 142     case POWERPC_EXCP_FP_VXZDZ:
 143         /* Division of zero by zero */
 144         env->fpscr |= 1 << FPSCR_VXZDZ;
 145         goto update_arith;
 146     case POWERPC_EXCP_FP_VXIMZ:
 147         /* Multiplication of zero by infinity */
 148         env->fpscr |= 1 << FPSCR_VXIMZ;
 149         goto update_arith;
 150     case POWERPC_EXCP_FP_VXVC:
 151         /* Ordered comparison of NaN */
 152         env->fpscr |= 1 << FPSCR_VXVC;
 153         if (set_fpcc) {
 154             env->fpscr &= ~(0xF << FPSCR_FPCC);
 155             env->fpscr |= 0x11 << FPSCR_FPCC;
 156         }
 157         /* We must update the target FPR before raising the exception */
 158         if (ve != 0) {
 159             cs->exception_index = POWERPC_EXCP_PROGRAM;
 160             env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
 161             /* Update the floating-point enabled exception summary */
 162             env->fpscr |= 1 << FPSCR_FEX;
 163             /* Exception is differed */
 164             ve = 0;
 165         }
 166         break;
 167     case POWERPC_EXCP_FP_VXSQRT:
 168         /* Square root of a negative number */
 169         env->fpscr |= 1 << FPSCR_VXSQRT;
 170     update_arith:
 171         env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 172         if (ve == 0) {
 173             /* Set the result to quiet NaN */
 174             ret = 0x7FF8000000000000ULL;
 175             if (set_fpcc) {
 176                 env->fpscr &= ~(0xF << FPSCR_FPCC);
 177                 env->fpscr |= 0x11 << FPSCR_FPCC;
 178             }
 179         }
 180         break;
 181     case POWERPC_EXCP_FP_VXCVI:
 182         /* Invalid conversion */
 183         env->fpscr |= 1 << FPSCR_VXCVI;
 184         env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 185         if (ve == 0) {
 186             /* Set the result to quiet NaN */
 187             ret = 0x7FF8000000000000ULL;
 188             if (set_fpcc) {
 189                 env->fpscr &= ~(0xF << FPSCR_FPCC);
 190                 env->fpscr |= 0x11 << FPSCR_FPCC;
 191             }
 192         }
 193         break;
 194     }
 195     /* Update the floating-point invalid operation summary */
 196     env->fpscr |= 1 << FPSCR_VX;
 197     /* Update the floating-point exception summary */
 198     env->fpscr |= 1 << FPSCR_FX;
 199     if (ve != 0) {
 200         /* Update the floating-point enabled exception summary */
 201         env->fpscr |= 1 << FPSCR_FEX;
 202         if (msr_fe0 != 0 || msr_fe1 != 0) {
 203             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 204                                        POWERPC_EXCP_FP | op);
 205         }
 206     }
 207     return ret;
 208 }
 209
 210 static inline void float_zero_divide_excp(CPUPPCState *env)
 211 {
 212     env->fpscr |= 1 << FPSCR_ZX;
 213     env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 214     /* Update the floating-point exception summary */
 215     env->fpscr |= 1 << FPSCR_FX;
 216     if (fpscr_ze != 0) {
 217         /* Update the floating-point enabled exception summary */
 218         env->fpscr |= 1 << FPSCR_FEX;
 219         if (msr_fe0 != 0 || msr_fe1 != 0) {
 220             helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 221                                        POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
 222         }
 223     }
 224 }
 225
 226 static inline void float_overflow_excp(CPUPPCState *env)
 227 {
 228     CPUState *cs = CPU(ppc_env_get_cpu(env));
 229
 230     env->fpscr |= 1 << FPSCR_OX;
 231     /* Update the floating-point exception summary */
 232     env->fpscr |= 1 << FPSCR_FX;
 233     if (fpscr_oe != 0) {
 234         /* XXX: should adjust the result */
 235         /* Update the floating-point enabled exception summary */
 236         env->fpscr |= 1 << FPSCR_FEX;
 237         /* We must update the target FPR before raising the exception */
 238         cs->exception_index = POWERPC_EXCP_PROGRAM;
 239         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
 240     } else {
 241         env->fpscr |= 1 << FPSCR_XX;
 242         env->fpscr |= 1 << FPSCR_FI;
 243     }
 244 }
 245
 246 static inline void float_underflow_excp(CPUPPCState *env)
 247 {
 248     CPUState *cs = CPU(ppc_env_get_cpu(env));
 249
 250     env->fpscr |= 1 << FPSCR_UX;
 251     /* Update the floating-point exception summary */
 252     env->fpscr |= 1 << FPSCR_FX;
 253     if (fpscr_ue != 0) {
 254         /* XXX: should adjust the result */
 255         /* Update the floating-point enabled exception summary */
 256         env->fpscr |= 1 << FPSCR_FEX;
 257         /* We must update the target FPR before raising the exception */
 258         cs->exception_index = POWERPC_EXCP_PROGRAM;
 259         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
 260     }
 261 }
 262
 263 static inline void float_inexact_excp(CPUPPCState *env)
 264 {
 265     CPUState *cs = CPU(ppc_env_get_cpu(env));
 266
 267     env->fpscr |= 1 << FPSCR_XX;
 268     /* Update the floating-point exception summary */
 269     env->fpscr |= 1 << FPSCR_FX;
 270     if (fpscr_xe != 0) {
 271         /* Update the floating-point enabled exception summary */
 272         env->fpscr |= 1 << FPSCR_FEX;
 273         /* We must update the target FPR before raising the exception */
 274         cs->exception_index = POWERPC_EXCP_PROGRAM;
 275         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
 276     }
 277 }
 278
 279 static inline void fpscr_set_rounding_mode(CPUPPCState *env)
 280 {
 281     int rnd_type;
 282
 283     /* Set rounding mode */
 284     switch (fpscr_rn) {
 285     case 0:
 286         /* Best approximation (round to nearest) */
 287         rnd_type = float_round_nearest_even;
 288         break;
 289     case 1:
 290         /* Smaller magnitude (round toward zero) */
 291         rnd_type = float_round_to_zero;
 292         break;
 293     case 2:
 294         /* Round toward +infinite */
 295         rnd_type = float_round_up;
 296         break;
 297     default:
 298     case 3:
 299         /* Round toward -infinite */
 300         rnd_type = float_round_down;
 301         break;
 302     }
 303     set_float_rounding_mode(rnd_type, &env->fp_status);
 304 }
 305
 306 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
 307 {
 308     int prev;
 309
 310     prev = (env->fpscr >> bit) & 1;
 311     env->fpscr &= ~(1 << bit);
 312     if (prev == 1) {
 313         switch (bit) {
 314         case FPSCR_RN1:
 315         case FPSCR_RN:
 316             fpscr_set_rounding_mode(env);
 317             break;
 318         default:
 319             break;
 320         }
 321     }
 322 }
 323
 324 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
 325 {
 326     CPUState *cs = CPU(ppc_env_get_cpu(env));
 327     int prev;
 328
 329     prev = (env->fpscr >> bit) & 1;
 330     env->fpscr |= 1 << bit;
 331     if (prev == 0) {
 332         switch (bit) {
 333         case FPSCR_VX:
 334             env->fpscr |= 1 << FPSCR_FX;
 335             if (fpscr_ve) {
 336                 goto raise_ve;
 337             }
 338             break;
 339         case FPSCR_OX:
 340             env->fpscr |= 1 << FPSCR_FX;
 341             if (fpscr_oe) {
 342                 goto raise_oe;
 343             }
 344             break;
 345         case FPSCR_UX:
 346             env->fpscr |= 1 << FPSCR_FX;
 347             if (fpscr_ue) {
 348                 goto raise_ue;
 349             }
 350             break;
 351         case FPSCR_ZX:
 352             env->fpscr |= 1 << FPSCR_FX;
 353             if (fpscr_ze) {
 354                 goto raise_ze;
 355             }
 356             break;
 357         case FPSCR_XX:
 358             env->fpscr |= 1 << FPSCR_FX;
 359             if (fpscr_xe) {
 360                 goto raise_xe;
 361             }
 362             break;
 363         case FPSCR_VXSNAN:
 364         case FPSCR_VXISI:
 365         case FPSCR_VXIDI:
 366         case FPSCR_VXZDZ:
 367         case FPSCR_VXIMZ:
 368         case FPSCR_VXVC:
 369         case FPSCR_VXSOFT:
 370         case FPSCR_VXSQRT:
 371         case FPSCR_VXCVI:
 372             env->fpscr |= 1 << FPSCR_VX;
 373             env->fpscr |= 1 << FPSCR_FX;
 374             if (fpscr_ve != 0) {
 375                 goto raise_ve;
 376             }
 377             break;
 378         case FPSCR_VE:
 379             if (fpscr_vx != 0) {
 380             raise_ve:
 381                 env->error_code = POWERPC_EXCP_FP;
 382                 if (fpscr_vxsnan) {
 383                     env->error_code |= POWERPC_EXCP_FP_VXSNAN;
 384                 }
 385                 if (fpscr_vxisi) {
 386                     env->error_code |= POWERPC_EXCP_FP_VXISI;
 387                 }
 388                 if (fpscr_vxidi) {
 389                     env->error_code |= POWERPC_EXCP_FP_VXIDI;
 390                 }
 391                 if (fpscr_vxzdz) {
 392                     env->error_code |= POWERPC_EXCP_FP_VXZDZ;
 393                 }
 394                 if (fpscr_vximz) {
 395                     env->error_code |= POWERPC_EXCP_FP_VXIMZ;
 396                 }
 397                 if (fpscr_vxvc) {
 398                     env->error_code |= POWERPC_EXCP_FP_VXVC;
 399                 }
 400                 if (fpscr_vxsoft) {
 401                     env->error_code |= POWERPC_EXCP_FP_VXSOFT;
 402                 }
 403                 if (fpscr_vxsqrt) {
 404                     env->error_code |= POWERPC_EXCP_FP_VXSQRT;
 405                 }
 406                 if (fpscr_vxcvi) {
 407                     env->error_code |= POWERPC_EXCP_FP_VXCVI;
 408                 }
 409                 goto raise_excp;
 410             }
 411             break;
 412         case FPSCR_OE:
 413             if (fpscr_ox != 0) {
 414             raise_oe:
 415                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
 416                 goto raise_excp;
 417             }
 418             break;
 419         case FPSCR_UE:
 420             if (fpscr_ux != 0) {
 421             raise_ue:
 422                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
 423                 goto raise_excp;
 424             }
 425             break;
 426         case FPSCR_ZE:
 427             if (fpscr_zx != 0) {
 428             raise_ze:
 429                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
 430                 goto raise_excp;
 431             }
 432             break;
 433         case FPSCR_XE:
 434             if (fpscr_xx != 0) {
 435             raise_xe:
 436                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
 437                 goto raise_excp;
 438             }
 439             break;
 440         case FPSCR_RN1:
 441         case FPSCR_RN:
 442             fpscr_set_rounding_mode(env);
 443             break;
 444         default:
 445             break;
 446         raise_excp:
 447             /* Update the floating-point enabled exception summary */
 448             env->fpscr |= 1 << FPSCR_FEX;
 449             /* We have to update Rc1 before raising the exception */
 450             cs->exception_index = POWERPC_EXCP_PROGRAM;
 451             break;
 452         }
 453     }
 454 }
 455
 456 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 457 {
 458     CPUState *cs = CPU(ppc_env_get_cpu(env));
 459     target_ulong prev, new;
 460     int i;
 461
 462     prev = env->fpscr;
 463     new = (target_ulong)arg;
 464     new &= ~0x60000000LL;
 465     new |= prev & 0x60000000LL;
 466     for (i = 0; i < sizeof(target_ulong) * 2; i++) {
 467         if (mask & (1 << i)) {
 468             env->fpscr &= ~(0xFLL << (4 * i));
 469             env->fpscr |= new & (0xFLL << (4 * i));
 470         }
 471     }
 472     /* Update VX and FEX */
 473     if (fpscr_ix != 0) {
 474         env->fpscr |= 1 << FPSCR_VX;
 475     } else {
 476         env->fpscr &= ~(1 << FPSCR_VX);
 477     }
 478     if ((fpscr_ex & fpscr_eex) != 0) {
 479         env->fpscr |= 1 << FPSCR_FEX;
 480         cs->exception_index = POWERPC_EXCP_PROGRAM;
 481         /* XXX: we should compute it properly */
 482         env->error_code = POWERPC_EXCP_FP;
 483     } else {
 484         env->fpscr &= ~(1 << FPSCR_FEX);
 485     }
 486     fpscr_set_rounding_mode(env);
 487 }
 488
 489 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 490 {
 491     helper_store_fpscr(env, arg, mask);
 492 }
 493
 494 void helper_float_check_status(CPUPPCState *env)
 495 {
 496     CPUState *cs = CPU(ppc_env_get_cpu(env));
 497     int status = get_float_exception_flags(&env->fp_status);
 498
 499     if (status & float_flag_divbyzero) {
 500         float_zero_divide_excp(env);
 501     } else if (status & float_flag_overflow) {
 502         float_overflow_excp(env);
 503     } else if (status & float_flag_underflow) {
 504         float_underflow_excp(env);
 505     } else if (status & float_flag_inexact) {
 506         float_inexact_excp(env);
 507     }
 508
 509     if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
 510         (env->error_code & POWERPC_EXCP_FP)) {
 511         /* Differred floating-point exception after target FPR update */
 512         if (msr_fe0 != 0 || msr_fe1 != 0) {
 513             helper_raise_exception_err(env, cs->exception_index,
 514                                        env->error_code);
 515         }
 516     }
 517 }
 518
 519 void helper_reset_fpstatus(CPUPPCState *env)
 520 {
 521     set_float_exception_flags(0, &env->fp_status);
 522 }
 523
 524 /* fadd - fadd. */
 525 uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 526 {
 527     CPU_DoubleU farg1, farg2;
 528
 529     farg1.ll = arg1;
 530     farg2.ll = arg2;
 531
 532     if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
 533                  float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
 534         /* Magnitude subtraction of infinities */
 535         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 536     } else {
 537         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 538                      float64_is_signaling_nan(farg2.d))) {
 539             /* sNaN addition */
 540             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 541         }
 542         farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
 543     }
 544
 545     return farg1.ll;
 546 }
 547
 548 /* fsub - fsub. */
 549 uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 550 {
 551     CPU_DoubleU farg1, farg2;
 552
 553     farg1.ll = arg1;
 554     farg2.ll = arg2;
 555
 556     if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
 557                  float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
 558         /* Magnitude subtraction of infinities */
 559         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 560     } else {
 561         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 562                      float64_is_signaling_nan(farg2.d))) {
 563             /* sNaN subtraction */
 564             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 565         }
 566         farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
 567     }
 568
 569     return farg1.ll;
 570 }
 571
 572 /* fmul - fmul. */
 573 uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 574 {
 575     CPU_DoubleU farg1, farg2;
 576
 577     farg1.ll = arg1;
 578     farg2.ll = arg2;
 579
 580     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 581                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 582         /* Multiplication of zero by infinity */
 583         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 584     } else {
 585         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 586                      float64_is_signaling_nan(farg2.d))) {
 587             /* sNaN multiplication */
 588             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 589         }
 590         farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
 591     }
 592
 593     return farg1.ll;
 594 }
 595
 596 /* fdiv - fdiv. */
 597 uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 598 {
 599     CPU_DoubleU farg1, farg2;
 600
 601     farg1.ll = arg1;
 602     farg2.ll = arg2;
 603
 604     if (unlikely(float64_is_infinity(farg1.d) &&
 605                  float64_is_infinity(farg2.d))) {
 606         /* Division of infinity by infinity */
 607         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1);
 608     } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
 609         /* Division of zero by zero */
 610         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
 611     } else {
 612         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 613                      float64_is_signaling_nan(farg2.d))) {
 614             /* sNaN division */
 615             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 616         }
 617         farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
 618     }
 619
 620     return farg1.ll;
 621 }
 622
 623
 624 #define FPU_FCTI(op, cvt, nanval)                                      \
 625 uint64_t helper_##op(CPUPPCState *env, uint64_t arg)                   \
 626 {                                                                      \
 627     CPU_DoubleU farg;                                                  \
 628                                                                        \
 629     farg.ll = arg;                                                     \
 630     farg.ll = float64_to_##cvt(farg.d, &env->fp_status);               \
 631                                                                        \
 632     if (unlikely(env->fp_status.float_exception_flags)) {              \
 633         if (float64_is_any_nan(arg)) {                                 \
 634             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);      \
 635             if (float64_is_signaling_nan(arg)) {                       \
 636                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
 637             }                                                          \
 638             farg.ll = nanval;                                          \
 639         } else if (env->fp_status.float_exception_flags &              \
 640                    float_flag_invalid) {                               \
 641             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);      \
 642         }                                                              \
 643         helper_float_check_status(env);                                \
 644     }                                                                  \
 645     return farg.ll;                                                    \
 646  }
 647
 648 FPU_FCTI(fctiw, int32, 0x80000000U)
 649 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
 650 FPU_FCTI(fctiwu, uint32, 0x00000000U)
 651 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
 652 #if defined(TARGET_PPC64)
 653 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
 654 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
 655 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
 656 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
 657 #endif
 658
 659 #if defined(TARGET_PPC64)
 660
 661 #define FPU_FCFI(op, cvtr, is_single)                      \
 662 uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
 663 {                                                          \
 664     CPU_DoubleU farg;                                      \
 665                                                            \
 666     if (is_single) {                                       \
 667         float32 tmp = cvtr(arg, &env->fp_status);          \
 668         farg.d = float32_to_float64(tmp, &env->fp_status); \
 669     } else {                                               \
 670         farg.d = cvtr(arg, &env->fp_status);               \
 671     }                                                      \
 672     helper_float_check_status(env);                        \
 673     return farg.ll;                                        \
 674 }
 675
 676 FPU_FCFI(fcfid, int64_to_float64, 0)
 677 FPU_FCFI(fcfids, int64_to_float32, 1)
 678 FPU_FCFI(fcfidu, uint64_to_float64, 0)
 679 FPU_FCFI(fcfidus, uint64_to_float32, 1)
 680
 681 #endif
 682
 683 static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
 684                               int rounding_mode)
 685 {
 686     CPU_DoubleU farg;
 687
 688     farg.ll = arg;
 689
 690     if (unlikely(float64_is_signaling_nan(farg.d))) {
 691         /* sNaN round */
 692         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 693         farg.ll = arg | 0x0008000000000000ULL;
 694     } else {
 695         int inexact = get_float_exception_flags(&env->fp_status) &
 696                       float_flag_inexact;
 697         set_float_rounding_mode(rounding_mode, &env->fp_status);
 698         farg.ll = float64_round_to_int(farg.d, &env->fp_status);
 699         /* Restore rounding mode from FPSCR */
 700         fpscr_set_rounding_mode(env);
 701
 702         /* fri* does not set FPSCR[XX] */
 703         if (!inexact) {
 704             env->fp_status.float_exception_flags &= ~float_flag_inexact;
 705         }
 706     }
 707     helper_float_check_status(env);
 708     return farg.ll;
 709 }
 710
 711 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
 712 {
 713     return do_fri(env, arg, float_round_ties_away);
 714 }
 715
 716 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
 717 {
 718     return do_fri(env, arg, float_round_to_zero);
 719 }
 720
 721 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
 722 {
 723     return do_fri(env, arg, float_round_up);
 724 }
 725
 726 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
 727 {
 728     return do_fri(env, arg, float_round_down);
 729 }
 730
 731 /* fmadd - fmadd. */
 732 uint64_t helper_fmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 733                       uint64_t arg3)
 734 {
 735     CPU_DoubleU farg1, farg2, farg3;
 736
 737     farg1.ll = arg1;
 738     farg2.ll = arg2;
 739     farg3.ll = arg3;
 740
 741     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 742                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 743         /* Multiplication of zero by infinity */
 744         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 745     } else {
 746         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 747                      float64_is_signaling_nan(farg2.d) ||
 748                      float64_is_signaling_nan(farg3.d))) {
 749             /* sNaN operation */
 750             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 751         }
 752         /* This is the way the PowerPC specification defines it */
 753         float128 ft0_128, ft1_128;
 754
 755         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 756         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 757         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 758         if (unlikely(float128_is_infinity(ft0_128) &&
 759                      float64_is_infinity(farg3.d) &&
 760                      float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
 761             /* Magnitude subtraction of infinities */
 762             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 763         } else {
 764             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 765             ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 766             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 767         }
 768     }
 769
 770     return farg1.ll;
 771 }
 772
 773 /* fmsub - fmsub. */
 774 uint64_t helper_fmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 775                       uint64_t arg3)
 776 {
 777     CPU_DoubleU farg1, farg2, farg3;
 778
 779     farg1.ll = arg1;
 780     farg2.ll = arg2;
 781     farg3.ll = arg3;
 782
 783     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 784                  (float64_is_zero(farg1.d) &&
 785                   float64_is_infinity(farg2.d)))) {
 786         /* Multiplication of zero by infinity */
 787         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 788     } else {
 789         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 790                      float64_is_signaling_nan(farg2.d) ||
 791                      float64_is_signaling_nan(farg3.d))) {
 792             /* sNaN operation */
 793             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 794         }
 795         /* This is the way the PowerPC specification defines it */
 796         float128 ft0_128, ft1_128;
 797
 798         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 799         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 800         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 801         if (unlikely(float128_is_infinity(ft0_128) &&
 802                      float64_is_infinity(farg3.d) &&
 803                      float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
 804             /* Magnitude subtraction of infinities */
 805             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 806         } else {
 807             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 808             ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 809             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 810         }
 811     }
 812     return farg1.ll;
 813 }
 814
 815 /* fnmadd - fnmadd. */
 816 uint64_t helper_fnmadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 817                        uint64_t arg3)
 818 {
 819     CPU_DoubleU farg1, farg2, farg3;
 820
 821     farg1.ll = arg1;
 822     farg2.ll = arg2;
 823     farg3.ll = arg3;
 824
 825     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 826                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 827         /* Multiplication of zero by infinity */
 828         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 829     } else {
 830         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 831                      float64_is_signaling_nan(farg2.d) ||
 832                      float64_is_signaling_nan(farg3.d))) {
 833             /* sNaN operation */
 834             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 835         }
 836         /* This is the way the PowerPC specification defines it */
 837         float128 ft0_128, ft1_128;
 838
 839         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 840         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 841         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 842         if (unlikely(float128_is_infinity(ft0_128) &&
 843                      float64_is_infinity(farg3.d) &&
 844                      float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
 845             /* Magnitude subtraction of infinities */
 846             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 847         } else {
 848             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 849             ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
 850             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 851         }
 852         if (likely(!float64_is_any_nan(farg1.d))) {
 853             farg1.d = float64_chs(farg1.d);
 854         }
 855     }
 856     return farg1.ll;
 857 }
 858
 859 /* fnmsub - fnmsub. */
 860 uint64_t helper_fnmsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 861                        uint64_t arg3)
 862 {
 863     CPU_DoubleU farg1, farg2, farg3;
 864
 865     farg1.ll = arg1;
 866     farg2.ll = arg2;
 867     farg3.ll = arg3;
 868
 869     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 870                  (float64_is_zero(farg1.d) &&
 871                   float64_is_infinity(farg2.d)))) {
 872         /* Multiplication of zero by infinity */
 873         farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 874     } else {
 875         if (unlikely(float64_is_signaling_nan(farg1.d) ||
 876                      float64_is_signaling_nan(farg2.d) ||
 877                      float64_is_signaling_nan(farg3.d))) {
 878             /* sNaN operation */
 879             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 880         }
 881         /* This is the way the PowerPC specification defines it */
 882         float128 ft0_128, ft1_128;
 883
 884         ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
 885         ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
 886         ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
 887         if (unlikely(float128_is_infinity(ft0_128) &&
 888                      float64_is_infinity(farg3.d) &&
 889                      float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
 890             /* Magnitude subtraction of infinities */
 891             farg1.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 892         } else {
 893             ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
 894             ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
 895             farg1.d = float128_to_float64(ft0_128, &env->fp_status);
 896         }
 897         if (likely(!float64_is_any_nan(farg1.d))) {
 898             farg1.d = float64_chs(farg1.d);
 899         }
 900     }
 901     return farg1.ll;
 902 }
 903
 904 /* frsp - frsp. */
 905 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
 906 {
 907     CPU_DoubleU farg;
 908     float32 f32;
 909
 910     farg.ll = arg;
 911
 912     if (unlikely(float64_is_signaling_nan(farg.d))) {
 913         /* sNaN square root */
 914         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 915     }
 916     f32 = float64_to_float32(farg.d, &env->fp_status);
 917     farg.d = float32_to_float64(f32, &env->fp_status);
 918
 919     return farg.ll;
 920 }
 921
 922 /* fsqrt - fsqrt. */
 923 uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
 924 {
 925     CPU_DoubleU farg;
 926
 927     farg.ll = arg;
 928
 929     if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
 930         /* Square root of a negative nonzero number */
 931         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
 932     } else {
 933         if (unlikely(float64_is_signaling_nan(farg.d))) {
 934             /* sNaN square root */
 935             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 936         }
 937         farg.d = float64_sqrt(farg.d, &env->fp_status);
 938     }
 939     return farg.ll;
 940 }
 941
 942 /* fre - fre. */
 943 uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
 944 {
 945     CPU_DoubleU farg;
 946
 947     farg.ll = arg;
 948
 949     if (unlikely(float64_is_signaling_nan(farg.d))) {
 950         /* sNaN reciprocal */
 951         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 952     }
 953     farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 954     return farg.d;
 955 }
 956
 957 /* fres - fres. */
 958 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
 959 {
 960     CPU_DoubleU farg;
 961     float32 f32;
 962
 963     farg.ll = arg;
 964
 965     if (unlikely(float64_is_signaling_nan(farg.d))) {
 966         /* sNaN reciprocal */
 967         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 968     }
 969     farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 970     f32 = float64_to_float32(farg.d, &env->fp_status);
 971     farg.d = float32_to_float64(f32, &env->fp_status);
 972
 973     return farg.ll;
 974 }
 975
 976 /* frsqrte  - frsqrte. */
 977 uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
 978 {
 979     CPU_DoubleU farg;
 980     float32 f32;
 981
 982     farg.ll = arg;
 983
 984     if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
 985         /* Reciprocal square root of a negative nonzero number */
 986         farg.ll = fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
 987     } else {
 988         if (unlikely(float64_is_signaling_nan(farg.d))) {
 989             /* sNaN reciprocal square root */
 990             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 991         }
 992         farg.d = float64_sqrt(farg.d, &env->fp_status);
 993         farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 994         f32 = float64_to_float32(farg.d, &env->fp_status);
 995         farg.d = float32_to_float64(f32, &env->fp_status);
 996     }
 997     return farg.ll;
 998 }
 999
1000 /* fsel - fsel. */
1001 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1002                      uint64_t arg3)
1003 {
1004     CPU_DoubleU farg1;
1005
1006     farg1.ll = arg1;
1007
1008     if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
1009         !float64_is_any_nan(farg1.d)) {
1010         return arg2;
1011     } else {
1012         return arg3;
1013     }
1014 }
1015
1016 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
1017 {
1018     int fe_flag = 0;
1019     int fg_flag = 0;
1020
1021     if (unlikely(float64_is_infinity(fra) ||
1022                  float64_is_infinity(frb) ||
1023                  float64_is_zero(frb))) {
1024         fe_flag = 1;
1025         fg_flag = 1;
1026     } else {
1027         int e_a = ppc_float64_get_unbiased_exp(fra);
1028         int e_b = ppc_float64_get_unbiased_exp(frb);
1029
1030         if (unlikely(float64_is_any_nan(fra) ||
1031                      float64_is_any_nan(frb))) {
1032             fe_flag = 1;
1033         } else if ((e_b <= -1022) || (e_b >= 1021)) {
1034             fe_flag = 1;
1035         } else if (!float64_is_zero(fra) &&
1036                    (((e_a - e_b) >= 1023) ||
1037                     ((e_a - e_b) <= -1021) ||
1038                     (e_a <= -970))) {
1039             fe_flag = 1;
1040         }
1041
1042         if (unlikely(float64_is_zero_or_denormal(frb))) {
1043             /* XB is not zero because of the above check and */
1044             /* so must be denormalized.                      */
1045             fg_flag = 1;
1046         }
1047     }
1048
1049     return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1050 }
1051
1052 uint32_t helper_ftsqrt(uint64_t frb)
1053 {
1054     int fe_flag = 0;
1055     int fg_flag = 0;
1056
1057     if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
1058         fe_flag = 1;
1059         fg_flag = 1;
1060     } else {
1061         int e_b = ppc_float64_get_unbiased_exp(frb);
1062
1063         if (unlikely(float64_is_any_nan(frb))) {
1064             fe_flag = 1;
1065         } else if (unlikely(float64_is_zero(frb))) {
1066             fe_flag = 1;
1067         } else if (unlikely(float64_is_neg(frb))) {
1068             fe_flag = 1;
1069         } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) {
1070             fe_flag = 1;
1071         }
1072
1073         if (unlikely(float64_is_zero_or_denormal(frb))) {
1074             /* XB is not zero because of the above check and */
1075             /* therefore must be denormalized.               */
1076             fg_flag = 1;
1077         }
1078     }
1079
1080     return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
1081 }
1082
1083 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1084                   uint32_t crfD)
1085 {
1086     CPU_DoubleU farg1, farg2;
1087     uint32_t ret = 0;
1088
1089     farg1.ll = arg1;
1090     farg2.ll = arg2;
1091
1092     if (unlikely(float64_is_any_nan(farg1.d) ||
1093                  float64_is_any_nan(farg2.d))) {
1094         ret = 0x01UL;
1095     } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1096         ret = 0x08UL;
1097     } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1098         ret = 0x04UL;
1099     } else {
1100         ret = 0x02UL;
1101     }
1102
1103     env->fpscr &= ~(0x0F << FPSCR_FPRF);
1104     env->fpscr |= ret << FPSCR_FPRF;
1105     env->crf[crfD] = ret;
1106     if (unlikely(ret == 0x01UL
1107                  && (float64_is_signaling_nan(farg1.d) ||
1108                      float64_is_signaling_nan(farg2.d)))) {
1109         /* sNaN comparison */
1110         fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
1111     }
1112 }
1113
1114 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1115                   uint32_t crfD)
1116 {
1117     CPU_DoubleU farg1, farg2;
1118     uint32_t ret = 0;
1119
1120     farg1.ll = arg1;
1121     farg2.ll = arg2;
1122
1123     if (unlikely(float64_is_any_nan(farg1.d) ||
1124                  float64_is_any_nan(farg2.d))) {
1125         ret = 0x01UL;
1126     } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1127         ret = 0x08UL;
1128     } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1129         ret = 0x04UL;
1130     } else {
1131         ret = 0x02UL;
1132     }
1133
1134     env->fpscr &= ~(0x0F << FPSCR_FPRF);
1135     env->fpscr |= ret << FPSCR_FPRF;
1136     env->crf[crfD] = ret;
1137     if (unlikely(ret == 0x01UL)) {
1138         if (float64_is_signaling_nan(farg1.d) ||
1139             float64_is_signaling_nan(farg2.d)) {
1140             /* sNaN comparison */
1141             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
1142                                   POWERPC_EXCP_FP_VXVC, 1);
1143         } else {
1144             /* qNaN comparison */
1145             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 1);
1146         }
1147     }
1148 }
1149
1150 /* Single-precision floating-point conversions */
1151 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
1152 {
1153     CPU_FloatU u;
1154
1155     u.f = int32_to_float32(val, &env->vec_status);
1156
1157     return u.l;
1158 }
1159
1160 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
1161 {
1162     CPU_FloatU u;
1163
1164     u.f = uint32_to_float32(val, &env->vec_status);
1165
1166     return u.l;
1167 }
1168
1169 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
1170 {
1171     CPU_FloatU u;
1172
1173     u.l = val;
1174     /* NaN are not treated the same way IEEE 754 does */
1175     if (unlikely(float32_is_quiet_nan(u.f))) {
1176         return 0;
1177     }
1178
1179     return float32_to_int32(u.f, &env->vec_status);
1180 }
1181
1182 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1183 {
1184     CPU_FloatU u;
1185
1186     u.l = val;
1187     /* NaN are not treated the same way IEEE 754 does */
1188     if (unlikely(float32_is_quiet_nan(u.f))) {
1189         return 0;
1190     }
1191
1192     return float32_to_uint32(u.f, &env->vec_status);
1193 }
1194
1195 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1196 {
1197     CPU_FloatU u;
1198
1199     u.l = val;
1200     /* NaN are not treated the same way IEEE 754 does */
1201     if (unlikely(float32_is_quiet_nan(u.f))) {
1202         return 0;
1203     }
1204
1205     return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1206 }
1207
1208 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1209 {
1210     CPU_FloatU u;
1211
1212     u.l = val;
1213     /* NaN are not treated the same way IEEE 754 does */
1214     if (unlikely(float32_is_quiet_nan(u.f))) {
1215         return 0;
1216     }
1217
1218     return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1219 }
1220
1221 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1222 {
1223     CPU_FloatU u;
1224     float32 tmp;
1225
1226     u.f = int32_to_float32(val, &env->vec_status);
1227     tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1228     u.f = float32_div(u.f, tmp, &env->vec_status);
1229
1230     return u.l;
1231 }
1232
1233 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1234 {
1235     CPU_FloatU u;
1236     float32 tmp;
1237
1238     u.f = uint32_to_float32(val, &env->vec_status);
1239     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1240     u.f = float32_div(u.f, tmp, &env->vec_status);
1241
1242     return u.l;
1243 }
1244
1245 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1246 {
1247     CPU_FloatU u;
1248     float32 tmp;
1249
1250     u.l = val;
1251     /* NaN are not treated the same way IEEE 754 does */
1252     if (unlikely(float32_is_quiet_nan(u.f))) {
1253         return 0;
1254     }
1255     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1256     u.f = float32_mul(u.f, tmp, &env->vec_status);
1257
1258     return float32_to_int32(u.f, &env->vec_status);
1259 }
1260
1261 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1262 {
1263     CPU_FloatU u;
1264     float32 tmp;
1265
1266     u.l = val;
1267     /* NaN are not treated the same way IEEE 754 does */
1268     if (unlikely(float32_is_quiet_nan(u.f))) {
1269         return 0;
1270     }
1271     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1272     u.f = float32_mul(u.f, tmp, &env->vec_status);
1273
1274     return float32_to_uint32(u.f, &env->vec_status);
1275 }
1276
1277 #define HELPER_SPE_SINGLE_CONV(name)                              \
1278     uint32_t helper_e##name(CPUPPCState *env, uint32_t val)       \
1279     {                                                             \
1280         return e##name(env, val);                                 \
1281     }
1282 /* efscfsi */
1283 HELPER_SPE_SINGLE_CONV(fscfsi);
1284 /* efscfui */
1285 HELPER_SPE_SINGLE_CONV(fscfui);
1286 /* efscfuf */
1287 HELPER_SPE_SINGLE_CONV(fscfuf);
1288 /* efscfsf */
1289 HELPER_SPE_SINGLE_CONV(fscfsf);
1290 /* efsctsi */
1291 HELPER_SPE_SINGLE_CONV(fsctsi);
1292 /* efsctui */
1293 HELPER_SPE_SINGLE_CONV(fsctui);
1294 /* efsctsiz */
1295 HELPER_SPE_SINGLE_CONV(fsctsiz);
1296 /* efsctuiz */
1297 HELPER_SPE_SINGLE_CONV(fsctuiz);
1298 /* efsctsf */
1299 HELPER_SPE_SINGLE_CONV(fsctsf);
1300 /* efsctuf */
1301 HELPER_SPE_SINGLE_CONV(fsctuf);
1302
1303 #define HELPER_SPE_VECTOR_CONV(name)                            \
1304     uint64_t helper_ev##name(CPUPPCState *env, uint64_t val)    \
1305     {                                                           \
1306         return ((uint64_t)e##name(env, val >> 32) << 32) |      \
1307             (uint64_t)e##name(env, val);                        \
1308     }
1309 /* evfscfsi */
1310 HELPER_SPE_VECTOR_CONV(fscfsi);
1311 /* evfscfui */
1312 HELPER_SPE_VECTOR_CONV(fscfui);
1313 /* evfscfuf */
1314 HELPER_SPE_VECTOR_CONV(fscfuf);
1315 /* evfscfsf */
1316 HELPER_SPE_VECTOR_CONV(fscfsf);
1317 /* evfsctsi */
1318 HELPER_SPE_VECTOR_CONV(fsctsi);
1319 /* evfsctui */
1320 HELPER_SPE_VECTOR_CONV(fsctui);
1321 /* evfsctsiz */
1322 HELPER_SPE_VECTOR_CONV(fsctsiz);
1323 /* evfsctuiz */
1324 HELPER_SPE_VECTOR_CONV(fsctuiz);
1325 /* evfsctsf */
1326 HELPER_SPE_VECTOR_CONV(fsctsf);
1327 /* evfsctuf */
1328 HELPER_SPE_VECTOR_CONV(fsctuf);
1329
1330 /* Single-precision floating-point arithmetic */
1331 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1332 {
1333     CPU_FloatU u1, u2;
1334
1335     u1.l = op1;
1336     u2.l = op2;
1337     u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1338     return u1.l;
1339 }
1340
1341 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1342 {
1343     CPU_FloatU u1, u2;
1344
1345     u1.l = op1;
1346     u2.l = op2;
1347     u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1348     return u1.l;
1349 }
1350
1351 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1352 {
1353     CPU_FloatU u1, u2;
1354
1355     u1.l = op1;
1356     u2.l = op2;
1357     u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1358     return u1.l;
1359 }
1360
1361 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1362 {
1363     CPU_FloatU u1, u2;
1364
1365     u1.l = op1;
1366     u2.l = op2;
1367     u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1368     return u1.l;
1369 }
1370
1371 #define HELPER_SPE_SINGLE_ARITH(name)                                   \
1372     uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1373     {                                                                   \
1374         return e##name(env, op1, op2);                                  \
1375     }
1376 /* efsadd */
1377 HELPER_SPE_SINGLE_ARITH(fsadd);
1378 /* efssub */
1379 HELPER_SPE_SINGLE_ARITH(fssub);
1380 /* efsmul */
1381 HELPER_SPE_SINGLE_ARITH(fsmul);
1382 /* efsdiv */
1383 HELPER_SPE_SINGLE_ARITH(fsdiv);
1384
1385 #define HELPER_SPE_VECTOR_ARITH(name)                                   \
1386     uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1387     {                                                                   \
1388         return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) |   \
1389             (uint64_t)e##name(env, op1, op2);                           \
1390     }
1391 /* evfsadd */
1392 HELPER_SPE_VECTOR_ARITH(fsadd);
1393 /* evfssub */
1394 HELPER_SPE_VECTOR_ARITH(fssub);
1395 /* evfsmul */
1396 HELPER_SPE_VECTOR_ARITH(fsmul);
1397 /* evfsdiv */
1398 HELPER_SPE_VECTOR_ARITH(fsdiv);
1399
1400 /* Single-precision floating-point comparisons */
1401 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1402 {
1403     CPU_FloatU u1, u2;
1404
1405     u1.l = op1;
1406     u2.l = op2;
1407     return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1408 }
1409
1410 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1411 {
1412     CPU_FloatU u1, u2;
1413
1414     u1.l = op1;
1415     u2.l = op2;
1416     return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1417 }
1418
1419 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1420 {
1421     CPU_FloatU u1, u2;
1422
1423     u1.l = op1;
1424     u2.l = op2;
1425     return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1426 }
1427
1428 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1429 {
1430     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1431     return efscmplt(env, op1, op2);
1432 }
1433
1434 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1435 {
1436     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1437     return efscmpgt(env, op1, op2);
1438 }
1439
1440 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1441 {
1442     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1443     return efscmpeq(env, op1, op2);
1444 }
1445
1446 #define HELPER_SINGLE_SPE_CMP(name)                                     \
1447     uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1448     {                                                                   \
1449         return e##name(env, op1, op2) << 2;                             \
1450     }
1451 /* efststlt */
1452 HELPER_SINGLE_SPE_CMP(fststlt);
1453 /* efststgt */
1454 HELPER_SINGLE_SPE_CMP(fststgt);
1455 /* efststeq */
1456 HELPER_SINGLE_SPE_CMP(fststeq);
1457 /* efscmplt */
1458 HELPER_SINGLE_SPE_CMP(fscmplt);
1459 /* efscmpgt */
1460 HELPER_SINGLE_SPE_CMP(fscmpgt);
1461 /* efscmpeq */
1462 HELPER_SINGLE_SPE_CMP(fscmpeq);
1463
1464 static inline uint32_t evcmp_merge(int t0, int t1)
1465 {
1466     return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1467 }
1468
1469 #define HELPER_VECTOR_SPE_CMP(name)                                     \
1470     uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1471     {                                                                   \
1472         return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32),          \
1473                            e##name(env, op1, op2));                     \
1474     }
1475 /* evfststlt */
1476 HELPER_VECTOR_SPE_CMP(fststlt);
1477 /* evfststgt */
1478 HELPER_VECTOR_SPE_CMP(fststgt);
1479 /* evfststeq */
1480 HELPER_VECTOR_SPE_CMP(fststeq);
1481 /* evfscmplt */
1482 HELPER_VECTOR_SPE_CMP(fscmplt);
1483 /* evfscmpgt */
1484 HELPER_VECTOR_SPE_CMP(fscmpgt);
1485 /* evfscmpeq */
1486 HELPER_VECTOR_SPE_CMP(fscmpeq);
1487
1488 /* Double-precision floating-point conversion */
1489 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1490 {
1491     CPU_DoubleU u;
1492
1493     u.d = int32_to_float64(val, &env->vec_status);
1494
1495     return u.ll;
1496 }
1497
1498 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1499 {
1500     CPU_DoubleU u;
1501
1502     u.d = int64_to_float64(val, &env->vec_status);
1503
1504     return u.ll;
1505 }
1506
1507 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1508 {
1509     CPU_DoubleU u;
1510
1511     u.d = uint32_to_float64(val, &env->vec_status);
1512
1513     return u.ll;
1514 }
1515
1516 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1517 {
1518     CPU_DoubleU u;
1519
1520     u.d = uint64_to_float64(val, &env->vec_status);
1521
1522     return u.ll;
1523 }
1524
1525 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1526 {
1527     CPU_DoubleU u;
1528
1529     u.ll = val;
1530     /* NaN are not treated the same way IEEE 754 does */
1531     if (unlikely(float64_is_any_nan(u.d))) {
1532         return 0;
1533     }
1534
1535     return float64_to_int32(u.d, &env->vec_status);
1536 }
1537
1538 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1539 {
1540     CPU_DoubleU u;
1541
1542     u.ll = val;
1543     /* NaN are not treated the same way IEEE 754 does */
1544     if (unlikely(float64_is_any_nan(u.d))) {
1545         return 0;
1546     }
1547
1548     return float64_to_uint32(u.d, &env->vec_status);
1549 }
1550
1551 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1552 {
1553     CPU_DoubleU u;
1554
1555     u.ll = val;
1556     /* NaN are not treated the same way IEEE 754 does */
1557     if (unlikely(float64_is_any_nan(u.d))) {
1558         return 0;
1559     }
1560
1561     return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1562 }
1563
1564 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1565 {
1566     CPU_DoubleU u;
1567
1568     u.ll = val;
1569     /* NaN are not treated the same way IEEE 754 does */
1570     if (unlikely(float64_is_any_nan(u.d))) {
1571         return 0;
1572     }
1573
1574     return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1575 }
1576
1577 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1578 {
1579     CPU_DoubleU u;
1580
1581     u.ll = val;
1582     /* NaN are not treated the same way IEEE 754 does */
1583     if (unlikely(float64_is_any_nan(u.d))) {
1584         return 0;
1585     }
1586
1587     return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1588 }
1589
1590 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1591 {
1592     CPU_DoubleU u;
1593
1594     u.ll = val;
1595     /* NaN are not treated the same way IEEE 754 does */
1596     if (unlikely(float64_is_any_nan(u.d))) {
1597         return 0;
1598     }
1599
1600     return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1601 }
1602
1603 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1604 {
1605     CPU_DoubleU u;
1606     float64 tmp;
1607
1608     u.d = int32_to_float64(val, &env->vec_status);
1609     tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1610     u.d = float64_div(u.d, tmp, &env->vec_status);
1611
1612     return u.ll;
1613 }
1614
1615 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1616 {
1617     CPU_DoubleU u;
1618     float64 tmp;
1619
1620     u.d = uint32_to_float64(val, &env->vec_status);
1621     tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1622     u.d = float64_div(u.d, tmp, &env->vec_status);
1623
1624     return u.ll;
1625 }
1626
1627 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1628 {
1629     CPU_DoubleU u;
1630     float64 tmp;
1631
1632     u.ll = val;
1633     /* NaN are not treated the same way IEEE 754 does */
1634     if (unlikely(float64_is_any_nan(u.d))) {
1635         return 0;
1636     }
1637     tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1638     u.d = float64_mul(u.d, tmp, &env->vec_status);
1639
1640     return float64_to_int32(u.d, &env->vec_status);
1641 }
1642
1643 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1644 {
1645     CPU_DoubleU u;
1646     float64 tmp;
1647
1648     u.ll = val;
1649     /* NaN are not treated the same way IEEE 754 does */
1650     if (unlikely(float64_is_any_nan(u.d))) {
1651         return 0;
1652     }
1653     tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1654     u.d = float64_mul(u.d, tmp, &env->vec_status);
1655
1656     return float64_to_uint32(u.d, &env->vec_status);
1657 }
1658
1659 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1660 {
1661     CPU_DoubleU u1;
1662     CPU_FloatU u2;
1663
1664     u1.ll = val;
1665     u2.f = float64_to_float32(u1.d, &env->vec_status);
1666
1667     return u2.l;
1668 }
1669
1670 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1671 {
1672     CPU_DoubleU u2;
1673     CPU_FloatU u1;
1674
1675     u1.l = val;
1676     u2.d = float32_to_float64(u1.f, &env->vec_status);
1677
1678     return u2.ll;
1679 }
1680
1681 /* Double precision fixed-point arithmetic */
1682 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1683 {
1684     CPU_DoubleU u1, u2;
1685
1686     u1.ll = op1;
1687     u2.ll = op2;
1688     u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1689     return u1.ll;
1690 }
1691
1692 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1693 {
1694     CPU_DoubleU u1, u2;
1695
1696     u1.ll = op1;
1697     u2.ll = op2;
1698     u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1699     return u1.ll;
1700 }
1701
1702 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1703 {
1704     CPU_DoubleU u1, u2;
1705
1706     u1.ll = op1;
1707     u2.ll = op2;
1708     u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1709     return u1.ll;
1710 }
1711
1712 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1713 {
1714     CPU_DoubleU u1, u2;
1715
1716     u1.ll = op1;
1717     u2.ll = op2;
1718     u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1719     return u1.ll;
1720 }
1721
1722 /* Double precision floating point helpers */
1723 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1724 {
1725     CPU_DoubleU u1, u2;
1726
1727     u1.ll = op1;
1728     u2.ll = op2;
1729     return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1730 }
1731
1732 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1733 {
1734     CPU_DoubleU u1, u2;
1735
1736     u1.ll = op1;
1737     u2.ll = op2;
1738     return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1739 }
1740
1741 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1742 {
1743     CPU_DoubleU u1, u2;
1744
1745     u1.ll = op1;
1746     u2.ll = op2;
1747     return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1748 }
1749
1750 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1751 {
1752     /* XXX: TODO: test special values (NaN, infinites, ...) */
1753     return helper_efdtstlt(env, op1, op2);
1754 }
1755
1756 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1757 {
1758     /* XXX: TODO: test special values (NaN, infinites, ...) */
1759     return helper_efdtstgt(env, op1, op2);
1760 }
1761
1762 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1763 {
1764     /* XXX: TODO: test special values (NaN, infinites, ...) */
1765     return helper_efdtsteq(env, op1, op2);
1766 }
1767
1768 #define DECODE_SPLIT(opcode, shift1, nb1, shift2, nb2) \
1769     (((((opcode) >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |    \
1770      (((opcode) >> (shift2)) & ((1 << (nb2)) - 1)))
1771
1772 #define xT(opcode) DECODE_SPLIT(opcode, 0, 1, 21, 5)
1773 #define xA(opcode) DECODE_SPLIT(opcode, 2, 1, 16, 5)
1774 #define xB(opcode) DECODE_SPLIT(opcode, 1, 1, 11, 5)
1775 #define xC(opcode) DECODE_SPLIT(opcode, 3, 1,  6, 5)
1776 #define BF(opcode) (((opcode) >> (31-8)) & 7)
1777
1778 typedef union _ppc_vsr_t {
1779     uint64_t u64[2];
1780     uint32_t u32[4];
1781     float32 f32[4];
1782     float64 f64[2];
1783 } ppc_vsr_t;
1784
1785 #if defined(HOST_WORDS_BIGENDIAN)
1786 #define VsrW(i) u32[i]
1787 #define VsrD(i) u64[i]
1788 #else
1789 #define VsrW(i) u32[3-(i)]
1790 #define VsrD(i) u64[1-(i)]
1791 #endif
1792
1793 static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
1794 {
1795     if (n < 32) {
1796         vsr->VsrD(0) = env->fpr[n];
1797         vsr->VsrD(1) = env->vsr[n];
1798     } else {
1799         vsr->u64[0] = env->avr[n-32].u64[0];
1800         vsr->u64[1] = env->avr[n-32].u64[1];
1801     }
1802 }
1803
1804 static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
1805 {
1806     if (n < 32) {
1807         env->fpr[n] = vsr->VsrD(0);
1808         env->vsr[n] = vsr->VsrD(1);
1809     } else {
1810         env->avr[n-32].u64[0] = vsr->u64[0];
1811         env->avr[n-32].u64[1] = vsr->u64[1];
1812     }
1813 }
1814
1815 #define float64_to_float64(x, env) x
1816
1817
1818 /* VSX_ADD_SUB - VSX floating point add/subract
1819  *   name  - instruction mnemonic
1820  *   op    - operation (add or sub)
1821  *   nels  - number of elements (1, 2 or 4)
1822  *   tp    - type (float32 or float64)
1823  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1824  *   sfprf - set FPRF
1825  */
1826 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp)                    \
1827 void helper_##name(CPUPPCState *env, uint32_t opcode)                        \
1828 {                                                                            \
1829     ppc_vsr_t xt, xa, xb;                                                    \
1830     int i;                                                                   \
1831                                                                              \
1832     getVSR(xA(opcode), &xa, env);                                            \
1833     getVSR(xB(opcode), &xb, env);                                            \
1834     getVSR(xT(opcode), &xt, env);                                            \
1835     helper_reset_fpstatus(env);                                              \
1836                                                                              \
1837     for (i = 0; i < nels; i++) {                                             \
1838         float_status tstat = env->fp_status;                                 \
1839         set_float_exception_flags(0, &tstat);                                \
1840         xt.fld = tp##_##op(xa.fld, xb.fld, &tstat);                          \
1841         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1842                                                                              \
1843         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
1844             if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) {      \
1845                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf);    \
1846             } else if (tp##_is_signaling_nan(xa.fld) ||                      \
1847                        tp##_is_signaling_nan(xb.fld)) {                      \
1848                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
1849             }                                                                \
1850         }                                                                    \
1851                                                                              \
1852         if (r2sp) {                                                          \
1853             xt.fld = helper_frsp(env, xt.fld);                               \
1854         }                                                                    \
1855                                                                              \
1856         if (sfprf) {                                                         \
1857             helper_compute_fprf(env, xt.fld, sfprf);                         \
1858         }                                                                    \
1859     }                                                                        \
1860     putVSR(xT(opcode), &xt, env);                                            \
1861     helper_float_check_status(env);                                          \
1862 }
1863
1864 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1865 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1866 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1867 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1868 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1869 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1870 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1871 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1872
1873 /* VSX_MUL - VSX floating point multiply
1874  *   op    - instruction mnemonic
1875  *   nels  - number of elements (1, 2 or 4)
1876  *   tp    - type (float32 or float64)
1877  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1878  *   sfprf - set FPRF
1879  */
1880 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp)                              \
1881 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
1882 {                                                                            \
1883     ppc_vsr_t xt, xa, xb;                                                    \
1884     int i;                                                                   \
1885                                                                              \
1886     getVSR(xA(opcode), &xa, env);                                            \
1887     getVSR(xB(opcode), &xb, env);                                            \
1888     getVSR(xT(opcode), &xt, env);                                            \
1889     helper_reset_fpstatus(env);                                              \
1890                                                                              \
1891     for (i = 0; i < nels; i++) {                                             \
1892         float_status tstat = env->fp_status;                                 \
1893         set_float_exception_flags(0, &tstat);                                \
1894         xt.fld = tp##_mul(xa.fld, xb.fld, &tstat);                           \
1895         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1896                                                                              \
1897         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
1898             if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) ||        \
1899                 (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) {        \
1900                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf);    \
1901             } else if (tp##_is_signaling_nan(xa.fld) ||                      \
1902                        tp##_is_signaling_nan(xb.fld)) {                      \
1903                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
1904             }                                                                \
1905         }                                                                    \
1906                                                                              \
1907         if (r2sp) {                                                          \
1908             xt.fld = helper_frsp(env, xt.fld);                               \
1909         }                                                                    \
1910                                                                              \
1911         if (sfprf) {                                                         \
1912             helper_compute_fprf(env, xt.fld, sfprf);                         \
1913         }                                                                    \
1914     }                                                                        \
1915                                                                              \
1916     putVSR(xT(opcode), &xt, env);                                            \
1917     helper_float_check_status(env);                                          \
1918 }
1919
1920 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1921 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1922 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1923 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1924
1925 /* VSX_DIV - VSX floating point divide
1926  *   op    - instruction mnemonic
1927  *   nels  - number of elements (1, 2 or 4)
1928  *   tp    - type (float32 or float64)
1929  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1930  *   sfprf - set FPRF
1931  */
1932 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp)                               \
1933 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
1934 {                                                                             \
1935     ppc_vsr_t xt, xa, xb;                                                     \
1936     int i;                                                                    \
1937                                                                               \
1938     getVSR(xA(opcode), &xa, env);                                             \
1939     getVSR(xB(opcode), &xb, env);                                             \
1940     getVSR(xT(opcode), &xt, env);                                             \
1941     helper_reset_fpstatus(env);                                               \
1942                                                                               \
1943     for (i = 0; i < nels; i++) {                                              \
1944         float_status tstat = env->fp_status;                                  \
1945         set_float_exception_flags(0, &tstat);                                 \
1946         xt.fld = tp##_div(xa.fld, xb.fld, &tstat);                            \
1947         env->fp_status.float_exception_flags |= tstat.float_exception_flags;  \
1948                                                                               \
1949         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {     \
1950             if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) {       \
1951                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf);     \
1952             } else if (tp##_is_zero(xa.fld) &&                                \
1953                 tp##_is_zero(xb.fld)) {                                       \
1954                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf);     \
1955             } else if (tp##_is_signaling_nan(xa.fld) ||                       \
1956                 tp##_is_signaling_nan(xb.fld)) {                              \
1957                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
1958             }                                                                 \
1959         }                                                                     \
1960                                                                               \
1961         if (r2sp) {                                                           \
1962             xt.fld = helper_frsp(env, xt.fld);                                \
1963         }                                                                     \
1964                                                                               \
1965         if (sfprf) {                                                          \
1966             helper_compute_fprf(env, xt.fld, sfprf);                          \
1967         }                                                                     \
1968     }                                                                         \
1969                                                                               \
1970     putVSR(xT(opcode), &xt, env);                                             \
1971     helper_float_check_status(env);                                           \
1972 }
1973
1974 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1975 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
1976 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
1977 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
1978
1979 /* VSX_RE  - VSX floating point reciprocal estimate
1980  *   op    - instruction mnemonic
1981  *   nels  - number of elements (1, 2 or 4)
1982  *   tp    - type (float32 or float64)
1983  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1984  *   sfprf - set FPRF
1985  */
1986 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp)                                \
1987 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
1988 {                                                                             \
1989     ppc_vsr_t xt, xb;                                                         \
1990     int i;                                                                    \
1991                                                                               \
1992     getVSR(xB(opcode), &xb, env);                                             \
1993     getVSR(xT(opcode), &xt, env);                                             \
1994     helper_reset_fpstatus(env);                                               \
1995                                                                               \
1996     for (i = 0; i < nels; i++) {                                              \
1997         if (unlikely(tp##_is_signaling_nan(xb.fld))) {                        \
1998                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
1999         }                                                                     \
2000         xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status);                 \
2001                                                                               \
2002         if (r2sp) {                                                           \
2003             xt.fld = helper_frsp(env, xt.fld);                                \
2004         }                                                                     \
2005                                                                               \
2006         if (sfprf) {                                                          \
2007             helper_compute_fprf(env, xt.fld, sfprf);                          \
2008         }                                                                     \
2009     }                                                                         \
2010                                                                               \
2011     putVSR(xT(opcode), &xt, env);                                             \
2012     helper_float_check_status(env);                                           \
2013 }
2014
2015 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
2016 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
2017 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
2018 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
2019
2020 /* VSX_SQRT - VSX floating point square root
2021  *   op    - instruction mnemonic
2022  *   nels  - number of elements (1, 2 or 4)
2023  *   tp    - type (float32 or float64)
2024  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2025  *   sfprf - set FPRF
2026  */
2027 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp)                             \
2028 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2029 {                                                                            \
2030     ppc_vsr_t xt, xb;                                                        \
2031     int i;                                                                   \
2032                                                                              \
2033     getVSR(xB(opcode), &xb, env);                                            \
2034     getVSR(xT(opcode), &xt, env);                                            \
2035     helper_reset_fpstatus(env);                                              \
2036                                                                              \
2037     for (i = 0; i < nels; i++) {                                             \
2038         float_status tstat = env->fp_status;                                 \
2039         set_float_exception_flags(0, &tstat);                                \
2040         xt.fld = tp##_sqrt(xb.fld, &tstat);                                  \
2041         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2042                                                                              \
2043         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
2044             if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) {              \
2045                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf);   \
2046             } else if (tp##_is_signaling_nan(xb.fld)) {                      \
2047                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
2048             }                                                                \
2049         }                                                                    \
2050                                                                              \
2051         if (r2sp) {                                                          \
2052             xt.fld = helper_frsp(env, xt.fld);                               \
2053         }                                                                    \
2054                                                                              \
2055         if (sfprf) {                                                         \
2056             helper_compute_fprf(env, xt.fld, sfprf);                         \
2057         }                                                                    \
2058     }                                                                        \
2059                                                                              \
2060     putVSR(xT(opcode), &xt, env);                                            \
2061     helper_float_check_status(env);                                          \
2062 }
2063
2064 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
2065 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
2066 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
2067 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
2068
2069 /* VSX_RSQRTE - VSX floating point reciprocal square root estimate
2070  *   op    - instruction mnemonic
2071  *   nels  - number of elements (1, 2 or 4)
2072  *   tp    - type (float32 or float64)
2073  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2074  *   sfprf - set FPRF
2075  */
2076 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp)                           \
2077 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2078 {                                                                            \
2079     ppc_vsr_t xt, xb;                                                        \
2080     int i;                                                                   \
2081                                                                              \
2082     getVSR(xB(opcode), &xb, env);                                            \
2083     getVSR(xT(opcode), &xt, env);                                            \
2084     helper_reset_fpstatus(env);                                              \
2085                                                                              \
2086     for (i = 0; i < nels; i++) {                                             \
2087         float_status tstat = env->fp_status;                                 \
2088         set_float_exception_flags(0, &tstat);                                \
2089         xt.fld = tp##_sqrt(xb.fld, &tstat);                                  \
2090         xt.fld = tp##_div(tp##_one, xt.fld, &tstat);                         \
2091         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2092                                                                              \
2093         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
2094             if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) {              \
2095                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf);   \
2096             } else if (tp##_is_signaling_nan(xb.fld)) {                      \
2097                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
2098             }                                                                \
2099         }                                                                    \
2100                                                                              \
2101         if (r2sp) {                                                          \
2102             xt.fld = helper_frsp(env, xt.fld);                               \
2103         }                                                                    \
2104                                                                              \
2105         if (sfprf) {                                                         \
2106             helper_compute_fprf(env, xt.fld, sfprf);                         \
2107         }                                                                    \
2108     }                                                                        \
2109                                                                              \
2110     putVSR(xT(opcode), &xt, env);                                            \
2111     helper_float_check_status(env);                                          \
2112 }
2113
2114 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
2115 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
2116 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
2117 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
2118
2119 /* VSX_TDIV - VSX floating point test for divide
2120  *   op    - instruction mnemonic
2121  *   nels  - number of elements (1, 2 or 4)
2122  *   tp    - type (float32 or float64)
2123  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2124  *   emin  - minimum unbiased exponent
2125  *   emax  - maximum unbiased exponent
2126  *   nbits - number of fraction bits
2127  */
2128 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits)                  \
2129 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2130 {                                                                       \
2131     ppc_vsr_t xa, xb;                                                   \
2132     int i;                                                              \
2133     int fe_flag = 0;                                                    \
2134     int fg_flag = 0;                                                    \
2135                                                                         \
2136     getVSR(xA(opcode), &xa, env);                                       \
2137     getVSR(xB(opcode), &xb, env);                                       \
2138                                                                         \
2139     for (i = 0; i < nels; i++) {                                        \
2140         if (unlikely(tp##_is_infinity(xa.fld) ||                        \
2141                      tp##_is_infinity(xb.fld) ||                        \
2142                      tp##_is_zero(xb.fld))) {                           \
2143             fe_flag = 1;                                                \
2144             fg_flag = 1;                                                \
2145         } else {                                                        \
2146             int e_a = ppc_##tp##_get_unbiased_exp(xa.fld);              \
2147             int e_b = ppc_##tp##_get_unbiased_exp(xb.fld);              \
2148                                                                         \
2149             if (unlikely(tp##_is_any_nan(xa.fld) ||                     \
2150                          tp##_is_any_nan(xb.fld))) {                    \
2151                 fe_flag = 1;                                            \
2152             } else if ((e_b <= emin) || (e_b >= (emax-2))) {            \
2153                 fe_flag = 1;                                            \
2154             } else if (!tp##_is_zero(xa.fld) &&                         \
2155                        (((e_a - e_b) >= emax) ||                        \
2156                         ((e_a - e_b) <= (emin+1)) ||                    \
2157                          (e_a <= (emin+nbits)))) {                      \
2158                 fe_flag = 1;                                            \
2159             }                                                           \
2160                                                                         \
2161             if (unlikely(tp##_is_zero_or_denormal(xb.fld))) {           \
2162                 /* XB is not zero because of the above check and */     \
2163                 /* so must be denormalized.                      */     \
2164                 fg_flag = 1;                                            \
2165             }                                                           \
2166         }                                                               \
2167     }                                                                   \
2168                                                                         \
2169     env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2170 }
2171
2172 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2173 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2174 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2175
2176 /* VSX_TSQRT - VSX floating point test for square root
2177  *   op    - instruction mnemonic
2178  *   nels  - number of elements (1, 2 or 4)
2179  *   tp    - type (float32 or float64)
2180  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2181  *   emin  - minimum unbiased exponent
2182  *   emax  - maximum unbiased exponent
2183  *   nbits - number of fraction bits
2184  */
2185 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits)                       \
2186 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2187 {                                                                       \
2188     ppc_vsr_t xa, xb;                                                   \
2189     int i;                                                              \
2190     int fe_flag = 0;                                                    \
2191     int fg_flag = 0;                                                    \
2192                                                                         \
2193     getVSR(xA(opcode), &xa, env);                                       \
2194     getVSR(xB(opcode), &xb, env);                                       \
2195                                                                         \
2196     for (i = 0; i < nels; i++) {                                        \
2197         if (unlikely(tp##_is_infinity(xb.fld) ||                        \
2198                      tp##_is_zero(xb.fld))) {                           \
2199             fe_flag = 1;                                                \
2200             fg_flag = 1;                                                \
2201         } else {                                                        \
2202             int e_b = ppc_##tp##_get_unbiased_exp(xb.fld);              \
2203                                                                         \
2204             if (unlikely(tp##_is_any_nan(xb.fld))) {                    \
2205                 fe_flag = 1;                                            \
2206             } else if (unlikely(tp##_is_zero(xb.fld))) {                \
2207                 fe_flag = 1;                                            \
2208             } else if (unlikely(tp##_is_neg(xb.fld))) {                 \
2209                 fe_flag = 1;                                            \
2210             } else if (!tp##_is_zero(xb.fld) &&                         \
2211                       (e_b <= (emin+nbits))) {                          \
2212                 fe_flag = 1;                                            \
2213             }                                                           \
2214                                                                         \
2215             if (unlikely(tp##_is_zero_or_denormal(xb.fld))) {           \
2216                 /* XB is not zero because of the above check and */     \
2217                 /* therefore must be denormalized.               */     \
2218                 fg_flag = 1;                                            \
2219             }                                                           \
2220         }                                                               \
2221     }                                                                   \
2222                                                                         \
2223     env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2224 }
2225
2226 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2227 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2228 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2229
2230 /* VSX_MADD - VSX floating point muliply/add variations
2231  *   op    - instruction mnemonic
2232  *   nels  - number of elements (1, 2 or 4)
2233  *   tp    - type (float32 or float64)
2234  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2235  *   maddflgs - flags for the float*muladd routine that control the
2236  *           various forms (madd, msub, nmadd, nmsub)
2237  *   afrm  - A form (1=A, 0=M)
2238  *   sfprf - set FPRF
2239  */
2240 #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp)              \
2241 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
2242 {                                                                             \
2243     ppc_vsr_t xt_in, xa, xb, xt_out;                                          \
2244     ppc_vsr_t *b, *c;                                                         \
2245     int i;                                                                    \
2246                                                                               \
2247     if (afrm) { /* AxB + T */                                                 \
2248         b = &xb;                                                              \
2249         c = &xt_in;                                                           \
2250     } else { /* AxT + B */                                                    \
2251         b = &xt_in;                                                           \
2252         c = &xb;                                                              \
2253     }                                                                         \
2254                                                                               \
2255     getVSR(xA(opcode), &xa, env);                                             \
2256     getVSR(xB(opcode), &xb, env);                                             \
2257     getVSR(xT(opcode), &xt_in, env);                                          \
2258                                                                               \
2259     xt_out = xt_in;                                                           \
2260                                                                               \
2261     helper_reset_fpstatus(env);                                               \
2262                                                                               \
2263     for (i = 0; i < nels; i++) {                                              \
2264         float_status tstat = env->fp_status;                                  \
2265         set_float_exception_flags(0, &tstat);                                 \
2266         if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2267             /* Avoid double rounding errors by rounding the intermediate */   \
2268             /* result to odd.                                            */   \
2269             set_float_rounding_mode(float_round_to_zero, &tstat);             \
2270             xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld,                  \
2271                                        maddflgs, &tstat);                     \
2272             xt_out.fld |= (get_float_exception_flags(&tstat) &                \
2273                               float_flag_inexact) != 0;                       \
2274         } else {                                                              \
2275             xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld,                  \
2276                                         maddflgs, &tstat);                    \
2277         }                                                                     \
2278         env->fp_status.float_exception_flags |= tstat.float_exception_flags;  \
2279                                                                               \
2280         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {     \
2281             if (tp##_is_signaling_nan(xa.fld) ||                              \
2282                 tp##_is_signaling_nan(b->fld) ||                              \
2283                 tp##_is_signaling_nan(c->fld)) {                              \
2284                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
2285                 tstat.float_exception_flags &= ~float_flag_invalid;           \
2286             }                                                                 \
2287             if ((tp##_is_infinity(xa.fld) && tp##_is_zero(b->fld)) ||         \
2288                 (tp##_is_zero(xa.fld) && tp##_is_infinity(b->fld))) {         \
2289                 xt_out.fld = float64_to_##tp(fload_invalid_op_excp(env,       \
2290                     POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status);          \
2291                 tstat.float_exception_flags &= ~float_flag_invalid;           \
2292             }                                                                 \
2293             if ((tstat.float_exception_flags & float_flag_invalid) &&         \
2294                 ((tp##_is_infinity(xa.fld) ||                                 \
2295                   tp##_is_infinity(b->fld)) &&                                \
2296                   tp##_is_infinity(c->fld))) {                                \
2297                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf);     \
2298             }                                                                 \
2299         }                                                                     \
2300                                                                               \
2301         if (r2sp) {                                                           \
2302             xt_out.fld = helper_frsp(env, xt_out.fld);                        \
2303         }                                                                     \
2304                                                                               \
2305         if (sfprf) {                                                          \
2306             helper_compute_fprf(env, xt_out.fld, sfprf);                      \
2307         }                                                                     \
2308     }                                                                         \
2309     putVSR(xT(opcode), &xt_out, env);                                         \
2310     helper_float_check_status(env);                                           \
2311 }
2312
2313 #define MADD_FLGS 0
2314 #define MSUB_FLGS float_muladd_negate_c
2315 #define NMADD_FLGS float_muladd_negate_result
2316 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
2317
2318 VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
2319 VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
2320 VSX_MADD(xsmsubadp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 0)
2321 VSX_MADD(xsmsubmdp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 0)
2322 VSX_MADD(xsnmaddadp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 0)
2323 VSX_MADD(xsnmaddmdp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 0)
2324 VSX_MADD(xsnmsubadp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 0)
2325 VSX_MADD(xsnmsubmdp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 0)
2326
2327 VSX_MADD(xsmaddasp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 1)
2328 VSX_MADD(xsmaddmsp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 1)
2329 VSX_MADD(xsmsubasp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 1)
2330 VSX_MADD(xsmsubmsp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 1)
2331 VSX_MADD(xsnmaddasp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 1)
2332 VSX_MADD(xsnmaddmsp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 1)
2333 VSX_MADD(xsnmsubasp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 1)
2334 VSX_MADD(xsnmsubmsp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 1)
2335
2336 VSX_MADD(xvmaddadp, 2, float64, VsrD(i), MADD_FLGS, 1, 0, 0)
2337 VSX_MADD(xvmaddmdp, 2, float64, VsrD(i), MADD_FLGS, 0, 0, 0)
2338 VSX_MADD(xvmsubadp, 2, float64, VsrD(i), MSUB_FLGS, 1, 0, 0)
2339 VSX_MADD(xvmsubmdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0, 0)
2340 VSX_MADD(xvnmaddadp, 2, float64, VsrD(i), NMADD_FLGS, 1, 0, 0)
2341 VSX_MADD(xvnmaddmdp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0, 0)
2342 VSX_MADD(xvnmsubadp, 2, float64, VsrD(i), NMSUB_FLGS, 1, 0, 0)
2343 VSX_MADD(xvnmsubmdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0, 0)
2344
2345 VSX_MADD(xvmaddasp, 4, float32, VsrW(i), MADD_FLGS, 1, 0, 0)
2346 VSX_MADD(xvmaddmsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0, 0)
2347 VSX_MADD(xvmsubasp, 4, float32, VsrW(i), MSUB_FLGS, 1, 0, 0)
2348 VSX_MADD(xvmsubmsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0, 0)
2349 VSX_MADD(xvnmaddasp, 4, float32, VsrW(i), NMADD_FLGS, 1, 0, 0)
2350 VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0)
2351 VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0)
2352 VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0)
2353
2354 #define VSX_SCALAR_CMP(op, ordered)                                      \
2355 void helper_##op(CPUPPCState *env, uint32_t opcode)                      \
2356 {                                                                        \
2357     ppc_vsr_t xa, xb;                                                    \
2358     uint32_t cc = 0;                                                     \
2359                                                                          \
2360     getVSR(xA(opcode), &xa, env);                                        \
2361     getVSR(xB(opcode), &xb, env);                                        \
2362                                                                          \
2363     if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||                       \
2364                  float64_is_any_nan(xb.VsrD(0)))) {                      \
2365         if (float64_is_signaling_nan(xa.VsrD(0)) ||                      \
2366             float64_is_signaling_nan(xb.VsrD(0))) {                      \
2367             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);       \
2368         }                                                                \
2369         if (ordered) {                                                   \
2370             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);         \
2371         }                                                                \
2372         cc = 1;                                                          \
2373     } else {                                                             \
2374         if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) {       \
2375             cc = 8;                                                      \
2376         } else if (!float64_le(xa.VsrD(0), xb.VsrD(0),                   \
2377                                &env->fp_status)) { \
2378             cc = 4;                                                      \
2379         } else {                                                         \
2380             cc = 2;                                                      \
2381         }                                                                \
2382     }                                                                    \
2383                                                                          \
2384     env->fpscr &= ~(0x0F << FPSCR_FPRF);                                 \
2385     env->fpscr |= cc << FPSCR_FPRF;                                      \
2386     env->crf[BF(opcode)] = cc;                                           \
2387                                                                          \
2388     helper_float_check_status(env);                                      \
2389 }
2390
2391 VSX_SCALAR_CMP(xscmpodp, 1)
2392 VSX_SCALAR_CMP(xscmpudp, 0)
2393
2394 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
2395 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
2396
2397 /* VSX_MAX_MIN - VSX floating point maximum/minimum
2398  *   name  - instruction mnemonic
2399  *   op    - operation (max or min)
2400  *   nels  - number of elements (1, 2 or 4)
2401  *   tp    - type (float32 or float64)
2402  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2403  */
2404 #define VSX_MAX_MIN(name, op, nels, tp, fld)                                  \
2405 void helper_##name(CPUPPCState *env, uint32_t opcode)                         \
2406 {                                                                             \
2407     ppc_vsr_t xt, xa, xb;                                                     \
2408     int i;                                                                    \
2409                                                                               \
2410     getVSR(xA(opcode), &xa, env);                                             \
2411     getVSR(xB(opcode), &xb, env);                                             \
2412     getVSR(xT(opcode), &xt, env);                                             \
2413                                                                               \
2414     for (i = 0; i < nels; i++) {                                              \
2415         xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status);                  \
2416         if (unlikely(tp##_is_signaling_nan(xa.fld) ||                         \
2417                      tp##_is_signaling_nan(xb.fld))) {                        \
2418             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);            \
2419         }                                                                     \
2420     }                                                                         \
2421                                                                               \
2422     putVSR(xT(opcode), &xt, env);                                             \
2423     helper_float_check_status(env);                                           \
2424 }
2425
2426 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2427 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2428 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2429 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2430 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2431 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2432
2433 /* VSX_CMP - VSX floating point compare
2434  *   op    - instruction mnemonic
2435  *   nels  - number of elements (1, 2 or 4)
2436  *   tp    - type (float32 or float64)
2437  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2438  *   cmp   - comparison operation
2439  *   svxvc - set VXVC bit
2440  */
2441 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc)                            \
2442 void helper_##op(CPUPPCState *env, uint32_t opcode)                       \
2443 {                                                                         \
2444     ppc_vsr_t xt, xa, xb;                                                 \
2445     int i;                                                                \
2446     int all_true = 1;                                                     \
2447     int all_false = 1;                                                    \
2448                                                                           \
2449     getVSR(xA(opcode), &xa, env);                                         \
2450     getVSR(xB(opcode), &xb, env);                                         \
2451     getVSR(xT(opcode), &xt, env);                                         \
2452                                                                           \
2453     for (i = 0; i < nels; i++) {                                          \
2454         if (unlikely(tp##_is_any_nan(xa.fld) ||                           \
2455                      tp##_is_any_nan(xb.fld))) {                          \
2456             if (tp##_is_signaling_nan(xa.fld) ||                          \
2457                 tp##_is_signaling_nan(xb.fld)) {                          \
2458                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);    \
2459             }                                                             \
2460             if (svxvc) {                                                  \
2461                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);      \
2462             }                                                             \
2463             xt.fld = 0;                                                   \
2464             all_true = 0;                                                 \
2465         } else {                                                          \
2466             if (tp##_##cmp(xb.fld, xa.fld, &env->fp_status) == 1) {       \
2467                 xt.fld = -1;                                              \
2468                 all_false = 0;                                            \
2469             } else {                                                      \
2470                 xt.fld = 0;                                               \
2471                 all_true = 0;                                             \
2472             }                                                             \
2473         }                                                                 \
2474     }                                                                     \
2475                                                                           \
2476     putVSR(xT(opcode), &xt, env);                                         \
2477     if ((opcode >> (31-21)) & 1) {                                        \
2478         env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0);       \
2479     }                                                                     \
2480     helper_float_check_status(env);                                       \
2481  }
2482
2483 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0)
2484 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1)
2485 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1)
2486 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0)
2487 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1)
2488 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1)
2489
2490 /* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2491  *   op    - instruction mnemonic
2492  *   nels  - number of elements (1, 2 or 4)
2493  *   stp   - source type (float32 or float64)
2494  *   ttp   - target type (float32 or float64)
2495  *   sfld  - source vsr_t field
2496  *   tfld  - target vsr_t field (f32 or f64)
2497  *   sfprf - set FPRF
2498  */
2499 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf)    \
2500 void helper_##op(CPUPPCState *env, uint32_t opcode)                \
2501 {                                                                  \
2502     ppc_vsr_t xt, xb;                                              \
2503     int i;                                                         \
2504                                                                    \
2505     getVSR(xB(opcode), &xb, env);                                  \
2506     getVSR(xT(opcode), &xt, env);                                  \
2507                                                                    \
2508     for (i = 0; i < nels; i++) {                                   \
2509         xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);        \
2510         if (unlikely(stp##_is_signaling_nan(xb.sfld))) {           \
2511             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2512             xt.tfld = ttp##_snan_to_qnan(xt.tfld);                 \
2513         }                                                          \
2514         if (sfprf) {                                               \
2515             helper_compute_fprf(env, ttp##_to_float64(xt.tfld,     \
2516                                 &env->fp_status), sfprf);          \
2517         }                                                          \
2518     }                                                              \
2519                                                                    \
2520     putVSR(xT(opcode), &xt, env);                                  \
2521     helper_float_check_status(env);                                \
2522 }
2523
2524 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2525 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2526 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
2527 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
2528
2529 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2530 {
2531     float_status tstat = env->fp_status;
2532     set_float_exception_flags(0, &tstat);
2533
2534     return (uint64_t)float64_to_float32(xb, &tstat) << 32;
2535 }
2536
2537 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2538 {
2539     float_status tstat = env->fp_status;
2540     set_float_exception_flags(0, &tstat);
2541
2542     return float32_to_float64(xb >> 32, &tstat);
2543 }
2544
2545 /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2546  *   op    - instruction mnemonic
2547  *   nels  - number of elements (1, 2 or 4)
2548  *   stp   - source type (float32 or float64)
2549  *   ttp   - target type (int32, uint32, int64 or uint64)
2550  *   sfld  - source vsr_t field
2551  *   tfld  - target vsr_t field
2552  *   rnan  - resulting NaN
2553  */
2554 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan)              \
2555 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2556 {                                                                            \
2557     ppc_vsr_t xt, xb;                                                        \
2558     int i;                                                                   \
2559                                                                              \
2560     getVSR(xB(opcode), &xb, env);                                            \
2561     getVSR(xT(opcode), &xt, env);                                            \
2562                                                                              \
2563     for (i = 0; i < nels; i++) {                                             \
2564         if (unlikely(stp##_is_any_nan(xb.sfld))) {                           \
2565             if (stp##_is_signaling_nan(xb.sfld)) {                           \
2566                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);       \
2567             }                                                                \
2568             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);            \
2569             xt.tfld = rnan;                                                  \
2570         } else {                                                             \
2571             xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld,                \
2572                           &env->fp_status);                                  \
2573             if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2574                 fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);        \
2575             }                                                                \
2576         }                                                                    \
2577     }                                                                        \
2578                                                                              \
2579     putVSR(xT(opcode), &xt, env);                                            \
2580     helper_float_check_status(env);                                          \
2581 }
2582
2583 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2584                   0x8000000000000000ULL)
2585 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2586                   0x80000000U)
2587 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2588 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2589 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
2590                   0x8000000000000000ULL)
2591 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2*i), \
2592                   0x80000000U)
2593 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
2594 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2*i), 0U)
2595 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2*i), VsrD(i), \
2596                   0x8000000000000000ULL)
2597 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
2598 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2*i), VsrD(i), 0ULL)
2599 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
2600
2601 /* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2602  *   op    - instruction mnemonic
2603  *   nels  - number of elements (1, 2 or 4)
2604  *   stp   - source type (int32, uint32, int64 or uint64)
2605  *   ttp   - target type (float32 or float64)
2606  *   sfld  - source vsr_t field
2607  *   tfld  - target vsr_t field
2608  *   jdef  - definition of the j index (i or 2*i)
2609  *   sfprf - set FPRF
2610  */
2611 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp)  \
2612 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2613 {                                                                       \
2614     ppc_vsr_t xt, xb;                                                   \
2615     int i;                                                              \
2616                                                                         \
2617     getVSR(xB(opcode), &xb, env);                                       \
2618     getVSR(xT(opcode), &xt, env);                                       \
2619                                                                         \
2620     for (i = 0; i < nels; i++) {                                        \
2621         xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);             \
2622         if (r2sp) {                                                     \
2623             xt.tfld = helper_frsp(env, xt.tfld);                        \
2624         }                                                               \
2625         if (sfprf) {                                                    \
2626             helper_compute_fprf(env, xt.tfld, sfprf);                   \
2627         }                                                               \
2628     }                                                                   \
2629                                                                         \
2630     putVSR(xT(opcode), &xt, env);                                       \
2631     helper_float_check_status(env);                                     \
2632 }
2633
2634 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2635 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
2636 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2637 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
2638 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2639 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
2640 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2*i), VsrD(i), 0, 0)
2641 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2*i), VsrD(i), 0, 0)
2642 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2*i), 0, 0)
2643 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2*i), 0, 0)
2644 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
2645 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
2646
2647 /* For "use current rounding mode", define a value that will not be one of
2648  * the existing rounding model enums.
2649  */
2650 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2651   float_round_up + float_round_to_zero)
2652
2653 /* VSX_ROUND - VSX floating point round
2654  *   op    - instruction mnemonic
2655  *   nels  - number of elements (1, 2 or 4)
2656  *   tp    - type (float32 or float64)
2657  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2658  *   rmode - rounding mode
2659  *   sfprf - set FPRF
2660  */
2661 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf)                     \
2662 void helper_##op(CPUPPCState *env, uint32_t opcode)                    \
2663 {                                                                      \
2664     ppc_vsr_t xt, xb;                                                  \
2665     int i;                                                             \
2666     getVSR(xB(opcode), &xb, env);                                      \
2667     getVSR(xT(opcode), &xt, env);                                      \
2668                                                                        \
2669     if (rmode != FLOAT_ROUND_CURRENT) {                                \
2670         set_float_rounding_mode(rmode, &env->fp_status);               \
2671     }                                                                  \
2672                                                                        \
2673     for (i = 0; i < nels; i++) {                                       \
2674         if (unlikely(tp##_is_signaling_nan(xb.fld))) {                 \
2675             fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);     \
2676             xt.fld = tp##_snan_to_qnan(xb.fld);                        \
2677         } else {                                                       \
2678             xt.fld = tp##_round_to_int(xb.fld, &env->fp_status);       \
2679         }                                                              \
2680         if (sfprf) {                                                   \
2681             helper_compute_fprf(env, xt.fld, sfprf);                   \
2682         }                                                              \
2683     }                                                                  \
2684                                                                        \
2685     /* If this is not a "use current rounding mode" instruction,       \
2686      * then inhibit setting of the XX bit and restore rounding         \
2687      * mode from FPSCR */                                              \
2688     if (rmode != FLOAT_ROUND_CURRENT) {                                \
2689         fpscr_set_rounding_mode(env);                                  \
2690         env->fp_status.float_exception_flags &= ~float_flag_inexact;   \
2691     }                                                                  \
2692                                                                        \
2693     putVSR(xT(opcode), &xt, env);                                      \
2694     helper_float_check_status(env);                                    \
2695 }
2696
2697 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_nearest_even, 1)
2698 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
2699 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
2700 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
2701 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
2702
2703 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_nearest_even, 0)
2704 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
2705 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
2706 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
2707 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
2708
2709 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_nearest_even, 0)
2710 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
2711 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
2712 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
2713 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
2714
2715 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
2716 {
2717     helper_reset_fpstatus(env);
2718
2719     uint64_t xt = helper_frsp(env, xb);
2720
2721     helper_compute_fprf(env, xt, 1);
2722     helper_float_check_status(env);
2723     return xt;
2724 }