hw/timer/hpet.c

   1 /*
   2  *  High Precision Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw/hw.h"
  28 #include "hw/i386/pc.h"
  29 #include "ui/console.h"
  30 #include "qemu/timer.h"
  31 #include "hw/timer/hpet.h"
  32 #include "hw/sysbus.h"
  33 #include "hw/timer/mc146818rtc.h"
  34 #include "hw/timer/i8254.h"
  35
  36 //#define HPET_DEBUG
  37 #ifdef HPET_DEBUG
  38 #define DPRINTF printf
  39 #else
  40 #define DPRINTF(...)
  41 #endif
  42
  43 #define HPET_MSI_SUPPORT        0
  44
  45 #define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET)
  46
  47 struct HPETState;
  48 typedef struct HPETTimer {  /* timers */
  49     uint8_t tn;             /*timer number*/
  50     QEMUTimer *qemu_timer;
  51     struct HPETState *state;
  52     /* Memory-mapped, software visible timer registers */
  53     uint64_t config;        /* configuration/cap */
  54     uint64_t cmp;           /* comparator */
  55     uint64_t fsb;           /* FSB route */
  56     /* Hidden register state */
  57     uint64_t period;        /* Last value written to comparator */
  58     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  59                              * mode. Next pop will be actual timer expiration.
  60                              */
  61 } HPETTimer;
  62
  63 typedef struct HPETState {
  64     /*< private >*/
  65     SysBusDevice parent_obj;
  66     /*< public >*/
  67
  68     MemoryRegion iomem;
  69     uint64_t hpet_offset;
  70     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  71     uint32_t flags;
  72     uint8_t rtc_irq_level;
  73     qemu_irq pit_enabled;
  74     uint8_t num_timers;
  75     uint32_t intcap;
  76     HPETTimer timer[HPET_MAX_TIMERS];
  77
  78     /* Memory-mapped, software visible registers */
  79     uint64_t capability;        /* capabilities */
  80     uint64_t config;            /* configuration */
  81     uint64_t isr;               /* interrupt status reg */
  82     uint64_t hpet_counter;      /* main counter */
  83     uint8_t  hpet_id;           /* instance id */
  84 } HPETState;
  85
  86 static uint32_t hpet_in_legacy_mode(HPETState *s)
  87 {
  88     return s->config & HPET_CFG_LEGACY;
  89 }
  90
  91 static uint32_t timer_int_route(struct HPETTimer *timer)
  92 {
  93     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  94 }
  95
  96 static uint32_t timer_fsb_route(HPETTimer *t)
  97 {
  98     return t->config & HPET_TN_FSB_ENABLE;
  99 }
 100
 101 static uint32_t hpet_enabled(HPETState *s)
 102 {
 103     return s->config & HPET_CFG_ENABLE;
 104 }
 105
 106 static uint32_t timer_is_periodic(HPETTimer *t)
 107 {
 108     return t->config & HPET_TN_PERIODIC;
 109 }
 110
 111 static uint32_t timer_enabled(HPETTimer *t)
 112 {
 113     return t->config & HPET_TN_ENABLE;
 114 }
 115
 116 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 117 {
 118     return ((int32_t)(b) - (int32_t)(a) < 0);
 119 }
 120
 121 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 122 {
 123     return ((int64_t)(b) - (int64_t)(a) < 0);
 124 }
 125
 126 static uint64_t ticks_to_ns(uint64_t value)
 127 {
 128     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 129 }
 130
 131 static uint64_t ns_to_ticks(uint64_t value)
 132 {
 133     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 134 }
 135
 136 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 137 {
 138     new &= mask;
 139     new |= old & ~mask;
 140     return new;
 141 }
 142
 143 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 144 {
 145     return (!(old & mask) && (new & mask));
 146 }
 147
 148 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 149 {
 150     return ((old & mask) && !(new & mask));
 151 }
 152
 153 static uint64_t hpet_get_ticks(HPETState *s)
 154 {
 155     return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hpet_offset);
 156 }
 157
 158 /*
 159  * calculate diff between comparator value and current ticks
 160  */
 161 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 162 {
 163
 164     if (t->config & HPET_TN_32BIT) {
 165         uint32_t diff, cmp;
 166
 167         cmp = (uint32_t)t->cmp;
 168         diff = cmp - (uint32_t)current;
 169         diff = (int32_t)diff > 0 ? diff : (uint32_t)1;
 170         return (uint64_t)diff;
 171     } else {
 172         uint64_t diff, cmp;
 173
 174         cmp = t->cmp;
 175         diff = cmp - current;
 176         diff = (int64_t)diff > 0 ? diff : (uint64_t)1;
 177         return diff;
 178     }
 179 }
 180
 181 static void update_irq(struct HPETTimer *timer, int set)
 182 {
 183     uint64_t mask;
 184     HPETState *s;
 185     int route;
 186
 187     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 188         /* if LegacyReplacementRoute bit is set, HPET specification requires
 189          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 190          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 191          */
 192         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 193     } else {
 194         route = timer_int_route(timer);
 195     }
 196     s = timer->state;
 197     mask = 1 << timer->tn;
 198     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 199         s->isr &= ~mask;
 200         if (!timer_fsb_route(timer)) {
 201             /* fold the ICH PIRQ# pin's internal inversion logic into hpet */
 202             if (route >= ISA_NUM_IRQS) {
 203                 qemu_irq_raise(s->irqs[route]);
 204             } else {
 205                 qemu_irq_lower(s->irqs[route]);
 206             }
 207         }
 208     } else if (timer_fsb_route(timer)) {
 209         address_space_stl_le(&address_space_memory, timer->fsb >> 32,
 210                              timer->fsb & 0xffffffff, MEMTXATTRS_UNSPECIFIED,
 211                              NULL);
 212     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 213         s->isr |= mask;
 214         /* fold the ICH PIRQ# pin's internal inversion logic into hpet */
 215         if (route >= ISA_NUM_IRQS) {
 216             qemu_irq_lower(s->irqs[route]);
 217         } else {
 218             qemu_irq_raise(s->irqs[route]);
 219         }
 220     } else {
 221         s->isr &= ~mask;
 222         qemu_irq_pulse(s->irqs[route]);
 223     }
 224 }
 225
 226 static void hpet_pre_save(void *opaque)
 227 {
 228     HPETState *s = opaque;
 229
 230     /* save current counter value */
 231     s->hpet_counter = hpet_get_ticks(s);
 232 }
 233
 234 static int hpet_pre_load(void *opaque)
 235 {
 236     HPETState *s = opaque;
 237
 238     /* version 1 only supports 3, later versions will load the actual value */
 239     s->num_timers = HPET_MIN_TIMERS;
 240     return 0;
 241 }
 242
 243 static bool hpet_validate_num_timers(void *opaque, int version_id)
 244 {
 245     HPETState *s = opaque;
 246
 247     if (s->num_timers < HPET_MIN_TIMERS) {
 248         return false;
 249     } else if (s->num_timers > HPET_MAX_TIMERS) {
 250         return false;
 251     }
 252     return true;
 253 }
 254
 255 static int hpet_post_load(void *opaque, int version_id)
 256 {
 257     HPETState *s = opaque;
 258
 259     /* Recalculate the offset between the main counter and guest time */
 260     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 261
 262     /* Push number of timers into capability returned via HPET_ID */
 263     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 264     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 265     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 266
 267     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 268     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 269     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 270         s->flags |= 1 << HPET_MSI_SUPPORT;
 271     }
 272     return 0;
 273 }
 274
 275 static bool hpet_rtc_irq_level_needed(void *opaque)
 276 {
 277     HPETState *s = opaque;
 278
 279     return s->rtc_irq_level != 0;
 280 }
 281
 282 static const VMStateDescription vmstate_hpet_rtc_irq_level = {
 283     .name = "hpet/rtc_irq_level",
 284     .version_id = 1,
 285     .minimum_version_id = 1,
 286     .needed = hpet_rtc_irq_level_needed,
 287     .fields = (VMStateField[]) {
 288         VMSTATE_UINT8(rtc_irq_level, HPETState),
 289         VMSTATE_END_OF_LIST()
 290     }
 291 };
 292
 293 static const VMStateDescription vmstate_hpet_timer = {
 294     .name = "hpet_timer",
 295     .version_id = 1,
 296     .minimum_version_id = 1,
 297     .fields = (VMStateField[]) {
 298         VMSTATE_UINT8(tn, HPETTimer),
 299         VMSTATE_UINT64(config, HPETTimer),
 300         VMSTATE_UINT64(cmp, HPETTimer),
 301         VMSTATE_UINT64(fsb, HPETTimer),
 302         VMSTATE_UINT64(period, HPETTimer),
 303         VMSTATE_UINT8(wrap_flag, HPETTimer),
 304         VMSTATE_TIMER_PTR(qemu_timer, HPETTimer),
 305         VMSTATE_END_OF_LIST()
 306     }
 307 };
 308
 309 static const VMStateDescription vmstate_hpet = {
 310     .name = "hpet",
 311     .version_id = 2,
 312     .minimum_version_id = 1,
 313     .pre_save = hpet_pre_save,
 314     .pre_load = hpet_pre_load,
 315     .post_load = hpet_post_load,
 316     .fields = (VMStateField[]) {
 317         VMSTATE_UINT64(config, HPETState),
 318         VMSTATE_UINT64(isr, HPETState),
 319         VMSTATE_UINT64(hpet_counter, HPETState),
 320         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 321         VMSTATE_VALIDATE("num_timers in range", hpet_validate_num_timers),
 322         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 323                                     vmstate_hpet_timer, HPETTimer),
 324         VMSTATE_END_OF_LIST()
 325     },
 326     .subsections = (const VMStateDescription*[]) {
 327         &vmstate_hpet_rtc_irq_level,
 328         NULL
 329     }
 330 };
 331
 332 /*
 333  * timer expiration callback
 334  */
 335 static void hpet_timer(void *opaque)
 336 {
 337     HPETTimer *t = opaque;
 338     uint64_t diff;
 339
 340     uint64_t period = t->period;
 341     uint64_t cur_tick = hpet_get_ticks(t->state);
 342
 343     if (timer_is_periodic(t) && period != 0) {
 344         if (t->config & HPET_TN_32BIT) {
 345             while (hpet_time_after(cur_tick, t->cmp)) {
 346                 t->cmp = (uint32_t)(t->cmp + t->period);
 347             }
 348         } else {
 349             while (hpet_time_after64(cur_tick, t->cmp)) {
 350                 t->cmp += period;
 351             }
 352         }
 353         diff = hpet_calculate_diff(t, cur_tick);
 354         timer_mod(t->qemu_timer,
 355                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
 356     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 357         if (t->wrap_flag) {
 358             diff = hpet_calculate_diff(t, cur_tick);
 359             timer_mod(t->qemu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 360                            (int64_t)ticks_to_ns(diff));
 361             t->wrap_flag = 0;
 362         }
 363     }
 364     update_irq(t, 1);
 365 }
 366
 367 static void hpet_set_timer(HPETTimer *t)
 368 {
 369     uint64_t diff;
 370     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 371     uint64_t cur_tick = hpet_get_ticks(t->state);
 372
 373     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 374     t->wrap_flag = 0;
 375     diff = hpet_calculate_diff(t, cur_tick);
 376
 377     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 378      * counter wraps in addition to an interrupt with comparator match.
 379      */
 380     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 381         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 382         if (wrap_diff < (uint32_t)diff) {
 383             diff = wrap_diff;
 384             t->wrap_flag = 1;
 385         }
 386     }
 387     timer_mod(t->qemu_timer,
 388                    qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
 389 }
 390
 391 static void hpet_del_timer(HPETTimer *t)
 392 {
 393     timer_del(t->qemu_timer);
 394     update_irq(t, 0);
 395 }
 396
 397 #ifdef HPET_DEBUG
 398 static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
 399 {
 400     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 401     return 0;
 402 }
 403
 404 static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
 405 {
 406     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 407     return 0;
 408 }
 409 #endif
 410
 411 static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
 412                               unsigned size)
 413 {
 414     HPETState *s = opaque;
 415     uint64_t cur_tick, index;
 416
 417     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 418     index = addr;
 419     /*address range of all TN regs*/
 420     if (index >= 0x100 && index <= 0x3ff) {
 421         uint8_t timer_id = (addr - 0x100) / 0x20;
 422         HPETTimer *timer = &s->timer[timer_id];
 423
 424         if (timer_id > s->num_timers) {
 425             DPRINTF("qemu: timer id out of range\n");
 426             return 0;
 427         }
 428
 429         switch ((addr - 0x100) % 0x20) {
 430         case HPET_TN_CFG:
 431             return timer->config;
 432         case HPET_TN_CFG + 4: // Interrupt capabilities
 433             return timer->config >> 32;
 434         case HPET_TN_CMP: // comparator register
 435             return timer->cmp;
 436         case HPET_TN_CMP + 4:
 437             return timer->cmp >> 32;
 438         case HPET_TN_ROUTE:
 439             return timer->fsb;
 440         case HPET_TN_ROUTE + 4:
 441             return timer->fsb >> 32;
 442         default:
 443             DPRINTF("qemu: invalid hpet_ram_readl\n");
 444             break;
 445         }
 446     } else {
 447         switch (index) {
 448         case HPET_ID:
 449             return s->capability;
 450         case HPET_PERIOD:
 451             return s->capability >> 32;
 452         case HPET_CFG:
 453             return s->config;
 454         case HPET_CFG + 4:
 455             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
 456             return 0;
 457         case HPET_COUNTER:
 458             if (hpet_enabled(s)) {
 459                 cur_tick = hpet_get_ticks(s);
 460             } else {
 461                 cur_tick = s->hpet_counter;
 462             }
 463             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 464             return cur_tick;
 465         case HPET_COUNTER + 4:
 466             if (hpet_enabled(s)) {
 467                 cur_tick = hpet_get_ticks(s);
 468             } else {
 469                 cur_tick = s->hpet_counter;
 470             }
 471             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 472             return cur_tick >> 32;
 473         case HPET_STATUS:
 474             return s->isr;
 475         default:
 476             DPRINTF("qemu: invalid hpet_ram_readl\n");
 477             break;
 478         }
 479     }
 480     return 0;
 481 }
 482
 483 static void hpet_ram_write(void *opaque, hwaddr addr,
 484                            uint64_t value, unsigned size)
 485 {
 486     int i;
 487     HPETState *s = opaque;
 488     uint64_t old_val, new_val, val, index;
 489
 490     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 491     index = addr;
 492     old_val = hpet_ram_read(opaque, addr, 4);
 493     new_val = value;
 494
 495     /*address range of all TN regs*/
 496     if (index >= 0x100 && index <= 0x3ff) {
 497         uint8_t timer_id = (addr - 0x100) / 0x20;
 498         HPETTimer *timer = &s->timer[timer_id];
 499
 500         DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
 501         if (timer_id > s->num_timers) {
 502             DPRINTF("qemu: timer id out of range\n");
 503             return;
 504         }
 505         switch ((addr - 0x100) % 0x20) {
 506         case HPET_TN_CFG:
 507             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 508             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 509                 update_irq(timer, 0);
 510             }
 511             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 512             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 513             if (new_val & HPET_TN_32BIT) {
 514                 timer->cmp = (uint32_t)timer->cmp;
 515                 timer->period = (uint32_t)timer->period;
 516             }
 517             if (activating_bit(old_val, new_val, HPET_TN_ENABLE) &&
 518                 hpet_enabled(s)) {
 519                 hpet_set_timer(timer);
 520             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 521                 hpet_del_timer(timer);
 522             }
 523             break;
 524         case HPET_TN_CFG + 4: // Interrupt capabilities
 525             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 526             break;
 527         case HPET_TN_CMP: // comparator register
 528             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
 529             if (timer->config & HPET_TN_32BIT) {
 530                 new_val = (uint32_t)new_val;
 531             }
 532             if (!timer_is_periodic(timer)
 533                 || (timer->config & HPET_TN_SETVAL)) {
 534                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 535             }
 536             if (timer_is_periodic(timer)) {
 537                 /*
 538                  * FIXME: Clamp period to reasonable min value?
 539                  * Clamp period to reasonable max value
 540                  */
 541                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 542                 timer->period =
 543                     (timer->period & 0xffffffff00000000ULL) | new_val;
 544             }
 545             timer->config &= ~HPET_TN_SETVAL;
 546             if (hpet_enabled(s)) {
 547                 hpet_set_timer(timer);
 548             }
 549             break;
 550         case HPET_TN_CMP + 4: // comparator register high order
 551             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 552             if (!timer_is_periodic(timer)
 553                 || (timer->config & HPET_TN_SETVAL)) {
 554                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 555             } else {
 556                 /*
 557                  * FIXME: Clamp period to reasonable min value?
 558                  * Clamp period to reasonable max value
 559                  */
 560                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 561                 timer->period =
 562                     (timer->period & 0xffffffffULL) | new_val << 32;
 563                 }
 564                 timer->config &= ~HPET_TN_SETVAL;
 565                 if (hpet_enabled(s)) {
 566                     hpet_set_timer(timer);
 567                 }
 568                 break;
 569         case HPET_TN_ROUTE:
 570             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 571             break;
 572         case HPET_TN_ROUTE + 4:
 573             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 574             break;
 575         default:
 576             DPRINTF("qemu: invalid hpet_ram_writel\n");
 577             break;
 578         }
 579         return;
 580     } else {
 581         switch (index) {
 582         case HPET_ID:
 583             return;
 584         case HPET_CFG:
 585             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 586             s->config = (s->config & 0xffffffff00000000ULL) | val;
 587             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 588                 /* Enable main counter and interrupt generation. */
 589                 s->hpet_offset =
 590                     ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 591                 for (i = 0; i < s->num_timers; i++) {
 592                     if ((&s->timer[i])->cmp != ~0ULL) {
 593                         hpet_set_timer(&s->timer[i]);
 594                     }
 595                 }
 596             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 597                 /* Halt main counter and disable interrupt generation. */
 598                 s->hpet_counter = hpet_get_ticks(s);
 599                 for (i = 0; i < s->num_timers; i++) {
 600                     hpet_del_timer(&s->timer[i]);
 601                 }
 602             }
 603             /* i8254 and RTC output pins are disabled
 604              * when HPET is in legacy mode */
 605             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 606                 qemu_set_irq(s->pit_enabled, 0);
 607                 qemu_irq_lower(s->irqs[0]);
 608                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 609             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 610                 qemu_irq_lower(s->irqs[0]);
 611                 qemu_set_irq(s->pit_enabled, 1);
 612                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 613             }
 614             break;
 615         case HPET_CFG + 4:
 616             DPRINTF("qemu: invalid HPET_CFG+4 write\n");
 617             break;
 618         case HPET_STATUS:
 619             val = new_val & s->isr;
 620             for (i = 0; i < s->num_timers; i++) {
 621                 if (val & (1 << i)) {
 622                     update_irq(&s->timer[i], 0);
 623                 }
 624             }
 625             break;
 626         case HPET_COUNTER:
 627             if (hpet_enabled(s)) {
 628                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 629             }
 630             s->hpet_counter =
 631                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 632             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 633                     value, s->hpet_counter);
 634             break;
 635         case HPET_COUNTER + 4:
 636             if (hpet_enabled(s)) {
 637                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 638             }
 639             s->hpet_counter =
 640                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 641             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 642                     value, s->hpet_counter);
 643             break;
 644         default:
 645             DPRINTF("qemu: invalid hpet_ram_writel\n");
 646             break;
 647         }
 648     }
 649 }
 650
 651 static const MemoryRegionOps hpet_ram_ops = {
 652     .read = hpet_ram_read,
 653     .write = hpet_ram_write,
 654     .valid = {
 655         .min_access_size = 4,
 656         .max_access_size = 4,
 657     },
 658     .endianness = DEVICE_NATIVE_ENDIAN,
 659 };
 660
 661 static void hpet_reset(DeviceState *d)
 662 {
 663     HPETState *s = HPET(d);
 664     SysBusDevice *sbd = SYS_BUS_DEVICE(d);
 665     int i;
 666
 667     for (i = 0; i < s->num_timers; i++) {
 668         HPETTimer *timer = &s->timer[i];
 669
 670         hpet_del_timer(timer);
 671         timer->cmp = ~0ULL;
 672         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 673         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 674             timer->config |= HPET_TN_FSB_CAP;
 675         }
 676         /* advertise availability of ioapic int */
 677         timer->config |=  (uint64_t)s->intcap << 32;
 678         timer->period = 0ULL;
 679         timer->wrap_flag = 0;
 680     }
 681
 682     qemu_set_irq(s->pit_enabled, 1);
 683     s->hpet_counter = 0ULL;
 684     s->hpet_offset = 0ULL;
 685     s->config = 0ULL;
 686     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 687     hpet_cfg.hpet[s->hpet_id].address = sbd->mmio[0].addr;
 688
 689     /* to document that the RTC lowers its output on reset as well */
 690     s->rtc_irq_level = 0;
 691 }
 692
 693 static void hpet_handle_legacy_irq(void *opaque, int n, int level)
 694 {
 695     HPETState *s = HPET(opaque);
 696
 697     if (n == HPET_LEGACY_PIT_INT) {
 698         if (!hpet_in_legacy_mode(s)) {
 699             qemu_set_irq(s->irqs[0], level);
 700         }
 701     } else {
 702         s->rtc_irq_level = level;
 703         if (!hpet_in_legacy_mode(s)) {
 704             qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 705         }
 706     }
 707 }
 708
 709 static void hpet_init(Object *obj)
 710 {
 711     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 712     HPETState *s = HPET(obj);
 713
 714     /* HPET Area */
 715     memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", 0x400);
 716     sysbus_init_mmio(sbd, &s->iomem);
 717 }
 718
 719 static void hpet_realize(DeviceState *dev, Error **errp)
 720 {
 721     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 722     HPETState *s = HPET(dev);
 723     int i;
 724     HPETTimer *timer;
 725
 726     if (!s->intcap) {
 727         error_printf("Hpet's intcap not initialized.\n");
 728     }
 729     if (hpet_cfg.count == UINT8_MAX) {
 730         /* first instance */
 731         hpet_cfg.count = 0;
 732     }
 733
 734     if (hpet_cfg.count == 8) {
 735         error_setg(errp, "Only 8 instances of HPET is allowed");
 736         return;
 737     }
 738
 739     s->hpet_id = hpet_cfg.count++;
 740
 741     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 742         sysbus_init_irq(sbd, &s->irqs[i]);
 743     }
 744
 745     if (s->num_timers < HPET_MIN_TIMERS) {
 746         s->num_timers = HPET_MIN_TIMERS;
 747     } else if (s->num_timers > HPET_MAX_TIMERS) {
 748         s->num_timers = HPET_MAX_TIMERS;
 749     }
 750     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 751         timer = &s->timer[i];
 752         timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);
 753         timer->tn = i;
 754         timer->state = s;
 755     }
 756
 757     /* 64-bit main counter; LegacyReplacementRoute. */
 758     s->capability = 0x8086a001ULL;
 759     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 760     s->capability |= ((HPET_CLK_PERIOD) << 32);
 761
 762     qdev_init_gpio_in(dev, hpet_handle_legacy_irq, 2);
 763     qdev_init_gpio_out(dev, &s->pit_enabled, 1);
 764 }
 765
 766 static Property hpet_device_properties[] = {
 767     DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 768     DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 769     DEFINE_PROP_UINT32(HPET_INTCAP, HPETState, intcap, 0),
 770     DEFINE_PROP_END_OF_LIST(),
 771 };
 772
 773 static void hpet_device_class_init(ObjectClass *klass, void *data)
 774 {
 775     DeviceClass *dc = DEVICE_CLASS(klass);
 776
 777     dc->realize = hpet_realize;
 778     dc->reset = hpet_reset;
 779     dc->vmsd = &vmstate_hpet;
 780     dc->props = hpet_device_properties;
 781 }
 782
 783 static const TypeInfo hpet_device_info = {
 784     .name          = TYPE_HPET,
 785     .parent        = TYPE_SYS_BUS_DEVICE,
 786     .instance_size = sizeof(HPETState),
 787     .instance_init = hpet_init,
 788     .class_init    = hpet_device_class_init,
 789 };
 790
 791 static void hpet_register_types(void)
 792 {
 793     type_register_static(&hpet_device_info);
 794 }
 795
 796 type_init(hpet_register_types)