2 * QEMU PowerMac emulation shared definitions and prototypes
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #if !defined(__PPC_MAC_H__)
28 /* SMP is not enabled, for now */
31 #define BIOS_SIZE (1024 * 1024)
32 #define BIOS_FILENAME "ppc_rom.bin"
33 #define NVRAM_SIZE 0x2000
34 #define PROM_FILENAME "openbios-ppc"
35 #define PROM_ADDR 0xfff00000
37 #define KERNEL_LOAD_ADDR 0x01000000
38 #define CMDLINE_ADDR 0x027ff000
39 #define INITRD_LOAD_ADDR 0x02800000
41 #define ESCC_CLOCK 3686400
44 void cuda_init (int *cuda_mem_index
, qemu_irq irq
);
47 void macio_init (PCIBus
*bus
, int device_id
, int is_oldworld
, int pic_mem_index
,
48 int dbdma_mem_index
, int cuda_mem_index
, void *nvram
,
49 int nb_ide
, int *ide_mem_index
, int escc_mem_index
);
52 qemu_irq
*heathrow_pic_init(int *pmem_index
,
53 int nb_cpus
, qemu_irq
**irqs
);
56 PCIBus
*pci_grackle_init(uint32_t base
, qemu_irq
*pic
);
59 PCIBus
*pci_pmac_init(qemu_irq
*pic
);
60 PCIBus
*pci_pmac_u3_init(qemu_irq
*pic
);
63 typedef struct MacIONVRAMState MacIONVRAMState
;
65 MacIONVRAMState
*macio_nvram_init (int *mem_index
, target_phys_addr_t size
,
66 unsigned int it_shift
);
67 void macio_nvram_map (void *opaque
, target_phys_addr_t mem_base
);
68 void pmac_format_nvram_partition (MacIONVRAMState
*nvr
, int len
);
69 uint32_t macio_nvram_read (void *opaque
, uint32_t addr
);
70 void macio_nvram_write (void *opaque
, uint32_t addr
, uint32_t val
);
74 #define MAX_ADB_DEVICES 16
76 #define ADB_MAX_OUT_LEN 16
78 typedef struct ADBDevice ADBDevice
;
80 /* buf = NULL means polling */
81 typedef int ADBDeviceRequest(ADBDevice
*d
, uint8_t *buf_out
,
82 const uint8_t *buf
, int len
);
83 typedef int ADBDeviceReset(ADBDevice
*d
);
86 struct ADBBusState
*bus
;
89 ADBDeviceRequest
*devreq
;
90 ADBDeviceReset
*devreset
;
94 typedef struct ADBBusState
{
95 ADBDevice devices
[MAX_ADB_DEVICES
];
100 int adb_request(ADBBusState
*s
, uint8_t *buf_out
,
101 const uint8_t *buf
, int len
);
102 int adb_poll(ADBBusState
*s
, uint8_t *buf_out
);
104 ADBDevice
*adb_register_device(ADBBusState
*s
, int devaddr
,
105 ADBDeviceRequest
*devreq
,
106 ADBDeviceReset
*devreset
,
108 void adb_kbd_init(ADBBusState
*bus
);
109 void adb_mouse_init(ADBBusState
*bus
);
111 extern ADBBusState adb_bus
;
113 #endif /* !defined(__PPC_MAC_H__) */