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Merge branch 'stable-0.15' of git://git.qemu.org/qemu
[qemu.git] / hw / usb-ohci.c
blob8491d599280b55442975b79dd6e1cc401685899a
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
27 */
28
29 #include "hw.h"
30 #include "qemu-timer.h"
31 #include "usb.h"
32 #include "pci.h"
33 #include "usb-ohci.h"
34 #include "sysbus.h"
35 #include "qdev-addr.h"
36
37 //#define DEBUG_OHCI
38 /* Dump packet contents. */
39 //#define DEBUG_PACKET
40 //#define DEBUG_ISOCH
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #ifdef DEBUG_OHCI
45 #define DPRINTF printf
46 #else
47 #define DPRINTF(...)
48 #endif
49
50 /* Number of Downstream Ports on the root hub. */
51
52 #define OHCI_MAX_PORTS 15
53
54 static int64_t usb_frame_time;
55 static int64_t usb_bit_time;
56
57 typedef struct OHCIPort {
58 USBPort port;
59 uint32_t ctrl;
60 } OHCIPort;
61
62 typedef struct {
63 USBBus bus;
64 qemu_irq irq;
65 int mem;
66 int num_ports;
67 const char *name;
68
69 QEMUTimer *eof_timer;
70 int64_t sof_time;
71
72 /* OHCI state */
73 /* Control partition */
74 uint32_t ctl, status;
75 uint32_t intr_status;
76 uint32_t intr;
77
78 /* memory pointer partition */
79 uint32_t hcca;
80 uint32_t ctrl_head, ctrl_cur;
81 uint32_t bulk_head, bulk_cur;
82 uint32_t per_cur;
83 uint32_t done;
84 int done_count;
85
86 /* Frame counter partition */
87 uint32_t fsmps:15;
88 uint32_t fit:1;
89 uint32_t fi:14;
90 uint32_t frt:1;
91 uint16_t frame_number;
92 uint16_t padding;
93 uint32_t pstart;
94 uint32_t lst;
95
96 /* Root Hub partition */
97 uint32_t rhdesc_a, rhdesc_b;
98 uint32_t rhstatus;
99 OHCIPort rhport[OHCI_MAX_PORTS];
100
101 /* PXA27x Non-OHCI events */
102 uint32_t hstatus;
103 uint32_t hmask;
104 uint32_t hreset;
105 uint32_t htest;
106
107 /* SM501 local memory offset */
108 target_phys_addr_t localmem_base;
109
110 /* Active packets. */
111 uint32_t old_ctl;
112 USBPacket usb_packet;
113 uint8_t usb_buf[8192];
114 uint32_t async_td;
115 int async_complete;
116
117 } OHCIState;
118
119 /* Host Controller Communications Area */
120 struct ohci_hcca {
121 uint32_t intr[32];
122 uint16_t frame, pad;
123 uint32_t done;
124 };
125
126 static void ohci_bus_stop(OHCIState *ohci);
127 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev);
128
129 /* Bitfields for the first word of an Endpoint Desciptor. */
130 #define OHCI_ED_FA_SHIFT 0
131 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
132 #define OHCI_ED_EN_SHIFT 7
133 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
134 #define OHCI_ED_D_SHIFT 11
135 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
136 #define OHCI_ED_S (1<<13)
137 #define OHCI_ED_K (1<<14)
138 #define OHCI_ED_F (1<<15)
139 #define OHCI_ED_MPS_SHIFT 16
140 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
141
142 /* Flags in the head field of an Endpoint Desciptor. */
143 #define OHCI_ED_H 1
144 #define OHCI_ED_C 2
145
146 /* Bitfields for the first word of a Transfer Desciptor. */
147 #define OHCI_TD_R (1<<18)
148 #define OHCI_TD_DP_SHIFT 19
149 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
150 #define OHCI_TD_DI_SHIFT 21
151 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
152 #define OHCI_TD_T0 (1<<24)
153 #define OHCI_TD_T1 (1<<24)
154 #define OHCI_TD_EC_SHIFT 26
155 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
156 #define OHCI_TD_CC_SHIFT 28
157 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
158
159 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
160 /* CC & DI - same as in the General Transfer Desciptor */
161 #define OHCI_TD_SF_SHIFT 0
162 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
163 #define OHCI_TD_FC_SHIFT 24
164 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
165
166 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
167 #define OHCI_TD_PSW_CC_SHIFT 12
168 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
169 #define OHCI_TD_PSW_SIZE_SHIFT 0
170 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
171
172 #define OHCI_PAGE_MASK 0xfffff000
173 #define OHCI_OFFSET_MASK 0xfff
174
175 #define OHCI_DPTR_MASK 0xfffffff0
176
177 #define OHCI_BM(val, field) \
178 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
179
180 #define OHCI_SET_BM(val, field, newval) do { \
181 val &= ~OHCI_##field##_MASK; \
182 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
183 } while(0)
184
185 /* endpoint descriptor */
186 struct ohci_ed {
187 uint32_t flags;
188 uint32_t tail;
189 uint32_t head;
190 uint32_t next;
191 };
192
193 /* General transfer descriptor */
194 struct ohci_td {
195 uint32_t flags;
196 uint32_t cbp;
197 uint32_t next;
198 uint32_t be;
199 };
200
201 /* Isochronous transfer descriptor */
202 struct ohci_iso_td {
203 uint32_t flags;
204 uint32_t bp;
205 uint32_t next;
206 uint32_t be;
207 uint16_t offset[8];
208 };
209
210 #define USB_HZ 12000000
211
212 /* OHCI Local stuff */
213 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
214 #define OHCI_CTL_PLE (1<<2)
215 #define OHCI_CTL_IE (1<<3)
216 #define OHCI_CTL_CLE (1<<4)
217 #define OHCI_CTL_BLE (1<<5)
218 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
219 #define OHCI_USB_RESET 0x00
220 #define OHCI_USB_RESUME 0x40
221 #define OHCI_USB_OPERATIONAL 0x80
222 #define OHCI_USB_SUSPEND 0xc0
223 #define OHCI_CTL_IR (1<<8)
224 #define OHCI_CTL_RWC (1<<9)
225 #define OHCI_CTL_RWE (1<<10)
226
227 #define OHCI_STATUS_HCR (1<<0)
228 #define OHCI_STATUS_CLF (1<<1)
229 #define OHCI_STATUS_BLF (1<<2)
230 #define OHCI_STATUS_OCR (1<<3)
231 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
232
233 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
234 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
235 #define OHCI_INTR_SF (1<<2) /* Start of frame */
236 #define OHCI_INTR_RD (1<<3) /* Resume detect */
237 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
238 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
239 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
240 #define OHCI_INTR_OC (1<<30) /* Ownership change */
241 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
242
243 #define OHCI_HCCA_SIZE 0x100
244 #define OHCI_HCCA_MASK 0xffffff00
245
246 #define OHCI_EDPTR_MASK 0xfffffff0
247
248 #define OHCI_FMI_FI 0x00003fff
249 #define OHCI_FMI_FSMPS 0xffff0000
250 #define OHCI_FMI_FIT 0x80000000
251
252 #define OHCI_FR_RT (1<<31)
253
254 #define OHCI_LS_THRESH 0x628
255
256 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
257 #define OHCI_RHA_PSM (1<<8)
258 #define OHCI_RHA_NPS (1<<9)
259 #define OHCI_RHA_DT (1<<10)
260 #define OHCI_RHA_OCPM (1<<11)
261 #define OHCI_RHA_NOCP (1<<12)
262 #define OHCI_RHA_POTPGT_MASK 0xff000000
263
264 #define OHCI_RHS_LPS (1<<0)
265 #define OHCI_RHS_OCI (1<<1)
266 #define OHCI_RHS_DRWE (1<<15)
267 #define OHCI_RHS_LPSC (1<<16)
268 #define OHCI_RHS_OCIC (1<<17)
269 #define OHCI_RHS_CRWE (1<<31)
270
271 #define OHCI_PORT_CCS (1<<0)
272 #define OHCI_PORT_PES (1<<1)
273 #define OHCI_PORT_PSS (1<<2)
274 #define OHCI_PORT_POCI (1<<3)
275 #define OHCI_PORT_PRS (1<<4)
276 #define OHCI_PORT_PPS (1<<8)
277 #define OHCI_PORT_LSDA (1<<9)
278 #define OHCI_PORT_CSC (1<<16)
279 #define OHCI_PORT_PESC (1<<17)
280 #define OHCI_PORT_PSSC (1<<18)
281 #define OHCI_PORT_OCIC (1<<19)
282 #define OHCI_PORT_PRSC (1<<20)
283 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
284 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
285
286 #define OHCI_TD_DIR_SETUP 0x0
287 #define OHCI_TD_DIR_OUT 0x1
288 #define OHCI_TD_DIR_IN 0x2
289 #define OHCI_TD_DIR_RESERVED 0x3
290
291 #define OHCI_CC_NOERROR 0x0
292 #define OHCI_CC_CRC 0x1
293 #define OHCI_CC_BITSTUFFING 0x2
294 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
295 #define OHCI_CC_STALL 0x4
296 #define OHCI_CC_DEVICENOTRESPONDING 0x5
297 #define OHCI_CC_PIDCHECKFAILURE 0x6
298 #define OHCI_CC_UNDEXPETEDPID 0x7
299 #define OHCI_CC_DATAOVERRUN 0x8
300 #define OHCI_CC_DATAUNDERRUN 0x9
301 #define OHCI_CC_BUFFEROVERRUN 0xc
302 #define OHCI_CC_BUFFERUNDERRUN 0xd
303
304 #define OHCI_HRESET_FSBIR (1 << 0)
305
306 /* Update IRQ levels */
307 static inline void ohci_intr_update(OHCIState *ohci)
308 {
309 int level = 0;
310
311 if ((ohci->intr & OHCI_INTR_MIE) &&
312 (ohci->intr_status & ohci->intr))
313 level = 1;
314
315 qemu_set_irq(ohci->irq, level);
316 }
317
318 /* Set an interrupt */
319 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
320 {
321 ohci->intr_status |= intr;
322 ohci_intr_update(ohci);
323 }
324
325 /* Attach or detach a device on a root hub port. */
326 static void ohci_attach(USBPort *port1)
327 {
328 OHCIState *s = port1->opaque;
329 OHCIPort *port = &s->rhport[port1->index];
330 uint32_t old_state = port->ctrl;
331
332 /* set connect status */
333 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
334
335 /* update speed */
336 if (port->port.dev->speed == USB_SPEED_LOW) {
337 port->ctrl |= OHCI_PORT_LSDA;
338 } else {
339 port->ctrl &= ~OHCI_PORT_LSDA;
340 }
341
342 /* notify of remote-wakeup */
343 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
344 ohci_set_interrupt(s, OHCI_INTR_RD);
345 }
346
347 DPRINTF("usb-ohci: Attached port %d\n", port1->index);
348
349 if (old_state != port->ctrl) {
350 ohci_set_interrupt(s, OHCI_INTR_RHSC);
351 }
352 }
353
354 static void ohci_detach(USBPort *port1)
355 {
356 OHCIState *s = port1->opaque;
357 OHCIPort *port = &s->rhport[port1->index];
358 uint32_t old_state = port->ctrl;
359
360 ohci_async_cancel_device(s, port1->dev);
361
362 /* set connect status */
363 if (port->ctrl & OHCI_PORT_CCS) {
364 port->ctrl &= ~OHCI_PORT_CCS;
365 port->ctrl |= OHCI_PORT_CSC;
366 }
367 /* disable port */
368 if (port->ctrl & OHCI_PORT_PES) {
369 port->ctrl &= ~OHCI_PORT_PES;
370 port->ctrl |= OHCI_PORT_PESC;
371 }
372 DPRINTF("usb-ohci: Detached port %d\n", port1->index);
373
374 if (old_state != port->ctrl) {
375 ohci_set_interrupt(s, OHCI_INTR_RHSC);
376 }
377 }
378
379 static void ohci_wakeup(USBPort *port1)
380 {
381 OHCIState *s = port1->opaque;
382 OHCIPort *port = &s->rhport[port1->index];
383 uint32_t intr = 0;
384 if (port->ctrl & OHCI_PORT_PSS) {
385 DPRINTF("usb-ohci: port %d: wakeup\n", port1->index);
386 port->ctrl |= OHCI_PORT_PSSC;
387 port->ctrl &= ~OHCI_PORT_PSS;
388 intr = OHCI_INTR_RHSC;
389 }
390 /* Note that the controller can be suspended even if this port is not */
391 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
392 DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
393 /* This is the one state transition the controller can do by itself */
394 s->ctl &= ~OHCI_CTL_HCFS;
395 s->ctl |= OHCI_USB_RESUME;
396 /* In suspend mode only ResumeDetected is possible, not RHSC:
397 * see the OHCI spec 5.1.2.3.
398 */
399 intr = OHCI_INTR_RD;
400 }
401 ohci_set_interrupt(s, intr);
402 }
403
404 static void ohci_child_detach(USBPort *port1, USBDevice *child)
405 {
406 OHCIState *s = port1->opaque;
407
408 ohci_async_cancel_device(s, child);
409 }
410
411 /* Reset the controller */
412 static void ohci_reset(void *opaque)
413 {
414 OHCIState *ohci = opaque;
415 OHCIPort *port;
416 int i;
417
418 ohci_bus_stop(ohci);
419 ohci->ctl = 0;
420 ohci->old_ctl = 0;
421 ohci->status = 0;
422 ohci->intr_status = 0;
423 ohci->intr = OHCI_INTR_MIE;
424
425 ohci->hcca = 0;
426 ohci->ctrl_head = ohci->ctrl_cur = 0;
427 ohci->bulk_head = ohci->bulk_cur = 0;
428 ohci->per_cur = 0;
429 ohci->done = 0;
430 ohci->done_count = 7;
431
432 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
433 * I took the value linux sets ...
434 */
435 ohci->fsmps = 0x2778;
436 ohci->fi = 0x2edf;
437 ohci->fit = 0;
438 ohci->frt = 0;
439 ohci->frame_number = 0;
440 ohci->pstart = 0;
441 ohci->lst = OHCI_LS_THRESH;
442
443 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
444 ohci->rhdesc_b = 0x0; /* Impl. specific */
445 ohci->rhstatus = 0;
446
447 for (i = 0; i < ohci->num_ports; i++)
448 {
449 port = &ohci->rhport[i];
450 port->ctrl = 0;
451 if (port->port.dev) {
452 usb_attach(&port->port, port->port.dev);
453 }
454 }
455 if (ohci->async_td) {
456 usb_cancel_packet(&ohci->usb_packet);
457 ohci->async_td = 0;
458 }
459 DPRINTF("usb-ohci: Reset %s\n", ohci->name);
460 }
461
462 /* Get an array of dwords from main memory */
463 static inline int get_dwords(OHCIState *ohci,
464 uint32_t addr, uint32_t *buf, int num)
465 {
466 int i;
467
468 addr += ohci->localmem_base;
469
470 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
471 cpu_physical_memory_read(addr, buf, sizeof(*buf));
472 *buf = le32_to_cpu(*buf);
473 }
474
475 return 1;
476 }
477
478 /* Put an array of dwords in to main memory */
479 static inline int put_dwords(OHCIState *ohci,
480 uint32_t addr, uint32_t *buf, int num)
481 {
482 int i;
483
484 addr += ohci->localmem_base;
485
486 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
487 uint32_t tmp = cpu_to_le32(*buf);
488 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
489 }
490
491 return 1;
492 }
493
494 /* Get an array of words from main memory */
495 static inline int get_words(OHCIState *ohci,
496 uint32_t addr, uint16_t *buf, int num)
497 {
498 int i;
499
500 addr += ohci->localmem_base;
501
502 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
503 cpu_physical_memory_read(addr, buf, sizeof(*buf));
504 *buf = le16_to_cpu(*buf);
505 }
506
507 return 1;
508 }
509
510 /* Put an array of words in to main memory */
511 static inline int put_words(OHCIState *ohci,
512 uint32_t addr, uint16_t *buf, int num)
513 {
514 int i;
515
516 addr += ohci->localmem_base;
517
518 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
519 uint16_t tmp = cpu_to_le16(*buf);
520 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
521 }
522
523 return 1;
524 }
525
526 static inline int ohci_read_ed(OHCIState *ohci,
527 uint32_t addr, struct ohci_ed *ed)
528 {
529 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
530 }
531
532 static inline int ohci_read_td(OHCIState *ohci,
533 uint32_t addr, struct ohci_td *td)
534 {
535 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
536 }
537
538 static inline int ohci_read_iso_td(OHCIState *ohci,
539 uint32_t addr, struct ohci_iso_td *td)
540 {
541 return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
542 get_words(ohci, addr + 16, td->offset, 8));
543 }
544
545 static inline int ohci_read_hcca(OHCIState *ohci,
546 uint32_t addr, struct ohci_hcca *hcca)
547 {
548 cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
549 return 1;
550 }
551
552 static inline int ohci_put_ed(OHCIState *ohci,
553 uint32_t addr, struct ohci_ed *ed)
554 {
555 return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
556 }
557
558 static inline int ohci_put_td(OHCIState *ohci,
559 uint32_t addr, struct ohci_td *td)
560 {
561 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
562 }
563
564 static inline int ohci_put_iso_td(OHCIState *ohci,
565 uint32_t addr, struct ohci_iso_td *td)
566 {
567 return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
568 put_words(ohci, addr + 16, td->offset, 8));
569 }
570
571 static inline int ohci_put_hcca(OHCIState *ohci,
572 uint32_t addr, struct ohci_hcca *hcca)
573 {
574 cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
575 return 1;
576 }
577
578 /* Read/Write the contents of a TD from/to main memory. */
579 static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
580 uint8_t *buf, int len, int write)
581 {
582 uint32_t ptr;
583 uint32_t n;
584
585 ptr = td->cbp;
586 n = 0x1000 - (ptr & 0xfff);
587 if (n > len)
588 n = len;
589 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
590 if (n == len)
591 return;
592 ptr = td->be & ~0xfffu;
593 buf += n;
594 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
595 }
596
597 /* Read/Write the contents of an ISO TD from/to main memory. */
598 static void ohci_copy_iso_td(OHCIState *ohci,
599 uint32_t start_addr, uint32_t end_addr,
600 uint8_t *buf, int len, int write)
601 {
602 uint32_t ptr;
603 uint32_t n;
604
605 ptr = start_addr;
606 n = 0x1000 - (ptr & 0xfff);
607 if (n > len)
608 n = len;
609 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
610 if (n == len)
611 return;
612 ptr = end_addr & ~0xfffu;
613 buf += n;
614 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
615 }
616
617 static void ohci_process_lists(OHCIState *ohci, int completion);
618
619 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
620 {
621 OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
622 #ifdef DEBUG_PACKET
623 DPRINTF("Async packet complete\n");
624 #endif
625 ohci->async_complete = 1;
626 ohci_process_lists(ohci, 1);
627 }
628
629 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
630
631 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
632 int completion)
633 {
634 int dir;
635 size_t len = 0;
636 #ifdef DEBUG_ISOCH
637 const char *str = NULL;
638 #endif
639 int pid;
640 int ret;
641 int i;
642 USBDevice *dev;
643 struct ohci_iso_td iso_td;
644 uint32_t addr;
645 uint16_t starting_frame;
646 int16_t relative_frame_number;
647 int frame_count;
648 uint32_t start_offset, next_offset, end_offset = 0;
649 uint32_t start_addr, end_addr;
650
651 addr = ed->head & OHCI_DPTR_MASK;
652
653 if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
654 printf("usb-ohci: ISO_TD read error at %x\n", addr);
655 return 0;
656 }
657
658 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
659 frame_count = OHCI_BM(iso_td.flags, TD_FC);
660 relative_frame_number = USUB(ohci->frame_number, starting_frame);
661
662 #ifdef DEBUG_ISOCH
663 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
664 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
665 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
666 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
667 "frame_number 0x%.8x starting_frame 0x%.8x\n"
668 "frame_count 0x%.8x relative %d\n"
669 "di 0x%.8x cc 0x%.8x\n",
670 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
671 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
672 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
673 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
674 ohci->frame_number, starting_frame,
675 frame_count, relative_frame_number,
676 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
677 #endif
678
679 if (relative_frame_number < 0) {
680 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
681 return 1;
682 } else if (relative_frame_number > frame_count) {
683 /* ISO TD expired - retire the TD to the Done Queue and continue with
684 the next ISO TD of the same ED */
685 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
686 frame_count);
687 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
688 ed->head &= ~OHCI_DPTR_MASK;
689 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
690 iso_td.next = ohci->done;
691 ohci->done = addr;
692 i = OHCI_BM(iso_td.flags, TD_DI);
693 if (i < ohci->done_count)
694 ohci->done_count = i;
695 ohci_put_iso_td(ohci, addr, &iso_td);
696 return 0;
697 }
698
699 dir = OHCI_BM(ed->flags, ED_D);
700 switch (dir) {
701 case OHCI_TD_DIR_IN:
702 #ifdef DEBUG_ISOCH
703 str = "in";
704 #endif
705 pid = USB_TOKEN_IN;
706 break;
707 case OHCI_TD_DIR_OUT:
708 #ifdef DEBUG_ISOCH
709 str = "out";
710 #endif
711 pid = USB_TOKEN_OUT;
712 break;
713 case OHCI_TD_DIR_SETUP:
714 #ifdef DEBUG_ISOCH
715 str = "setup";
716 #endif
717 pid = USB_TOKEN_SETUP;
718 break;
719 default:
720 printf("usb-ohci: Bad direction %d\n", dir);
721 return 1;
722 }
723
724 if (!iso_td.bp || !iso_td.be) {
725 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
726 return 1;
727 }
728
729 start_offset = iso_td.offset[relative_frame_number];
730 next_offset = iso_td.offset[relative_frame_number + 1];
731
732 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
733 ((relative_frame_number < frame_count) &&
734 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
735 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
736 start_offset, next_offset);
737 return 1;
738 }
739
740 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
741 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
742 start_offset, next_offset);
743 return 1;
744 }
745
746 if ((start_offset & 0x1000) == 0) {
747 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
748 (start_offset & OHCI_OFFSET_MASK);
749 } else {
750 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
751 (start_offset & OHCI_OFFSET_MASK);
752 }
753
754 if (relative_frame_number < frame_count) {
755 end_offset = next_offset - 1;
756 if ((end_offset & 0x1000) == 0) {
757 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
758 (end_offset & OHCI_OFFSET_MASK);
759 } else {
760 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
761 (end_offset & OHCI_OFFSET_MASK);
762 }
763 } else {
764 /* Last packet in the ISO TD */
765 end_addr = iso_td.be;
766 }
767
768 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
769 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
770 - (start_addr & OHCI_OFFSET_MASK);
771 } else {
772 len = end_addr - start_addr + 1;
773 }
774
775 if (len && dir != OHCI_TD_DIR_IN) {
776 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
777 }
778
779 if (completion) {
780 ret = ohci->usb_packet.len;
781 } else {
782 ret = USB_RET_NODEV;
783 for (i = 0; i < ohci->num_ports; i++) {
784 dev = ohci->rhport[i].port.dev;
785 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
786 continue;
787 ohci->usb_packet.pid = pid;
788 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
789 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
790 ohci->usb_packet.data = ohci->usb_buf;
791 ohci->usb_packet.len = len;
792 ret = usb_handle_packet(dev, &ohci->usb_packet);
793 if (ret != USB_RET_NODEV)
794 break;
795 }
796
797 if (ret == USB_RET_ASYNC) {
798 return 1;
799 }
800 }
801
802 #ifdef DEBUG_ISOCH
803 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
804 start_offset, end_offset, start_addr, end_addr, str, len, ret);
805 #endif
806
807 /* Writeback */
808 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
809 /* IN transfer succeeded */
810 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
811 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
812 OHCI_CC_NOERROR);
813 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
814 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
815 /* OUT transfer succeeded */
816 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
817 OHCI_CC_NOERROR);
818 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
819 } else {
820 if (ret > (ssize_t) len) {
821 printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
822 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
823 OHCI_CC_DATAOVERRUN);
824 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
825 len);
826 } else if (ret >= 0) {
827 printf("usb-ohci: DataUnderrun %d\n", ret);
828 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
829 OHCI_CC_DATAUNDERRUN);
830 } else {
831 switch (ret) {
832 case USB_RET_NODEV:
833 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
834 OHCI_CC_DEVICENOTRESPONDING);
835 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
836 0);
837 break;
838 case USB_RET_NAK:
839 case USB_RET_STALL:
840 printf("usb-ohci: got NAK/STALL %d\n", ret);
841 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
842 OHCI_CC_STALL);
843 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
844 0);
845 break;
846 default:
847 printf("usb-ohci: Bad device response %d\n", ret);
848 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
849 OHCI_CC_UNDEXPETEDPID);
850 break;
851 }
852 }
853 }
854
855 if (relative_frame_number == frame_count) {
856 /* Last data packet of ISO TD - retire the TD to the Done Queue */
857 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
858 ed->head &= ~OHCI_DPTR_MASK;
859 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
860 iso_td.next = ohci->done;
861 ohci->done = addr;
862 i = OHCI_BM(iso_td.flags, TD_DI);
863 if (i < ohci->done_count)
864 ohci->done_count = i;
865 }
866 ohci_put_iso_td(ohci, addr, &iso_td);
867 return 1;
868 }
869
870 /* Service a transport descriptor.
871 Returns nonzero to terminate processing of this endpoint. */
872
873 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
874 {
875 int dir;
876 size_t len = 0;
877 #ifdef DEBUG_PACKET
878 const char *str = NULL;
879 #endif
880 int pid;
881 int ret;
882 int i;
883 USBDevice *dev;
884 struct ohci_td td;
885 uint32_t addr;
886 int flag_r;
887 int completion;
888
889 addr = ed->head & OHCI_DPTR_MASK;
890 /* See if this TD has already been submitted to the device. */
891 completion = (addr == ohci->async_td);
892 if (completion && !ohci->async_complete) {
893 #ifdef DEBUG_PACKET
894 DPRINTF("Skipping async TD\n");
895 #endif
896 return 1;
897 }
898 if (!ohci_read_td(ohci, addr, &td)) {
899 fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
900 return 0;
901 }
902
903 dir = OHCI_BM(ed->flags, ED_D);
904 switch (dir) {
905 case OHCI_TD_DIR_OUT:
906 case OHCI_TD_DIR_IN:
907 /* Same value. */
908 break;
909 default:
910 dir = OHCI_BM(td.flags, TD_DP);
911 break;
912 }
913
914 switch (dir) {
915 case OHCI_TD_DIR_IN:
916 #ifdef DEBUG_PACKET
917 str = "in";
918 #endif
919 pid = USB_TOKEN_IN;
920 break;
921 case OHCI_TD_DIR_OUT:
922 #ifdef DEBUG_PACKET
923 str = "out";
924 #endif
925 pid = USB_TOKEN_OUT;
926 break;
927 case OHCI_TD_DIR_SETUP:
928 #ifdef DEBUG_PACKET
929 str = "setup";
930 #endif
931 pid = USB_TOKEN_SETUP;
932 break;
933 default:
934 fprintf(stderr, "usb-ohci: Bad direction\n");
935 return 1;
936 }
937 if (td.cbp && td.be) {
938 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
939 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
940 } else {
941 len = (td.be - td.cbp) + 1;
942 }
943
944 if (len && dir != OHCI_TD_DIR_IN && !completion) {
945 ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
946 }
947 }
948
949 flag_r = (td.flags & OHCI_TD_R) != 0;
950 #ifdef DEBUG_PACKET
951 DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
952 addr, (int64_t)len, str, flag_r, td.cbp, td.be);
953
954 if (len > 0 && dir != OHCI_TD_DIR_IN) {
955 DPRINTF(" data:");
956 for (i = 0; i < len; i++)
957 printf(" %.2x", ohci->usb_buf[i]);
958 DPRINTF("\n");
959 }
960 #endif
961 if (completion) {
962 ret = ohci->usb_packet.len;
963 ohci->async_td = 0;
964 ohci->async_complete = 0;
965 } else {
966 ret = USB_RET_NODEV;
967 for (i = 0; i < ohci->num_ports; i++) {
968 dev = ohci->rhport[i].port.dev;
969 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
970 continue;
971
972 if (ohci->async_td) {
973 /* ??? The hardware should allow one active packet per
974 endpoint. We only allow one active packet per controller.
975 This should be sufficient as long as devices respond in a
976 timely manner.
977 */
978 #ifdef DEBUG_PACKET
979 DPRINTF("Too many pending packets\n");
980 #endif
981 return 1;
982 }
983 ohci->usb_packet.pid = pid;
984 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
985 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
986 ohci->usb_packet.data = ohci->usb_buf;
987 ohci->usb_packet.len = len;
988 ret = usb_handle_packet(dev, &ohci->usb_packet);
989 if (ret != USB_RET_NODEV)
990 break;
991 }
992 #ifdef DEBUG_PACKET
993 DPRINTF("ret=%d\n", ret);
994 #endif
995 if (ret == USB_RET_ASYNC) {
996 ohci->async_td = addr;
997 return 1;
998 }
999 }
1000 if (ret >= 0) {
1001 if (dir == OHCI_TD_DIR_IN) {
1002 ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
1003 #ifdef DEBUG_PACKET
1004 DPRINTF(" data:");
1005 for (i = 0; i < ret; i++)
1006 printf(" %.2x", ohci->usb_buf[i]);
1007 DPRINTF("\n");
1008 #endif
1009 } else {
1010 ret = len;
1011 }
1012 }
1013
1014 /* Writeback */
1015 if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
1016 /* Transmission succeeded. */
1017 if (ret == len) {
1018 td.cbp = 0;
1019 } else {
1020 td.cbp += ret;
1021 if ((td.cbp & 0xfff) + ret > 0xfff) {
1022 td.cbp &= 0xfff;
1023 td.cbp |= td.be & ~0xfff;
1024 }
1025 }
1026 td.flags |= OHCI_TD_T1;
1027 td.flags ^= OHCI_TD_T0;
1028 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1029 OHCI_SET_BM(td.flags, TD_EC, 0);
1030
1031 ed->head &= ~OHCI_ED_C;
1032 if (td.flags & OHCI_TD_T0)
1033 ed->head |= OHCI_ED_C;
1034 } else {
1035 if (ret >= 0) {
1036 DPRINTF("usb-ohci: Underrun\n");
1037 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1038 } else {
1039 switch (ret) {
1040 case USB_RET_NODEV:
1041 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1042 case USB_RET_NAK:
1043 DPRINTF("usb-ohci: got NAK\n");
1044 return 1;
1045 case USB_RET_STALL:
1046 DPRINTF("usb-ohci: got STALL\n");
1047 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1048 break;
1049 case USB_RET_BABBLE:
1050 DPRINTF("usb-ohci: got BABBLE\n");
1051 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1052 break;
1053 default:
1054 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1055 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1056 OHCI_SET_BM(td.flags, TD_EC, 3);
1057 break;
1058 }
1059 }
1060 ed->head |= OHCI_ED_H;
1061 }
1062
1063 /* Retire this TD */
1064 ed->head &= ~OHCI_DPTR_MASK;
1065 ed->head |= td.next & OHCI_DPTR_MASK;
1066 td.next = ohci->done;
1067 ohci->done = addr;
1068 i = OHCI_BM(td.flags, TD_DI);
1069 if (i < ohci->done_count)
1070 ohci->done_count = i;
1071 ohci_put_td(ohci, addr, &td);
1072 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1073 }
1074
1075 /* Service an endpoint list. Returns nonzero if active TD were found. */
1076 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1077 {
1078 struct ohci_ed ed;
1079 uint32_t next_ed;
1080 uint32_t cur;
1081 int active;
1082
1083 active = 0;
1084
1085 if (head == 0)
1086 return 0;
1087
1088 for (cur = head; cur; cur = next_ed) {
1089 if (!ohci_read_ed(ohci, cur, &ed)) {
1090 fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1091 return 0;
1092 }
1093
1094 next_ed = ed.next & OHCI_DPTR_MASK;
1095
1096 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1097 uint32_t addr;
1098 /* Cancel pending packets for ED that have been paused. */
1099 addr = ed.head & OHCI_DPTR_MASK;
1100 if (ohci->async_td && addr == ohci->async_td) {
1101 usb_cancel_packet(&ohci->usb_packet);
1102 ohci->async_td = 0;
1103 }
1104 continue;
1105 }
1106
1107 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1108 #ifdef DEBUG_PACKET
1109 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1110 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1111 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1112 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1113 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1114 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1115 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1116 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1117 #endif
1118 active = 1;
1119
1120 if ((ed.flags & OHCI_ED_F) == 0) {
1121 if (ohci_service_td(ohci, &ed))
1122 break;
1123 } else {
1124 /* Handle isochronous endpoints */
1125 if (ohci_service_iso_td(ohci, &ed, completion))
1126 break;
1127 }
1128 }
1129
1130 ohci_put_ed(ohci, cur, &ed);
1131 }
1132
1133 return active;
1134 }
1135
1136 /* Generate a SOF event, and set a timer for EOF */
1137 static void ohci_sof(OHCIState *ohci)
1138 {
1139 ohci->sof_time = qemu_get_clock_ns(vm_clock);
1140 qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1141 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1142 }
1143
1144 /* Process Control and Bulk lists. */
1145 static void ohci_process_lists(OHCIState *ohci, int completion)
1146 {
1147 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1148 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1149 DPRINTF("usb-ohci: head %x, cur %x\n",
1150 ohci->ctrl_head, ohci->ctrl_cur);
1151 }
1152 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1153 ohci->ctrl_cur = 0;
1154 ohci->status &= ~OHCI_STATUS_CLF;
1155 }
1156 }
1157
1158 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1159 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1160 ohci->bulk_cur = 0;
1161 ohci->status &= ~OHCI_STATUS_BLF;
1162 }
1163 }
1164 }
1165
1166 /* Do frame processing on frame boundary */
1167 static void ohci_frame_boundary(void *opaque)
1168 {
1169 OHCIState *ohci = opaque;
1170 struct ohci_hcca hcca;
1171
1172 ohci_read_hcca(ohci, ohci->hcca, &hcca);
1173
1174 /* Process all the lists at the end of the frame */
1175 if (ohci->ctl & OHCI_CTL_PLE) {
1176 int n;
1177
1178 n = ohci->frame_number & 0x1f;
1179 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1180 }
1181
1182 /* Cancel all pending packets if either of the lists has been disabled. */
1183 if (ohci->async_td &&
1184 ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1185 usb_cancel_packet(&ohci->usb_packet);
1186 ohci->async_td = 0;
1187 }
1188 ohci->old_ctl = ohci->ctl;
1189 ohci_process_lists(ohci, 0);
1190
1191 /* Frame boundary, so do EOF stuf here */
1192 ohci->frt = ohci->fit;
1193
1194 /* Increment frame number and take care of endianness. */
1195 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1196 hcca.frame = cpu_to_le16(ohci->frame_number);
1197
1198 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1199 if (!ohci->done)
1200 abort();
1201 if (ohci->intr & ohci->intr_status)
1202 ohci->done |= 1;
1203 hcca.done = cpu_to_le32(ohci->done);
1204 ohci->done = 0;
1205 ohci->done_count = 7;
1206 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1207 }
1208
1209 if (ohci->done_count != 7 && ohci->done_count != 0)
1210 ohci->done_count--;
1211
1212 /* Do SOF stuff here */
1213 ohci_sof(ohci);
1214
1215 /* Writeback HCCA */
1216 ohci_put_hcca(ohci, ohci->hcca, &hcca);
1217 }
1218
1219 /* Start sending SOF tokens across the USB bus, lists are processed in
1220 * next frame
1221 */
1222 static int ohci_bus_start(OHCIState *ohci)
1223 {
1224 ohci->eof_timer = qemu_new_timer_ns(vm_clock,
1225 ohci_frame_boundary,
1226 ohci);
1227
1228 if (ohci->eof_timer == NULL) {
1229 fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
1230 /* TODO: Signal unrecoverable error */
1231 return 0;
1232 }
1233
1234 DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1235
1236 ohci_sof(ohci);
1237
1238 return 1;
1239 }
1240
1241 /* Stop sending SOF tokens on the bus */
1242 static void ohci_bus_stop(OHCIState *ohci)
1243 {
1244 if (ohci->eof_timer)
1245 qemu_del_timer(ohci->eof_timer);
1246 ohci->eof_timer = NULL;
1247 }
1248
1249 /* Sets a flag in a port status register but only set it if the port is
1250 * connected, if not set ConnectStatusChange flag. If flag is enabled
1251 * return 1.
1252 */
1253 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1254 {
1255 int ret = 1;
1256
1257 /* writing a 0 has no effect */
1258 if (val == 0)
1259 return 0;
1260
1261 /* If CurrentConnectStatus is cleared we set
1262 * ConnectStatusChange
1263 */
1264 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1265 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1266 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1267 /* TODO: CSC is a wakeup event */
1268 }
1269 return 0;
1270 }
1271
1272 if (ohci->rhport[i].ctrl & val)
1273 ret = 0;
1274
1275 /* set the bit */
1276 ohci->rhport[i].ctrl |= val;
1277
1278 return ret;
1279 }
1280
1281 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1282 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1283 {
1284 val &= OHCI_FMI_FI;
1285
1286 if (val != ohci->fi) {
1287 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1288 ohci->name, ohci->fi, ohci->fi);
1289 }
1290
1291 ohci->fi = val;
1292 }
1293
1294 static void ohci_port_power(OHCIState *ohci, int i, int p)
1295 {
1296 if (p) {
1297 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1298 } else {
1299 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1300 OHCI_PORT_CCS|
1301 OHCI_PORT_PSS|
1302 OHCI_PORT_PRS);
1303 }
1304 }
1305
1306 /* Set HcControlRegister */
1307 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1308 {
1309 uint32_t old_state;
1310 uint32_t new_state;
1311
1312 old_state = ohci->ctl & OHCI_CTL_HCFS;
1313 ohci->ctl = val;
1314 new_state = ohci->ctl & OHCI_CTL_HCFS;
1315
1316 /* no state change */
1317 if (old_state == new_state)
1318 return;
1319
1320 switch (new_state) {
1321 case OHCI_USB_OPERATIONAL:
1322 ohci_bus_start(ohci);
1323 break;
1324 case OHCI_USB_SUSPEND:
1325 ohci_bus_stop(ohci);
1326 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1327 break;
1328 case OHCI_USB_RESUME:
1329 DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1330 break;
1331 case OHCI_USB_RESET:
1332 ohci_reset(ohci);
1333 DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1334 break;
1335 }
1336 }
1337
1338 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1339 {
1340 uint16_t fr;
1341 int64_t tks;
1342
1343 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1344 return (ohci->frt << 31);
1345
1346 /* Being in USB operational state guarnatees sof_time was
1347 * set already.
1348 */
1349 tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
1350
1351 /* avoid muldiv if possible */
1352 if (tks >= usb_frame_time)
1353 return (ohci->frt << 31);
1354
1355 tks = muldiv64(1, tks, usb_bit_time);
1356 fr = (uint16_t)(ohci->fi - tks);
1357
1358 return (ohci->frt << 31) | fr;
1359 }
1360
1361
1362 /* Set root hub status */
1363 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1364 {
1365 uint32_t old_state;
1366
1367 old_state = ohci->rhstatus;
1368
1369 /* write 1 to clear OCIC */
1370 if (val & OHCI_RHS_OCIC)
1371 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1372
1373 if (val & OHCI_RHS_LPS) {
1374 int i;
1375
1376 for (i = 0; i < ohci->num_ports; i++)
1377 ohci_port_power(ohci, i, 0);
1378 DPRINTF("usb-ohci: powered down all ports\n");
1379 }
1380
1381 if (val & OHCI_RHS_LPSC) {
1382 int i;
1383
1384 for (i = 0; i < ohci->num_ports; i++)
1385 ohci_port_power(ohci, i, 1);
1386 DPRINTF("usb-ohci: powered up all ports\n");
1387 }
1388
1389 if (val & OHCI_RHS_DRWE)
1390 ohci->rhstatus |= OHCI_RHS_DRWE;
1391
1392 if (val & OHCI_RHS_CRWE)
1393 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1394
1395 if (old_state != ohci->rhstatus)
1396 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1397 }
1398
1399 /* Set root hub port status */
1400 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1401 {
1402 uint32_t old_state;
1403 OHCIPort *port;
1404
1405 port = &ohci->rhport[portnum];
1406 old_state = port->ctrl;
1407
1408 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1409 if (val & OHCI_PORT_WTC)
1410 port->ctrl &= ~(val & OHCI_PORT_WTC);
1411
1412 if (val & OHCI_PORT_CCS)
1413 port->ctrl &= ~OHCI_PORT_PES;
1414
1415 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1416
1417 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1418 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1419 }
1420
1421 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1422 DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1423 usb_send_msg(port->port.dev, USB_MSG_RESET);
1424 port->ctrl &= ~OHCI_PORT_PRS;
1425 /* ??? Should this also set OHCI_PORT_PESC. */
1426 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1427 }
1428
1429 /* Invert order here to ensure in ambiguous case, device is
1430 * powered up...
1431 */
1432 if (val & OHCI_PORT_LSDA)
1433 ohci_port_power(ohci, portnum, 0);
1434 if (val & OHCI_PORT_PPS)
1435 ohci_port_power(ohci, portnum, 1);
1436
1437 if (old_state != port->ctrl)
1438 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1439
1440 return;
1441 }
1442
1443 static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1444 {
1445 OHCIState *ohci = ptr;
1446 uint32_t retval;
1447
1448 addr &= 0xff;
1449
1450 /* Only aligned reads are allowed on OHCI */
1451 if (addr & 3) {
1452 fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1453 return 0xffffffff;
1454 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1455 /* HcRhPortStatus */
1456 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1457 } else {
1458 switch (addr >> 2) {
1459 case 0: /* HcRevision */
1460 retval = 0x10;
1461 break;
1462
1463 case 1: /* HcControl */
1464 retval = ohci->ctl;
1465 break;
1466
1467 case 2: /* HcCommandStatus */
1468 retval = ohci->status;
1469 break;
1470
1471 case 3: /* HcInterruptStatus */
1472 retval = ohci->intr_status;
1473 break;
1474
1475 case 4: /* HcInterruptEnable */
1476 case 5: /* HcInterruptDisable */
1477 retval = ohci->intr;
1478 break;
1479
1480 case 6: /* HcHCCA */
1481 retval = ohci->hcca;
1482 break;
1483
1484 case 7: /* HcPeriodCurrentED */
1485 retval = ohci->per_cur;
1486 break;
1487
1488 case 8: /* HcControlHeadED */
1489 retval = ohci->ctrl_head;
1490 break;
1491
1492 case 9: /* HcControlCurrentED */
1493 retval = ohci->ctrl_cur;
1494 break;
1495
1496 case 10: /* HcBulkHeadED */
1497 retval = ohci->bulk_head;
1498 break;
1499
1500 case 11: /* HcBulkCurrentED */
1501 retval = ohci->bulk_cur;
1502 break;
1503
1504 case 12: /* HcDoneHead */
1505 retval = ohci->done;
1506 break;
1507
1508 case 13: /* HcFmInterretval */
1509 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1510 break;
1511
1512 case 14: /* HcFmRemaining */
1513 retval = ohci_get_frame_remaining(ohci);
1514 break;
1515
1516 case 15: /* HcFmNumber */
1517 retval = ohci->frame_number;
1518 break;
1519
1520 case 16: /* HcPeriodicStart */
1521 retval = ohci->pstart;
1522 break;
1523
1524 case 17: /* HcLSThreshold */
1525 retval = ohci->lst;
1526 break;
1527
1528 case 18: /* HcRhDescriptorA */
1529 retval = ohci->rhdesc_a;
1530 break;
1531
1532 case 19: /* HcRhDescriptorB */
1533 retval = ohci->rhdesc_b;
1534 break;
1535
1536 case 20: /* HcRhStatus */
1537 retval = ohci->rhstatus;
1538 break;
1539
1540 /* PXA27x specific registers */
1541 case 24: /* HcStatus */
1542 retval = ohci->hstatus & ohci->hmask;
1543 break;
1544
1545 case 25: /* HcHReset */
1546 retval = ohci->hreset;
1547 break;
1548
1549 case 26: /* HcHInterruptEnable */
1550 retval = ohci->hmask;
1551 break;
1552
1553 case 27: /* HcHInterruptTest */
1554 retval = ohci->htest;
1555 break;
1556
1557 default:
1558 fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1559 retval = 0xffffffff;
1560 }
1561 }
1562
1563 return retval;
1564 }
1565
1566 static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1567 {
1568 OHCIState *ohci = ptr;
1569
1570 addr &= 0xff;
1571
1572 /* Only aligned reads are allowed on OHCI */
1573 if (addr & 3) {
1574 fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1575 return;
1576 }
1577
1578 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1579 /* HcRhPortStatus */
1580 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1581 return;
1582 }
1583
1584 switch (addr >> 2) {
1585 case 1: /* HcControl */
1586 ohci_set_ctl(ohci, val);
1587 break;
1588
1589 case 2: /* HcCommandStatus */
1590 /* SOC is read-only */
1591 val = (val & ~OHCI_STATUS_SOC);
1592
1593 /* Bits written as '0' remain unchanged in the register */
1594 ohci->status |= val;
1595
1596 if (ohci->status & OHCI_STATUS_HCR)
1597 ohci_reset(ohci);
1598 break;
1599
1600 case 3: /* HcInterruptStatus */
1601 ohci->intr_status &= ~val;
1602 ohci_intr_update(ohci);
1603 break;
1604
1605 case 4: /* HcInterruptEnable */
1606 ohci->intr |= val;
1607 ohci_intr_update(ohci);
1608 break;
1609
1610 case 5: /* HcInterruptDisable */
1611 ohci->intr &= ~val;
1612 ohci_intr_update(ohci);
1613 break;
1614
1615 case 6: /* HcHCCA */
1616 ohci->hcca = val & OHCI_HCCA_MASK;
1617 break;
1618
1619 case 7: /* HcPeriodCurrentED */
1620 /* Ignore writes to this read-only register, Linux does them */
1621 break;
1622
1623 case 8: /* HcControlHeadED */
1624 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1625 break;
1626
1627 case 9: /* HcControlCurrentED */
1628 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1629 break;
1630
1631 case 10: /* HcBulkHeadED */
1632 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1633 break;
1634
1635 case 11: /* HcBulkCurrentED */
1636 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1637 break;
1638
1639 case 13: /* HcFmInterval */
1640 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1641 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1642 ohci_set_frame_interval(ohci, val);
1643 break;
1644
1645 case 15: /* HcFmNumber */
1646 break;
1647
1648 case 16: /* HcPeriodicStart */
1649 ohci->pstart = val & 0xffff;
1650 break;
1651
1652 case 17: /* HcLSThreshold */
1653 ohci->lst = val & 0xffff;
1654 break;
1655
1656 case 18: /* HcRhDescriptorA */
1657 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1658 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1659 break;
1660
1661 case 19: /* HcRhDescriptorB */
1662 break;
1663
1664 case 20: /* HcRhStatus */
1665 ohci_set_hub_status(ohci, val);
1666 break;
1667
1668 /* PXA27x specific registers */
1669 case 24: /* HcStatus */
1670 ohci->hstatus &= ~(val & ohci->hmask);
1671
1672 case 25: /* HcHReset */
1673 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1674 if (val & OHCI_HRESET_FSBIR)
1675 ohci_reset(ohci);
1676 break;
1677
1678 case 26: /* HcHInterruptEnable */
1679 ohci->hmask = val;
1680 break;
1681
1682 case 27: /* HcHInterruptTest */
1683 ohci->htest = val;
1684 break;
1685
1686 default:
1687 fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1688 break;
1689 }
1690 }
1691
1692 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev)
1693 {
1694 if (ohci->async_td && ohci->usb_packet.owner == dev) {
1695 usb_cancel_packet(&ohci->usb_packet);
1696 ohci->async_td = 0;
1697 }
1698 }
1699
1700 /* Only dword reads are defined on OHCI register space */
1701 static CPUReadMemoryFunc * const ohci_readfn[3]={
1702 ohci_mem_read,
1703 ohci_mem_read,
1704 ohci_mem_read
1705 };
1706
1707 /* Only dword writes are defined on OHCI register space */
1708 static CPUWriteMemoryFunc * const ohci_writefn[3]={
1709 ohci_mem_write,
1710 ohci_mem_write,
1711 ohci_mem_write
1712 };
1713
1714 static USBPortOps ohci_port_ops = {
1715 .attach = ohci_attach,
1716 .detach = ohci_detach,
1717 .child_detach = ohci_child_detach,
1718 .wakeup = ohci_wakeup,
1719 .complete = ohci_async_complete_packet,
1720 };
1721
1722 static USBBusOps ohci_bus_ops = {
1723 };
1724
1725 static int usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1726 int num_ports, uint32_t localmem_base,
1727 char *masterbus, uint32_t firstport)
1728 {
1729 int i;
1730
1731 if (usb_frame_time == 0) {
1732 #ifdef OHCI_TIME_WARP
1733 usb_frame_time = get_ticks_per_sec();
1734 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1735 #else
1736 usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1737 if (get_ticks_per_sec() >= USB_HZ) {
1738 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1739 } else {
1740 usb_bit_time = 1;
1741 }
1742 #endif
1743 DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1744 usb_frame_time, usb_bit_time);
1745 }
1746
1747 ohci->num_ports = num_ports;
1748 if (masterbus) {
1749 USBPort *ports[OHCI_MAX_PORTS];
1750 for(i = 0; i < num_ports; i++) {
1751 ports[i] = &ohci->rhport[i].port;
1752 }
1753 if (usb_register_companion(masterbus, ports, num_ports,
1754 firstport, ohci, &ohci_port_ops,
1755 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1756 return -1;
1757 }
1758 } else {
1759 usb_bus_new(&ohci->bus, &ohci_bus_ops, dev);
1760 for (i = 0; i < num_ports; i++) {
1761 usb_register_port(&ohci->bus, &ohci->rhport[i].port,
1762 ohci, i, &ohci_port_ops,
1763 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1764 }
1765 }
1766
1767 ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
1768 DEVICE_LITTLE_ENDIAN);
1769 ohci->localmem_base = localmem_base;
1770
1771 ohci->name = dev->info->name;
1772
1773 ohci->async_td = 0;
1774 qemu_register_reset(ohci_reset, ohci);
1775
1776 return 0;
1777 }
1778
1779 typedef struct {
1780 PCIDevice pci_dev;
1781 OHCIState state;
1782 char *masterbus;
1783 uint32_t num_ports;
1784 uint32_t firstport;
1785 } OHCIPCIState;
1786
1787 static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1788 {
1789 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1790
1791 ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1792 /* TODO: RST# value should be 0. */
1793 ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
1794
1795 if (usb_ohci_init(&ohci->state, &dev->qdev, ohci->num_ports, 0,
1796 ohci->masterbus, ohci->firstport) != 0) {
1797 return -1;
1798 }
1799 ohci->state.irq = ohci->pci_dev.irq[0];
1800
1801 /* TODO: avoid cast below by using dev */
1802 pci_register_bar_simple(&ohci->pci_dev, 0, 256, 0, ohci->state.mem);
1803 return 0;
1804 }
1805
1806 void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1807 {
1808 pci_create_simple(bus, devfn, "pci-ohci");
1809 }
1810
1811 typedef struct {
1812 SysBusDevice busdev;
1813 OHCIState ohci;
1814 uint32_t num_ports;
1815 target_phys_addr_t dma_offset;
1816 } OHCISysBusState;
1817
1818 static int ohci_init_pxa(SysBusDevice *dev)
1819 {
1820 OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1821
1822 /* Cannot fail as we pass NULL for masterbus */
1823 usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset, NULL, 0);
1824 sysbus_init_irq(dev, &s->ohci.irq);
1825 sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
1826
1827 return 0;
1828 }
1829
1830 static PCIDeviceInfo ohci_pci_info = {
1831 .qdev.name = "pci-ohci",
1832 .qdev.desc = "Apple USB Controller",
1833 .qdev.size = sizeof(OHCIPCIState),
1834 .init = usb_ohci_initfn_pci,
1835 .vendor_id = PCI_VENDOR_ID_APPLE,
1836 .device_id = PCI_DEVICE_ID_APPLE_IPID_USB,
1837 .class_id = PCI_CLASS_SERIAL_USB,
1838 .qdev.props = (Property[]) {
1839 DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
1840 DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
1841 DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
1842 DEFINE_PROP_END_OF_LIST(),
1843 },
1844 };
1845
1846 static SysBusDeviceInfo ohci_sysbus_info = {
1847 .init = ohci_init_pxa,
1848 .qdev.name = "sysbus-ohci",
1849 .qdev.desc = "OHCI USB Controller",
1850 .qdev.size = sizeof(OHCISysBusState),
1851 .qdev.props = (Property[]) {
1852 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1853 DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1854 DEFINE_PROP_END_OF_LIST(),
1855 }
1856 };
1857
1858 static void ohci_register(void)
1859 {
1860 pci_qdev_register(&ohci_pci_info);
1861 sysbus_register_withprop(&ohci_sysbus_info);
1862 }
1863 device_init(ohci_register);
QEmu